1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #endif 49 50 #include <dev/uart/uart.h> 51 #include <dev/uart/uart_cpu.h> 52 #ifdef FDT 53 #include <dev/uart/uart_cpu_fdt.h> 54 #endif 55 #include <dev/uart/uart_bus.h> 56 #include <dev/uart/uart_dev_ns8250.h> 57 #include <dev/uart/uart_ppstypes.h> 58 #ifdef DEV_ACPI 59 #include <dev/uart/uart_cpu_acpi.h> 60 #endif 61 62 #include <dev/ic/ns16550.h> 63 64 #include "uart_if.h" 65 66 #define DEFAULT_RCLK 1843200 67 68 /* 69 * Set the default baudrate tolerance to 3.0%. 70 * 71 * Some embedded boards have odd reference clocks (eg 25MHz) 72 * and we need to handle higher variances in the target baud rate. 73 */ 74 #ifndef UART_DEV_TOLERANCE_PCT 75 #define UART_DEV_TOLERANCE_PCT 30 76 #endif /* UART_DEV_TOLERANCE_PCT */ 77 78 static int broken_txfifo = 0; 79 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 80 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 81 82 /* 83 * Clear pending interrupts. THRE is cleared by reading IIR. Data 84 * that may have been received gets lost here. 85 */ 86 static void 87 ns8250_clrint(struct uart_bas *bas) 88 { 89 uint8_t iir, lsr; 90 91 iir = uart_getreg(bas, REG_IIR); 92 while ((iir & IIR_NOPEND) == 0) { 93 iir &= IIR_IMASK; 94 if (iir == IIR_RLS) { 95 lsr = uart_getreg(bas, REG_LSR); 96 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 97 (void)uart_getreg(bas, REG_DATA); 98 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 99 (void)uart_getreg(bas, REG_DATA); 100 else if (iir == IIR_MLSC) 101 (void)uart_getreg(bas, REG_MSR); 102 uart_barrier(bas); 103 iir = uart_getreg(bas, REG_IIR); 104 } 105 } 106 107 static int 108 ns8250_delay(struct uart_bas *bas) 109 { 110 int divisor; 111 u_char lcr; 112 113 lcr = uart_getreg(bas, REG_LCR); 114 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 115 uart_barrier(bas); 116 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 117 uart_barrier(bas); 118 uart_setreg(bas, REG_LCR, lcr); 119 uart_barrier(bas); 120 121 /* 1/10th the time to transmit 1 character (estimate). */ 122 if (divisor <= 134) 123 return (16000000 * divisor / bas->rclk); 124 return (16000 * divisor / (bas->rclk / 1000)); 125 } 126 127 static int 128 ns8250_divisor(int rclk, int baudrate) 129 { 130 int actual_baud, divisor; 131 int error; 132 133 if (baudrate == 0) 134 return (0); 135 136 divisor = (rclk / (baudrate << 3) + 1) >> 1; 137 if (divisor == 0 || divisor >= 65536) 138 return (0); 139 actual_baud = rclk / (divisor << 4); 140 141 /* 10 times error in percent: */ 142 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 143 144 /* enforce maximum error tolerance: */ 145 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 146 return (0); 147 148 return (divisor); 149 } 150 151 static int 152 ns8250_drain(struct uart_bas *bas, int what) 153 { 154 int delay, limit; 155 156 delay = ns8250_delay(bas); 157 158 if (what & UART_DRAIN_TRANSMITTER) { 159 /* 160 * Pick an arbitrary high limit to avoid getting stuck in 161 * an infinite loop when the hardware is broken. Make the 162 * limit high enough to handle large FIFOs. 163 */ 164 limit = 10*1024; 165 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 166 DELAY(delay); 167 if (limit == 0) { 168 /* printf("ns8250: transmitter appears stuck... "); */ 169 return (EIO); 170 } 171 } 172 173 if (what & UART_DRAIN_RECEIVER) { 174 /* 175 * Pick an arbitrary high limit to avoid getting stuck in 176 * an infinite loop when the hardware is broken. Make the 177 * limit high enough to handle large FIFOs and integrated 178 * UARTs. The HP rx2600 for example has 3 UARTs on the 179 * management board that tend to get a lot of data send 180 * to it when the UART is first activated. 181 */ 182 limit=10*4096; 183 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 184 (void)uart_getreg(bas, REG_DATA); 185 uart_barrier(bas); 186 DELAY(delay << 2); 187 } 188 if (limit == 0) { 189 /* printf("ns8250: receiver appears broken... "); */ 190 return (EIO); 191 } 192 } 193 194 return (0); 195 } 196 197 /* 198 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 199 * drained. WARNING: this function clobbers the FIFO setting! 200 */ 201 static void 202 ns8250_flush(struct uart_bas *bas, int what) 203 { 204 uint8_t fcr; 205 206 fcr = FCR_ENABLE; 207 #ifdef CPU_XBURST 208 fcr |= FCR_UART_ON; 209 #endif 210 if (what & UART_FLUSH_TRANSMITTER) 211 fcr |= FCR_XMT_RST; 212 if (what & UART_FLUSH_RECEIVER) 213 fcr |= FCR_RCV_RST; 214 uart_setreg(bas, REG_FCR, fcr); 215 uart_barrier(bas); 216 } 217 218 static int 219 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 220 int parity) 221 { 222 int divisor; 223 uint8_t lcr; 224 225 lcr = 0; 226 if (databits >= 8) 227 lcr |= LCR_8BITS; 228 else if (databits == 7) 229 lcr |= LCR_7BITS; 230 else if (databits == 6) 231 lcr |= LCR_6BITS; 232 else 233 lcr |= LCR_5BITS; 234 if (stopbits > 1) 235 lcr |= LCR_STOPB; 236 lcr |= parity << 3; 237 238 /* Set baudrate. */ 239 if (baudrate > 0) { 240 divisor = ns8250_divisor(bas->rclk, baudrate); 241 if (divisor == 0) 242 return (EINVAL); 243 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 244 uart_barrier(bas); 245 uart_setreg(bas, REG_DLL, divisor & 0xff); 246 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 247 uart_barrier(bas); 248 } 249 250 /* Set LCR and clear DLAB. */ 251 uart_setreg(bas, REG_LCR, lcr); 252 uart_barrier(bas); 253 return (0); 254 } 255 256 /* 257 * Low-level UART interface. 258 */ 259 static int ns8250_probe(struct uart_bas *bas); 260 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 261 static void ns8250_term(struct uart_bas *bas); 262 static void ns8250_putc(struct uart_bas *bas, int); 263 static int ns8250_rxready(struct uart_bas *bas); 264 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 265 266 struct uart_ops uart_ns8250_ops = { 267 .probe = ns8250_probe, 268 .init = ns8250_init, 269 .term = ns8250_term, 270 .putc = ns8250_putc, 271 .rxready = ns8250_rxready, 272 .getc = ns8250_getc, 273 }; 274 275 static int 276 ns8250_probe(struct uart_bas *bas) 277 { 278 u_char val; 279 280 #ifdef CPU_XBURST 281 uart_setreg(bas, REG_FCR, FCR_UART_ON); 282 #endif 283 284 /* Check known 0 bits that don't depend on DLAB. */ 285 val = uart_getreg(bas, REG_IIR); 286 if (val & 0x30) 287 return (ENXIO); 288 /* 289 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 290 * chip, but otherwise doesn't seem to have a function. In 291 * other words, uart(4) works regardless. Ignore that bit so 292 * the probe succeeds. 293 */ 294 val = uart_getreg(bas, REG_MCR); 295 if (val & 0xa0) 296 return (ENXIO); 297 298 return (0); 299 } 300 301 static void 302 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 303 int parity) 304 { 305 u_char ier, val; 306 307 if (bas->rclk == 0) 308 bas->rclk = DEFAULT_RCLK; 309 ns8250_param(bas, baudrate, databits, stopbits, parity); 310 311 /* Disable all interrupt sources. */ 312 /* 313 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 314 * UARTs split the receive time-out interrupt bit out separately as 315 * 0x10. This gets handled by ier_mask and ier_rxbits below. 316 */ 317 ier = uart_getreg(bas, REG_IER) & 0xe0; 318 uart_setreg(bas, REG_IER, ier); 319 uart_barrier(bas); 320 321 /* Disable the FIFO (if present). */ 322 val = 0; 323 #ifdef CPU_XBURST 324 val |= FCR_UART_ON; 325 #endif 326 uart_setreg(bas, REG_FCR, val); 327 uart_barrier(bas); 328 329 /* Set RTS & DTR. */ 330 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 331 uart_barrier(bas); 332 333 ns8250_clrint(bas); 334 } 335 336 static void 337 ns8250_term(struct uart_bas *bas) 338 { 339 340 /* Clear RTS & DTR. */ 341 uart_setreg(bas, REG_MCR, MCR_IE); 342 uart_barrier(bas); 343 } 344 345 static void 346 ns8250_putc(struct uart_bas *bas, int c) 347 { 348 int limit; 349 350 limit = 250000; 351 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 352 DELAY(4); 353 uart_setreg(bas, REG_DATA, c); 354 uart_barrier(bas); 355 } 356 357 static int 358 ns8250_rxready(struct uart_bas *bas) 359 { 360 361 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 362 } 363 364 static int 365 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 366 { 367 int c; 368 369 uart_lock(hwmtx); 370 371 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 372 uart_unlock(hwmtx); 373 DELAY(4); 374 uart_lock(hwmtx); 375 } 376 377 c = uart_getreg(bas, REG_DATA); 378 379 uart_unlock(hwmtx); 380 381 return (c); 382 } 383 384 static kobj_method_t ns8250_methods[] = { 385 KOBJMETHOD(uart_attach, ns8250_bus_attach), 386 KOBJMETHOD(uart_detach, ns8250_bus_detach), 387 KOBJMETHOD(uart_flush, ns8250_bus_flush), 388 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 389 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 390 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 391 KOBJMETHOD(uart_param, ns8250_bus_param), 392 KOBJMETHOD(uart_probe, ns8250_bus_probe), 393 KOBJMETHOD(uart_receive, ns8250_bus_receive), 394 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 395 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 396 KOBJMETHOD(uart_grab, ns8250_bus_grab), 397 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 398 { 0, 0 } 399 }; 400 401 struct uart_class uart_ns8250_class = { 402 "ns8250", 403 ns8250_methods, 404 sizeof(struct ns8250_softc), 405 .uc_ops = &uart_ns8250_ops, 406 .uc_range = 8, 407 .uc_rclk = DEFAULT_RCLK, 408 .uc_rshift = 0 409 }; 410 411 /* 412 * XXX -- refactor out ACPI and FDT ifdefs 413 */ 414 #ifdef DEV_ACPI 415 static struct acpi_uart_compat_data acpi_compat_data[] = { 416 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 417 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 418 {"MRVL0001", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 419 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 420 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 421 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 422 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 423 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 424 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 425 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 426 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 427 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 428 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 429 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 430 }; 431 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 432 #endif 433 434 #ifdef FDT 435 static struct ofw_compat_data compat_data[] = { 436 {"ns16550", (uintptr_t)&uart_ns8250_class}, 437 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 438 {NULL, (uintptr_t)NULL}, 439 }; 440 UART_FDT_CLASS_AND_DEVICE(compat_data); 441 #endif 442 443 /* Use token-pasting to form SER_ and MSR_ named constants. */ 444 #define SER(sig) SER_##sig 445 #define SERD(sig) SER_D##sig 446 #define MSR(sig) MSR_##sig 447 #define MSRD(sig) MSR_D##sig 448 449 /* 450 * Detect signal changes using software delta detection. The previous state of 451 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 452 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 453 * new state of both the signal and the delta bits. 454 */ 455 #define SIGCHGSW(var, msr, sig) \ 456 if ((msr) & MSR(sig)) { \ 457 if ((var & SER(sig)) == 0) \ 458 var |= SERD(sig) | SER(sig); \ 459 } else { \ 460 if ((var & SER(sig)) != 0) \ 461 var = SERD(sig) | (var & ~SER(sig)); \ 462 } 463 464 /* 465 * Detect signal changes using the hardware msr delta bits. This is currently 466 * used only when PPS timing information is being captured using the "narrow 467 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 468 * by time the interrupt handler is invoked. The hardware will latch the fact 469 * that it changed in the delta bits. 470 */ 471 #define SIGCHGHW(var, msr, sig) \ 472 if ((msr) & MSRD(sig)) { \ 473 if (((msr) & MSR(sig)) != 0) \ 474 var |= SERD(sig) | SER(sig); \ 475 else \ 476 var = SERD(sig) | (var & ~SER(sig)); \ 477 } 478 479 int 480 ns8250_bus_attach(struct uart_softc *sc) 481 { 482 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 483 struct uart_bas *bas; 484 unsigned int ivar; 485 #ifdef FDT 486 phandle_t node; 487 pcell_t cell; 488 #endif 489 490 #ifdef FDT 491 /* Check whether uart has a broken txfifo. */ 492 node = ofw_bus_get_node(sc->sc_dev); 493 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 494 broken_txfifo = cell ? 1 : 0; 495 #endif 496 497 bas = &sc->sc_bas; 498 499 ns8250->busy_detect = bas->busy_detect; 500 ns8250->mcr = uart_getreg(bas, REG_MCR); 501 ns8250->fcr = FCR_ENABLE; 502 #ifdef CPU_XBURST 503 ns8250->fcr |= FCR_UART_ON; 504 #endif 505 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 506 &ivar)) { 507 if (UART_FLAGS_FCR_RX_LOW(ivar)) 508 ns8250->fcr |= FCR_RX_LOW; 509 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 510 ns8250->fcr |= FCR_RX_MEDL; 511 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 512 ns8250->fcr |= FCR_RX_HIGH; 513 else 514 ns8250->fcr |= FCR_RX_MEDH; 515 } else 516 ns8250->fcr |= FCR_RX_MEDH; 517 518 /* Get IER mask */ 519 ivar = 0xf0; 520 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 521 &ivar); 522 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 523 524 /* Get IER RX interrupt bits */ 525 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 526 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 527 &ivar); 528 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 529 530 uart_setreg(bas, REG_FCR, ns8250->fcr); 531 uart_barrier(bas); 532 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 533 534 if (ns8250->mcr & MCR_DTR) 535 sc->sc_hwsig |= SER_DTR; 536 if (ns8250->mcr & MCR_RTS) 537 sc->sc_hwsig |= SER_RTS; 538 ns8250_bus_getsig(sc); 539 540 ns8250_clrint(bas); 541 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 542 ns8250->ier |= ns8250->ier_rxbits; 543 uart_setreg(bas, REG_IER, ns8250->ier); 544 uart_barrier(bas); 545 546 /* 547 * Timing of the H/W access was changed with r253161 of uart_core.c 548 * It has been observed that an ITE IT8513E would signal a break 549 * condition with pretty much every character it received, unless 550 * it had enough time to settle between ns8250_bus_attach() and 551 * ns8250_bus_ipend() -- which it accidentally had before r253161. 552 * It's not understood why the UART chip behaves this way and it 553 * could very well be that the DELAY make the H/W work in the same 554 * accidental manner as before. More analysis is warranted, but 555 * at least now we fixed a known regression. 556 */ 557 DELAY(200); 558 return (0); 559 } 560 561 int 562 ns8250_bus_detach(struct uart_softc *sc) 563 { 564 struct ns8250_softc *ns8250; 565 struct uart_bas *bas; 566 u_char ier; 567 568 ns8250 = (struct ns8250_softc *)sc; 569 bas = &sc->sc_bas; 570 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 571 uart_setreg(bas, REG_IER, ier); 572 uart_barrier(bas); 573 ns8250_clrint(bas); 574 return (0); 575 } 576 577 int 578 ns8250_bus_flush(struct uart_softc *sc, int what) 579 { 580 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 581 struct uart_bas *bas; 582 int error; 583 584 bas = &sc->sc_bas; 585 uart_lock(sc->sc_hwmtx); 586 if (sc->sc_rxfifosz > 1) { 587 ns8250_flush(bas, what); 588 uart_setreg(bas, REG_FCR, ns8250->fcr); 589 uart_barrier(bas); 590 error = 0; 591 } else 592 error = ns8250_drain(bas, what); 593 uart_unlock(sc->sc_hwmtx); 594 return (error); 595 } 596 597 int 598 ns8250_bus_getsig(struct uart_softc *sc) 599 { 600 uint32_t old, sig; 601 uint8_t msr; 602 603 /* 604 * The delta bits are reputed to be broken on some hardware, so use 605 * software delta detection by default. Use the hardware delta bits 606 * when capturing PPS pulses which are too narrow for software detection 607 * to see the edges. Hardware delta for RI doesn't work like the 608 * others, so always use software for it. Other threads may be changing 609 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 610 * update without other changes happening. Note that the SIGCHGxx() 611 * macros carefully preserve the delta bits when we have to loop several 612 * times and a signal transitions between iterations. 613 */ 614 do { 615 old = sc->sc_hwsig; 616 sig = old; 617 uart_lock(sc->sc_hwmtx); 618 msr = uart_getreg(&sc->sc_bas, REG_MSR); 619 uart_unlock(sc->sc_hwmtx); 620 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 621 SIGCHGHW(sig, msr, DSR); 622 SIGCHGHW(sig, msr, CTS); 623 SIGCHGHW(sig, msr, DCD); 624 } else { 625 SIGCHGSW(sig, msr, DSR); 626 SIGCHGSW(sig, msr, CTS); 627 SIGCHGSW(sig, msr, DCD); 628 } 629 SIGCHGSW(sig, msr, RI); 630 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 631 return (sig); 632 } 633 634 int 635 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 636 { 637 struct uart_bas *bas; 638 int baudrate, divisor, error; 639 uint8_t efr, lcr; 640 641 bas = &sc->sc_bas; 642 error = 0; 643 uart_lock(sc->sc_hwmtx); 644 switch (request) { 645 case UART_IOCTL_BREAK: 646 lcr = uart_getreg(bas, REG_LCR); 647 if (data) 648 lcr |= LCR_SBREAK; 649 else 650 lcr &= ~LCR_SBREAK; 651 uart_setreg(bas, REG_LCR, lcr); 652 uart_barrier(bas); 653 break; 654 case UART_IOCTL_IFLOW: 655 lcr = uart_getreg(bas, REG_LCR); 656 uart_barrier(bas); 657 uart_setreg(bas, REG_LCR, 0xbf); 658 uart_barrier(bas); 659 efr = uart_getreg(bas, REG_EFR); 660 if (data) 661 efr |= EFR_RTS; 662 else 663 efr &= ~EFR_RTS; 664 uart_setreg(bas, REG_EFR, efr); 665 uart_barrier(bas); 666 uart_setreg(bas, REG_LCR, lcr); 667 uart_barrier(bas); 668 break; 669 case UART_IOCTL_OFLOW: 670 lcr = uart_getreg(bas, REG_LCR); 671 uart_barrier(bas); 672 uart_setreg(bas, REG_LCR, 0xbf); 673 uart_barrier(bas); 674 efr = uart_getreg(bas, REG_EFR); 675 if (data) 676 efr |= EFR_CTS; 677 else 678 efr &= ~EFR_CTS; 679 uart_setreg(bas, REG_EFR, efr); 680 uart_barrier(bas); 681 uart_setreg(bas, REG_LCR, lcr); 682 uart_barrier(bas); 683 break; 684 case UART_IOCTL_BAUD: 685 lcr = uart_getreg(bas, REG_LCR); 686 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 687 uart_barrier(bas); 688 divisor = uart_getreg(bas, REG_DLL) | 689 (uart_getreg(bas, REG_DLH) << 8); 690 uart_barrier(bas); 691 uart_setreg(bas, REG_LCR, lcr); 692 uart_barrier(bas); 693 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 694 if (baudrate > 0) 695 *(int*)data = baudrate; 696 else 697 error = ENXIO; 698 break; 699 default: 700 error = EINVAL; 701 break; 702 } 703 uart_unlock(sc->sc_hwmtx); 704 return (error); 705 } 706 707 int 708 ns8250_bus_ipend(struct uart_softc *sc) 709 { 710 struct uart_bas *bas; 711 struct ns8250_softc *ns8250; 712 int ipend; 713 uint8_t iir, lsr; 714 715 ns8250 = (struct ns8250_softc *)sc; 716 bas = &sc->sc_bas; 717 uart_lock(sc->sc_hwmtx); 718 iir = uart_getreg(bas, REG_IIR); 719 720 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 721 (void)uart_getreg(bas, DW_REG_USR); 722 uart_unlock(sc->sc_hwmtx); 723 return (0); 724 } 725 if (iir & IIR_NOPEND) { 726 uart_unlock(sc->sc_hwmtx); 727 return (0); 728 } 729 ipend = 0; 730 if (iir & IIR_RXRDY) { 731 lsr = uart_getreg(bas, REG_LSR); 732 if (lsr & LSR_OE) 733 ipend |= SER_INT_OVERRUN; 734 if (lsr & LSR_BI) 735 ipend |= SER_INT_BREAK; 736 if (lsr & LSR_RXRDY) 737 ipend |= SER_INT_RXREADY; 738 } else { 739 if (iir & IIR_TXRDY) { 740 ipend |= SER_INT_TXIDLE; 741 uart_setreg(bas, REG_IER, ns8250->ier); 742 uart_barrier(bas); 743 } else 744 ipend |= SER_INT_SIGCHG; 745 } 746 if (ipend == 0) 747 ns8250_clrint(bas); 748 uart_unlock(sc->sc_hwmtx); 749 return (ipend); 750 } 751 752 int 753 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 754 int stopbits, int parity) 755 { 756 struct ns8250_softc *ns8250; 757 struct uart_bas *bas; 758 int error, limit; 759 760 ns8250 = (struct ns8250_softc*)sc; 761 bas = &sc->sc_bas; 762 uart_lock(sc->sc_hwmtx); 763 /* 764 * When using DW UART with BUSY detection it is necessary to wait 765 * until all serial transfers are finished before manipulating the 766 * line control. LCR will not be affected when UART is busy. 767 */ 768 if (ns8250->busy_detect != 0) { 769 /* 770 * Pick an arbitrary high limit to avoid getting stuck in 771 * an infinite loop in case when the hardware is broken. 772 */ 773 limit = 10 * 1024; 774 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 775 --limit) 776 DELAY(4); 777 778 if (limit <= 0) { 779 /* UART appears to be stuck */ 780 uart_unlock(sc->sc_hwmtx); 781 return (EIO); 782 } 783 } 784 785 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 786 uart_unlock(sc->sc_hwmtx); 787 return (error); 788 } 789 790 int 791 ns8250_bus_probe(struct uart_softc *sc) 792 { 793 struct ns8250_softc *ns8250; 794 struct uart_bas *bas; 795 int count, delay, error, limit; 796 uint8_t lsr, mcr, ier; 797 uint8_t val; 798 799 ns8250 = (struct ns8250_softc *)sc; 800 bas = &sc->sc_bas; 801 802 error = ns8250_probe(bas); 803 if (error) 804 return (error); 805 806 mcr = MCR_IE; 807 if (sc->sc_sysdev == NULL) { 808 /* By using ns8250_init() we also set DTR and RTS. */ 809 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 810 } else 811 mcr |= MCR_DTR | MCR_RTS; 812 813 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 814 if (error) 815 return (error); 816 817 /* 818 * Set loopback mode. This avoids having garbage on the wire and 819 * also allows us send and receive data. We set DTR and RTS to 820 * avoid the possibility that automatic flow-control prevents 821 * any data from being sent. 822 */ 823 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 824 uart_barrier(bas); 825 826 /* 827 * Enable FIFOs. And check that the UART has them. If not, we're 828 * done. Since this is the first time we enable the FIFOs, we reset 829 * them. 830 */ 831 val = FCR_ENABLE; 832 #ifdef CPU_XBURST 833 val |= FCR_UART_ON; 834 #endif 835 uart_setreg(bas, REG_FCR, val); 836 uart_barrier(bas); 837 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 838 /* 839 * NS16450 or INS8250. We don't bother to differentiate 840 * between them. They're too old to be interesting. 841 */ 842 uart_setreg(bas, REG_MCR, mcr); 843 uart_barrier(bas); 844 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 845 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 846 return (0); 847 } 848 849 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 850 #ifdef CPU_XBURST 851 val |= FCR_UART_ON; 852 #endif 853 uart_setreg(bas, REG_FCR, val); 854 uart_barrier(bas); 855 856 count = 0; 857 delay = ns8250_delay(bas); 858 859 /* We have FIFOs. Drain the transmitter and receiver. */ 860 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 861 if (error) { 862 uart_setreg(bas, REG_MCR, mcr); 863 val = 0; 864 #ifdef CPU_XBURST 865 val |= FCR_UART_ON; 866 #endif 867 uart_setreg(bas, REG_FCR, val); 868 uart_barrier(bas); 869 goto describe; 870 } 871 872 /* 873 * We should have a sufficiently clean "pipe" to determine the 874 * size of the FIFOs. We send as much characters as is reasonable 875 * and wait for the overflow bit in the LSR register to be 876 * asserted, counting the characters as we send them. Based on 877 * that count we know the FIFO size. 878 */ 879 do { 880 uart_setreg(bas, REG_DATA, 0); 881 uart_barrier(bas); 882 count++; 883 884 limit = 30; 885 lsr = 0; 886 /* 887 * LSR bits are cleared upon read, so we must accumulate 888 * them to be able to test LSR_OE below. 889 */ 890 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 891 --limit) 892 DELAY(delay); 893 if (limit == 0) { 894 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 895 uart_setreg(bas, REG_IER, ier); 896 uart_setreg(bas, REG_MCR, mcr); 897 val = 0; 898 #ifdef CPU_XBURST 899 val |= FCR_UART_ON; 900 #endif 901 uart_setreg(bas, REG_FCR, val); 902 uart_barrier(bas); 903 count = 0; 904 goto describe; 905 } 906 } while ((lsr & LSR_OE) == 0 && count < 260); 907 count--; 908 909 uart_setreg(bas, REG_MCR, mcr); 910 911 /* Reset FIFOs. */ 912 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 913 914 describe: 915 if (count >= 14 && count <= 16) { 916 sc->sc_rxfifosz = 16; 917 device_set_desc(sc->sc_dev, "16550 or compatible"); 918 } else if (count >= 28 && count <= 32) { 919 sc->sc_rxfifosz = 32; 920 device_set_desc(sc->sc_dev, "16650 or compatible"); 921 } else if (count >= 56 && count <= 64) { 922 sc->sc_rxfifosz = 64; 923 device_set_desc(sc->sc_dev, "16750 or compatible"); 924 } else if (count >= 112 && count <= 128) { 925 sc->sc_rxfifosz = 128; 926 device_set_desc(sc->sc_dev, "16950 or compatible"); 927 } else if (count >= 224 && count <= 256) { 928 sc->sc_rxfifosz = 256; 929 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 930 } else { 931 sc->sc_rxfifosz = 16; 932 device_set_desc(sc->sc_dev, 933 "Non-standard ns8250 class UART with FIFOs"); 934 } 935 936 /* 937 * Force the Tx FIFO size to 16 bytes for now. We don't program the 938 * Tx trigger. Also, we assume that all data has been sent when the 939 * interrupt happens. 940 */ 941 sc->sc_txfifosz = 16; 942 943 #if 0 944 /* 945 * XXX there are some issues related to hardware flow control and 946 * it's likely that uart(4) is the cause. This basically needs more 947 * investigation, but we avoid using for hardware flow control 948 * until then. 949 */ 950 /* 16650s or higher have automatic flow control. */ 951 if (sc->sc_rxfifosz > 16) { 952 sc->sc_hwiflow = 1; 953 sc->sc_hwoflow = 1; 954 } 955 #endif 956 957 return (0); 958 } 959 960 int 961 ns8250_bus_receive(struct uart_softc *sc) 962 { 963 struct uart_bas *bas; 964 int xc; 965 uint8_t lsr; 966 967 bas = &sc->sc_bas; 968 uart_lock(sc->sc_hwmtx); 969 lsr = uart_getreg(bas, REG_LSR); 970 while (lsr & LSR_RXRDY) { 971 if (uart_rx_full(sc)) { 972 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 973 break; 974 } 975 xc = uart_getreg(bas, REG_DATA); 976 if (lsr & LSR_FE) 977 xc |= UART_STAT_FRAMERR; 978 if (lsr & LSR_PE) 979 xc |= UART_STAT_PARERR; 980 uart_rx_put(sc, xc); 981 lsr = uart_getreg(bas, REG_LSR); 982 } 983 /* Discard everything left in the Rx FIFO. */ 984 while (lsr & LSR_RXRDY) { 985 (void)uart_getreg(bas, REG_DATA); 986 uart_barrier(bas); 987 lsr = uart_getreg(bas, REG_LSR); 988 } 989 uart_unlock(sc->sc_hwmtx); 990 return (0); 991 } 992 993 int 994 ns8250_bus_setsig(struct uart_softc *sc, int sig) 995 { 996 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 997 struct uart_bas *bas; 998 uint32_t new, old; 999 1000 bas = &sc->sc_bas; 1001 do { 1002 old = sc->sc_hwsig; 1003 new = old; 1004 if (sig & SER_DDTR) { 1005 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1006 } 1007 if (sig & SER_DRTS) { 1008 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1009 } 1010 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1011 uart_lock(sc->sc_hwmtx); 1012 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1013 if (new & SER_DTR) 1014 ns8250->mcr |= MCR_DTR; 1015 if (new & SER_RTS) 1016 ns8250->mcr |= MCR_RTS; 1017 uart_setreg(bas, REG_MCR, ns8250->mcr); 1018 uart_barrier(bas); 1019 uart_unlock(sc->sc_hwmtx); 1020 return (0); 1021 } 1022 1023 int 1024 ns8250_bus_transmit(struct uart_softc *sc) 1025 { 1026 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1027 struct uart_bas *bas; 1028 int i; 1029 1030 bas = &sc->sc_bas; 1031 uart_lock(sc->sc_hwmtx); 1032 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1033 DELAY(4); 1034 for (i = 0; i < sc->sc_txdatasz; i++) { 1035 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1036 uart_barrier(bas); 1037 } 1038 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 1039 uart_barrier(bas); 1040 if (broken_txfifo) 1041 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1042 else 1043 sc->sc_txbusy = 1; 1044 uart_unlock(sc->sc_hwmtx); 1045 if (broken_txfifo) 1046 uart_sched_softih(sc, SER_INT_TXIDLE); 1047 return (0); 1048 } 1049 1050 void 1051 ns8250_bus_grab(struct uart_softc *sc) 1052 { 1053 struct uart_bas *bas = &sc->sc_bas; 1054 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1055 u_char ier; 1056 1057 /* 1058 * turn off all interrupts to enter polling mode. Leave the 1059 * saved mask alone. We'll restore whatever it was in ungrab. 1060 * All pending interrupt signals are reset when IER is set to 0. 1061 */ 1062 uart_lock(sc->sc_hwmtx); 1063 ier = uart_getreg(bas, REG_IER); 1064 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1065 uart_barrier(bas); 1066 uart_unlock(sc->sc_hwmtx); 1067 } 1068 1069 void 1070 ns8250_bus_ungrab(struct uart_softc *sc) 1071 { 1072 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1073 struct uart_bas *bas = &sc->sc_bas; 1074 1075 /* 1076 * Restore previous interrupt mask 1077 */ 1078 uart_lock(sc->sc_hwmtx); 1079 uart_setreg(bas, REG_IER, ns8250->ier); 1080 uart_barrier(bas); 1081 uart_unlock(sc->sc_hwmtx); 1082 } 1083