1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/sysctl.h> 38 #include <machine/bus.h> 39 40 #ifdef FDT 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #endif 45 46 #include <dev/uart/uart.h> 47 #include <dev/uart/uart_cpu.h> 48 #include <dev/uart/uart_bus.h> 49 #include <dev/uart/uart_dev_ns8250.h> 50 51 #include <dev/ic/ns16550.h> 52 53 #include "uart_if.h" 54 55 #define DEFAULT_RCLK 1843200 56 57 static int broken_txfifo = 0; 58 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61 62 /* 63 * Clear pending interrupts. THRE is cleared by reading IIR. Data 64 * that may have been received gets lost here. 65 */ 66 static void 67 ns8250_clrint(struct uart_bas *bas) 68 { 69 uint8_t iir, lsr; 70 71 iir = uart_getreg(bas, REG_IIR); 72 while ((iir & IIR_NOPEND) == 0) { 73 iir &= IIR_IMASK; 74 if (iir == IIR_RLS) { 75 lsr = uart_getreg(bas, REG_LSR); 76 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77 (void)uart_getreg(bas, REG_DATA); 78 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 79 (void)uart_getreg(bas, REG_DATA); 80 else if (iir == IIR_MLSC) 81 (void)uart_getreg(bas, REG_MSR); 82 uart_barrier(bas); 83 iir = uart_getreg(bas, REG_IIR); 84 } 85 } 86 87 static int 88 ns8250_delay(struct uart_bas *bas) 89 { 90 int divisor; 91 u_char lcr; 92 93 lcr = uart_getreg(bas, REG_LCR); 94 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 95 uart_barrier(bas); 96 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 97 uart_barrier(bas); 98 uart_setreg(bas, REG_LCR, lcr); 99 uart_barrier(bas); 100 101 /* 1/10th the time to transmit 1 character (estimate). */ 102 if (divisor <= 134) 103 return (16000000 * divisor / bas->rclk); 104 return (16000 * divisor / (bas->rclk / 1000)); 105 } 106 107 static int 108 ns8250_divisor(int rclk, int baudrate) 109 { 110 int actual_baud, divisor; 111 int error; 112 113 if (baudrate == 0) 114 return (0); 115 116 divisor = (rclk / (baudrate << 3) + 1) >> 1; 117 if (divisor == 0 || divisor >= 65536) 118 return (0); 119 actual_baud = rclk / (divisor << 4); 120 121 /* 10 times error in percent: */ 122 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 123 124 /* 3.0% maximum error tolerance: */ 125 if (error < -30 || error > 30) 126 return (0); 127 128 return (divisor); 129 } 130 131 static int 132 ns8250_drain(struct uart_bas *bas, int what) 133 { 134 int delay, limit; 135 136 delay = ns8250_delay(bas); 137 138 if (what & UART_DRAIN_TRANSMITTER) { 139 /* 140 * Pick an arbitrary high limit to avoid getting stuck in 141 * an infinite loop when the hardware is broken. Make the 142 * limit high enough to handle large FIFOs. 143 */ 144 limit = 10*1024; 145 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 146 DELAY(delay); 147 if (limit == 0) { 148 /* printf("ns8250: transmitter appears stuck... "); */ 149 return (EIO); 150 } 151 } 152 153 if (what & UART_DRAIN_RECEIVER) { 154 /* 155 * Pick an arbitrary high limit to avoid getting stuck in 156 * an infinite loop when the hardware is broken. Make the 157 * limit high enough to handle large FIFOs and integrated 158 * UARTs. The HP rx2600 for example has 3 UARTs on the 159 * management board that tend to get a lot of data send 160 * to it when the UART is first activated. 161 */ 162 limit=10*4096; 163 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 164 (void)uart_getreg(bas, REG_DATA); 165 uart_barrier(bas); 166 DELAY(delay << 2); 167 } 168 if (limit == 0) { 169 /* printf("ns8250: receiver appears broken... "); */ 170 return (EIO); 171 } 172 } 173 174 return (0); 175 } 176 177 /* 178 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 179 * drained. WARNING: this function clobbers the FIFO setting! 180 */ 181 static void 182 ns8250_flush(struct uart_bas *bas, int what) 183 { 184 uint8_t fcr; 185 186 fcr = FCR_ENABLE; 187 if (what & UART_FLUSH_TRANSMITTER) 188 fcr |= FCR_XMT_RST; 189 if (what & UART_FLUSH_RECEIVER) 190 fcr |= FCR_RCV_RST; 191 uart_setreg(bas, REG_FCR, fcr); 192 uart_barrier(bas); 193 } 194 195 static int 196 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197 int parity) 198 { 199 int divisor; 200 uint8_t lcr; 201 202 lcr = 0; 203 if (databits >= 8) 204 lcr |= LCR_8BITS; 205 else if (databits == 7) 206 lcr |= LCR_7BITS; 207 else if (databits == 6) 208 lcr |= LCR_6BITS; 209 else 210 lcr |= LCR_5BITS; 211 if (stopbits > 1) 212 lcr |= LCR_STOPB; 213 lcr |= parity << 3; 214 215 /* Set baudrate. */ 216 if (baudrate > 0) { 217 divisor = ns8250_divisor(bas->rclk, baudrate); 218 if (divisor == 0) 219 return (EINVAL); 220 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 221 uart_barrier(bas); 222 uart_setreg(bas, REG_DLL, divisor & 0xff); 223 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 224 uart_barrier(bas); 225 } 226 227 /* Set LCR and clear DLAB. */ 228 uart_setreg(bas, REG_LCR, lcr); 229 uart_barrier(bas); 230 return (0); 231 } 232 233 /* 234 * Low-level UART interface. 235 */ 236 static int ns8250_probe(struct uart_bas *bas); 237 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 238 static void ns8250_term(struct uart_bas *bas); 239 static void ns8250_putc(struct uart_bas *bas, int); 240 static int ns8250_rxready(struct uart_bas *bas); 241 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 242 243 struct uart_ops uart_ns8250_ops = { 244 .probe = ns8250_probe, 245 .init = ns8250_init, 246 .term = ns8250_term, 247 .putc = ns8250_putc, 248 .rxready = ns8250_rxready, 249 .getc = ns8250_getc, 250 }; 251 252 static int 253 ns8250_probe(struct uart_bas *bas) 254 { 255 u_char val; 256 257 /* Check known 0 bits that don't depend on DLAB. */ 258 val = uart_getreg(bas, REG_IIR); 259 if (val & 0x30) 260 return (ENXIO); 261 /* 262 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 263 * chip, but otherwise doesn't seem to have a function. In 264 * other words, uart(4) works regardless. Ignore that bit so 265 * the probe succeeds. 266 */ 267 val = uart_getreg(bas, REG_MCR); 268 if (val & 0xa0) 269 return (ENXIO); 270 271 return (0); 272 } 273 274 static void 275 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 276 int parity) 277 { 278 u_char ier; 279 280 if (bas->rclk == 0) 281 bas->rclk = DEFAULT_RCLK; 282 ns8250_param(bas, baudrate, databits, stopbits, parity); 283 284 /* Disable all interrupt sources. */ 285 /* 286 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 287 * UARTs split the receive time-out interrupt bit out separately as 288 * 0x10. This gets handled by ier_mask and ier_rxbits below. 289 */ 290 ier = uart_getreg(bas, REG_IER) & 0xe0; 291 uart_setreg(bas, REG_IER, ier); 292 uart_barrier(bas); 293 294 /* Disable the FIFO (if present). */ 295 uart_setreg(bas, REG_FCR, 0); 296 uart_barrier(bas); 297 298 /* Set RTS & DTR. */ 299 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 300 uart_barrier(bas); 301 302 ns8250_clrint(bas); 303 } 304 305 static void 306 ns8250_term(struct uart_bas *bas) 307 { 308 309 /* Clear RTS & DTR. */ 310 uart_setreg(bas, REG_MCR, MCR_IE); 311 uart_barrier(bas); 312 } 313 314 static void 315 ns8250_putc(struct uart_bas *bas, int c) 316 { 317 int limit; 318 319 limit = 250000; 320 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 321 DELAY(4); 322 uart_setreg(bas, REG_DATA, c); 323 uart_barrier(bas); 324 limit = 250000; 325 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 326 DELAY(4); 327 } 328 329 static int 330 ns8250_rxready(struct uart_bas *bas) 331 { 332 333 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 334 } 335 336 static int 337 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 338 { 339 int c; 340 341 uart_lock(hwmtx); 342 343 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344 uart_unlock(hwmtx); 345 DELAY(4); 346 uart_lock(hwmtx); 347 } 348 349 c = uart_getreg(bas, REG_DATA); 350 351 uart_unlock(hwmtx); 352 353 return (c); 354 } 355 356 static kobj_method_t ns8250_methods[] = { 357 KOBJMETHOD(uart_attach, ns8250_bus_attach), 358 KOBJMETHOD(uart_detach, ns8250_bus_detach), 359 KOBJMETHOD(uart_flush, ns8250_bus_flush), 360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 363 KOBJMETHOD(uart_param, ns8250_bus_param), 364 KOBJMETHOD(uart_probe, ns8250_bus_probe), 365 KOBJMETHOD(uart_receive, ns8250_bus_receive), 366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 368 { 0, 0 } 369 }; 370 371 struct uart_class uart_ns8250_class = { 372 "ns8250", 373 ns8250_methods, 374 sizeof(struct ns8250_softc), 375 .uc_ops = &uart_ns8250_ops, 376 .uc_range = 8, 377 .uc_rclk = DEFAULT_RCLK 378 }; 379 380 #define SIGCHG(c, i, s, d) \ 381 if (c) { \ 382 i |= (i & s) ? s : s | d; \ 383 } else { \ 384 i = (i & s) ? (i & ~s) | d : i; \ 385 } 386 387 int 388 ns8250_bus_attach(struct uart_softc *sc) 389 { 390 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 391 struct uart_bas *bas; 392 unsigned int ivar; 393 #ifdef FDT 394 phandle_t node; 395 pcell_t cell; 396 #endif 397 398 ns8250->busy_detect = 0; 399 400 #ifdef FDT 401 /* 402 * Check whether uart requires to read USR reg when IIR_BUSY and 403 * has broken txfifo. 404 */ 405 node = ofw_bus_get_node(sc->sc_dev); 406 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 407 ns8250->busy_detect = 1; 408 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 409 broken_txfifo = 1; 410 #endif 411 412 bas = &sc->sc_bas; 413 414 ns8250->mcr = uart_getreg(bas, REG_MCR); 415 ns8250->fcr = FCR_ENABLE; 416 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 417 &ivar)) { 418 if (UART_FLAGS_FCR_RX_LOW(ivar)) 419 ns8250->fcr |= FCR_RX_LOW; 420 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 421 ns8250->fcr |= FCR_RX_MEDL; 422 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 423 ns8250->fcr |= FCR_RX_HIGH; 424 else 425 ns8250->fcr |= FCR_RX_MEDH; 426 } else 427 ns8250->fcr |= FCR_RX_MEDH; 428 429 /* Get IER mask */ 430 ivar = 0xf0; 431 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 432 &ivar); 433 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 434 435 /* Get IER RX interrupt bits */ 436 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 437 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 438 &ivar); 439 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 440 441 uart_setreg(bas, REG_FCR, ns8250->fcr); 442 uart_barrier(bas); 443 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 444 445 if (ns8250->mcr & MCR_DTR) 446 sc->sc_hwsig |= SER_DTR; 447 if (ns8250->mcr & MCR_RTS) 448 sc->sc_hwsig |= SER_RTS; 449 ns8250_bus_getsig(sc); 450 451 ns8250_clrint(bas); 452 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 453 ns8250->ier |= ns8250->ier_rxbits; 454 uart_setreg(bas, REG_IER, ns8250->ier); 455 uart_barrier(bas); 456 457 return (0); 458 } 459 460 int 461 ns8250_bus_detach(struct uart_softc *sc) 462 { 463 struct ns8250_softc *ns8250; 464 struct uart_bas *bas; 465 u_char ier; 466 467 ns8250 = (struct ns8250_softc *)sc; 468 bas = &sc->sc_bas; 469 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 470 uart_setreg(bas, REG_IER, ier); 471 uart_barrier(bas); 472 ns8250_clrint(bas); 473 return (0); 474 } 475 476 int 477 ns8250_bus_flush(struct uart_softc *sc, int what) 478 { 479 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 480 struct uart_bas *bas; 481 int error; 482 483 bas = &sc->sc_bas; 484 uart_lock(sc->sc_hwmtx); 485 if (sc->sc_rxfifosz > 1) { 486 ns8250_flush(bas, what); 487 uart_setreg(bas, REG_FCR, ns8250->fcr); 488 uart_barrier(bas); 489 error = 0; 490 } else 491 error = ns8250_drain(bas, what); 492 uart_unlock(sc->sc_hwmtx); 493 return (error); 494 } 495 496 int 497 ns8250_bus_getsig(struct uart_softc *sc) 498 { 499 uint32_t new, old, sig; 500 uint8_t msr; 501 502 do { 503 old = sc->sc_hwsig; 504 sig = old; 505 uart_lock(sc->sc_hwmtx); 506 msr = uart_getreg(&sc->sc_bas, REG_MSR); 507 uart_unlock(sc->sc_hwmtx); 508 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 509 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 510 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 511 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 512 new = sig & ~SER_MASK_DELTA; 513 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 514 return (sig); 515 } 516 517 int 518 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 519 { 520 struct uart_bas *bas; 521 int baudrate, divisor, error; 522 uint8_t efr, lcr; 523 524 bas = &sc->sc_bas; 525 error = 0; 526 uart_lock(sc->sc_hwmtx); 527 switch (request) { 528 case UART_IOCTL_BREAK: 529 lcr = uart_getreg(bas, REG_LCR); 530 if (data) 531 lcr |= LCR_SBREAK; 532 else 533 lcr &= ~LCR_SBREAK; 534 uart_setreg(bas, REG_LCR, lcr); 535 uart_barrier(bas); 536 break; 537 case UART_IOCTL_IFLOW: 538 lcr = uart_getreg(bas, REG_LCR); 539 uart_barrier(bas); 540 uart_setreg(bas, REG_LCR, 0xbf); 541 uart_barrier(bas); 542 efr = uart_getreg(bas, REG_EFR); 543 if (data) 544 efr |= EFR_RTS; 545 else 546 efr &= ~EFR_RTS; 547 uart_setreg(bas, REG_EFR, efr); 548 uart_barrier(bas); 549 uart_setreg(bas, REG_LCR, lcr); 550 uart_barrier(bas); 551 break; 552 case UART_IOCTL_OFLOW: 553 lcr = uart_getreg(bas, REG_LCR); 554 uart_barrier(bas); 555 uart_setreg(bas, REG_LCR, 0xbf); 556 uart_barrier(bas); 557 efr = uart_getreg(bas, REG_EFR); 558 if (data) 559 efr |= EFR_CTS; 560 else 561 efr &= ~EFR_CTS; 562 uart_setreg(bas, REG_EFR, efr); 563 uart_barrier(bas); 564 uart_setreg(bas, REG_LCR, lcr); 565 uart_barrier(bas); 566 break; 567 case UART_IOCTL_BAUD: 568 lcr = uart_getreg(bas, REG_LCR); 569 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 570 uart_barrier(bas); 571 divisor = uart_getreg(bas, REG_DLL) | 572 (uart_getreg(bas, REG_DLH) << 8); 573 uart_barrier(bas); 574 uart_setreg(bas, REG_LCR, lcr); 575 uart_barrier(bas); 576 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 577 if (baudrate > 0) 578 *(int*)data = baudrate; 579 else 580 error = ENXIO; 581 break; 582 default: 583 error = EINVAL; 584 break; 585 } 586 uart_unlock(sc->sc_hwmtx); 587 return (error); 588 } 589 590 int 591 ns8250_bus_ipend(struct uart_softc *sc) 592 { 593 struct uart_bas *bas; 594 struct ns8250_softc *ns8250; 595 int ipend; 596 uint8_t iir, lsr; 597 598 ns8250 = (struct ns8250_softc *)sc; 599 bas = &sc->sc_bas; 600 uart_lock(sc->sc_hwmtx); 601 iir = uart_getreg(bas, REG_IIR); 602 603 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 604 (void)uart_getreg(bas, DW_REG_USR); 605 uart_unlock(sc->sc_hwmtx); 606 return (0); 607 } 608 if (iir & IIR_NOPEND) { 609 uart_unlock(sc->sc_hwmtx); 610 return (0); 611 } 612 ipend = 0; 613 if (iir & IIR_RXRDY) { 614 lsr = uart_getreg(bas, REG_LSR); 615 if (lsr & LSR_OE) 616 ipend |= SER_INT_OVERRUN; 617 if (lsr & LSR_BI) 618 ipend |= SER_INT_BREAK; 619 if (lsr & LSR_RXRDY) 620 ipend |= SER_INT_RXREADY; 621 } else { 622 if (iir & IIR_TXRDY) { 623 ipend |= SER_INT_TXIDLE; 624 uart_setreg(bas, REG_IER, ns8250->ier); 625 } else 626 ipend |= SER_INT_SIGCHG; 627 } 628 if (ipend == 0) 629 ns8250_clrint(bas); 630 uart_unlock(sc->sc_hwmtx); 631 return (ipend); 632 } 633 634 int 635 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 636 int stopbits, int parity) 637 { 638 struct uart_bas *bas; 639 int error; 640 641 bas = &sc->sc_bas; 642 uart_lock(sc->sc_hwmtx); 643 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 644 uart_unlock(sc->sc_hwmtx); 645 return (error); 646 } 647 648 int 649 ns8250_bus_probe(struct uart_softc *sc) 650 { 651 struct ns8250_softc *ns8250; 652 struct uart_bas *bas; 653 int count, delay, error, limit; 654 uint8_t lsr, mcr, ier; 655 656 ns8250 = (struct ns8250_softc *)sc; 657 bas = &sc->sc_bas; 658 659 error = ns8250_probe(bas); 660 if (error) 661 return (error); 662 663 mcr = MCR_IE; 664 if (sc->sc_sysdev == NULL) { 665 /* By using ns8250_init() we also set DTR and RTS. */ 666 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 667 } else 668 mcr |= MCR_DTR | MCR_RTS; 669 670 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 671 if (error) 672 return (error); 673 674 /* 675 * Set loopback mode. This avoids having garbage on the wire and 676 * also allows us send and receive data. We set DTR and RTS to 677 * avoid the possibility that automatic flow-control prevents 678 * any data from being sent. 679 */ 680 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 681 uart_barrier(bas); 682 683 /* 684 * Enable FIFOs. And check that the UART has them. If not, we're 685 * done. Since this is the first time we enable the FIFOs, we reset 686 * them. 687 */ 688 uart_setreg(bas, REG_FCR, FCR_ENABLE); 689 uart_barrier(bas); 690 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 691 /* 692 * NS16450 or INS8250. We don't bother to differentiate 693 * between them. They're too old to be interesting. 694 */ 695 uart_setreg(bas, REG_MCR, mcr); 696 uart_barrier(bas); 697 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 698 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 699 return (0); 700 } 701 702 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 703 uart_barrier(bas); 704 705 count = 0; 706 delay = ns8250_delay(bas); 707 708 /* We have FIFOs. Drain the transmitter and receiver. */ 709 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 710 if (error) { 711 uart_setreg(bas, REG_MCR, mcr); 712 uart_setreg(bas, REG_FCR, 0); 713 uart_barrier(bas); 714 goto describe; 715 } 716 717 /* 718 * We should have a sufficiently clean "pipe" to determine the 719 * size of the FIFOs. We send as much characters as is reasonable 720 * and wait for the overflow bit in the LSR register to be 721 * asserted, counting the characters as we send them. Based on 722 * that count we know the FIFO size. 723 */ 724 do { 725 uart_setreg(bas, REG_DATA, 0); 726 uart_barrier(bas); 727 count++; 728 729 limit = 30; 730 lsr = 0; 731 /* 732 * LSR bits are cleared upon read, so we must accumulate 733 * them to be able to test LSR_OE below. 734 */ 735 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 736 --limit) 737 DELAY(delay); 738 if (limit == 0) { 739 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 740 uart_setreg(bas, REG_IER, ier); 741 uart_setreg(bas, REG_MCR, mcr); 742 uart_setreg(bas, REG_FCR, 0); 743 uart_barrier(bas); 744 count = 0; 745 goto describe; 746 } 747 } while ((lsr & LSR_OE) == 0 && count < 130); 748 count--; 749 750 uart_setreg(bas, REG_MCR, mcr); 751 752 /* Reset FIFOs. */ 753 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 754 755 describe: 756 if (count >= 14 && count <= 16) { 757 sc->sc_rxfifosz = 16; 758 device_set_desc(sc->sc_dev, "16550 or compatible"); 759 } else if (count >= 28 && count <= 32) { 760 sc->sc_rxfifosz = 32; 761 device_set_desc(sc->sc_dev, "16650 or compatible"); 762 } else if (count >= 56 && count <= 64) { 763 sc->sc_rxfifosz = 64; 764 device_set_desc(sc->sc_dev, "16750 or compatible"); 765 } else if (count >= 112 && count <= 128) { 766 sc->sc_rxfifosz = 128; 767 device_set_desc(sc->sc_dev, "16950 or compatible"); 768 } else { 769 sc->sc_rxfifosz = 16; 770 device_set_desc(sc->sc_dev, 771 "Non-standard ns8250 class UART with FIFOs"); 772 } 773 774 /* 775 * Force the Tx FIFO size to 16 bytes for now. We don't program the 776 * Tx trigger. Also, we assume that all data has been sent when the 777 * interrupt happens. 778 */ 779 sc->sc_txfifosz = 16; 780 781 #if 0 782 /* 783 * XXX there are some issues related to hardware flow control and 784 * it's likely that uart(4) is the cause. This basicly needs more 785 * investigation, but we avoid using for hardware flow control 786 * until then. 787 */ 788 /* 16650s or higher have automatic flow control. */ 789 if (sc->sc_rxfifosz > 16) { 790 sc->sc_hwiflow = 1; 791 sc->sc_hwoflow = 1; 792 } 793 #endif 794 795 return (0); 796 } 797 798 int 799 ns8250_bus_receive(struct uart_softc *sc) 800 { 801 struct uart_bas *bas; 802 int xc; 803 uint8_t lsr; 804 805 bas = &sc->sc_bas; 806 uart_lock(sc->sc_hwmtx); 807 lsr = uart_getreg(bas, REG_LSR); 808 while (lsr & LSR_RXRDY) { 809 if (uart_rx_full(sc)) { 810 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 811 break; 812 } 813 xc = uart_getreg(bas, REG_DATA); 814 if (lsr & LSR_FE) 815 xc |= UART_STAT_FRAMERR; 816 if (lsr & LSR_PE) 817 xc |= UART_STAT_PARERR; 818 uart_rx_put(sc, xc); 819 lsr = uart_getreg(bas, REG_LSR); 820 } 821 /* Discard everything left in the Rx FIFO. */ 822 while (lsr & LSR_RXRDY) { 823 (void)uart_getreg(bas, REG_DATA); 824 uart_barrier(bas); 825 lsr = uart_getreg(bas, REG_LSR); 826 } 827 uart_unlock(sc->sc_hwmtx); 828 return (0); 829 } 830 831 int 832 ns8250_bus_setsig(struct uart_softc *sc, int sig) 833 { 834 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 835 struct uart_bas *bas; 836 uint32_t new, old; 837 838 bas = &sc->sc_bas; 839 do { 840 old = sc->sc_hwsig; 841 new = old; 842 if (sig & SER_DDTR) { 843 SIGCHG(sig & SER_DTR, new, SER_DTR, 844 SER_DDTR); 845 } 846 if (sig & SER_DRTS) { 847 SIGCHG(sig & SER_RTS, new, SER_RTS, 848 SER_DRTS); 849 } 850 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 851 uart_lock(sc->sc_hwmtx); 852 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 853 if (new & SER_DTR) 854 ns8250->mcr |= MCR_DTR; 855 if (new & SER_RTS) 856 ns8250->mcr |= MCR_RTS; 857 uart_setreg(bas, REG_MCR, ns8250->mcr); 858 uart_barrier(bas); 859 uart_unlock(sc->sc_hwmtx); 860 return (0); 861 } 862 863 int 864 ns8250_bus_transmit(struct uart_softc *sc) 865 { 866 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 867 struct uart_bas *bas; 868 int i; 869 870 bas = &sc->sc_bas; 871 uart_lock(sc->sc_hwmtx); 872 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 873 ; 874 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 875 uart_barrier(bas); 876 for (i = 0; i < sc->sc_txdatasz; i++) { 877 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 878 uart_barrier(bas); 879 } 880 if (broken_txfifo) 881 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 882 else 883 sc->sc_txbusy = 1; 884 uart_unlock(sc->sc_hwmtx); 885 if (broken_txfifo) 886 uart_sched_softih(sc, SER_INT_TXIDLE); 887 return (0); 888 } 889