1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #endif 49 50 #include <dev/uart/uart.h> 51 #include <dev/uart/uart_cpu.h> 52 #ifdef FDT 53 #include <dev/uart/uart_cpu_fdt.h> 54 #endif 55 #include <dev/uart/uart_bus.h> 56 #include <dev/uart/uart_dev_ns8250.h> 57 #include <dev/uart/uart_ppstypes.h> 58 #ifdef DEV_ACPI 59 #include <dev/uart/uart_cpu_acpi.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #endif 62 63 #include <dev/ic/ns16550.h> 64 65 #include "uart_if.h" 66 67 #define DEFAULT_RCLK 1843200 68 69 /* 70 * Set the default baudrate tolerance to 3.0%. 71 * 72 * Some embedded boards have odd reference clocks (eg 25MHz) 73 * and we need to handle higher variances in the target baud rate. 74 */ 75 #ifndef UART_DEV_TOLERANCE_PCT 76 #define UART_DEV_TOLERANCE_PCT 30 77 #endif /* UART_DEV_TOLERANCE_PCT */ 78 79 static int broken_txfifo = 0; 80 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 81 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 82 83 /* 84 * Clear pending interrupts. THRE is cleared by reading IIR. Data 85 * that may have been received gets lost here. 86 */ 87 static void 88 ns8250_clrint(struct uart_bas *bas) 89 { 90 uint8_t iir, lsr; 91 92 iir = uart_getreg(bas, REG_IIR); 93 while ((iir & IIR_NOPEND) == 0) { 94 iir &= IIR_IMASK; 95 if (iir == IIR_RLS) { 96 lsr = uart_getreg(bas, REG_LSR); 97 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 98 (void)uart_getreg(bas, REG_DATA); 99 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 100 (void)uart_getreg(bas, REG_DATA); 101 else if (iir == IIR_MLSC) 102 (void)uart_getreg(bas, REG_MSR); 103 uart_barrier(bas); 104 iir = uart_getreg(bas, REG_IIR); 105 } 106 } 107 108 static int 109 ns8250_delay(struct uart_bas *bas) 110 { 111 int divisor; 112 u_char lcr; 113 114 lcr = uart_getreg(bas, REG_LCR); 115 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 116 uart_barrier(bas); 117 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 118 uart_barrier(bas); 119 uart_setreg(bas, REG_LCR, lcr); 120 uart_barrier(bas); 121 122 /* 1/10th the time to transmit 1 character (estimate). */ 123 if (divisor <= 134) 124 return (16000000 * divisor / bas->rclk); 125 return (16000 * divisor / (bas->rclk / 1000)); 126 } 127 128 static int 129 ns8250_divisor(int rclk, int baudrate) 130 { 131 int actual_baud, divisor; 132 int error; 133 134 if (baudrate == 0) 135 return (0); 136 137 divisor = (rclk / (baudrate << 3) + 1) >> 1; 138 if (divisor == 0 || divisor >= 65536) 139 return (0); 140 actual_baud = rclk / (divisor << 4); 141 142 /* 10 times error in percent: */ 143 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 144 145 /* enforce maximum error tolerance: */ 146 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 147 return (0); 148 149 return (divisor); 150 } 151 152 static int 153 ns8250_drain(struct uart_bas *bas, int what) 154 { 155 int delay, limit; 156 157 delay = ns8250_delay(bas); 158 159 if (what & UART_DRAIN_TRANSMITTER) { 160 /* 161 * Pick an arbitrary high limit to avoid getting stuck in 162 * an infinite loop when the hardware is broken. Make the 163 * limit high enough to handle large FIFOs. 164 */ 165 limit = 10*1024; 166 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 167 DELAY(delay); 168 if (limit == 0) { 169 /* printf("ns8250: transmitter appears stuck... "); */ 170 return (EIO); 171 } 172 } 173 174 if (what & UART_DRAIN_RECEIVER) { 175 /* 176 * Pick an arbitrary high limit to avoid getting stuck in 177 * an infinite loop when the hardware is broken. Make the 178 * limit high enough to handle large FIFOs and integrated 179 * UARTs. The HP rx2600 for example has 3 UARTs on the 180 * management board that tend to get a lot of data send 181 * to it when the UART is first activated. 182 */ 183 limit=10*4096; 184 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 185 (void)uart_getreg(bas, REG_DATA); 186 uart_barrier(bas); 187 DELAY(delay << 2); 188 } 189 if (limit == 0) { 190 /* printf("ns8250: receiver appears broken... "); */ 191 return (EIO); 192 } 193 } 194 195 return (0); 196 } 197 198 /* 199 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 200 * drained. WARNING: this function clobbers the FIFO setting! 201 */ 202 static void 203 ns8250_flush(struct uart_bas *bas, int what) 204 { 205 uint8_t fcr; 206 207 fcr = FCR_ENABLE; 208 #ifdef CPU_XBURST 209 fcr |= FCR_UART_ON; 210 #endif 211 if (what & UART_FLUSH_TRANSMITTER) 212 fcr |= FCR_XMT_RST; 213 if (what & UART_FLUSH_RECEIVER) 214 fcr |= FCR_RCV_RST; 215 uart_setreg(bas, REG_FCR, fcr); 216 uart_barrier(bas); 217 } 218 219 static int 220 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 221 int parity) 222 { 223 int divisor; 224 uint8_t lcr; 225 226 lcr = 0; 227 if (databits >= 8) 228 lcr |= LCR_8BITS; 229 else if (databits == 7) 230 lcr |= LCR_7BITS; 231 else if (databits == 6) 232 lcr |= LCR_6BITS; 233 else 234 lcr |= LCR_5BITS; 235 if (stopbits > 1) 236 lcr |= LCR_STOPB; 237 lcr |= parity << 3; 238 239 /* Set baudrate. */ 240 if (baudrate > 0) { 241 divisor = ns8250_divisor(bas->rclk, baudrate); 242 if (divisor == 0) 243 return (EINVAL); 244 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 245 uart_barrier(bas); 246 uart_setreg(bas, REG_DLL, divisor & 0xff); 247 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 248 uart_barrier(bas); 249 } 250 251 /* Set LCR and clear DLAB. */ 252 uart_setreg(bas, REG_LCR, lcr); 253 uart_barrier(bas); 254 return (0); 255 } 256 257 /* 258 * Low-level UART interface. 259 */ 260 static int ns8250_probe(struct uart_bas *bas); 261 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 262 static void ns8250_term(struct uart_bas *bas); 263 static void ns8250_putc(struct uart_bas *bas, int); 264 static int ns8250_rxready(struct uart_bas *bas); 265 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 266 267 struct uart_ops uart_ns8250_ops = { 268 .probe = ns8250_probe, 269 .init = ns8250_init, 270 .term = ns8250_term, 271 .putc = ns8250_putc, 272 .rxready = ns8250_rxready, 273 .getc = ns8250_getc, 274 }; 275 276 static int 277 ns8250_probe(struct uart_bas *bas) 278 { 279 u_char val; 280 281 #ifdef CPU_XBURST 282 uart_setreg(bas, REG_FCR, FCR_UART_ON); 283 #endif 284 285 /* Check known 0 bits that don't depend on DLAB. */ 286 val = uart_getreg(bas, REG_IIR); 287 if (val & 0x30) 288 return (ENXIO); 289 /* 290 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 291 * chip, but otherwise doesn't seem to have a function. In 292 * other words, uart(4) works regardless. Ignore that bit so 293 * the probe succeeds. 294 */ 295 val = uart_getreg(bas, REG_MCR); 296 if (val & 0xa0) 297 return (ENXIO); 298 299 return (0); 300 } 301 302 static void 303 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 304 int parity) 305 { 306 u_char ier, val; 307 308 if (bas->rclk == 0) 309 bas->rclk = DEFAULT_RCLK; 310 ns8250_param(bas, baudrate, databits, stopbits, parity); 311 312 /* Disable all interrupt sources. */ 313 /* 314 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 315 * UARTs split the receive time-out interrupt bit out separately as 316 * 0x10. This gets handled by ier_mask and ier_rxbits below. 317 */ 318 ier = uart_getreg(bas, REG_IER) & 0xe0; 319 uart_setreg(bas, REG_IER, ier); 320 uart_barrier(bas); 321 322 /* Disable the FIFO (if present). */ 323 val = 0; 324 #ifdef CPU_XBURST 325 val |= FCR_UART_ON; 326 #endif 327 uart_setreg(bas, REG_FCR, val); 328 uart_barrier(bas); 329 330 /* Set RTS & DTR. */ 331 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 332 uart_barrier(bas); 333 334 ns8250_clrint(bas); 335 } 336 337 static void 338 ns8250_term(struct uart_bas *bas) 339 { 340 341 /* Clear RTS & DTR. */ 342 uart_setreg(bas, REG_MCR, MCR_IE); 343 uart_barrier(bas); 344 } 345 346 static void 347 ns8250_putc(struct uart_bas *bas, int c) 348 { 349 int limit; 350 351 limit = 250000; 352 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 353 DELAY(4); 354 uart_setreg(bas, REG_DATA, c); 355 uart_barrier(bas); 356 } 357 358 static int 359 ns8250_rxready(struct uart_bas *bas) 360 { 361 362 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 363 } 364 365 static int 366 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 367 { 368 int c; 369 370 uart_lock(hwmtx); 371 372 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 373 uart_unlock(hwmtx); 374 DELAY(4); 375 uart_lock(hwmtx); 376 } 377 378 c = uart_getreg(bas, REG_DATA); 379 380 uart_unlock(hwmtx); 381 382 return (c); 383 } 384 385 static kobj_method_t ns8250_methods[] = { 386 KOBJMETHOD(uart_attach, ns8250_bus_attach), 387 KOBJMETHOD(uart_detach, ns8250_bus_detach), 388 KOBJMETHOD(uart_flush, ns8250_bus_flush), 389 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 390 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 391 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 392 KOBJMETHOD(uart_param, ns8250_bus_param), 393 KOBJMETHOD(uart_probe, ns8250_bus_probe), 394 KOBJMETHOD(uart_receive, ns8250_bus_receive), 395 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 396 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 397 KOBJMETHOD(uart_grab, ns8250_bus_grab), 398 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 399 { 0, 0 } 400 }; 401 402 struct uart_class uart_ns8250_class = { 403 "ns8250", 404 ns8250_methods, 405 sizeof(struct ns8250_softc), 406 .uc_ops = &uart_ns8250_ops, 407 .uc_range = 8, 408 .uc_rclk = DEFAULT_RCLK, 409 .uc_rshift = 0 410 }; 411 412 /* 413 * XXX -- refactor out ACPI and FDT ifdefs 414 */ 415 #ifdef DEV_ACPI 416 static struct acpi_uart_compat_data acpi_compat_data[] = { 417 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 418 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 419 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 420 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 421 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 422 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 423 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 424 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 425 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 426 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 427 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 428 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 429 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 430 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 431 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 432 }; 433 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 434 #endif 435 436 #ifdef FDT 437 static struct ofw_compat_data compat_data[] = { 438 {"ns16550", (uintptr_t)&uart_ns8250_class}, 439 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 440 {NULL, (uintptr_t)NULL}, 441 }; 442 UART_FDT_CLASS_AND_DEVICE(compat_data); 443 #endif 444 445 /* Use token-pasting to form SER_ and MSR_ named constants. */ 446 #define SER(sig) SER_##sig 447 #define SERD(sig) SER_D##sig 448 #define MSR(sig) MSR_##sig 449 #define MSRD(sig) MSR_D##sig 450 451 /* 452 * Detect signal changes using software delta detection. The previous state of 453 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 454 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 455 * new state of both the signal and the delta bits. 456 */ 457 #define SIGCHGSW(var, msr, sig) \ 458 if ((msr) & MSR(sig)) { \ 459 if ((var & SER(sig)) == 0) \ 460 var |= SERD(sig) | SER(sig); \ 461 } else { \ 462 if ((var & SER(sig)) != 0) \ 463 var = SERD(sig) | (var & ~SER(sig)); \ 464 } 465 466 /* 467 * Detect signal changes using the hardware msr delta bits. This is currently 468 * used only when PPS timing information is being captured using the "narrow 469 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 470 * by time the interrupt handler is invoked. The hardware will latch the fact 471 * that it changed in the delta bits. 472 */ 473 #define SIGCHGHW(var, msr, sig) \ 474 if ((msr) & MSRD(sig)) { \ 475 if (((msr) & MSR(sig)) != 0) \ 476 var |= SERD(sig) | SER(sig); \ 477 else \ 478 var = SERD(sig) | (var & ~SER(sig)); \ 479 } 480 481 int 482 ns8250_bus_attach(struct uart_softc *sc) 483 { 484 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 485 struct uart_bas *bas; 486 unsigned int ivar; 487 #ifdef FDT 488 phandle_t node; 489 pcell_t cell; 490 #endif 491 492 #ifdef FDT 493 /* Check whether uart has a broken txfifo. */ 494 node = ofw_bus_get_node(sc->sc_dev); 495 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 496 broken_txfifo = cell ? 1 : 0; 497 #endif 498 499 bas = &sc->sc_bas; 500 501 ns8250->busy_detect = bas->busy_detect; 502 ns8250->mcr = uart_getreg(bas, REG_MCR); 503 ns8250->fcr = FCR_ENABLE; 504 #ifdef CPU_XBURST 505 ns8250->fcr |= FCR_UART_ON; 506 #endif 507 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 508 &ivar)) { 509 if (UART_FLAGS_FCR_RX_LOW(ivar)) 510 ns8250->fcr |= FCR_RX_LOW; 511 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 512 ns8250->fcr |= FCR_RX_MEDL; 513 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 514 ns8250->fcr |= FCR_RX_HIGH; 515 else 516 ns8250->fcr |= FCR_RX_MEDH; 517 } else 518 ns8250->fcr |= FCR_RX_MEDH; 519 520 /* Get IER mask */ 521 ivar = 0xf0; 522 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 523 &ivar); 524 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 525 526 /* Get IER RX interrupt bits */ 527 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 528 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 529 &ivar); 530 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 531 532 uart_setreg(bas, REG_FCR, ns8250->fcr); 533 uart_barrier(bas); 534 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 535 536 if (ns8250->mcr & MCR_DTR) 537 sc->sc_hwsig |= SER_DTR; 538 if (ns8250->mcr & MCR_RTS) 539 sc->sc_hwsig |= SER_RTS; 540 ns8250_bus_getsig(sc); 541 542 ns8250_clrint(bas); 543 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 544 ns8250->ier |= ns8250->ier_rxbits; 545 uart_setreg(bas, REG_IER, ns8250->ier); 546 uart_barrier(bas); 547 548 /* 549 * Timing of the H/W access was changed with r253161 of uart_core.c 550 * It has been observed that an ITE IT8513E would signal a break 551 * condition with pretty much every character it received, unless 552 * it had enough time to settle between ns8250_bus_attach() and 553 * ns8250_bus_ipend() -- which it accidentally had before r253161. 554 * It's not understood why the UART chip behaves this way and it 555 * could very well be that the DELAY make the H/W work in the same 556 * accidental manner as before. More analysis is warranted, but 557 * at least now we fixed a known regression. 558 */ 559 DELAY(200); 560 return (0); 561 } 562 563 int 564 ns8250_bus_detach(struct uart_softc *sc) 565 { 566 struct ns8250_softc *ns8250; 567 struct uart_bas *bas; 568 u_char ier; 569 570 ns8250 = (struct ns8250_softc *)sc; 571 bas = &sc->sc_bas; 572 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 573 uart_setreg(bas, REG_IER, ier); 574 uart_barrier(bas); 575 ns8250_clrint(bas); 576 return (0); 577 } 578 579 int 580 ns8250_bus_flush(struct uart_softc *sc, int what) 581 { 582 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 583 struct uart_bas *bas; 584 int error; 585 586 bas = &sc->sc_bas; 587 uart_lock(sc->sc_hwmtx); 588 if (sc->sc_rxfifosz > 1) { 589 ns8250_flush(bas, what); 590 uart_setreg(bas, REG_FCR, ns8250->fcr); 591 uart_barrier(bas); 592 error = 0; 593 } else 594 error = ns8250_drain(bas, what); 595 uart_unlock(sc->sc_hwmtx); 596 return (error); 597 } 598 599 int 600 ns8250_bus_getsig(struct uart_softc *sc) 601 { 602 uint32_t old, sig; 603 uint8_t msr; 604 605 /* 606 * The delta bits are reputed to be broken on some hardware, so use 607 * software delta detection by default. Use the hardware delta bits 608 * when capturing PPS pulses which are too narrow for software detection 609 * to see the edges. Hardware delta for RI doesn't work like the 610 * others, so always use software for it. Other threads may be changing 611 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 612 * update without other changes happening. Note that the SIGCHGxx() 613 * macros carefully preserve the delta bits when we have to loop several 614 * times and a signal transitions between iterations. 615 */ 616 do { 617 old = sc->sc_hwsig; 618 sig = old; 619 uart_lock(sc->sc_hwmtx); 620 msr = uart_getreg(&sc->sc_bas, REG_MSR); 621 uart_unlock(sc->sc_hwmtx); 622 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 623 SIGCHGHW(sig, msr, DSR); 624 SIGCHGHW(sig, msr, CTS); 625 SIGCHGHW(sig, msr, DCD); 626 } else { 627 SIGCHGSW(sig, msr, DSR); 628 SIGCHGSW(sig, msr, CTS); 629 SIGCHGSW(sig, msr, DCD); 630 } 631 SIGCHGSW(sig, msr, RI); 632 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 633 return (sig); 634 } 635 636 int 637 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 638 { 639 struct uart_bas *bas; 640 int baudrate, divisor, error; 641 uint8_t efr, lcr; 642 643 bas = &sc->sc_bas; 644 error = 0; 645 uart_lock(sc->sc_hwmtx); 646 switch (request) { 647 case UART_IOCTL_BREAK: 648 lcr = uart_getreg(bas, REG_LCR); 649 if (data) 650 lcr |= LCR_SBREAK; 651 else 652 lcr &= ~LCR_SBREAK; 653 uart_setreg(bas, REG_LCR, lcr); 654 uart_barrier(bas); 655 break; 656 case UART_IOCTL_IFLOW: 657 lcr = uart_getreg(bas, REG_LCR); 658 uart_barrier(bas); 659 uart_setreg(bas, REG_LCR, 0xbf); 660 uart_barrier(bas); 661 efr = uart_getreg(bas, REG_EFR); 662 if (data) 663 efr |= EFR_RTS; 664 else 665 efr &= ~EFR_RTS; 666 uart_setreg(bas, REG_EFR, efr); 667 uart_barrier(bas); 668 uart_setreg(bas, REG_LCR, lcr); 669 uart_barrier(bas); 670 break; 671 case UART_IOCTL_OFLOW: 672 lcr = uart_getreg(bas, REG_LCR); 673 uart_barrier(bas); 674 uart_setreg(bas, REG_LCR, 0xbf); 675 uart_barrier(bas); 676 efr = uart_getreg(bas, REG_EFR); 677 if (data) 678 efr |= EFR_CTS; 679 else 680 efr &= ~EFR_CTS; 681 uart_setreg(bas, REG_EFR, efr); 682 uart_barrier(bas); 683 uart_setreg(bas, REG_LCR, lcr); 684 uart_barrier(bas); 685 break; 686 case UART_IOCTL_BAUD: 687 lcr = uart_getreg(bas, REG_LCR); 688 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 689 uart_barrier(bas); 690 divisor = uart_getreg(bas, REG_DLL) | 691 (uart_getreg(bas, REG_DLH) << 8); 692 uart_barrier(bas); 693 uart_setreg(bas, REG_LCR, lcr); 694 uart_barrier(bas); 695 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 696 if (baudrate > 0) 697 *(int*)data = baudrate; 698 else 699 error = ENXIO; 700 break; 701 default: 702 error = EINVAL; 703 break; 704 } 705 uart_unlock(sc->sc_hwmtx); 706 return (error); 707 } 708 709 int 710 ns8250_bus_ipend(struct uart_softc *sc) 711 { 712 struct uart_bas *bas; 713 struct ns8250_softc *ns8250; 714 int ipend; 715 uint8_t iir, lsr; 716 717 ns8250 = (struct ns8250_softc *)sc; 718 bas = &sc->sc_bas; 719 uart_lock(sc->sc_hwmtx); 720 iir = uart_getreg(bas, REG_IIR); 721 722 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 723 (void)uart_getreg(bas, DW_REG_USR); 724 uart_unlock(sc->sc_hwmtx); 725 return (0); 726 } 727 if (iir & IIR_NOPEND) { 728 uart_unlock(sc->sc_hwmtx); 729 return (0); 730 } 731 ipend = 0; 732 if (iir & IIR_RXRDY) { 733 lsr = uart_getreg(bas, REG_LSR); 734 if (lsr & LSR_OE) 735 ipend |= SER_INT_OVERRUN; 736 if (lsr & LSR_BI) 737 ipend |= SER_INT_BREAK; 738 if (lsr & LSR_RXRDY) 739 ipend |= SER_INT_RXREADY; 740 } else { 741 if (iir & IIR_TXRDY) { 742 ipend |= SER_INT_TXIDLE; 743 ns8250->ier &= ~IER_ETXRDY; 744 uart_setreg(bas, REG_IER, ns8250->ier); 745 uart_barrier(bas); 746 } else 747 ipend |= SER_INT_SIGCHG; 748 } 749 if (ipend == 0) 750 ns8250_clrint(bas); 751 uart_unlock(sc->sc_hwmtx); 752 return (ipend); 753 } 754 755 int 756 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 757 int stopbits, int parity) 758 { 759 struct ns8250_softc *ns8250; 760 struct uart_bas *bas; 761 int error, limit; 762 763 ns8250 = (struct ns8250_softc*)sc; 764 bas = &sc->sc_bas; 765 uart_lock(sc->sc_hwmtx); 766 /* 767 * When using DW UART with BUSY detection it is necessary to wait 768 * until all serial transfers are finished before manipulating the 769 * line control. LCR will not be affected when UART is busy. 770 */ 771 if (ns8250->busy_detect != 0) { 772 /* 773 * Pick an arbitrary high limit to avoid getting stuck in 774 * an infinite loop in case when the hardware is broken. 775 */ 776 limit = 10 * 1024; 777 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 778 --limit) 779 DELAY(4); 780 781 if (limit <= 0) { 782 /* UART appears to be stuck */ 783 uart_unlock(sc->sc_hwmtx); 784 return (EIO); 785 } 786 } 787 788 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 789 uart_unlock(sc->sc_hwmtx); 790 return (error); 791 } 792 793 int 794 ns8250_bus_probe(struct uart_softc *sc) 795 { 796 struct uart_bas *bas; 797 int count, delay, error, limit; 798 uint8_t lsr, mcr, ier; 799 uint8_t val; 800 801 bas = &sc->sc_bas; 802 803 error = ns8250_probe(bas); 804 if (error) 805 return (error); 806 807 mcr = MCR_IE; 808 if (sc->sc_sysdev == NULL) { 809 /* By using ns8250_init() we also set DTR and RTS. */ 810 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 811 } else 812 mcr |= MCR_DTR | MCR_RTS; 813 814 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 815 if (error) 816 return (error); 817 818 /* 819 * Set loopback mode. This avoids having garbage on the wire and 820 * also allows us send and receive data. We set DTR and RTS to 821 * avoid the possibility that automatic flow-control prevents 822 * any data from being sent. 823 */ 824 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 825 uart_barrier(bas); 826 827 /* 828 * Enable FIFOs. And check that the UART has them. If not, we're 829 * done. Since this is the first time we enable the FIFOs, we reset 830 * them. 831 */ 832 val = FCR_ENABLE; 833 #ifdef CPU_XBURST 834 val |= FCR_UART_ON; 835 #endif 836 uart_setreg(bas, REG_FCR, val); 837 uart_barrier(bas); 838 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 839 /* 840 * NS16450 or INS8250. We don't bother to differentiate 841 * between them. They're too old to be interesting. 842 */ 843 uart_setreg(bas, REG_MCR, mcr); 844 uart_barrier(bas); 845 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 846 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 847 return (0); 848 } 849 850 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 851 #ifdef CPU_XBURST 852 val |= FCR_UART_ON; 853 #endif 854 uart_setreg(bas, REG_FCR, val); 855 uart_barrier(bas); 856 857 count = 0; 858 delay = ns8250_delay(bas); 859 860 /* We have FIFOs. Drain the transmitter and receiver. */ 861 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 862 if (error) { 863 uart_setreg(bas, REG_MCR, mcr); 864 val = 0; 865 #ifdef CPU_XBURST 866 val |= FCR_UART_ON; 867 #endif 868 uart_setreg(bas, REG_FCR, val); 869 uart_barrier(bas); 870 goto describe; 871 } 872 873 /* 874 * We should have a sufficiently clean "pipe" to determine the 875 * size of the FIFOs. We send as much characters as is reasonable 876 * and wait for the overflow bit in the LSR register to be 877 * asserted, counting the characters as we send them. Based on 878 * that count we know the FIFO size. 879 */ 880 do { 881 uart_setreg(bas, REG_DATA, 0); 882 uart_barrier(bas); 883 count++; 884 885 limit = 30; 886 lsr = 0; 887 /* 888 * LSR bits are cleared upon read, so we must accumulate 889 * them to be able to test LSR_OE below. 890 */ 891 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 892 --limit) 893 DELAY(delay); 894 if (limit == 0) { 895 /* See the comment in ns8250_init(). */ 896 ier = uart_getreg(bas, REG_IER) & 0xe0; 897 uart_setreg(bas, REG_IER, ier); 898 uart_setreg(bas, REG_MCR, mcr); 899 val = 0; 900 #ifdef CPU_XBURST 901 val |= FCR_UART_ON; 902 #endif 903 uart_setreg(bas, REG_FCR, val); 904 uart_barrier(bas); 905 count = 0; 906 goto describe; 907 } 908 } while ((lsr & LSR_OE) == 0 && count < 260); 909 count--; 910 911 uart_setreg(bas, REG_MCR, mcr); 912 913 /* Reset FIFOs. */ 914 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 915 916 describe: 917 if (count >= 14 && count <= 16) { 918 sc->sc_rxfifosz = 16; 919 device_set_desc(sc->sc_dev, "16550 or compatible"); 920 } else if (count >= 28 && count <= 32) { 921 sc->sc_rxfifosz = 32; 922 device_set_desc(sc->sc_dev, "16650 or compatible"); 923 } else if (count >= 56 && count <= 64) { 924 sc->sc_rxfifosz = 64; 925 device_set_desc(sc->sc_dev, "16750 or compatible"); 926 } else if (count >= 112 && count <= 128) { 927 sc->sc_rxfifosz = 128; 928 device_set_desc(sc->sc_dev, "16950 or compatible"); 929 } else if (count >= 224 && count <= 256) { 930 sc->sc_rxfifosz = 256; 931 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 932 } else { 933 sc->sc_rxfifosz = 16; 934 device_set_desc(sc->sc_dev, 935 "Non-standard ns8250 class UART with FIFOs"); 936 } 937 938 /* 939 * Force the Tx FIFO size to 16 bytes for now. We don't program the 940 * Tx trigger. Also, we assume that all data has been sent when the 941 * interrupt happens. 942 */ 943 sc->sc_txfifosz = 16; 944 945 #if 0 946 /* 947 * XXX there are some issues related to hardware flow control and 948 * it's likely that uart(4) is the cause. This basically needs more 949 * investigation, but we avoid using for hardware flow control 950 * until then. 951 */ 952 /* 16650s or higher have automatic flow control. */ 953 if (sc->sc_rxfifosz > 16) { 954 sc->sc_hwiflow = 1; 955 sc->sc_hwoflow = 1; 956 } 957 #endif 958 959 return (0); 960 } 961 962 int 963 ns8250_bus_receive(struct uart_softc *sc) 964 { 965 struct uart_bas *bas; 966 int xc; 967 uint8_t lsr; 968 969 bas = &sc->sc_bas; 970 uart_lock(sc->sc_hwmtx); 971 lsr = uart_getreg(bas, REG_LSR); 972 while (lsr & LSR_RXRDY) { 973 if (uart_rx_full(sc)) { 974 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 975 break; 976 } 977 xc = uart_getreg(bas, REG_DATA); 978 if (lsr & LSR_FE) 979 xc |= UART_STAT_FRAMERR; 980 if (lsr & LSR_PE) 981 xc |= UART_STAT_PARERR; 982 uart_rx_put(sc, xc); 983 lsr = uart_getreg(bas, REG_LSR); 984 } 985 /* Discard everything left in the Rx FIFO. */ 986 while (lsr & LSR_RXRDY) { 987 (void)uart_getreg(bas, REG_DATA); 988 uart_barrier(bas); 989 lsr = uart_getreg(bas, REG_LSR); 990 } 991 uart_unlock(sc->sc_hwmtx); 992 return (0); 993 } 994 995 int 996 ns8250_bus_setsig(struct uart_softc *sc, int sig) 997 { 998 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 999 struct uart_bas *bas; 1000 uint32_t new, old; 1001 1002 bas = &sc->sc_bas; 1003 do { 1004 old = sc->sc_hwsig; 1005 new = old; 1006 if (sig & SER_DDTR) { 1007 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1008 } 1009 if (sig & SER_DRTS) { 1010 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1011 } 1012 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1013 uart_lock(sc->sc_hwmtx); 1014 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1015 if (new & SER_DTR) 1016 ns8250->mcr |= MCR_DTR; 1017 if (new & SER_RTS) 1018 ns8250->mcr |= MCR_RTS; 1019 uart_setreg(bas, REG_MCR, ns8250->mcr); 1020 uart_barrier(bas); 1021 uart_unlock(sc->sc_hwmtx); 1022 return (0); 1023 } 1024 1025 int 1026 ns8250_bus_transmit(struct uart_softc *sc) 1027 { 1028 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1029 struct uart_bas *bas; 1030 int i; 1031 1032 bas = &sc->sc_bas; 1033 uart_lock(sc->sc_hwmtx); 1034 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1035 DELAY(4); 1036 for (i = 0; i < sc->sc_txdatasz; i++) { 1037 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1038 uart_barrier(bas); 1039 } 1040 if (!broken_txfifo) 1041 ns8250->ier |= IER_ETXRDY; 1042 uart_setreg(bas, REG_IER, ns8250->ier); 1043 uart_barrier(bas); 1044 if (broken_txfifo) 1045 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1046 else 1047 sc->sc_txbusy = 1; 1048 uart_unlock(sc->sc_hwmtx); 1049 if (broken_txfifo) 1050 uart_sched_softih(sc, SER_INT_TXIDLE); 1051 return (0); 1052 } 1053 1054 void 1055 ns8250_bus_grab(struct uart_softc *sc) 1056 { 1057 struct uart_bas *bas = &sc->sc_bas; 1058 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1059 u_char ier; 1060 1061 /* 1062 * turn off all interrupts to enter polling mode. Leave the 1063 * saved mask alone. We'll restore whatever it was in ungrab. 1064 * All pending interrupt signals are reset when IER is set to 0. 1065 */ 1066 uart_lock(sc->sc_hwmtx); 1067 ier = uart_getreg(bas, REG_IER); 1068 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1069 uart_barrier(bas); 1070 uart_unlock(sc->sc_hwmtx); 1071 } 1072 1073 void 1074 ns8250_bus_ungrab(struct uart_softc *sc) 1075 { 1076 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1077 struct uart_bas *bas = &sc->sc_bas; 1078 1079 /* 1080 * Restore previous interrupt mask 1081 */ 1082 uart_lock(sc->sc_hwmtx); 1083 uart_setreg(bas, REG_IER, ns8250->ier); 1084 uart_barrier(bas); 1085 uart_unlock(sc->sc_hwmtx); 1086 } 1087