1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <machine/bus.h> 41 42 #ifdef FDT 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #endif 47 48 #include <dev/uart/uart.h> 49 #include <dev/uart/uart_cpu.h> 50 #ifdef FDT 51 #include <dev/uart/uart_cpu_fdt.h> 52 #endif 53 #include <dev/uart/uart_bus.h> 54 #include <dev/uart/uart_dev_ns8250.h> 55 #include <dev/uart/uart_ppstypes.h> 56 #ifdef DEV_ACPI 57 #include <dev/uart/uart_cpu_acpi.h> 58 #include <contrib/dev/acpica/include/acpi.h> 59 #endif 60 61 #include <dev/ic/ns16550.h> 62 63 #include "uart_if.h" 64 65 #define DEFAULT_RCLK 1843200 66 67 /* 68 * Set the default baudrate tolerance to 3.0%. 69 * 70 * Some embedded boards have odd reference clocks (eg 25MHz) 71 * and we need to handle higher variances in the target baud rate. 72 */ 73 #ifndef UART_DEV_TOLERANCE_PCT 74 #define UART_DEV_TOLERANCE_PCT 30 75 #endif /* UART_DEV_TOLERANCE_PCT */ 76 77 static int broken_txfifo = 0; 78 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 79 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 80 81 /* 82 * To use early printf on x86, add the following to your kernel config: 83 * 84 * options UART_NS8250_EARLY_PORT=0x3f8 85 * options EARLY_PRINTF 86 */ 87 #if defined(EARLY_PRINTF) && (defined(__amd64__) || defined(__i386__)) 88 static void 89 uart_ns8250_early_putc(int c) 90 { 91 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 92 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 93 int limit = 10000; /* 10ms is plenty of time */ 94 95 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 96 continue; 97 outb(tx, c); 98 } 99 early_putc_t *early_putc = uart_ns8250_early_putc; 100 #endif /* EARLY_PRINTF */ 101 102 /* 103 * Clear pending interrupts. THRE is cleared by reading IIR. Data 104 * that may have been received gets lost here. 105 */ 106 static void 107 ns8250_clrint(struct uart_bas *bas) 108 { 109 uint8_t iir, lsr; 110 111 iir = uart_getreg(bas, REG_IIR); 112 while ((iir & IIR_NOPEND) == 0) { 113 iir &= IIR_IMASK; 114 if (iir == IIR_RLS) { 115 lsr = uart_getreg(bas, REG_LSR); 116 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 117 (void)uart_getreg(bas, REG_DATA); 118 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 119 (void)uart_getreg(bas, REG_DATA); 120 else if (iir == IIR_MLSC) 121 (void)uart_getreg(bas, REG_MSR); 122 uart_barrier(bas); 123 iir = uart_getreg(bas, REG_IIR); 124 } 125 } 126 127 static int 128 ns8250_delay(struct uart_bas *bas) 129 { 130 int divisor; 131 u_char lcr; 132 133 lcr = uart_getreg(bas, REG_LCR); 134 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 135 uart_barrier(bas); 136 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 137 uart_barrier(bas); 138 uart_setreg(bas, REG_LCR, lcr); 139 uart_barrier(bas); 140 141 /* 1/10th the time to transmit 1 character (estimate). */ 142 if (divisor <= 134) 143 return (16000000 * divisor / bas->rclk); 144 return (16000 * divisor / (bas->rclk / 1000)); 145 } 146 147 static int 148 ns8250_divisor(int rclk, int baudrate) 149 { 150 int actual_baud, divisor; 151 int error; 152 153 if (baudrate == 0) 154 return (0); 155 156 divisor = (rclk / (baudrate << 3) + 1) >> 1; 157 if (divisor == 0 || divisor >= 65536) 158 return (0); 159 actual_baud = rclk / (divisor << 4); 160 161 /* 10 times error in percent: */ 162 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 163 164 /* enforce maximum error tolerance: */ 165 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 166 return (0); 167 168 return (divisor); 169 } 170 171 static int 172 ns8250_drain(struct uart_bas *bas, int what) 173 { 174 int delay, limit; 175 176 delay = ns8250_delay(bas); 177 178 if (what & UART_DRAIN_TRANSMITTER) { 179 /* 180 * Pick an arbitrary high limit to avoid getting stuck in 181 * an infinite loop when the hardware is broken. Make the 182 * limit high enough to handle large FIFOs. 183 */ 184 limit = 10*1024; 185 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 186 DELAY(delay); 187 if (limit == 0) { 188 /* printf("ns8250: transmitter appears stuck... "); */ 189 return (EIO); 190 } 191 } 192 193 if (what & UART_DRAIN_RECEIVER) { 194 /* 195 * Pick an arbitrary high limit to avoid getting stuck in 196 * an infinite loop when the hardware is broken. Make the 197 * limit high enough to handle large FIFOs and integrated 198 * UARTs. The HP rx2600 for example has 3 UARTs on the 199 * management board that tend to get a lot of data send 200 * to it when the UART is first activated. Assume that we 201 * have finished draining if LSR_RXRDY is not asserted both 202 * prior to and after a DELAY; but as long as LSR_RXRDY is 203 * asserted, read (and discard) characters as quickly as 204 * possible. 205 */ 206 limit=10*4096; 207 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 208 do { 209 (void)uart_getreg(bas, REG_DATA); 210 uart_barrier(bas); 211 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 212 uart_barrier(bas); 213 DELAY(delay << 2); 214 } 215 if (limit == 0) { 216 /* printf("ns8250: receiver appears broken... "); */ 217 return (EIO); 218 } 219 } 220 221 return (0); 222 } 223 224 /* 225 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 226 * drained. WARNING: this function clobbers the FIFO setting! 227 */ 228 static void 229 ns8250_flush(struct uart_bas *bas, int what) 230 { 231 uint8_t fcr; 232 uint8_t lsr; 233 int drain = 0; 234 235 fcr = FCR_ENABLE; 236 if (what & UART_FLUSH_TRANSMITTER) 237 fcr |= FCR_XMT_RST; 238 if (what & UART_FLUSH_RECEIVER) 239 fcr |= FCR_RCV_RST; 240 uart_setreg(bas, REG_FCR, fcr); 241 uart_barrier(bas); 242 243 /* 244 * Detect and work around emulated UARTs which don't implement the 245 * FCR register; on these systems we need to drain the FIFO since 246 * the flush we request doesn't happen. One such system is the 247 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 248 * https://github.com/rust-vmm/vm-superio/issues/83 249 */ 250 lsr = uart_getreg(bas, REG_LSR); 251 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 252 drain |= UART_DRAIN_TRANSMITTER; 253 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 254 drain |= UART_DRAIN_RECEIVER; 255 if (drain != 0) { 256 printf("ns8250: UART FCR is broken\n"); 257 ns8250_drain(bas, drain); 258 } 259 } 260 261 static int 262 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 263 int parity) 264 { 265 int divisor; 266 uint8_t lcr; 267 268 /* Don't change settings when running on Hyper-V */ 269 if (vm_guest == VM_GUEST_HV) 270 return (0); 271 272 lcr = 0; 273 if (databits >= 8) 274 lcr |= LCR_8BITS; 275 else if (databits == 7) 276 lcr |= LCR_7BITS; 277 else if (databits == 6) 278 lcr |= LCR_6BITS; 279 else 280 lcr |= LCR_5BITS; 281 if (stopbits > 1) 282 lcr |= LCR_STOPB; 283 lcr |= parity << 3; 284 285 /* Set baudrate. */ 286 if (baudrate > 0) { 287 divisor = ns8250_divisor(bas->rclk, baudrate); 288 if (divisor == 0) 289 return (EINVAL); 290 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 291 uart_barrier(bas); 292 uart_setreg(bas, REG_DLL, divisor & 0xff); 293 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 294 uart_barrier(bas); 295 } 296 297 /* Set LCR and clear DLAB. */ 298 uart_setreg(bas, REG_LCR, lcr); 299 uart_barrier(bas); 300 return (0); 301 } 302 303 /* 304 * Low-level UART interface. 305 */ 306 static int ns8250_probe(struct uart_bas *bas); 307 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 308 static void ns8250_term(struct uart_bas *bas); 309 static void ns8250_putc(struct uart_bas *bas, int); 310 static int ns8250_rxready(struct uart_bas *bas); 311 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 312 313 struct uart_ops uart_ns8250_ops = { 314 .probe = ns8250_probe, 315 .init = ns8250_init, 316 .term = ns8250_term, 317 .putc = ns8250_putc, 318 .rxready = ns8250_rxready, 319 .getc = ns8250_getc, 320 }; 321 322 static int 323 ns8250_probe(struct uart_bas *bas) 324 { 325 u_char val; 326 327 /* Check known 0 bits that don't depend on DLAB. */ 328 val = uart_getreg(bas, REG_IIR); 329 if (val & 0x30) 330 return (ENXIO); 331 /* 332 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 333 * chip, but otherwise doesn't seem to have a function. In 334 * other words, uart(4) works regardless. Ignore that bit so 335 * the probe succeeds. 336 */ 337 val = uart_getreg(bas, REG_MCR); 338 if (val & 0xa0) 339 return (ENXIO); 340 341 return (0); 342 } 343 344 static void 345 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 346 int parity) 347 { 348 u_char ier; 349 350 if (bas->rclk == 0) 351 bas->rclk = DEFAULT_RCLK; 352 ns8250_param(bas, baudrate, databits, stopbits, parity); 353 354 /* Disable all interrupt sources. */ 355 /* 356 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 357 * UARTs split the receive time-out interrupt bit out separately as 358 * 0x10. This gets handled by ier_mask and ier_rxbits below. 359 */ 360 ier = uart_getreg(bas, REG_IER) & 0xe0; 361 uart_setreg(bas, REG_IER, ier); 362 uart_barrier(bas); 363 364 /* Disable the FIFO (if present). */ 365 uart_setreg(bas, REG_FCR, 0); 366 uart_barrier(bas); 367 368 /* Set RTS & DTR. */ 369 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 370 uart_barrier(bas); 371 372 ns8250_clrint(bas); 373 } 374 375 static void 376 ns8250_term(struct uart_bas *bas) 377 { 378 379 /* Clear RTS & DTR. */ 380 uart_setreg(bas, REG_MCR, MCR_IE); 381 uart_barrier(bas); 382 } 383 384 static void 385 ns8250_putc(struct uart_bas *bas, int c) 386 { 387 int limit; 388 389 if (vm_guest != VM_GUEST_HV) { 390 limit = 250000; 391 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 392 DELAY(4); 393 } 394 uart_setreg(bas, REG_DATA, c); 395 uart_barrier(bas); 396 } 397 398 static int 399 ns8250_rxready(struct uart_bas *bas) 400 { 401 402 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 403 } 404 405 static int 406 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 407 { 408 int c; 409 410 uart_lock(hwmtx); 411 412 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 413 uart_unlock(hwmtx); 414 DELAY(4); 415 uart_lock(hwmtx); 416 } 417 418 c = uart_getreg(bas, REG_DATA); 419 420 uart_unlock(hwmtx); 421 422 return (c); 423 } 424 425 static kobj_method_t ns8250_methods[] = { 426 KOBJMETHOD(uart_attach, ns8250_bus_attach), 427 KOBJMETHOD(uart_detach, ns8250_bus_detach), 428 KOBJMETHOD(uart_flush, ns8250_bus_flush), 429 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 430 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 431 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 432 KOBJMETHOD(uart_param, ns8250_bus_param), 433 KOBJMETHOD(uart_probe, ns8250_bus_probe), 434 KOBJMETHOD(uart_receive, ns8250_bus_receive), 435 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 436 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 437 KOBJMETHOD(uart_grab, ns8250_bus_grab), 438 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 439 { 0, 0 } 440 }; 441 442 struct uart_class uart_ns8250_class = { 443 "ns8250", 444 ns8250_methods, 445 sizeof(struct ns8250_softc), 446 .uc_ops = &uart_ns8250_ops, 447 .uc_range = 8, 448 .uc_rclk = DEFAULT_RCLK, 449 .uc_rshift = 0 450 }; 451 452 /* 453 * XXX -- refactor out ACPI and FDT ifdefs 454 */ 455 #ifdef DEV_ACPI 456 static struct acpi_uart_compat_data acpi_compat_data[] = { 457 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 458 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 459 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 460 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 461 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 462 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 463 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 464 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 465 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 466 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 467 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 468 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 469 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 470 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 471 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 472 }; 473 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 474 #endif 475 476 #ifdef FDT 477 static struct ofw_compat_data compat_data[] = { 478 {"ns16550", (uintptr_t)&uart_ns8250_class}, 479 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 480 {NULL, (uintptr_t)NULL}, 481 }; 482 UART_FDT_CLASS_AND_DEVICE(compat_data); 483 #endif 484 485 /* Use token-pasting to form SER_ and MSR_ named constants. */ 486 #define SER(sig) SER_##sig 487 #define SERD(sig) SER_D##sig 488 #define MSR(sig) MSR_##sig 489 #define MSRD(sig) MSR_D##sig 490 491 /* 492 * Detect signal changes using software delta detection. The previous state of 493 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 494 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 495 * new state of both the signal and the delta bits. 496 */ 497 #define SIGCHGSW(var, msr, sig) \ 498 if ((msr) & MSR(sig)) { \ 499 if ((var & SER(sig)) == 0) \ 500 var |= SERD(sig) | SER(sig); \ 501 } else { \ 502 if ((var & SER(sig)) != 0) \ 503 var = SERD(sig) | (var & ~SER(sig)); \ 504 } 505 506 /* 507 * Detect signal changes using the hardware msr delta bits. This is currently 508 * used only when PPS timing information is being captured using the "narrow 509 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 510 * by time the interrupt handler is invoked. The hardware will latch the fact 511 * that it changed in the delta bits. 512 */ 513 #define SIGCHGHW(var, msr, sig) \ 514 if ((msr) & MSRD(sig)) { \ 515 if (((msr) & MSR(sig)) != 0) \ 516 var |= SERD(sig) | SER(sig); \ 517 else \ 518 var = SERD(sig) | (var & ~SER(sig)); \ 519 } 520 521 int 522 ns8250_bus_attach(struct uart_softc *sc) 523 { 524 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 525 struct uart_bas *bas; 526 unsigned int ivar; 527 #ifdef FDT 528 phandle_t node; 529 pcell_t cell; 530 #endif 531 532 #ifdef FDT 533 /* Check whether uart has a broken txfifo. */ 534 node = ofw_bus_get_node(sc->sc_dev); 535 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 536 broken_txfifo = cell ? 1 : 0; 537 #endif 538 539 bas = &sc->sc_bas; 540 541 ns8250->busy_detect = bas->busy_detect; 542 ns8250->mcr = uart_getreg(bas, REG_MCR); 543 ns8250->fcr = FCR_ENABLE; 544 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 545 &ivar)) { 546 if (UART_FLAGS_FCR_RX_LOW(ivar)) 547 ns8250->fcr |= FCR_RX_LOW; 548 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 549 ns8250->fcr |= FCR_RX_MEDL; 550 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 551 ns8250->fcr |= FCR_RX_HIGH; 552 else 553 ns8250->fcr |= FCR_RX_MEDH; 554 } else 555 ns8250->fcr |= FCR_RX_MEDH; 556 557 /* Get IER mask */ 558 ivar = 0xf0; 559 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 560 &ivar); 561 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 562 563 /* Get IER RX interrupt bits */ 564 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 565 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 566 &ivar); 567 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 568 569 uart_setreg(bas, REG_FCR, ns8250->fcr); 570 uart_barrier(bas); 571 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 572 573 if (ns8250->mcr & MCR_DTR) 574 sc->sc_hwsig |= SER_DTR; 575 if (ns8250->mcr & MCR_RTS) 576 sc->sc_hwsig |= SER_RTS; 577 ns8250_bus_getsig(sc); 578 579 ns8250_clrint(bas); 580 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 581 ns8250->ier |= ns8250->ier_rxbits; 582 uart_setreg(bas, REG_IER, ns8250->ier); 583 uart_barrier(bas); 584 585 /* 586 * Timing of the H/W access was changed with r253161 of uart_core.c 587 * It has been observed that an ITE IT8513E would signal a break 588 * condition with pretty much every character it received, unless 589 * it had enough time to settle between ns8250_bus_attach() and 590 * ns8250_bus_ipend() -- which it accidentally had before r253161. 591 * It's not understood why the UART chip behaves this way and it 592 * could very well be that the DELAY make the H/W work in the same 593 * accidental manner as before. More analysis is warranted, but 594 * at least now we fixed a known regression. 595 */ 596 DELAY(200); 597 return (0); 598 } 599 600 int 601 ns8250_bus_detach(struct uart_softc *sc) 602 { 603 struct ns8250_softc *ns8250; 604 struct uart_bas *bas; 605 u_char ier; 606 607 ns8250 = (struct ns8250_softc *)sc; 608 bas = &sc->sc_bas; 609 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 610 uart_setreg(bas, REG_IER, ier); 611 uart_barrier(bas); 612 ns8250_clrint(bas); 613 return (0); 614 } 615 616 int 617 ns8250_bus_flush(struct uart_softc *sc, int what) 618 { 619 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 620 struct uart_bas *bas; 621 int error; 622 623 bas = &sc->sc_bas; 624 uart_lock(sc->sc_hwmtx); 625 if (sc->sc_rxfifosz > 1) { 626 ns8250_flush(bas, what); 627 uart_setreg(bas, REG_FCR, ns8250->fcr); 628 uart_barrier(bas); 629 error = 0; 630 } else 631 error = ns8250_drain(bas, what); 632 uart_unlock(sc->sc_hwmtx); 633 return (error); 634 } 635 636 int 637 ns8250_bus_getsig(struct uart_softc *sc) 638 { 639 uint32_t old, sig; 640 uint8_t msr; 641 642 /* 643 * The delta bits are reputed to be broken on some hardware, so use 644 * software delta detection by default. Use the hardware delta bits 645 * when capturing PPS pulses which are too narrow for software detection 646 * to see the edges. Hardware delta for RI doesn't work like the 647 * others, so always use software for it. Other threads may be changing 648 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 649 * update without other changes happening. Note that the SIGCHGxx() 650 * macros carefully preserve the delta bits when we have to loop several 651 * times and a signal transitions between iterations. 652 */ 653 do { 654 old = sc->sc_hwsig; 655 sig = old; 656 uart_lock(sc->sc_hwmtx); 657 msr = uart_getreg(&sc->sc_bas, REG_MSR); 658 uart_unlock(sc->sc_hwmtx); 659 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 660 SIGCHGHW(sig, msr, DSR); 661 SIGCHGHW(sig, msr, CTS); 662 SIGCHGHW(sig, msr, DCD); 663 } else { 664 SIGCHGSW(sig, msr, DSR); 665 SIGCHGSW(sig, msr, CTS); 666 SIGCHGSW(sig, msr, DCD); 667 } 668 SIGCHGSW(sig, msr, RI); 669 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 670 return (sig); 671 } 672 673 int 674 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 675 { 676 struct uart_bas *bas; 677 int baudrate, divisor, error; 678 uint8_t efr, lcr; 679 680 bas = &sc->sc_bas; 681 error = 0; 682 uart_lock(sc->sc_hwmtx); 683 switch (request) { 684 case UART_IOCTL_BREAK: 685 lcr = uart_getreg(bas, REG_LCR); 686 if (data) 687 lcr |= LCR_SBREAK; 688 else 689 lcr &= ~LCR_SBREAK; 690 uart_setreg(bas, REG_LCR, lcr); 691 uart_barrier(bas); 692 break; 693 case UART_IOCTL_IFLOW: 694 lcr = uart_getreg(bas, REG_LCR); 695 uart_barrier(bas); 696 uart_setreg(bas, REG_LCR, 0xbf); 697 uart_barrier(bas); 698 efr = uart_getreg(bas, REG_EFR); 699 if (data) 700 efr |= EFR_RTS; 701 else 702 efr &= ~EFR_RTS; 703 uart_setreg(bas, REG_EFR, efr); 704 uart_barrier(bas); 705 uart_setreg(bas, REG_LCR, lcr); 706 uart_barrier(bas); 707 break; 708 case UART_IOCTL_OFLOW: 709 lcr = uart_getreg(bas, REG_LCR); 710 uart_barrier(bas); 711 uart_setreg(bas, REG_LCR, 0xbf); 712 uart_barrier(bas); 713 efr = uart_getreg(bas, REG_EFR); 714 if (data) 715 efr |= EFR_CTS; 716 else 717 efr &= ~EFR_CTS; 718 uart_setreg(bas, REG_EFR, efr); 719 uart_barrier(bas); 720 uart_setreg(bas, REG_LCR, lcr); 721 uart_barrier(bas); 722 break; 723 case UART_IOCTL_BAUD: 724 lcr = uart_getreg(bas, REG_LCR); 725 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 726 uart_barrier(bas); 727 divisor = uart_getreg(bas, REG_DLL) | 728 (uart_getreg(bas, REG_DLH) << 8); 729 uart_barrier(bas); 730 uart_setreg(bas, REG_LCR, lcr); 731 uart_barrier(bas); 732 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 733 if (baudrate > 0) 734 *(int*)data = baudrate; 735 else 736 error = ENXIO; 737 break; 738 default: 739 error = EINVAL; 740 break; 741 } 742 uart_unlock(sc->sc_hwmtx); 743 return (error); 744 } 745 746 int 747 ns8250_bus_ipend(struct uart_softc *sc) 748 { 749 struct uart_bas *bas; 750 struct ns8250_softc *ns8250; 751 int ipend; 752 uint8_t iir, lsr; 753 754 ns8250 = (struct ns8250_softc *)sc; 755 bas = &sc->sc_bas; 756 uart_lock(sc->sc_hwmtx); 757 iir = uart_getreg(bas, REG_IIR); 758 759 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 760 (void)uart_getreg(bas, DW_REG_USR); 761 uart_unlock(sc->sc_hwmtx); 762 return (0); 763 } 764 if (iir & IIR_NOPEND) { 765 uart_unlock(sc->sc_hwmtx); 766 return (0); 767 } 768 ipend = 0; 769 if (iir & IIR_RXRDY) { 770 lsr = uart_getreg(bas, REG_LSR); 771 if (lsr & LSR_OE) 772 ipend |= SER_INT_OVERRUN; 773 if (lsr & LSR_BI) 774 ipend |= SER_INT_BREAK; 775 if (lsr & LSR_RXRDY) 776 ipend |= SER_INT_RXREADY; 777 } else { 778 if (iir & IIR_TXRDY) { 779 ipend |= SER_INT_TXIDLE; 780 ns8250->ier &= ~IER_ETXRDY; 781 uart_setreg(bas, REG_IER, ns8250->ier); 782 uart_barrier(bas); 783 } else 784 ipend |= SER_INT_SIGCHG; 785 } 786 if (ipend == 0) 787 ns8250_clrint(bas); 788 uart_unlock(sc->sc_hwmtx); 789 return (ipend); 790 } 791 792 int 793 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 794 int stopbits, int parity) 795 { 796 struct ns8250_softc *ns8250; 797 struct uart_bas *bas; 798 int error, limit; 799 800 ns8250 = (struct ns8250_softc*)sc; 801 bas = &sc->sc_bas; 802 uart_lock(sc->sc_hwmtx); 803 /* 804 * When using DW UART with BUSY detection it is necessary to wait 805 * until all serial transfers are finished before manipulating the 806 * line control. LCR will not be affected when UART is busy. 807 */ 808 if (ns8250->busy_detect != 0) { 809 /* 810 * Pick an arbitrary high limit to avoid getting stuck in 811 * an infinite loop in case when the hardware is broken. 812 */ 813 limit = 10 * 1024; 814 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 815 --limit) 816 DELAY(4); 817 818 if (limit <= 0) { 819 /* UART appears to be stuck */ 820 uart_unlock(sc->sc_hwmtx); 821 return (EIO); 822 } 823 } 824 825 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 826 uart_unlock(sc->sc_hwmtx); 827 return (error); 828 } 829 830 int 831 ns8250_bus_probe(struct uart_softc *sc) 832 { 833 struct uart_bas *bas; 834 int count, delay, error, limit; 835 uint8_t lsr, mcr, ier; 836 837 bas = &sc->sc_bas; 838 839 error = ns8250_probe(bas); 840 if (error) 841 return (error); 842 843 mcr = MCR_IE; 844 if (sc->sc_sysdev == NULL) { 845 /* By using ns8250_init() we also set DTR and RTS. */ 846 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 847 } else 848 mcr |= MCR_DTR | MCR_RTS; 849 850 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 851 if (error) 852 return (error); 853 854 /* 855 * Set loopback mode. This avoids having garbage on the wire and 856 * also allows us send and receive data. We set DTR and RTS to 857 * avoid the possibility that automatic flow-control prevents 858 * any data from being sent. 859 */ 860 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 861 uart_barrier(bas); 862 863 /* 864 * Enable FIFOs. And check that the UART has them. If not, we're 865 * done. Since this is the first time we enable the FIFOs, we reset 866 * them. 867 */ 868 uart_setreg(bas, REG_FCR, FCR_ENABLE); 869 uart_barrier(bas); 870 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 871 /* 872 * NS16450 or INS8250. We don't bother to differentiate 873 * between them. They're too old to be interesting. 874 */ 875 uart_setreg(bas, REG_MCR, mcr); 876 uart_barrier(bas); 877 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 878 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 879 return (0); 880 } 881 882 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 883 uart_barrier(bas); 884 885 count = 0; 886 delay = ns8250_delay(bas); 887 888 /* We have FIFOs. Drain the transmitter and receiver. */ 889 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 890 if (error) { 891 uart_setreg(bas, REG_MCR, mcr); 892 uart_setreg(bas, REG_FCR, 0); 893 uart_barrier(bas); 894 goto describe; 895 } 896 897 /* 898 * We should have a sufficiently clean "pipe" to determine the 899 * size of the FIFOs. We send as much characters as is reasonable 900 * and wait for the overflow bit in the LSR register to be 901 * asserted, counting the characters as we send them. Based on 902 * that count we know the FIFO size. 903 */ 904 do { 905 uart_setreg(bas, REG_DATA, 0); 906 uart_barrier(bas); 907 count++; 908 909 limit = 30; 910 lsr = 0; 911 /* 912 * LSR bits are cleared upon read, so we must accumulate 913 * them to be able to test LSR_OE below. 914 */ 915 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 916 --limit) 917 DELAY(delay); 918 if (limit == 0) { 919 /* See the comment in ns8250_init(). */ 920 ier = uart_getreg(bas, REG_IER) & 0xe0; 921 uart_setreg(bas, REG_IER, ier); 922 uart_setreg(bas, REG_MCR, mcr); 923 uart_setreg(bas, REG_FCR, 0); 924 uart_barrier(bas); 925 count = 0; 926 goto describe; 927 } 928 } while ((lsr & LSR_OE) == 0 && count < 260); 929 count--; 930 931 uart_setreg(bas, REG_MCR, mcr); 932 933 /* Reset FIFOs. */ 934 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 935 936 describe: 937 if (count >= 14 && count <= 16) { 938 sc->sc_rxfifosz = 16; 939 device_set_desc(sc->sc_dev, "16550 or compatible"); 940 } else if (count >= 28 && count <= 32) { 941 sc->sc_rxfifosz = 32; 942 device_set_desc(sc->sc_dev, "16650 or compatible"); 943 } else if (count >= 56 && count <= 64) { 944 sc->sc_rxfifosz = 64; 945 device_set_desc(sc->sc_dev, "16750 or compatible"); 946 } else if (count >= 112 && count <= 128) { 947 sc->sc_rxfifosz = 128; 948 device_set_desc(sc->sc_dev, "16950 or compatible"); 949 } else if (count >= 224 && count <= 256) { 950 sc->sc_rxfifosz = 256; 951 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 952 } else { 953 sc->sc_rxfifosz = 16; 954 device_set_desc(sc->sc_dev, 955 "Non-standard ns8250 class UART with FIFOs"); 956 } 957 958 /* 959 * Force the Tx FIFO size to 16 bytes for now. We don't program the 960 * Tx trigger. Also, we assume that all data has been sent when the 961 * interrupt happens. 962 */ 963 sc->sc_txfifosz = 16; 964 965 #if 0 966 /* 967 * XXX there are some issues related to hardware flow control and 968 * it's likely that uart(4) is the cause. This basically needs more 969 * investigation, but we avoid using for hardware flow control 970 * until then. 971 */ 972 /* 16650s or higher have automatic flow control. */ 973 if (sc->sc_rxfifosz > 16) { 974 sc->sc_hwiflow = 1; 975 sc->sc_hwoflow = 1; 976 } 977 #endif 978 979 return (0); 980 } 981 982 int 983 ns8250_bus_receive(struct uart_softc *sc) 984 { 985 struct uart_bas *bas; 986 int xc; 987 uint8_t lsr; 988 989 bas = &sc->sc_bas; 990 uart_lock(sc->sc_hwmtx); 991 lsr = uart_getreg(bas, REG_LSR); 992 while (lsr & LSR_RXRDY) { 993 if (uart_rx_full(sc)) { 994 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 995 break; 996 } 997 xc = uart_getreg(bas, REG_DATA); 998 if (lsr & LSR_FE) 999 xc |= UART_STAT_FRAMERR; 1000 if (lsr & LSR_PE) 1001 xc |= UART_STAT_PARERR; 1002 uart_rx_put(sc, xc); 1003 lsr = uart_getreg(bas, REG_LSR); 1004 } 1005 /* Discard everything left in the Rx FIFO. */ 1006 while (lsr & LSR_RXRDY) { 1007 (void)uart_getreg(bas, REG_DATA); 1008 uart_barrier(bas); 1009 lsr = uart_getreg(bas, REG_LSR); 1010 } 1011 uart_unlock(sc->sc_hwmtx); 1012 return (0); 1013 } 1014 1015 int 1016 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1017 { 1018 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1019 struct uart_bas *bas; 1020 uint32_t new, old; 1021 1022 bas = &sc->sc_bas; 1023 do { 1024 old = sc->sc_hwsig; 1025 new = old; 1026 if (sig & SER_DDTR) { 1027 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1028 } 1029 if (sig & SER_DRTS) { 1030 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1031 } 1032 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1033 uart_lock(sc->sc_hwmtx); 1034 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1035 if (new & SER_DTR) 1036 ns8250->mcr |= MCR_DTR; 1037 if (new & SER_RTS) 1038 ns8250->mcr |= MCR_RTS; 1039 uart_setreg(bas, REG_MCR, ns8250->mcr); 1040 uart_barrier(bas); 1041 uart_unlock(sc->sc_hwmtx); 1042 return (0); 1043 } 1044 1045 int 1046 ns8250_bus_transmit(struct uart_softc *sc) 1047 { 1048 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1049 struct uart_bas *bas; 1050 int i; 1051 1052 bas = &sc->sc_bas; 1053 uart_lock(sc->sc_hwmtx); 1054 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1055 DELAY(4); 1056 for (i = 0; i < sc->sc_txdatasz; i++) { 1057 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1058 uart_barrier(bas); 1059 } 1060 if (!broken_txfifo) 1061 ns8250->ier |= IER_ETXRDY; 1062 uart_setreg(bas, REG_IER, ns8250->ier); 1063 uart_barrier(bas); 1064 if (broken_txfifo) 1065 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1066 else 1067 sc->sc_txbusy = 1; 1068 uart_unlock(sc->sc_hwmtx); 1069 if (broken_txfifo) 1070 uart_sched_softih(sc, SER_INT_TXIDLE); 1071 return (0); 1072 } 1073 1074 void 1075 ns8250_bus_grab(struct uart_softc *sc) 1076 { 1077 struct uart_bas *bas = &sc->sc_bas; 1078 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1079 u_char ier; 1080 1081 /* 1082 * turn off all interrupts to enter polling mode. Leave the 1083 * saved mask alone. We'll restore whatever it was in ungrab. 1084 * All pending interrupt signals are reset when IER is set to 0. 1085 */ 1086 uart_lock(sc->sc_hwmtx); 1087 ier = uart_getreg(bas, REG_IER); 1088 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1089 uart_barrier(bas); 1090 uart_unlock(sc->sc_hwmtx); 1091 } 1092 1093 void 1094 ns8250_bus_ungrab(struct uart_softc *sc) 1095 { 1096 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1097 struct uart_bas *bas = &sc->sc_bas; 1098 1099 /* 1100 * Restore previous interrupt mask 1101 */ 1102 uart_lock(sc->sc_hwmtx); 1103 uart_setreg(bas, REG_IER, ns8250->ier); 1104 uart_barrier(bas); 1105 uart_unlock(sc->sc_hwmtx); 1106 } 1107