1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/ns16550.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 1843200 45 46 /* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50 static void 51 ns8250_clrint(struct uart_bas *bas) 52 { 53 uint8_t iir; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) 59 (void)uart_getreg(bas, REG_LSR); 60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61 (void)uart_getreg(bas, REG_DATA); 62 else if (iir == IIR_MLSC) 63 (void)uart_getreg(bas, REG_MSR); 64 uart_barrier(bas); 65 iir = uart_getreg(bas, REG_IIR); 66 } 67 } 68 69 static int 70 ns8250_delay(struct uart_bas *bas) 71 { 72 int divisor; 73 u_char lcr; 74 75 lcr = uart_getreg(bas, REG_LCR); 76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77 uart_barrier(bas); 78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79 uart_barrier(bas); 80 uart_setreg(bas, REG_LCR, lcr); 81 uart_barrier(bas); 82 83 /* 1/10th the time to transmit 1 character (estimate). */ 84 if (divisor <= 134) 85 return (16000000 * divisor / bas->rclk); 86 return (16000 * divisor / (bas->rclk / 1000)); 87 } 88 89 static int 90 ns8250_divisor(int rclk, int baudrate) 91 { 92 int actual_baud, divisor; 93 int error; 94 95 if (baudrate == 0) 96 return (0); 97 98 divisor = (rclk / (baudrate << 3) + 1) >> 1; 99 if (divisor == 0 || divisor >= 65536) 100 return (0); 101 actual_baud = rclk / (divisor << 4); 102 103 /* 10 times error in percent: */ 104 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 105 106 /* 3.0% maximum error tolerance: */ 107 if (error < -30 || error > 30) 108 return (0); 109 110 return (divisor); 111 } 112 113 static int 114 ns8250_drain(struct uart_bas *bas, int what) 115 { 116 int delay, limit; 117 118 delay = ns8250_delay(bas); 119 120 if (what & UART_DRAIN_TRANSMITTER) { 121 /* 122 * Pick an arbitrary high limit to avoid getting stuck in 123 * an infinite loop when the hardware is broken. Make the 124 * limit high enough to handle large FIFOs. 125 */ 126 limit = 10*1024; 127 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 128 DELAY(delay); 129 if (limit == 0) { 130 /* printf("ns8250: transmitter appears stuck... "); */ 131 return (EIO); 132 } 133 } 134 135 if (what & UART_DRAIN_RECEIVER) { 136 /* 137 * Pick an arbitrary high limit to avoid getting stuck in 138 * an infinite loop when the hardware is broken. Make the 139 * limit high enough to handle large FIFOs and integrated 140 * UARTs. The HP rx2600 for example has 3 UARTs on the 141 * management board that tend to get a lot of data send 142 * to it when the UART is first activated. 143 */ 144 limit=10*4096; 145 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 146 (void)uart_getreg(bas, REG_DATA); 147 uart_barrier(bas); 148 DELAY(delay << 2); 149 } 150 if (limit == 0) { 151 /* printf("ns8250: receiver appears broken... "); */ 152 return (EIO); 153 } 154 } 155 156 return (0); 157 } 158 159 /* 160 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 161 * drained. WARNING: this function clobbers the FIFO setting! 162 */ 163 static void 164 ns8250_flush(struct uart_bas *bas, int what) 165 { 166 uint8_t fcr; 167 168 fcr = FCR_ENABLE; 169 if (what & UART_FLUSH_TRANSMITTER) 170 fcr |= FCR_XMT_RST; 171 if (what & UART_FLUSH_RECEIVER) 172 fcr |= FCR_RCV_RST; 173 uart_setreg(bas, REG_FCR, fcr); 174 uart_barrier(bas); 175 } 176 177 static int 178 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 179 int parity) 180 { 181 int divisor; 182 uint8_t lcr; 183 184 lcr = 0; 185 if (databits >= 8) 186 lcr |= LCR_8BITS; 187 else if (databits == 7) 188 lcr |= LCR_7BITS; 189 else if (databits == 6) 190 lcr |= LCR_6BITS; 191 else 192 lcr |= LCR_5BITS; 193 if (stopbits > 1) 194 lcr |= LCR_STOPB; 195 lcr |= parity << 3; 196 197 /* Set baudrate. */ 198 if (baudrate > 0) { 199 divisor = ns8250_divisor(bas->rclk, baudrate); 200 if (divisor == 0) 201 return (EINVAL); 202 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 203 uart_barrier(bas); 204 uart_setreg(bas, REG_DLL, divisor & 0xff); 205 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 206 uart_barrier(bas); 207 } 208 209 /* Set LCR and clear DLAB. */ 210 uart_setreg(bas, REG_LCR, lcr); 211 uart_barrier(bas); 212 return (0); 213 } 214 215 /* 216 * Low-level UART interface. 217 */ 218 static int ns8250_probe(struct uart_bas *bas); 219 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 220 static void ns8250_term(struct uart_bas *bas); 221 static void ns8250_putc(struct uart_bas *bas, int); 222 static int ns8250_rxready(struct uart_bas *bas); 223 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 224 225 static struct uart_ops uart_ns8250_ops = { 226 .probe = ns8250_probe, 227 .init = ns8250_init, 228 .term = ns8250_term, 229 .putc = ns8250_putc, 230 .rxready = ns8250_rxready, 231 .getc = ns8250_getc, 232 }; 233 234 static int 235 ns8250_probe(struct uart_bas *bas) 236 { 237 u_char val; 238 239 /* Check known 0 bits that don't depend on DLAB. */ 240 val = uart_getreg(bas, REG_IIR); 241 if (val & 0x30) 242 return (ENXIO); 243 val = uart_getreg(bas, REG_MCR); 244 if (val & 0xe0) 245 return (ENXIO); 246 247 return (0); 248 } 249 250 static void 251 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 252 int parity) 253 { 254 u_char ier; 255 256 if (bas->rclk == 0) 257 bas->rclk = DEFAULT_RCLK; 258 ns8250_param(bas, baudrate, databits, stopbits, parity); 259 260 /* Disable all interrupt sources. */ 261 /* 262 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 263 * UARTs split the receive time-out interrupt bit out separately as 264 * 0x10. This gets handled by ier_mask and ier_rxbits below. 265 */ 266 ier = uart_getreg(bas, REG_IER) & 0xe0; 267 uart_setreg(bas, REG_IER, ier); 268 uart_barrier(bas); 269 270 /* Disable the FIFO (if present). */ 271 uart_setreg(bas, REG_FCR, 0); 272 uart_barrier(bas); 273 274 /* Set RTS & DTR. */ 275 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 276 uart_barrier(bas); 277 278 ns8250_clrint(bas); 279 } 280 281 static void 282 ns8250_term(struct uart_bas *bas) 283 { 284 285 /* Clear RTS & DTR. */ 286 uart_setreg(bas, REG_MCR, MCR_IE); 287 uart_barrier(bas); 288 } 289 290 static void 291 ns8250_putc(struct uart_bas *bas, int c) 292 { 293 int limit; 294 295 limit = 250000; 296 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 297 DELAY(4); 298 uart_setreg(bas, REG_DATA, c); 299 uart_barrier(bas); 300 limit = 250000; 301 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 302 DELAY(4); 303 } 304 305 static int 306 ns8250_rxready(struct uart_bas *bas) 307 { 308 309 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 310 } 311 312 static int 313 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 314 { 315 int c; 316 317 uart_lock(hwmtx); 318 319 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 320 uart_unlock(hwmtx); 321 DELAY(4); 322 uart_lock(hwmtx); 323 } 324 325 c = uart_getreg(bas, REG_DATA); 326 327 uart_unlock(hwmtx); 328 329 return (c); 330 } 331 332 /* 333 * High-level UART interface. 334 */ 335 struct ns8250_softc { 336 struct uart_softc base; 337 uint8_t fcr; 338 uint8_t ier; 339 uint8_t mcr; 340 341 uint8_t ier_mask; 342 uint8_t ier_rxbits; 343 }; 344 345 static int ns8250_bus_attach(struct uart_softc *); 346 static int ns8250_bus_detach(struct uart_softc *); 347 static int ns8250_bus_flush(struct uart_softc *, int); 348 static int ns8250_bus_getsig(struct uart_softc *); 349 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 350 static int ns8250_bus_ipend(struct uart_softc *); 351 static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 352 static int ns8250_bus_probe(struct uart_softc *); 353 static int ns8250_bus_receive(struct uart_softc *); 354 static int ns8250_bus_setsig(struct uart_softc *, int); 355 static int ns8250_bus_transmit(struct uart_softc *); 356 357 static kobj_method_t ns8250_methods[] = { 358 KOBJMETHOD(uart_attach, ns8250_bus_attach), 359 KOBJMETHOD(uart_detach, ns8250_bus_detach), 360 KOBJMETHOD(uart_flush, ns8250_bus_flush), 361 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 362 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 363 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 364 KOBJMETHOD(uart_param, ns8250_bus_param), 365 KOBJMETHOD(uart_probe, ns8250_bus_probe), 366 KOBJMETHOD(uart_receive, ns8250_bus_receive), 367 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 368 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 369 { 0, 0 } 370 }; 371 372 struct uart_class uart_ns8250_class = { 373 "ns8250", 374 ns8250_methods, 375 sizeof(struct ns8250_softc), 376 .uc_ops = &uart_ns8250_ops, 377 .uc_range = 8, 378 .uc_rclk = DEFAULT_RCLK 379 }; 380 381 #define SIGCHG(c, i, s, d) \ 382 if (c) { \ 383 i |= (i & s) ? s : s | d; \ 384 } else { \ 385 i = (i & s) ? (i & ~s) | d : i; \ 386 } 387 388 static int 389 ns8250_bus_attach(struct uart_softc *sc) 390 { 391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 392 struct uart_bas *bas; 393 unsigned int ivar; 394 395 bas = &sc->sc_bas; 396 397 ns8250->mcr = uart_getreg(bas, REG_MCR); 398 ns8250->fcr = FCR_ENABLE; 399 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 400 &ivar)) { 401 if (UART_FLAGS_FCR_RX_LOW(ivar)) 402 ns8250->fcr |= FCR_RX_LOW; 403 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 404 ns8250->fcr |= FCR_RX_MEDL; 405 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 406 ns8250->fcr |= FCR_RX_HIGH; 407 else 408 ns8250->fcr |= FCR_RX_MEDH; 409 } else 410 ns8250->fcr |= FCR_RX_MEDH; 411 412 /* Get IER mask */ 413 ivar = 0xf0; 414 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 415 &ivar); 416 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 417 418 /* Get IER RX interrupt bits */ 419 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 420 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 421 &ivar); 422 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 423 424 uart_setreg(bas, REG_FCR, ns8250->fcr); 425 uart_barrier(bas); 426 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 427 428 if (ns8250->mcr & MCR_DTR) 429 sc->sc_hwsig |= SER_DTR; 430 if (ns8250->mcr & MCR_RTS) 431 sc->sc_hwsig |= SER_RTS; 432 ns8250_bus_getsig(sc); 433 434 ns8250_clrint(bas); 435 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 436 ns8250->ier |= ns8250->ier_rxbits; 437 uart_setreg(bas, REG_IER, ns8250->ier); 438 uart_barrier(bas); 439 440 return (0); 441 } 442 443 static int 444 ns8250_bus_detach(struct uart_softc *sc) 445 { 446 struct ns8250_softc *ns8250; 447 struct uart_bas *bas; 448 u_char ier; 449 450 ns8250 = (struct ns8250_softc *)sc; 451 bas = &sc->sc_bas; 452 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 453 uart_setreg(bas, REG_IER, ier); 454 uart_barrier(bas); 455 ns8250_clrint(bas); 456 return (0); 457 } 458 459 static int 460 ns8250_bus_flush(struct uart_softc *sc, int what) 461 { 462 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 463 struct uart_bas *bas; 464 int error; 465 466 bas = &sc->sc_bas; 467 uart_lock(sc->sc_hwmtx); 468 if (sc->sc_rxfifosz > 1) { 469 ns8250_flush(bas, what); 470 uart_setreg(bas, REG_FCR, ns8250->fcr); 471 uart_barrier(bas); 472 error = 0; 473 } else 474 error = ns8250_drain(bas, what); 475 uart_unlock(sc->sc_hwmtx); 476 return (error); 477 } 478 479 static int 480 ns8250_bus_getsig(struct uart_softc *sc) 481 { 482 uint32_t new, old, sig; 483 uint8_t msr; 484 485 do { 486 old = sc->sc_hwsig; 487 sig = old; 488 uart_lock(sc->sc_hwmtx); 489 msr = uart_getreg(&sc->sc_bas, REG_MSR); 490 uart_unlock(sc->sc_hwmtx); 491 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 492 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 493 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 494 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 495 new = sig & ~SER_MASK_DELTA; 496 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 497 return (sig); 498 } 499 500 static int 501 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 502 { 503 struct uart_bas *bas; 504 int baudrate, divisor, error; 505 uint8_t efr, lcr; 506 507 bas = &sc->sc_bas; 508 error = 0; 509 uart_lock(sc->sc_hwmtx); 510 switch (request) { 511 case UART_IOCTL_BREAK: 512 lcr = uart_getreg(bas, REG_LCR); 513 if (data) 514 lcr |= LCR_SBREAK; 515 else 516 lcr &= ~LCR_SBREAK; 517 uart_setreg(bas, REG_LCR, lcr); 518 uart_barrier(bas); 519 break; 520 case UART_IOCTL_IFLOW: 521 lcr = uart_getreg(bas, REG_LCR); 522 uart_barrier(bas); 523 uart_setreg(bas, REG_LCR, 0xbf); 524 uart_barrier(bas); 525 efr = uart_getreg(bas, REG_EFR); 526 if (data) 527 efr |= EFR_RTS; 528 else 529 efr &= ~EFR_RTS; 530 uart_setreg(bas, REG_EFR, efr); 531 uart_barrier(bas); 532 uart_setreg(bas, REG_LCR, lcr); 533 uart_barrier(bas); 534 break; 535 case UART_IOCTL_OFLOW: 536 lcr = uart_getreg(bas, REG_LCR); 537 uart_barrier(bas); 538 uart_setreg(bas, REG_LCR, 0xbf); 539 uart_barrier(bas); 540 efr = uart_getreg(bas, REG_EFR); 541 if (data) 542 efr |= EFR_CTS; 543 else 544 efr &= ~EFR_CTS; 545 uart_setreg(bas, REG_EFR, efr); 546 uart_barrier(bas); 547 uart_setreg(bas, REG_LCR, lcr); 548 uart_barrier(bas); 549 break; 550 case UART_IOCTL_BAUD: 551 lcr = uart_getreg(bas, REG_LCR); 552 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 553 uart_barrier(bas); 554 divisor = uart_getreg(bas, REG_DLL) | 555 (uart_getreg(bas, REG_DLH) << 8); 556 uart_barrier(bas); 557 uart_setreg(bas, REG_LCR, lcr); 558 uart_barrier(bas); 559 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 560 if (baudrate > 0) 561 *(int*)data = baudrate; 562 else 563 error = ENXIO; 564 break; 565 default: 566 error = EINVAL; 567 break; 568 } 569 uart_unlock(sc->sc_hwmtx); 570 return (error); 571 } 572 573 static int 574 ns8250_bus_ipend(struct uart_softc *sc) 575 { 576 struct uart_bas *bas; 577 int ipend; 578 uint8_t iir, lsr; 579 580 bas = &sc->sc_bas; 581 uart_lock(sc->sc_hwmtx); 582 iir = uart_getreg(bas, REG_IIR); 583 if (iir & IIR_NOPEND) { 584 uart_unlock(sc->sc_hwmtx); 585 return (0); 586 } 587 ipend = 0; 588 if (iir & IIR_RXRDY) { 589 lsr = uart_getreg(bas, REG_LSR); 590 uart_unlock(sc->sc_hwmtx); 591 if (lsr & LSR_OE) 592 ipend |= SER_INT_OVERRUN; 593 if (lsr & LSR_BI) 594 ipend |= SER_INT_BREAK; 595 if (lsr & LSR_RXRDY) 596 ipend |= SER_INT_RXREADY; 597 } else { 598 uart_unlock(sc->sc_hwmtx); 599 if (iir & IIR_TXRDY) 600 ipend |= SER_INT_TXIDLE; 601 else 602 ipend |= SER_INT_SIGCHG; 603 } 604 return ((sc->sc_leaving) ? 0 : ipend); 605 } 606 607 static int 608 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 609 int stopbits, int parity) 610 { 611 struct uart_bas *bas; 612 int error; 613 614 bas = &sc->sc_bas; 615 uart_lock(sc->sc_hwmtx); 616 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 617 uart_unlock(sc->sc_hwmtx); 618 return (error); 619 } 620 621 static int 622 ns8250_bus_probe(struct uart_softc *sc) 623 { 624 struct ns8250_softc *ns8250; 625 struct uart_bas *bas; 626 int count, delay, error, limit; 627 uint8_t lsr, mcr, ier; 628 629 ns8250 = (struct ns8250_softc *)sc; 630 bas = &sc->sc_bas; 631 632 error = ns8250_probe(bas); 633 if (error) 634 return (error); 635 636 mcr = MCR_IE; 637 if (sc->sc_sysdev == NULL) { 638 /* By using ns8250_init() we also set DTR and RTS. */ 639 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 640 } else 641 mcr |= MCR_DTR | MCR_RTS; 642 643 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 644 if (error) 645 return (error); 646 647 /* 648 * Set loopback mode. This avoids having garbage on the wire and 649 * also allows us send and receive data. We set DTR and RTS to 650 * avoid the possibility that automatic flow-control prevents 651 * any data from being sent. 652 */ 653 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 654 uart_barrier(bas); 655 656 /* 657 * Enable FIFOs. And check that the UART has them. If not, we're 658 * done. Since this is the first time we enable the FIFOs, we reset 659 * them. 660 */ 661 uart_setreg(bas, REG_FCR, FCR_ENABLE); 662 uart_barrier(bas); 663 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 664 /* 665 * NS16450 or INS8250. We don't bother to differentiate 666 * between them. They're too old to be interesting. 667 */ 668 uart_setreg(bas, REG_MCR, mcr); 669 uart_barrier(bas); 670 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 671 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 672 return (0); 673 } 674 675 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 676 uart_barrier(bas); 677 678 count = 0; 679 delay = ns8250_delay(bas); 680 681 /* We have FIFOs. Drain the transmitter and receiver. */ 682 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 683 if (error) { 684 uart_setreg(bas, REG_MCR, mcr); 685 uart_setreg(bas, REG_FCR, 0); 686 uart_barrier(bas); 687 goto describe; 688 } 689 690 /* 691 * We should have a sufficiently clean "pipe" to determine the 692 * size of the FIFOs. We send as much characters as is reasonable 693 * and wait for the the overflow bit in the LSR register to be 694 * asserted, counting the characters as we send them. Based on 695 * that count we know the FIFO size. 696 */ 697 do { 698 uart_setreg(bas, REG_DATA, 0); 699 uart_barrier(bas); 700 count++; 701 702 limit = 30; 703 lsr = 0; 704 /* 705 * LSR bits are cleared upon read, so we must accumulate 706 * them to be able to test LSR_OE below. 707 */ 708 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 709 --limit) 710 DELAY(delay); 711 if (limit == 0) { 712 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 713 uart_setreg(bas, REG_IER, ier); 714 uart_setreg(bas, REG_MCR, mcr); 715 uart_setreg(bas, REG_FCR, 0); 716 uart_barrier(bas); 717 count = 0; 718 goto describe; 719 } 720 } while ((lsr & LSR_OE) == 0 && count < 130); 721 count--; 722 723 uart_setreg(bas, REG_MCR, mcr); 724 725 /* Reset FIFOs. */ 726 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 727 728 describe: 729 if (count >= 14 && count <= 16) { 730 sc->sc_rxfifosz = 16; 731 device_set_desc(sc->sc_dev, "16550 or compatible"); 732 } else if (count >= 28 && count <= 32) { 733 sc->sc_rxfifosz = 32; 734 device_set_desc(sc->sc_dev, "16650 or compatible"); 735 } else if (count >= 56 && count <= 64) { 736 sc->sc_rxfifosz = 64; 737 device_set_desc(sc->sc_dev, "16750 or compatible"); 738 } else if (count >= 112 && count <= 128) { 739 sc->sc_rxfifosz = 128; 740 device_set_desc(sc->sc_dev, "16950 or compatible"); 741 } else { 742 sc->sc_rxfifosz = 16; 743 device_set_desc(sc->sc_dev, 744 "Non-standard ns8250 class UART with FIFOs"); 745 } 746 747 /* 748 * Force the Tx FIFO size to 16 bytes for now. We don't program the 749 * Tx trigger. Also, we assume that all data has been sent when the 750 * interrupt happens. 751 */ 752 sc->sc_txfifosz = 16; 753 754 #if 0 755 /* 756 * XXX there are some issues related to hardware flow control and 757 * it's likely that uart(4) is the cause. This basicly needs more 758 * investigation, but we avoid using for hardware flow control 759 * until then. 760 */ 761 /* 16650s or higher have automatic flow control. */ 762 if (sc->sc_rxfifosz > 16) { 763 sc->sc_hwiflow = 1; 764 sc->sc_hwoflow = 1; 765 } 766 #endif 767 768 return (0); 769 } 770 771 static int 772 ns8250_bus_receive(struct uart_softc *sc) 773 { 774 struct uart_bas *bas; 775 int xc; 776 uint8_t lsr; 777 778 bas = &sc->sc_bas; 779 uart_lock(sc->sc_hwmtx); 780 lsr = uart_getreg(bas, REG_LSR); 781 while (lsr & LSR_RXRDY) { 782 if (uart_rx_full(sc)) { 783 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 784 break; 785 } 786 xc = uart_getreg(bas, REG_DATA); 787 if (lsr & LSR_FE) 788 xc |= UART_STAT_FRAMERR; 789 if (lsr & LSR_PE) 790 xc |= UART_STAT_PARERR; 791 uart_rx_put(sc, xc); 792 lsr = uart_getreg(bas, REG_LSR); 793 } 794 /* Discard everything left in the Rx FIFO. */ 795 while (lsr & LSR_RXRDY) { 796 (void)uart_getreg(bas, REG_DATA); 797 uart_barrier(bas); 798 lsr = uart_getreg(bas, REG_LSR); 799 } 800 uart_unlock(sc->sc_hwmtx); 801 return (0); 802 } 803 804 static int 805 ns8250_bus_setsig(struct uart_softc *sc, int sig) 806 { 807 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 808 struct uart_bas *bas; 809 uint32_t new, old; 810 811 bas = &sc->sc_bas; 812 do { 813 old = sc->sc_hwsig; 814 new = old; 815 if (sig & SER_DDTR) { 816 SIGCHG(sig & SER_DTR, new, SER_DTR, 817 SER_DDTR); 818 } 819 if (sig & SER_DRTS) { 820 SIGCHG(sig & SER_RTS, new, SER_RTS, 821 SER_DRTS); 822 } 823 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 824 uart_lock(sc->sc_hwmtx); 825 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 826 if (new & SER_DTR) 827 ns8250->mcr |= MCR_DTR; 828 if (new & SER_RTS) 829 ns8250->mcr |= MCR_RTS; 830 uart_setreg(bas, REG_MCR, ns8250->mcr); 831 uart_barrier(bas); 832 uart_unlock(sc->sc_hwmtx); 833 return (0); 834 } 835 836 static int 837 ns8250_bus_transmit(struct uart_softc *sc) 838 { 839 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 840 struct uart_bas *bas; 841 int i; 842 843 bas = &sc->sc_bas; 844 uart_lock(sc->sc_hwmtx); 845 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 846 ; 847 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 848 uart_barrier(bas); 849 for (i = 0; i < sc->sc_txdatasz; i++) { 850 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 851 uart_barrier(bas); 852 } 853 sc->sc_txbusy = 1; 854 uart_unlock(sc->sc_hwmtx); 855 return (0); 856 } 857