1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #endif 49 50 #include <dev/uart/uart.h> 51 #include <dev/uart/uart_cpu.h> 52 #ifdef FDT 53 #include <dev/uart/uart_cpu_fdt.h> 54 #endif 55 #include <dev/uart/uart_bus.h> 56 #include <dev/uart/uart_dev_ns8250.h> 57 #include <dev/uart/uart_ppstypes.h> 58 #ifdef DEV_ACPI 59 #include <dev/uart/uart_cpu_acpi.h> 60 #include <contrib/dev/acpica/include/acpi.h> 61 #endif 62 63 #include <dev/ic/ns16550.h> 64 65 #include "uart_if.h" 66 67 #define DEFAULT_RCLK 1843200 68 69 /* 70 * Set the default baudrate tolerance to 3.0%. 71 * 72 * Some embedded boards have odd reference clocks (eg 25MHz) 73 * and we need to handle higher variances in the target baud rate. 74 */ 75 #ifndef UART_DEV_TOLERANCE_PCT 76 #define UART_DEV_TOLERANCE_PCT 30 77 #endif /* UART_DEV_TOLERANCE_PCT */ 78 79 static int broken_txfifo = 0; 80 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 81 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 82 83 /* 84 * Clear pending interrupts. THRE is cleared by reading IIR. Data 85 * that may have been received gets lost here. 86 */ 87 static void 88 ns8250_clrint(struct uart_bas *bas) 89 { 90 uint8_t iir, lsr; 91 92 iir = uart_getreg(bas, REG_IIR); 93 while ((iir & IIR_NOPEND) == 0) { 94 iir &= IIR_IMASK; 95 if (iir == IIR_RLS) { 96 lsr = uart_getreg(bas, REG_LSR); 97 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 98 (void)uart_getreg(bas, REG_DATA); 99 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 100 (void)uart_getreg(bas, REG_DATA); 101 else if (iir == IIR_MLSC) 102 (void)uart_getreg(bas, REG_MSR); 103 uart_barrier(bas); 104 iir = uart_getreg(bas, REG_IIR); 105 } 106 } 107 108 static int 109 ns8250_delay(struct uart_bas *bas) 110 { 111 int divisor; 112 u_char lcr; 113 114 lcr = uart_getreg(bas, REG_LCR); 115 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 116 uart_barrier(bas); 117 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 118 uart_barrier(bas); 119 uart_setreg(bas, REG_LCR, lcr); 120 uart_barrier(bas); 121 122 /* 1/10th the time to transmit 1 character (estimate). */ 123 if (divisor <= 134) 124 return (16000000 * divisor / bas->rclk); 125 return (16000 * divisor / (bas->rclk / 1000)); 126 } 127 128 static int 129 ns8250_divisor(int rclk, int baudrate) 130 { 131 int actual_baud, divisor; 132 int error; 133 134 if (baudrate == 0) 135 return (0); 136 137 divisor = (rclk / (baudrate << 3) + 1) >> 1; 138 if (divisor == 0 || divisor >= 65536) 139 return (0); 140 actual_baud = rclk / (divisor << 4); 141 142 /* 10 times error in percent: */ 143 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 144 145 /* enforce maximum error tolerance: */ 146 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 147 return (0); 148 149 return (divisor); 150 } 151 152 static int 153 ns8250_drain(struct uart_bas *bas, int what) 154 { 155 int delay, limit; 156 157 delay = ns8250_delay(bas); 158 159 if (what & UART_DRAIN_TRANSMITTER) { 160 /* 161 * Pick an arbitrary high limit to avoid getting stuck in 162 * an infinite loop when the hardware is broken. Make the 163 * limit high enough to handle large FIFOs. 164 */ 165 limit = 10*1024; 166 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 167 DELAY(delay); 168 if (limit == 0) { 169 /* printf("ns8250: transmitter appears stuck... "); */ 170 return (EIO); 171 } 172 } 173 174 if (what & UART_DRAIN_RECEIVER) { 175 /* 176 * Pick an arbitrary high limit to avoid getting stuck in 177 * an infinite loop when the hardware is broken. Make the 178 * limit high enough to handle large FIFOs and integrated 179 * UARTs. The HP rx2600 for example has 3 UARTs on the 180 * management board that tend to get a lot of data send 181 * to it when the UART is first activated. Assume that we 182 * have finished draining if LSR_RXRDY is not asserted both 183 * prior to and after a DELAY; but as long as LSR_RXRDY is 184 * asserted, read (and discard) characters as quickly as 185 * possible. 186 */ 187 limit=10*4096; 188 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 189 do { 190 (void)uart_getreg(bas, REG_DATA); 191 uart_barrier(bas); 192 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 193 uart_barrier(bas); 194 DELAY(delay << 2); 195 } 196 if (limit == 0) { 197 /* printf("ns8250: receiver appears broken... "); */ 198 return (EIO); 199 } 200 } 201 202 return (0); 203 } 204 205 /* 206 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 207 * drained. WARNING: this function clobbers the FIFO setting! 208 */ 209 static void 210 ns8250_flush(struct uart_bas *bas, int what) 211 { 212 uint8_t fcr; 213 uint8_t lsr; 214 int drain = 0; 215 216 fcr = FCR_ENABLE; 217 #ifdef CPU_XBURST 218 fcr |= FCR_UART_ON; 219 #endif 220 if (what & UART_FLUSH_TRANSMITTER) 221 fcr |= FCR_XMT_RST; 222 if (what & UART_FLUSH_RECEIVER) 223 fcr |= FCR_RCV_RST; 224 uart_setreg(bas, REG_FCR, fcr); 225 uart_barrier(bas); 226 227 /* 228 * Detect and work around emulated UARTs which don't implement the 229 * FCR register; on these systems we need to drain the FIFO since 230 * the flush we request doesn't happen. One such system is the 231 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 232 * https://github.com/rust-vmm/vm-superio/issues/83 233 */ 234 lsr = uart_getreg(bas, REG_LSR); 235 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 236 drain |= UART_DRAIN_TRANSMITTER; 237 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 238 drain |= UART_DRAIN_RECEIVER; 239 if (drain != 0) { 240 printf("ns8250: UART FCR is broken\n"); 241 ns8250_drain(bas, drain); 242 } 243 } 244 245 static int 246 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 247 int parity) 248 { 249 int divisor; 250 uint8_t lcr; 251 252 /* Don't change settings when running on Hyper-V */ 253 if (vm_guest == VM_GUEST_HV) 254 return (0); 255 256 lcr = 0; 257 if (databits >= 8) 258 lcr |= LCR_8BITS; 259 else if (databits == 7) 260 lcr |= LCR_7BITS; 261 else if (databits == 6) 262 lcr |= LCR_6BITS; 263 else 264 lcr |= LCR_5BITS; 265 if (stopbits > 1) 266 lcr |= LCR_STOPB; 267 lcr |= parity << 3; 268 269 /* Set baudrate. */ 270 if (baudrate > 0) { 271 divisor = ns8250_divisor(bas->rclk, baudrate); 272 if (divisor == 0) 273 return (EINVAL); 274 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 275 uart_barrier(bas); 276 uart_setreg(bas, REG_DLL, divisor & 0xff); 277 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 278 uart_barrier(bas); 279 } 280 281 /* Set LCR and clear DLAB. */ 282 uart_setreg(bas, REG_LCR, lcr); 283 uart_barrier(bas); 284 return (0); 285 } 286 287 /* 288 * Low-level UART interface. 289 */ 290 static int ns8250_probe(struct uart_bas *bas); 291 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 292 static void ns8250_term(struct uart_bas *bas); 293 static void ns8250_putc(struct uart_bas *bas, int); 294 static int ns8250_rxready(struct uart_bas *bas); 295 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 296 297 struct uart_ops uart_ns8250_ops = { 298 .probe = ns8250_probe, 299 .init = ns8250_init, 300 .term = ns8250_term, 301 .putc = ns8250_putc, 302 .rxready = ns8250_rxready, 303 .getc = ns8250_getc, 304 }; 305 306 static int 307 ns8250_probe(struct uart_bas *bas) 308 { 309 u_char val; 310 311 #ifdef CPU_XBURST 312 uart_setreg(bas, REG_FCR, FCR_UART_ON); 313 #endif 314 315 /* Check known 0 bits that don't depend on DLAB. */ 316 val = uart_getreg(bas, REG_IIR); 317 if (val & 0x30) 318 return (ENXIO); 319 /* 320 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 321 * chip, but otherwise doesn't seem to have a function. In 322 * other words, uart(4) works regardless. Ignore that bit so 323 * the probe succeeds. 324 */ 325 val = uart_getreg(bas, REG_MCR); 326 if (val & 0xa0) 327 return (ENXIO); 328 329 return (0); 330 } 331 332 static void 333 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 334 int parity) 335 { 336 u_char ier, val; 337 338 if (bas->rclk == 0) 339 bas->rclk = DEFAULT_RCLK; 340 ns8250_param(bas, baudrate, databits, stopbits, parity); 341 342 /* Disable all interrupt sources. */ 343 /* 344 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 345 * UARTs split the receive time-out interrupt bit out separately as 346 * 0x10. This gets handled by ier_mask and ier_rxbits below. 347 */ 348 ier = uart_getreg(bas, REG_IER) & 0xe0; 349 uart_setreg(bas, REG_IER, ier); 350 uart_barrier(bas); 351 352 /* Disable the FIFO (if present). */ 353 val = 0; 354 #ifdef CPU_XBURST 355 val |= FCR_UART_ON; 356 #endif 357 uart_setreg(bas, REG_FCR, val); 358 uart_barrier(bas); 359 360 /* Set RTS & DTR. */ 361 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 362 uart_barrier(bas); 363 364 ns8250_clrint(bas); 365 } 366 367 static void 368 ns8250_term(struct uart_bas *bas) 369 { 370 371 /* Clear RTS & DTR. */ 372 uart_setreg(bas, REG_MCR, MCR_IE); 373 uart_barrier(bas); 374 } 375 376 static void 377 ns8250_putc(struct uart_bas *bas, int c) 378 { 379 int limit; 380 381 if (vm_guest != VM_GUEST_HV) { 382 limit = 250000; 383 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 384 DELAY(4); 385 } 386 uart_setreg(bas, REG_DATA, c); 387 uart_barrier(bas); 388 } 389 390 static int 391 ns8250_rxready(struct uart_bas *bas) 392 { 393 394 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 395 } 396 397 static int 398 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 399 { 400 int c; 401 402 uart_lock(hwmtx); 403 404 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 405 uart_unlock(hwmtx); 406 DELAY(4); 407 uart_lock(hwmtx); 408 } 409 410 c = uart_getreg(bas, REG_DATA); 411 412 uart_unlock(hwmtx); 413 414 return (c); 415 } 416 417 static kobj_method_t ns8250_methods[] = { 418 KOBJMETHOD(uart_attach, ns8250_bus_attach), 419 KOBJMETHOD(uart_detach, ns8250_bus_detach), 420 KOBJMETHOD(uart_flush, ns8250_bus_flush), 421 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 422 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 423 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 424 KOBJMETHOD(uart_param, ns8250_bus_param), 425 KOBJMETHOD(uart_probe, ns8250_bus_probe), 426 KOBJMETHOD(uart_receive, ns8250_bus_receive), 427 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 428 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 429 KOBJMETHOD(uart_grab, ns8250_bus_grab), 430 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 431 { 0, 0 } 432 }; 433 434 struct uart_class uart_ns8250_class = { 435 "ns8250", 436 ns8250_methods, 437 sizeof(struct ns8250_softc), 438 .uc_ops = &uart_ns8250_ops, 439 .uc_range = 8, 440 .uc_rclk = DEFAULT_RCLK, 441 .uc_rshift = 0 442 }; 443 444 /* 445 * XXX -- refactor out ACPI and FDT ifdefs 446 */ 447 #ifdef DEV_ACPI 448 static struct acpi_uart_compat_data acpi_compat_data[] = { 449 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 450 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 451 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 452 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 453 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 454 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 455 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 456 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 457 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 458 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 459 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 460 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 461 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 462 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 463 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 464 }; 465 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 466 #endif 467 468 #ifdef FDT 469 static struct ofw_compat_data compat_data[] = { 470 {"ns16550", (uintptr_t)&uart_ns8250_class}, 471 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 472 {NULL, (uintptr_t)NULL}, 473 }; 474 UART_FDT_CLASS_AND_DEVICE(compat_data); 475 #endif 476 477 /* Use token-pasting to form SER_ and MSR_ named constants. */ 478 #define SER(sig) SER_##sig 479 #define SERD(sig) SER_D##sig 480 #define MSR(sig) MSR_##sig 481 #define MSRD(sig) MSR_D##sig 482 483 /* 484 * Detect signal changes using software delta detection. The previous state of 485 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 486 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 487 * new state of both the signal and the delta bits. 488 */ 489 #define SIGCHGSW(var, msr, sig) \ 490 if ((msr) & MSR(sig)) { \ 491 if ((var & SER(sig)) == 0) \ 492 var |= SERD(sig) | SER(sig); \ 493 } else { \ 494 if ((var & SER(sig)) != 0) \ 495 var = SERD(sig) | (var & ~SER(sig)); \ 496 } 497 498 /* 499 * Detect signal changes using the hardware msr delta bits. This is currently 500 * used only when PPS timing information is being captured using the "narrow 501 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 502 * by time the interrupt handler is invoked. The hardware will latch the fact 503 * that it changed in the delta bits. 504 */ 505 #define SIGCHGHW(var, msr, sig) \ 506 if ((msr) & MSRD(sig)) { \ 507 if (((msr) & MSR(sig)) != 0) \ 508 var |= SERD(sig) | SER(sig); \ 509 else \ 510 var = SERD(sig) | (var & ~SER(sig)); \ 511 } 512 513 int 514 ns8250_bus_attach(struct uart_softc *sc) 515 { 516 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 517 struct uart_bas *bas; 518 unsigned int ivar; 519 #ifdef FDT 520 phandle_t node; 521 pcell_t cell; 522 #endif 523 524 #ifdef FDT 525 /* Check whether uart has a broken txfifo. */ 526 node = ofw_bus_get_node(sc->sc_dev); 527 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 528 broken_txfifo = cell ? 1 : 0; 529 #endif 530 531 bas = &sc->sc_bas; 532 533 ns8250->busy_detect = bas->busy_detect; 534 ns8250->mcr = uart_getreg(bas, REG_MCR); 535 ns8250->fcr = FCR_ENABLE; 536 #ifdef CPU_XBURST 537 ns8250->fcr |= FCR_UART_ON; 538 #endif 539 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 540 &ivar)) { 541 if (UART_FLAGS_FCR_RX_LOW(ivar)) 542 ns8250->fcr |= FCR_RX_LOW; 543 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 544 ns8250->fcr |= FCR_RX_MEDL; 545 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 546 ns8250->fcr |= FCR_RX_HIGH; 547 else 548 ns8250->fcr |= FCR_RX_MEDH; 549 } else 550 ns8250->fcr |= FCR_RX_MEDH; 551 552 /* Get IER mask */ 553 ivar = 0xf0; 554 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 555 &ivar); 556 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 557 558 /* Get IER RX interrupt bits */ 559 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 560 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 561 &ivar); 562 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 563 564 uart_setreg(bas, REG_FCR, ns8250->fcr); 565 uart_barrier(bas); 566 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 567 568 if (ns8250->mcr & MCR_DTR) 569 sc->sc_hwsig |= SER_DTR; 570 if (ns8250->mcr & MCR_RTS) 571 sc->sc_hwsig |= SER_RTS; 572 ns8250_bus_getsig(sc); 573 574 ns8250_clrint(bas); 575 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 576 ns8250->ier |= ns8250->ier_rxbits; 577 uart_setreg(bas, REG_IER, ns8250->ier); 578 uart_barrier(bas); 579 580 /* 581 * Timing of the H/W access was changed with r253161 of uart_core.c 582 * It has been observed that an ITE IT8513E would signal a break 583 * condition with pretty much every character it received, unless 584 * it had enough time to settle between ns8250_bus_attach() and 585 * ns8250_bus_ipend() -- which it accidentally had before r253161. 586 * It's not understood why the UART chip behaves this way and it 587 * could very well be that the DELAY make the H/W work in the same 588 * accidental manner as before. More analysis is warranted, but 589 * at least now we fixed a known regression. 590 */ 591 DELAY(200); 592 return (0); 593 } 594 595 int 596 ns8250_bus_detach(struct uart_softc *sc) 597 { 598 struct ns8250_softc *ns8250; 599 struct uart_bas *bas; 600 u_char ier; 601 602 ns8250 = (struct ns8250_softc *)sc; 603 bas = &sc->sc_bas; 604 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 605 uart_setreg(bas, REG_IER, ier); 606 uart_barrier(bas); 607 ns8250_clrint(bas); 608 return (0); 609 } 610 611 int 612 ns8250_bus_flush(struct uart_softc *sc, int what) 613 { 614 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 615 struct uart_bas *bas; 616 int error; 617 618 bas = &sc->sc_bas; 619 uart_lock(sc->sc_hwmtx); 620 if (sc->sc_rxfifosz > 1) { 621 ns8250_flush(bas, what); 622 uart_setreg(bas, REG_FCR, ns8250->fcr); 623 uart_barrier(bas); 624 error = 0; 625 } else 626 error = ns8250_drain(bas, what); 627 uart_unlock(sc->sc_hwmtx); 628 return (error); 629 } 630 631 int 632 ns8250_bus_getsig(struct uart_softc *sc) 633 { 634 uint32_t old, sig; 635 uint8_t msr; 636 637 /* 638 * The delta bits are reputed to be broken on some hardware, so use 639 * software delta detection by default. Use the hardware delta bits 640 * when capturing PPS pulses which are too narrow for software detection 641 * to see the edges. Hardware delta for RI doesn't work like the 642 * others, so always use software for it. Other threads may be changing 643 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 644 * update without other changes happening. Note that the SIGCHGxx() 645 * macros carefully preserve the delta bits when we have to loop several 646 * times and a signal transitions between iterations. 647 */ 648 do { 649 old = sc->sc_hwsig; 650 sig = old; 651 uart_lock(sc->sc_hwmtx); 652 msr = uart_getreg(&sc->sc_bas, REG_MSR); 653 uart_unlock(sc->sc_hwmtx); 654 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 655 SIGCHGHW(sig, msr, DSR); 656 SIGCHGHW(sig, msr, CTS); 657 SIGCHGHW(sig, msr, DCD); 658 } else { 659 SIGCHGSW(sig, msr, DSR); 660 SIGCHGSW(sig, msr, CTS); 661 SIGCHGSW(sig, msr, DCD); 662 } 663 SIGCHGSW(sig, msr, RI); 664 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 665 return (sig); 666 } 667 668 int 669 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 670 { 671 struct uart_bas *bas; 672 int baudrate, divisor, error; 673 uint8_t efr, lcr; 674 675 bas = &sc->sc_bas; 676 error = 0; 677 uart_lock(sc->sc_hwmtx); 678 switch (request) { 679 case UART_IOCTL_BREAK: 680 lcr = uart_getreg(bas, REG_LCR); 681 if (data) 682 lcr |= LCR_SBREAK; 683 else 684 lcr &= ~LCR_SBREAK; 685 uart_setreg(bas, REG_LCR, lcr); 686 uart_barrier(bas); 687 break; 688 case UART_IOCTL_IFLOW: 689 lcr = uart_getreg(bas, REG_LCR); 690 uart_barrier(bas); 691 uart_setreg(bas, REG_LCR, 0xbf); 692 uart_barrier(bas); 693 efr = uart_getreg(bas, REG_EFR); 694 if (data) 695 efr |= EFR_RTS; 696 else 697 efr &= ~EFR_RTS; 698 uart_setreg(bas, REG_EFR, efr); 699 uart_barrier(bas); 700 uart_setreg(bas, REG_LCR, lcr); 701 uart_barrier(bas); 702 break; 703 case UART_IOCTL_OFLOW: 704 lcr = uart_getreg(bas, REG_LCR); 705 uart_barrier(bas); 706 uart_setreg(bas, REG_LCR, 0xbf); 707 uart_barrier(bas); 708 efr = uart_getreg(bas, REG_EFR); 709 if (data) 710 efr |= EFR_CTS; 711 else 712 efr &= ~EFR_CTS; 713 uart_setreg(bas, REG_EFR, efr); 714 uart_barrier(bas); 715 uart_setreg(bas, REG_LCR, lcr); 716 uart_barrier(bas); 717 break; 718 case UART_IOCTL_BAUD: 719 lcr = uart_getreg(bas, REG_LCR); 720 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 721 uart_barrier(bas); 722 divisor = uart_getreg(bas, REG_DLL) | 723 (uart_getreg(bas, REG_DLH) << 8); 724 uart_barrier(bas); 725 uart_setreg(bas, REG_LCR, lcr); 726 uart_barrier(bas); 727 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 728 if (baudrate > 0) 729 *(int*)data = baudrate; 730 else 731 error = ENXIO; 732 break; 733 default: 734 error = EINVAL; 735 break; 736 } 737 uart_unlock(sc->sc_hwmtx); 738 return (error); 739 } 740 741 int 742 ns8250_bus_ipend(struct uart_softc *sc) 743 { 744 struct uart_bas *bas; 745 struct ns8250_softc *ns8250; 746 int ipend; 747 uint8_t iir, lsr; 748 749 ns8250 = (struct ns8250_softc *)sc; 750 bas = &sc->sc_bas; 751 uart_lock(sc->sc_hwmtx); 752 iir = uart_getreg(bas, REG_IIR); 753 754 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 755 (void)uart_getreg(bas, DW_REG_USR); 756 uart_unlock(sc->sc_hwmtx); 757 return (0); 758 } 759 if (iir & IIR_NOPEND) { 760 uart_unlock(sc->sc_hwmtx); 761 return (0); 762 } 763 ipend = 0; 764 if (iir & IIR_RXRDY) { 765 lsr = uart_getreg(bas, REG_LSR); 766 if (lsr & LSR_OE) 767 ipend |= SER_INT_OVERRUN; 768 if (lsr & LSR_BI) 769 ipend |= SER_INT_BREAK; 770 if (lsr & LSR_RXRDY) 771 ipend |= SER_INT_RXREADY; 772 } else { 773 if (iir & IIR_TXRDY) { 774 ipend |= SER_INT_TXIDLE; 775 ns8250->ier &= ~IER_ETXRDY; 776 uart_setreg(bas, REG_IER, ns8250->ier); 777 uart_barrier(bas); 778 } else 779 ipend |= SER_INT_SIGCHG; 780 } 781 if (ipend == 0) 782 ns8250_clrint(bas); 783 uart_unlock(sc->sc_hwmtx); 784 return (ipend); 785 } 786 787 int 788 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 789 int stopbits, int parity) 790 { 791 struct ns8250_softc *ns8250; 792 struct uart_bas *bas; 793 int error, limit; 794 795 ns8250 = (struct ns8250_softc*)sc; 796 bas = &sc->sc_bas; 797 uart_lock(sc->sc_hwmtx); 798 /* 799 * When using DW UART with BUSY detection it is necessary to wait 800 * until all serial transfers are finished before manipulating the 801 * line control. LCR will not be affected when UART is busy. 802 */ 803 if (ns8250->busy_detect != 0) { 804 /* 805 * Pick an arbitrary high limit to avoid getting stuck in 806 * an infinite loop in case when the hardware is broken. 807 */ 808 limit = 10 * 1024; 809 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 810 --limit) 811 DELAY(4); 812 813 if (limit <= 0) { 814 /* UART appears to be stuck */ 815 uart_unlock(sc->sc_hwmtx); 816 return (EIO); 817 } 818 } 819 820 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 821 uart_unlock(sc->sc_hwmtx); 822 return (error); 823 } 824 825 int 826 ns8250_bus_probe(struct uart_softc *sc) 827 { 828 struct uart_bas *bas; 829 int count, delay, error, limit; 830 uint8_t lsr, mcr, ier; 831 uint8_t val; 832 833 bas = &sc->sc_bas; 834 835 error = ns8250_probe(bas); 836 if (error) 837 return (error); 838 839 mcr = MCR_IE; 840 if (sc->sc_sysdev == NULL) { 841 /* By using ns8250_init() we also set DTR and RTS. */ 842 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 843 } else 844 mcr |= MCR_DTR | MCR_RTS; 845 846 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 847 if (error) 848 return (error); 849 850 /* 851 * Set loopback mode. This avoids having garbage on the wire and 852 * also allows us send and receive data. We set DTR and RTS to 853 * avoid the possibility that automatic flow-control prevents 854 * any data from being sent. 855 */ 856 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 857 uart_barrier(bas); 858 859 /* 860 * Enable FIFOs. And check that the UART has them. If not, we're 861 * done. Since this is the first time we enable the FIFOs, we reset 862 * them. 863 */ 864 val = FCR_ENABLE; 865 #ifdef CPU_XBURST 866 val |= FCR_UART_ON; 867 #endif 868 uart_setreg(bas, REG_FCR, val); 869 uart_barrier(bas); 870 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 871 /* 872 * NS16450 or INS8250. We don't bother to differentiate 873 * between them. They're too old to be interesting. 874 */ 875 uart_setreg(bas, REG_MCR, mcr); 876 uart_barrier(bas); 877 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 878 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 879 return (0); 880 } 881 882 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 883 #ifdef CPU_XBURST 884 val |= FCR_UART_ON; 885 #endif 886 uart_setreg(bas, REG_FCR, val); 887 uart_barrier(bas); 888 889 count = 0; 890 delay = ns8250_delay(bas); 891 892 /* We have FIFOs. Drain the transmitter and receiver. */ 893 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 894 if (error) { 895 uart_setreg(bas, REG_MCR, mcr); 896 val = 0; 897 #ifdef CPU_XBURST 898 val |= FCR_UART_ON; 899 #endif 900 uart_setreg(bas, REG_FCR, val); 901 uart_barrier(bas); 902 goto describe; 903 } 904 905 /* 906 * We should have a sufficiently clean "pipe" to determine the 907 * size of the FIFOs. We send as much characters as is reasonable 908 * and wait for the overflow bit in the LSR register to be 909 * asserted, counting the characters as we send them. Based on 910 * that count we know the FIFO size. 911 */ 912 do { 913 uart_setreg(bas, REG_DATA, 0); 914 uart_barrier(bas); 915 count++; 916 917 limit = 30; 918 lsr = 0; 919 /* 920 * LSR bits are cleared upon read, so we must accumulate 921 * them to be able to test LSR_OE below. 922 */ 923 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 924 --limit) 925 DELAY(delay); 926 if (limit == 0) { 927 /* See the comment in ns8250_init(). */ 928 ier = uart_getreg(bas, REG_IER) & 0xe0; 929 uart_setreg(bas, REG_IER, ier); 930 uart_setreg(bas, REG_MCR, mcr); 931 val = 0; 932 #ifdef CPU_XBURST 933 val |= FCR_UART_ON; 934 #endif 935 uart_setreg(bas, REG_FCR, val); 936 uart_barrier(bas); 937 count = 0; 938 goto describe; 939 } 940 } while ((lsr & LSR_OE) == 0 && count < 260); 941 count--; 942 943 uart_setreg(bas, REG_MCR, mcr); 944 945 /* Reset FIFOs. */ 946 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 947 948 describe: 949 if (count >= 14 && count <= 16) { 950 sc->sc_rxfifosz = 16; 951 device_set_desc(sc->sc_dev, "16550 or compatible"); 952 } else if (count >= 28 && count <= 32) { 953 sc->sc_rxfifosz = 32; 954 device_set_desc(sc->sc_dev, "16650 or compatible"); 955 } else if (count >= 56 && count <= 64) { 956 sc->sc_rxfifosz = 64; 957 device_set_desc(sc->sc_dev, "16750 or compatible"); 958 } else if (count >= 112 && count <= 128) { 959 sc->sc_rxfifosz = 128; 960 device_set_desc(sc->sc_dev, "16950 or compatible"); 961 } else if (count >= 224 && count <= 256) { 962 sc->sc_rxfifosz = 256; 963 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 964 } else { 965 sc->sc_rxfifosz = 16; 966 device_set_desc(sc->sc_dev, 967 "Non-standard ns8250 class UART with FIFOs"); 968 } 969 970 /* 971 * Force the Tx FIFO size to 16 bytes for now. We don't program the 972 * Tx trigger. Also, we assume that all data has been sent when the 973 * interrupt happens. 974 */ 975 sc->sc_txfifosz = 16; 976 977 #if 0 978 /* 979 * XXX there are some issues related to hardware flow control and 980 * it's likely that uart(4) is the cause. This basically needs more 981 * investigation, but we avoid using for hardware flow control 982 * until then. 983 */ 984 /* 16650s or higher have automatic flow control. */ 985 if (sc->sc_rxfifosz > 16) { 986 sc->sc_hwiflow = 1; 987 sc->sc_hwoflow = 1; 988 } 989 #endif 990 991 return (0); 992 } 993 994 int 995 ns8250_bus_receive(struct uart_softc *sc) 996 { 997 struct uart_bas *bas; 998 int xc; 999 uint8_t lsr; 1000 1001 bas = &sc->sc_bas; 1002 uart_lock(sc->sc_hwmtx); 1003 lsr = uart_getreg(bas, REG_LSR); 1004 while (lsr & LSR_RXRDY) { 1005 if (uart_rx_full(sc)) { 1006 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1007 break; 1008 } 1009 xc = uart_getreg(bas, REG_DATA); 1010 if (lsr & LSR_FE) 1011 xc |= UART_STAT_FRAMERR; 1012 if (lsr & LSR_PE) 1013 xc |= UART_STAT_PARERR; 1014 uart_rx_put(sc, xc); 1015 lsr = uart_getreg(bas, REG_LSR); 1016 } 1017 /* Discard everything left in the Rx FIFO. */ 1018 while (lsr & LSR_RXRDY) { 1019 (void)uart_getreg(bas, REG_DATA); 1020 uart_barrier(bas); 1021 lsr = uart_getreg(bas, REG_LSR); 1022 } 1023 uart_unlock(sc->sc_hwmtx); 1024 return (0); 1025 } 1026 1027 int 1028 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1029 { 1030 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1031 struct uart_bas *bas; 1032 uint32_t new, old; 1033 1034 bas = &sc->sc_bas; 1035 do { 1036 old = sc->sc_hwsig; 1037 new = old; 1038 if (sig & SER_DDTR) { 1039 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1040 } 1041 if (sig & SER_DRTS) { 1042 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1043 } 1044 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1045 uart_lock(sc->sc_hwmtx); 1046 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1047 if (new & SER_DTR) 1048 ns8250->mcr |= MCR_DTR; 1049 if (new & SER_RTS) 1050 ns8250->mcr |= MCR_RTS; 1051 uart_setreg(bas, REG_MCR, ns8250->mcr); 1052 uart_barrier(bas); 1053 uart_unlock(sc->sc_hwmtx); 1054 return (0); 1055 } 1056 1057 int 1058 ns8250_bus_transmit(struct uart_softc *sc) 1059 { 1060 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1061 struct uart_bas *bas; 1062 int i; 1063 1064 bas = &sc->sc_bas; 1065 uart_lock(sc->sc_hwmtx); 1066 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1067 DELAY(4); 1068 for (i = 0; i < sc->sc_txdatasz; i++) { 1069 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1070 uart_barrier(bas); 1071 } 1072 if (!broken_txfifo) 1073 ns8250->ier |= IER_ETXRDY; 1074 uart_setreg(bas, REG_IER, ns8250->ier); 1075 uart_barrier(bas); 1076 if (broken_txfifo) 1077 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1078 else 1079 sc->sc_txbusy = 1; 1080 uart_unlock(sc->sc_hwmtx); 1081 if (broken_txfifo) 1082 uart_sched_softih(sc, SER_INT_TXIDLE); 1083 return (0); 1084 } 1085 1086 void 1087 ns8250_bus_grab(struct uart_softc *sc) 1088 { 1089 struct uart_bas *bas = &sc->sc_bas; 1090 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1091 u_char ier; 1092 1093 /* 1094 * turn off all interrupts to enter polling mode. Leave the 1095 * saved mask alone. We'll restore whatever it was in ungrab. 1096 * All pending interrupt signals are reset when IER is set to 0. 1097 */ 1098 uart_lock(sc->sc_hwmtx); 1099 ier = uart_getreg(bas, REG_IER); 1100 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1101 uart_barrier(bas); 1102 uart_unlock(sc->sc_hwmtx); 1103 } 1104 1105 void 1106 ns8250_bus_ungrab(struct uart_softc *sc) 1107 { 1108 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1109 struct uart_bas *bas = &sc->sc_bas; 1110 1111 /* 1112 * Restore previous interrupt mask 1113 */ 1114 uart_lock(sc->sc_hwmtx); 1115 uart_setreg(bas, REG_IER, ns8250->ier); 1116 uart_barrier(bas); 1117 uart_unlock(sc->sc_hwmtx); 1118 } 1119