1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 #include "opt_uart.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 55 #include <dev/ic/ns16550.h> 56 57 #include "uart_if.h" 58 59 #define DEFAULT_RCLK 1843200 60 61 /* 62 * Set the default baudrate tolerance to 3.0%. 63 * 64 * Some embedded boards have odd reference clocks (eg 25MHz) 65 * and we need to handle higher variances in the target baud rate. 66 */ 67 #ifndef UART_DEV_TOLERANCE_PCT 68 #define UART_DEV_TOLERANCE_PCT 30 69 #endif /* UART_DEV_TOLERANCE_PCT */ 70 71 static int broken_txfifo = 0; 72 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 73 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 74 75 /* 76 * Clear pending interrupts. THRE is cleared by reading IIR. Data 77 * that may have been received gets lost here. 78 */ 79 static void 80 ns8250_clrint(struct uart_bas *bas) 81 { 82 uint8_t iir, lsr; 83 84 iir = uart_getreg(bas, REG_IIR); 85 while ((iir & IIR_NOPEND) == 0) { 86 iir &= IIR_IMASK; 87 if (iir == IIR_RLS) { 88 lsr = uart_getreg(bas, REG_LSR); 89 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 90 (void)uart_getreg(bas, REG_DATA); 91 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 92 (void)uart_getreg(bas, REG_DATA); 93 else if (iir == IIR_MLSC) 94 (void)uart_getreg(bas, REG_MSR); 95 uart_barrier(bas); 96 iir = uart_getreg(bas, REG_IIR); 97 } 98 } 99 100 static int 101 ns8250_delay(struct uart_bas *bas) 102 { 103 int divisor; 104 u_char lcr; 105 106 lcr = uart_getreg(bas, REG_LCR); 107 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 108 uart_barrier(bas); 109 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 110 uart_barrier(bas); 111 uart_setreg(bas, REG_LCR, lcr); 112 uart_barrier(bas); 113 114 /* 1/10th the time to transmit 1 character (estimate). */ 115 if (divisor <= 134) 116 return (16000000 * divisor / bas->rclk); 117 return (16000 * divisor / (bas->rclk / 1000)); 118 } 119 120 static int 121 ns8250_divisor(int rclk, int baudrate) 122 { 123 int actual_baud, divisor; 124 int error; 125 126 if (baudrate == 0) 127 return (0); 128 129 divisor = (rclk / (baudrate << 3) + 1) >> 1; 130 if (divisor == 0 || divisor >= 65536) 131 return (0); 132 actual_baud = rclk / (divisor << 4); 133 134 /* 10 times error in percent: */ 135 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 136 137 /* enforce maximum error tolerance: */ 138 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 139 return (0); 140 141 return (divisor); 142 } 143 144 static int 145 ns8250_drain(struct uart_bas *bas, int what) 146 { 147 int delay, limit; 148 149 delay = ns8250_delay(bas); 150 151 if (what & UART_DRAIN_TRANSMITTER) { 152 /* 153 * Pick an arbitrary high limit to avoid getting stuck in 154 * an infinite loop when the hardware is broken. Make the 155 * limit high enough to handle large FIFOs. 156 */ 157 limit = 10*1024; 158 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 159 DELAY(delay); 160 if (limit == 0) { 161 /* printf("ns8250: transmitter appears stuck... "); */ 162 return (EIO); 163 } 164 } 165 166 if (what & UART_DRAIN_RECEIVER) { 167 /* 168 * Pick an arbitrary high limit to avoid getting stuck in 169 * an infinite loop when the hardware is broken. Make the 170 * limit high enough to handle large FIFOs and integrated 171 * UARTs. The HP rx2600 for example has 3 UARTs on the 172 * management board that tend to get a lot of data send 173 * to it when the UART is first activated. 174 */ 175 limit=10*4096; 176 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 177 (void)uart_getreg(bas, REG_DATA); 178 uart_barrier(bas); 179 DELAY(delay << 2); 180 } 181 if (limit == 0) { 182 /* printf("ns8250: receiver appears broken... "); */ 183 return (EIO); 184 } 185 } 186 187 return (0); 188 } 189 190 /* 191 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 192 * drained. WARNING: this function clobbers the FIFO setting! 193 */ 194 static void 195 ns8250_flush(struct uart_bas *bas, int what) 196 { 197 uint8_t fcr; 198 199 fcr = FCR_ENABLE; 200 if (what & UART_FLUSH_TRANSMITTER) 201 fcr |= FCR_XMT_RST; 202 if (what & UART_FLUSH_RECEIVER) 203 fcr |= FCR_RCV_RST; 204 uart_setreg(bas, REG_FCR, fcr); 205 uart_barrier(bas); 206 } 207 208 static int 209 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 210 int parity) 211 { 212 int divisor; 213 uint8_t lcr; 214 215 lcr = 0; 216 if (databits >= 8) 217 lcr |= LCR_8BITS; 218 else if (databits == 7) 219 lcr |= LCR_7BITS; 220 else if (databits == 6) 221 lcr |= LCR_6BITS; 222 else 223 lcr |= LCR_5BITS; 224 if (stopbits > 1) 225 lcr |= LCR_STOPB; 226 lcr |= parity << 3; 227 228 /* Set baudrate. */ 229 if (baudrate > 0) { 230 divisor = ns8250_divisor(bas->rclk, baudrate); 231 if (divisor == 0) 232 return (EINVAL); 233 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 234 uart_barrier(bas); 235 uart_setreg(bas, REG_DLL, divisor & 0xff); 236 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 237 uart_barrier(bas); 238 } 239 240 /* Set LCR and clear DLAB. */ 241 uart_setreg(bas, REG_LCR, lcr); 242 uart_barrier(bas); 243 return (0); 244 } 245 246 /* 247 * Low-level UART interface. 248 */ 249 static int ns8250_probe(struct uart_bas *bas); 250 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 251 static void ns8250_term(struct uart_bas *bas); 252 static void ns8250_putc(struct uart_bas *bas, int); 253 static int ns8250_rxready(struct uart_bas *bas); 254 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 255 256 struct uart_ops uart_ns8250_ops = { 257 .probe = ns8250_probe, 258 .init = ns8250_init, 259 .term = ns8250_term, 260 .putc = ns8250_putc, 261 .rxready = ns8250_rxready, 262 .getc = ns8250_getc, 263 }; 264 265 static int 266 ns8250_probe(struct uart_bas *bas) 267 { 268 u_char val; 269 270 /* Check known 0 bits that don't depend on DLAB. */ 271 val = uart_getreg(bas, REG_IIR); 272 if (val & 0x30) 273 return (ENXIO); 274 /* 275 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 276 * chip, but otherwise doesn't seem to have a function. In 277 * other words, uart(4) works regardless. Ignore that bit so 278 * the probe succeeds. 279 */ 280 val = uart_getreg(bas, REG_MCR); 281 if (val & 0xa0) 282 return (ENXIO); 283 284 return (0); 285 } 286 287 static void 288 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 289 int parity) 290 { 291 u_char ier; 292 293 if (bas->rclk == 0) 294 bas->rclk = DEFAULT_RCLK; 295 ns8250_param(bas, baudrate, databits, stopbits, parity); 296 297 /* Disable all interrupt sources. */ 298 /* 299 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 300 * UARTs split the receive time-out interrupt bit out separately as 301 * 0x10. This gets handled by ier_mask and ier_rxbits below. 302 */ 303 ier = uart_getreg(bas, REG_IER) & 0xe0; 304 uart_setreg(bas, REG_IER, ier); 305 uart_barrier(bas); 306 307 /* Disable the FIFO (if present). */ 308 uart_setreg(bas, REG_FCR, 0); 309 uart_barrier(bas); 310 311 /* Set RTS & DTR. */ 312 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 313 uart_barrier(bas); 314 315 ns8250_clrint(bas); 316 } 317 318 static void 319 ns8250_term(struct uart_bas *bas) 320 { 321 322 /* Clear RTS & DTR. */ 323 uart_setreg(bas, REG_MCR, MCR_IE); 324 uart_barrier(bas); 325 } 326 327 static void 328 ns8250_putc(struct uart_bas *bas, int c) 329 { 330 int limit; 331 332 limit = 250000; 333 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 334 DELAY(4); 335 uart_setreg(bas, REG_DATA, c); 336 uart_barrier(bas); 337 limit = 250000; 338 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 339 DELAY(4); 340 } 341 342 static int 343 ns8250_rxready(struct uart_bas *bas) 344 { 345 346 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 347 } 348 349 static int 350 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 351 { 352 int c; 353 354 uart_lock(hwmtx); 355 356 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 357 uart_unlock(hwmtx); 358 DELAY(4); 359 uart_lock(hwmtx); 360 } 361 362 c = uart_getreg(bas, REG_DATA); 363 364 uart_unlock(hwmtx); 365 366 return (c); 367 } 368 369 static kobj_method_t ns8250_methods[] = { 370 KOBJMETHOD(uart_attach, ns8250_bus_attach), 371 KOBJMETHOD(uart_detach, ns8250_bus_detach), 372 KOBJMETHOD(uart_flush, ns8250_bus_flush), 373 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 374 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 375 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 376 KOBJMETHOD(uart_param, ns8250_bus_param), 377 KOBJMETHOD(uart_probe, ns8250_bus_probe), 378 KOBJMETHOD(uart_receive, ns8250_bus_receive), 379 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 380 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 381 KOBJMETHOD(uart_grab, ns8250_bus_grab), 382 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 383 { 0, 0 } 384 }; 385 386 struct uart_class uart_ns8250_class = { 387 "ns8250", 388 ns8250_methods, 389 sizeof(struct ns8250_softc), 390 .uc_ops = &uart_ns8250_ops, 391 .uc_range = 8, 392 .uc_rclk = DEFAULT_RCLK, 393 .uc_rshift = 0 394 }; 395 396 #ifdef FDT 397 static struct ofw_compat_data compat_data[] = { 398 {"ns16550", (uintptr_t)&uart_ns8250_class}, 399 {NULL, (uintptr_t)NULL}, 400 }; 401 UART_FDT_CLASS_AND_DEVICE(compat_data); 402 #endif 403 404 #define SIGCHG(c, i, s, d) \ 405 if (c) { \ 406 i |= (i & s) ? s : s | d; \ 407 } else { \ 408 i = (i & s) ? (i & ~s) | d : i; \ 409 } 410 411 int 412 ns8250_bus_attach(struct uart_softc *sc) 413 { 414 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 415 struct uart_bas *bas; 416 unsigned int ivar; 417 #ifdef FDT 418 phandle_t node; 419 pcell_t cell; 420 #endif 421 422 ns8250->busy_detect = 0; 423 424 #ifdef FDT 425 /* 426 * Check whether uart requires to read USR reg when IIR_BUSY and 427 * has broken txfifo. 428 */ 429 node = ofw_bus_get_node(sc->sc_dev); 430 if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 431 ns8250->busy_detect = cell ? 1 : 0; 432 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 433 broken_txfifo = cell ? 1 : 0; 434 #endif 435 436 bas = &sc->sc_bas; 437 438 ns8250->mcr = uart_getreg(bas, REG_MCR); 439 ns8250->fcr = FCR_ENABLE; 440 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 441 &ivar)) { 442 if (UART_FLAGS_FCR_RX_LOW(ivar)) 443 ns8250->fcr |= FCR_RX_LOW; 444 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 445 ns8250->fcr |= FCR_RX_MEDL; 446 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 447 ns8250->fcr |= FCR_RX_HIGH; 448 else 449 ns8250->fcr |= FCR_RX_MEDH; 450 } else 451 ns8250->fcr |= FCR_RX_MEDH; 452 453 /* Get IER mask */ 454 ivar = 0xf0; 455 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 456 &ivar); 457 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 458 459 /* Get IER RX interrupt bits */ 460 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 461 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 462 &ivar); 463 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 464 465 uart_setreg(bas, REG_FCR, ns8250->fcr); 466 uart_barrier(bas); 467 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 468 469 if (ns8250->mcr & MCR_DTR) 470 sc->sc_hwsig |= SER_DTR; 471 if (ns8250->mcr & MCR_RTS) 472 sc->sc_hwsig |= SER_RTS; 473 ns8250_bus_getsig(sc); 474 475 ns8250_clrint(bas); 476 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 477 ns8250->ier |= ns8250->ier_rxbits; 478 uart_setreg(bas, REG_IER, ns8250->ier); 479 uart_barrier(bas); 480 481 /* 482 * Timing of the H/W access was changed with r253161 of uart_core.c 483 * It has been observed that an ITE IT8513E would signal a break 484 * condition with pretty much every character it received, unless 485 * it had enough time to settle between ns8250_bus_attach() and 486 * ns8250_bus_ipend() -- which it accidentally had before r253161. 487 * It's not understood why the UART chip behaves this way and it 488 * could very well be that the DELAY make the H/W work in the same 489 * accidental manner as before. More analysis is warranted, but 490 * at least now we fixed a known regression. 491 */ 492 DELAY(200); 493 return (0); 494 } 495 496 int 497 ns8250_bus_detach(struct uart_softc *sc) 498 { 499 struct ns8250_softc *ns8250; 500 struct uart_bas *bas; 501 u_char ier; 502 503 ns8250 = (struct ns8250_softc *)sc; 504 bas = &sc->sc_bas; 505 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 506 uart_setreg(bas, REG_IER, ier); 507 uart_barrier(bas); 508 ns8250_clrint(bas); 509 return (0); 510 } 511 512 int 513 ns8250_bus_flush(struct uart_softc *sc, int what) 514 { 515 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 516 struct uart_bas *bas; 517 int error; 518 519 bas = &sc->sc_bas; 520 uart_lock(sc->sc_hwmtx); 521 if (sc->sc_rxfifosz > 1) { 522 ns8250_flush(bas, what); 523 uart_setreg(bas, REG_FCR, ns8250->fcr); 524 uart_barrier(bas); 525 error = 0; 526 } else 527 error = ns8250_drain(bas, what); 528 uart_unlock(sc->sc_hwmtx); 529 return (error); 530 } 531 532 int 533 ns8250_bus_getsig(struct uart_softc *sc) 534 { 535 uint32_t new, old, sig; 536 uint8_t msr; 537 538 do { 539 old = sc->sc_hwsig; 540 sig = old; 541 uart_lock(sc->sc_hwmtx); 542 msr = uart_getreg(&sc->sc_bas, REG_MSR); 543 uart_unlock(sc->sc_hwmtx); 544 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 545 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 546 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 547 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 548 new = sig & ~SER_MASK_DELTA; 549 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 550 return (sig); 551 } 552 553 int 554 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 555 { 556 struct uart_bas *bas; 557 int baudrate, divisor, error; 558 uint8_t efr, lcr; 559 560 bas = &sc->sc_bas; 561 error = 0; 562 uart_lock(sc->sc_hwmtx); 563 switch (request) { 564 case UART_IOCTL_BREAK: 565 lcr = uart_getreg(bas, REG_LCR); 566 if (data) 567 lcr |= LCR_SBREAK; 568 else 569 lcr &= ~LCR_SBREAK; 570 uart_setreg(bas, REG_LCR, lcr); 571 uart_barrier(bas); 572 break; 573 case UART_IOCTL_IFLOW: 574 lcr = uart_getreg(bas, REG_LCR); 575 uart_barrier(bas); 576 uart_setreg(bas, REG_LCR, 0xbf); 577 uart_barrier(bas); 578 efr = uart_getreg(bas, REG_EFR); 579 if (data) 580 efr |= EFR_RTS; 581 else 582 efr &= ~EFR_RTS; 583 uart_setreg(bas, REG_EFR, efr); 584 uart_barrier(bas); 585 uart_setreg(bas, REG_LCR, lcr); 586 uart_barrier(bas); 587 break; 588 case UART_IOCTL_OFLOW: 589 lcr = uart_getreg(bas, REG_LCR); 590 uart_barrier(bas); 591 uart_setreg(bas, REG_LCR, 0xbf); 592 uart_barrier(bas); 593 efr = uart_getreg(bas, REG_EFR); 594 if (data) 595 efr |= EFR_CTS; 596 else 597 efr &= ~EFR_CTS; 598 uart_setreg(bas, REG_EFR, efr); 599 uart_barrier(bas); 600 uart_setreg(bas, REG_LCR, lcr); 601 uart_barrier(bas); 602 break; 603 case UART_IOCTL_BAUD: 604 lcr = uart_getreg(bas, REG_LCR); 605 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 606 uart_barrier(bas); 607 divisor = uart_getreg(bas, REG_DLL) | 608 (uart_getreg(bas, REG_DLH) << 8); 609 uart_barrier(bas); 610 uart_setreg(bas, REG_LCR, lcr); 611 uart_barrier(bas); 612 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 613 if (baudrate > 0) 614 *(int*)data = baudrate; 615 else 616 error = ENXIO; 617 break; 618 default: 619 error = EINVAL; 620 break; 621 } 622 uart_unlock(sc->sc_hwmtx); 623 return (error); 624 } 625 626 int 627 ns8250_bus_ipend(struct uart_softc *sc) 628 { 629 struct uart_bas *bas; 630 struct ns8250_softc *ns8250; 631 int ipend; 632 uint8_t iir, lsr; 633 634 ns8250 = (struct ns8250_softc *)sc; 635 bas = &sc->sc_bas; 636 uart_lock(sc->sc_hwmtx); 637 iir = uart_getreg(bas, REG_IIR); 638 639 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 640 (void)uart_getreg(bas, DW_REG_USR); 641 uart_unlock(sc->sc_hwmtx); 642 return (0); 643 } 644 if (iir & IIR_NOPEND) { 645 uart_unlock(sc->sc_hwmtx); 646 return (0); 647 } 648 ipend = 0; 649 if (iir & IIR_RXRDY) { 650 lsr = uart_getreg(bas, REG_LSR); 651 if (lsr & LSR_OE) 652 ipend |= SER_INT_OVERRUN; 653 if (lsr & LSR_BI) 654 ipend |= SER_INT_BREAK; 655 if (lsr & LSR_RXRDY) 656 ipend |= SER_INT_RXREADY; 657 } else { 658 if (iir & IIR_TXRDY) { 659 ipend |= SER_INT_TXIDLE; 660 uart_setreg(bas, REG_IER, ns8250->ier); 661 } else 662 ipend |= SER_INT_SIGCHG; 663 } 664 if (ipend == 0) 665 ns8250_clrint(bas); 666 uart_unlock(sc->sc_hwmtx); 667 return (ipend); 668 } 669 670 int 671 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 672 int stopbits, int parity) 673 { 674 struct ns8250_softc *ns8250; 675 struct uart_bas *bas; 676 int error, limit; 677 678 ns8250 = (struct ns8250_softc*)sc; 679 bas = &sc->sc_bas; 680 uart_lock(sc->sc_hwmtx); 681 /* 682 * When using DW UART with BUSY detection it is necessary to wait 683 * until all serial transfers are finished before manipulating the 684 * line control. LCR will not be affected when UART is busy. 685 */ 686 if (ns8250->busy_detect != 0) { 687 /* 688 * Pick an arbitrary high limit to avoid getting stuck in 689 * an infinite loop in case when the hardware is broken. 690 */ 691 limit = 10 * 1024; 692 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 693 --limit) 694 DELAY(4); 695 696 if (limit <= 0) { 697 /* UART appears to be stuck */ 698 uart_unlock(sc->sc_hwmtx); 699 return (EIO); 700 } 701 } 702 703 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 704 uart_unlock(sc->sc_hwmtx); 705 return (error); 706 } 707 708 int 709 ns8250_bus_probe(struct uart_softc *sc) 710 { 711 struct ns8250_softc *ns8250; 712 struct uart_bas *bas; 713 int count, delay, error, limit; 714 uint8_t lsr, mcr, ier; 715 716 ns8250 = (struct ns8250_softc *)sc; 717 bas = &sc->sc_bas; 718 719 error = ns8250_probe(bas); 720 if (error) 721 return (error); 722 723 mcr = MCR_IE; 724 if (sc->sc_sysdev == NULL) { 725 /* By using ns8250_init() we also set DTR and RTS. */ 726 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 727 } else 728 mcr |= MCR_DTR | MCR_RTS; 729 730 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 731 if (error) 732 return (error); 733 734 /* 735 * Set loopback mode. This avoids having garbage on the wire and 736 * also allows us send and receive data. We set DTR and RTS to 737 * avoid the possibility that automatic flow-control prevents 738 * any data from being sent. 739 */ 740 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 741 uart_barrier(bas); 742 743 /* 744 * Enable FIFOs. And check that the UART has them. If not, we're 745 * done. Since this is the first time we enable the FIFOs, we reset 746 * them. 747 */ 748 uart_setreg(bas, REG_FCR, FCR_ENABLE); 749 uart_barrier(bas); 750 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 751 /* 752 * NS16450 or INS8250. We don't bother to differentiate 753 * between them. They're too old to be interesting. 754 */ 755 uart_setreg(bas, REG_MCR, mcr); 756 uart_barrier(bas); 757 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 758 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 759 return (0); 760 } 761 762 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 763 uart_barrier(bas); 764 765 count = 0; 766 delay = ns8250_delay(bas); 767 768 /* We have FIFOs. Drain the transmitter and receiver. */ 769 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 770 if (error) { 771 uart_setreg(bas, REG_MCR, mcr); 772 uart_setreg(bas, REG_FCR, 0); 773 uart_barrier(bas); 774 goto describe; 775 } 776 777 /* 778 * We should have a sufficiently clean "pipe" to determine the 779 * size of the FIFOs. We send as much characters as is reasonable 780 * and wait for the overflow bit in the LSR register to be 781 * asserted, counting the characters as we send them. Based on 782 * that count we know the FIFO size. 783 */ 784 do { 785 uart_setreg(bas, REG_DATA, 0); 786 uart_barrier(bas); 787 count++; 788 789 limit = 30; 790 lsr = 0; 791 /* 792 * LSR bits are cleared upon read, so we must accumulate 793 * them to be able to test LSR_OE below. 794 */ 795 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 796 --limit) 797 DELAY(delay); 798 if (limit == 0) { 799 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 800 uart_setreg(bas, REG_IER, ier); 801 uart_setreg(bas, REG_MCR, mcr); 802 uart_setreg(bas, REG_FCR, 0); 803 uart_barrier(bas); 804 count = 0; 805 goto describe; 806 } 807 } while ((lsr & LSR_OE) == 0 && count < 130); 808 count--; 809 810 uart_setreg(bas, REG_MCR, mcr); 811 812 /* Reset FIFOs. */ 813 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 814 815 describe: 816 if (count >= 14 && count <= 16) { 817 sc->sc_rxfifosz = 16; 818 device_set_desc(sc->sc_dev, "16550 or compatible"); 819 } else if (count >= 28 && count <= 32) { 820 sc->sc_rxfifosz = 32; 821 device_set_desc(sc->sc_dev, "16650 or compatible"); 822 } else if (count >= 56 && count <= 64) { 823 sc->sc_rxfifosz = 64; 824 device_set_desc(sc->sc_dev, "16750 or compatible"); 825 } else if (count >= 112 && count <= 128) { 826 sc->sc_rxfifosz = 128; 827 device_set_desc(sc->sc_dev, "16950 or compatible"); 828 } else { 829 sc->sc_rxfifosz = 16; 830 device_set_desc(sc->sc_dev, 831 "Non-standard ns8250 class UART with FIFOs"); 832 } 833 834 /* 835 * Force the Tx FIFO size to 16 bytes for now. We don't program the 836 * Tx trigger. Also, we assume that all data has been sent when the 837 * interrupt happens. 838 */ 839 sc->sc_txfifosz = 16; 840 841 #if 0 842 /* 843 * XXX there are some issues related to hardware flow control and 844 * it's likely that uart(4) is the cause. This basicly needs more 845 * investigation, but we avoid using for hardware flow control 846 * until then. 847 */ 848 /* 16650s or higher have automatic flow control. */ 849 if (sc->sc_rxfifosz > 16) { 850 sc->sc_hwiflow = 1; 851 sc->sc_hwoflow = 1; 852 } 853 #endif 854 855 return (0); 856 } 857 858 int 859 ns8250_bus_receive(struct uart_softc *sc) 860 { 861 struct uart_bas *bas; 862 int xc; 863 uint8_t lsr; 864 865 bas = &sc->sc_bas; 866 uart_lock(sc->sc_hwmtx); 867 lsr = uart_getreg(bas, REG_LSR); 868 while (lsr & LSR_RXRDY) { 869 if (uart_rx_full(sc)) { 870 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 871 break; 872 } 873 xc = uart_getreg(bas, REG_DATA); 874 if (lsr & LSR_FE) 875 xc |= UART_STAT_FRAMERR; 876 if (lsr & LSR_PE) 877 xc |= UART_STAT_PARERR; 878 uart_rx_put(sc, xc); 879 lsr = uart_getreg(bas, REG_LSR); 880 } 881 /* Discard everything left in the Rx FIFO. */ 882 while (lsr & LSR_RXRDY) { 883 (void)uart_getreg(bas, REG_DATA); 884 uart_barrier(bas); 885 lsr = uart_getreg(bas, REG_LSR); 886 } 887 uart_unlock(sc->sc_hwmtx); 888 return (0); 889 } 890 891 int 892 ns8250_bus_setsig(struct uart_softc *sc, int sig) 893 { 894 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 895 struct uart_bas *bas; 896 uint32_t new, old; 897 898 bas = &sc->sc_bas; 899 do { 900 old = sc->sc_hwsig; 901 new = old; 902 if (sig & SER_DDTR) { 903 SIGCHG(sig & SER_DTR, new, SER_DTR, 904 SER_DDTR); 905 } 906 if (sig & SER_DRTS) { 907 SIGCHG(sig & SER_RTS, new, SER_RTS, 908 SER_DRTS); 909 } 910 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 911 uart_lock(sc->sc_hwmtx); 912 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 913 if (new & SER_DTR) 914 ns8250->mcr |= MCR_DTR; 915 if (new & SER_RTS) 916 ns8250->mcr |= MCR_RTS; 917 uart_setreg(bas, REG_MCR, ns8250->mcr); 918 uart_barrier(bas); 919 uart_unlock(sc->sc_hwmtx); 920 return (0); 921 } 922 923 int 924 ns8250_bus_transmit(struct uart_softc *sc) 925 { 926 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 927 struct uart_bas *bas; 928 int i; 929 930 bas = &sc->sc_bas; 931 uart_lock(sc->sc_hwmtx); 932 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 933 ; 934 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 935 uart_barrier(bas); 936 for (i = 0; i < sc->sc_txdatasz; i++) { 937 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 938 uart_barrier(bas); 939 } 940 if (broken_txfifo) 941 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 942 else 943 sc->sc_txbusy = 1; 944 uart_unlock(sc->sc_hwmtx); 945 if (broken_txfifo) 946 uart_sched_softih(sc, SER_INT_TXIDLE); 947 return (0); 948 } 949 950 void 951 ns8250_bus_grab(struct uart_softc *sc) 952 { 953 struct uart_bas *bas = &sc->sc_bas; 954 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 955 u_char ier; 956 957 /* 958 * turn off all interrupts to enter polling mode. Leave the 959 * saved mask alone. We'll restore whatever it was in ungrab. 960 * All pending interupt signals are reset when IER is set to 0. 961 */ 962 uart_lock(sc->sc_hwmtx); 963 ier = uart_getreg(bas, REG_IER); 964 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 965 uart_barrier(bas); 966 uart_unlock(sc->sc_hwmtx); 967 } 968 969 void 970 ns8250_bus_ungrab(struct uart_softc *sc) 971 { 972 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 973 struct uart_bas *bas = &sc->sc_bas; 974 975 /* 976 * Restore previous interrupt mask 977 */ 978 uart_lock(sc->sc_hwmtx); 979 uart_setreg(bas, REG_IER, ns8250->ier); 980 uart_barrier(bas); 981 uart_unlock(sc->sc_hwmtx); 982 } 983