1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 #ifdef DEV_ACPI 56 #include <dev/uart/uart_cpu_acpi.h> 57 #include <contrib/dev/acpica/include/acpi.h> 58 #endif 59 60 #include <dev/ic/ns16550.h> 61 62 #include "uart_if.h" 63 64 #define DEFAULT_RCLK 1843200 65 66 /* 67 * Set the default baudrate tolerance to 3.0%. 68 * 69 * Some embedded boards have odd reference clocks (eg 25MHz) 70 * and we need to handle higher variances in the target baud rate. 71 */ 72 #ifndef UART_DEV_TOLERANCE_PCT 73 #define UART_DEV_TOLERANCE_PCT 30 74 #endif /* UART_DEV_TOLERANCE_PCT */ 75 76 static int broken_txfifo = 0; 77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 79 80 /* 81 * To use early printf on x86, add the following to your kernel config: 82 * 83 * options UART_NS8250_EARLY_PORT=0x3f8 84 * options EARLY_PRINTF=ns8250 85 */ 86 #if CHECK_EARLY_PRINTF(ns8250) 87 #if !(defined(__amd64__) || defined(__i386__)) 88 #error ns8250 early putc is x86 specific as it uses inb/outb 89 #endif 90 static void 91 uart_ns8250_early_putc(int c) 92 { 93 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 94 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 95 int limit = 10000; /* 10ms is plenty of time */ 96 97 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 98 continue; 99 outb(tx, c); 100 } 101 early_putc_t *early_putc = uart_ns8250_early_putc; 102 #endif /* EARLY_PRINTF */ 103 104 /* 105 * Clear pending interrupts. THRE is cleared by reading IIR. Data 106 * that may have been received gets lost here. 107 */ 108 static void 109 ns8250_clrint(struct uart_bas *bas) 110 { 111 uint8_t iir, lsr; 112 113 iir = uart_getreg(bas, REG_IIR); 114 while ((iir & IIR_NOPEND) == 0) { 115 iir &= IIR_IMASK; 116 if (iir == IIR_RLS) { 117 lsr = uart_getreg(bas, REG_LSR); 118 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 119 (void)uart_getreg(bas, REG_DATA); 120 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 121 (void)uart_getreg(bas, REG_DATA); 122 else if (iir == IIR_MLSC) 123 (void)uart_getreg(bas, REG_MSR); 124 uart_barrier(bas); 125 iir = uart_getreg(bas, REG_IIR); 126 } 127 } 128 129 static int 130 ns8250_delay(struct uart_bas *bas) 131 { 132 int divisor; 133 u_char lcr; 134 135 lcr = uart_getreg(bas, REG_LCR); 136 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 137 uart_barrier(bas); 138 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 139 uart_barrier(bas); 140 uart_setreg(bas, REG_LCR, lcr); 141 uart_barrier(bas); 142 143 /* 1/10th the time to transmit 1 character (estimate). */ 144 if (divisor <= 134) 145 return (16000000 * divisor / bas->rclk); 146 return (16000 * divisor / (bas->rclk / 1000)); 147 } 148 149 static int 150 ns8250_divisor(int rclk, int baudrate) 151 { 152 int actual_baud, divisor; 153 int error; 154 155 if (baudrate == 0) 156 return (0); 157 158 divisor = (rclk / (baudrate << 3) + 1) >> 1; 159 if (divisor == 0 || divisor >= 65536) 160 return (0); 161 actual_baud = rclk / (divisor << 4); 162 163 /* 10 times error in percent: */ 164 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 165 166 /* enforce maximum error tolerance: */ 167 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 168 return (0); 169 170 return (divisor); 171 } 172 173 static int 174 ns8250_drain(struct uart_bas *bas, int what) 175 { 176 int delay, limit; 177 178 delay = ns8250_delay(bas); 179 180 if (what & UART_DRAIN_TRANSMITTER) { 181 /* 182 * Pick an arbitrary high limit to avoid getting stuck in 183 * an infinite loop when the hardware is broken. Make the 184 * limit high enough to handle large FIFOs. 185 */ 186 limit = 10*1024; 187 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 188 DELAY(delay); 189 if (limit == 0) { 190 /* printf("ns8250: transmitter appears stuck... "); */ 191 return (EIO); 192 } 193 } 194 195 if (what & UART_DRAIN_RECEIVER) { 196 /* 197 * Pick an arbitrary high limit to avoid getting stuck in 198 * an infinite loop when the hardware is broken. Make the 199 * limit high enough to handle large FIFOs and integrated 200 * UARTs. The HP rx2600 for example has 3 UARTs on the 201 * management board that tend to get a lot of data send 202 * to it when the UART is first activated. Assume that we 203 * have finished draining if LSR_RXRDY is not asserted both 204 * prior to and after a DELAY; but as long as LSR_RXRDY is 205 * asserted, read (and discard) characters as quickly as 206 * possible. 207 */ 208 limit=10*4096; 209 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 210 do { 211 (void)uart_getreg(bas, REG_DATA); 212 uart_barrier(bas); 213 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 214 uart_barrier(bas); 215 DELAY(delay << 2); 216 } 217 if (limit == 0) { 218 /* printf("ns8250: receiver appears broken... "); */ 219 return (EIO); 220 } 221 } 222 223 return (0); 224 } 225 226 /* 227 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 228 * drained. WARNING: this function clobbers the FIFO setting! 229 */ 230 static void 231 ns8250_flush(struct uart_bas *bas, int what) 232 { 233 uint8_t fcr; 234 uint8_t lsr; 235 int drain = 0; 236 237 fcr = FCR_ENABLE; 238 if (what & UART_FLUSH_TRANSMITTER) 239 fcr |= FCR_XMT_RST; 240 if (what & UART_FLUSH_RECEIVER) 241 fcr |= FCR_RCV_RST; 242 uart_setreg(bas, REG_FCR, fcr); 243 uart_barrier(bas); 244 245 /* 246 * Detect and work around emulated UARTs which don't implement the 247 * FCR register; on these systems we need to drain the FIFO since 248 * the flush we request doesn't happen. One such system is the 249 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 250 * https://github.com/rust-vmm/vm-superio/issues/83 251 */ 252 lsr = uart_getreg(bas, REG_LSR); 253 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 254 drain |= UART_DRAIN_TRANSMITTER; 255 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 256 drain |= UART_DRAIN_RECEIVER; 257 if (drain != 0) { 258 printf("ns8250: UART FCR is broken\n"); 259 ns8250_drain(bas, drain); 260 } 261 } 262 263 static int 264 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 265 int parity) 266 { 267 int divisor; 268 uint8_t lcr; 269 270 /* Don't change settings when running on Hyper-V */ 271 if (vm_guest == VM_GUEST_HV) 272 return (0); 273 274 lcr = 0; 275 if (databits >= 8) 276 lcr |= LCR_8BITS; 277 else if (databits == 7) 278 lcr |= LCR_7BITS; 279 else if (databits == 6) 280 lcr |= LCR_6BITS; 281 else 282 lcr |= LCR_5BITS; 283 if (stopbits > 1) 284 lcr |= LCR_STOPB; 285 lcr |= parity << 3; 286 287 /* Set baudrate. */ 288 if (baudrate > 0) { 289 divisor = ns8250_divisor(bas->rclk, baudrate); 290 if (divisor == 0) 291 return (EINVAL); 292 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 293 uart_barrier(bas); 294 uart_setreg(bas, REG_DLL, divisor & 0xff); 295 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 296 uart_barrier(bas); 297 } 298 299 /* Set LCR and clear DLAB. */ 300 uart_setreg(bas, REG_LCR, lcr); 301 uart_barrier(bas); 302 return (0); 303 } 304 305 /* 306 * Low-level UART interface. 307 */ 308 static int ns8250_probe(struct uart_bas *bas); 309 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 310 static void ns8250_term(struct uart_bas *bas); 311 static void ns8250_putc(struct uart_bas *bas, int); 312 static int ns8250_rxready(struct uart_bas *bas); 313 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 314 315 struct uart_ops uart_ns8250_ops = { 316 .probe = ns8250_probe, 317 .init = ns8250_init, 318 .term = ns8250_term, 319 .putc = ns8250_putc, 320 .rxready = ns8250_rxready, 321 .getc = ns8250_getc, 322 }; 323 324 static int 325 ns8250_probe(struct uart_bas *bas) 326 { 327 u_char val; 328 329 /* Check known 0 bits that don't depend on DLAB. */ 330 val = uart_getreg(bas, REG_IIR); 331 if (val & 0x30) 332 return (ENXIO); 333 /* 334 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 335 * chip, but otherwise doesn't seem to have a function. In 336 * other words, uart(4) works regardless. Ignore that bit so 337 * the probe succeeds. 338 */ 339 val = uart_getreg(bas, REG_MCR); 340 if (val & 0xa0) 341 return (ENXIO); 342 343 return (0); 344 } 345 346 static void 347 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 348 int parity) 349 { 350 u_char ier; 351 352 if (bas->rclk == 0) 353 bas->rclk = DEFAULT_RCLK; 354 ns8250_param(bas, baudrate, databits, stopbits, parity); 355 356 /* Disable all interrupt sources. */ 357 /* 358 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 359 * UARTs split the receive time-out interrupt bit out separately as 360 * 0x10. This gets handled by ier_mask and ier_rxbits below. 361 */ 362 ier = uart_getreg(bas, REG_IER) & 0xe0; 363 uart_setreg(bas, REG_IER, ier); 364 uart_barrier(bas); 365 366 /* Disable the FIFO (if present). */ 367 uart_setreg(bas, REG_FCR, 0); 368 uart_barrier(bas); 369 370 /* Set RTS & DTR. */ 371 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 372 uart_barrier(bas); 373 374 ns8250_clrint(bas); 375 } 376 377 static void 378 ns8250_term(struct uart_bas *bas) 379 { 380 381 /* Clear RTS & DTR. */ 382 uart_setreg(bas, REG_MCR, MCR_IE); 383 uart_barrier(bas); 384 } 385 386 static void 387 ns8250_putc(struct uart_bas *bas, int c) 388 { 389 int limit; 390 391 if (vm_guest != VM_GUEST_HV) { 392 limit = 250000; 393 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 394 DELAY(4); 395 } 396 uart_setreg(bas, REG_DATA, c); 397 uart_barrier(bas); 398 } 399 400 static int 401 ns8250_rxready(struct uart_bas *bas) 402 { 403 404 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 405 } 406 407 static int 408 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 409 { 410 int c; 411 412 uart_lock(hwmtx); 413 414 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 415 uart_unlock(hwmtx); 416 DELAY(4); 417 uart_lock(hwmtx); 418 } 419 420 c = uart_getreg(bas, REG_DATA); 421 422 uart_unlock(hwmtx); 423 424 return (c); 425 } 426 427 static kobj_method_t ns8250_methods[] = { 428 KOBJMETHOD(uart_attach, ns8250_bus_attach), 429 KOBJMETHOD(uart_detach, ns8250_bus_detach), 430 KOBJMETHOD(uart_flush, ns8250_bus_flush), 431 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 432 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 433 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 434 KOBJMETHOD(uart_param, ns8250_bus_param), 435 KOBJMETHOD(uart_probe, ns8250_bus_probe), 436 KOBJMETHOD(uart_receive, ns8250_bus_receive), 437 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 438 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 439 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy), 440 KOBJMETHOD(uart_grab, ns8250_bus_grab), 441 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 442 KOBJMETHOD_END 443 }; 444 445 struct uart_class uart_ns8250_class = { 446 "ns8250", 447 ns8250_methods, 448 sizeof(struct ns8250_softc), 449 .uc_ops = &uart_ns8250_ops, 450 .uc_range = 8, 451 .uc_rclk = DEFAULT_RCLK, 452 .uc_rshift = 0 453 }; 454 UART_CLASS(uart_ns8250_class); 455 456 /* 457 * XXX -- refactor out ACPI and FDT ifdefs 458 */ 459 #ifdef DEV_ACPI 460 static struct acpi_uart_compat_data acpi_compat_data[] = { 461 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 462 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 463 {"APMC0D08", &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE, 2, 4, 0, 0, "APM compatible UART"}, 464 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 465 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 466 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 467 {"INTC1006", &uart_ns8250_class, 0, 2, 0, 25000000, 0, "Intel ARM64 UART"}, 468 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 469 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 470 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 471 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 472 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 473 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 474 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 475 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 476 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 477 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 478 }; 479 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 480 #endif 481 482 #ifdef FDT 483 static struct ofw_compat_data compat_data[] = { 484 {"ns16550", (uintptr_t)&uart_ns8250_class}, 485 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 486 {NULL, (uintptr_t)NULL}, 487 }; 488 UART_FDT_CLASS_AND_DEVICE(compat_data); 489 #endif 490 491 /* Use token-pasting to form SER_ and MSR_ named constants. */ 492 #define SER(sig) SER_##sig 493 #define SERD(sig) SER_D##sig 494 #define MSR(sig) MSR_##sig 495 #define MSRD(sig) MSR_D##sig 496 497 /* 498 * Detect signal changes using software delta detection. The previous state of 499 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 500 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 501 * new state of both the signal and the delta bits. 502 */ 503 #define SIGCHGSW(var, msr, sig) \ 504 if ((msr) & MSR(sig)) { \ 505 if ((var & SER(sig)) == 0) \ 506 var |= SERD(sig) | SER(sig); \ 507 } else { \ 508 if ((var & SER(sig)) != 0) \ 509 var = SERD(sig) | (var & ~SER(sig)); \ 510 } 511 512 /* 513 * Detect signal changes using the hardware msr delta bits. This is currently 514 * used only when PPS timing information is being captured using the "narrow 515 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 516 * by time the interrupt handler is invoked. The hardware will latch the fact 517 * that it changed in the delta bits. 518 */ 519 #define SIGCHGHW(var, msr, sig) \ 520 if ((msr) & MSRD(sig)) { \ 521 if (((msr) & MSR(sig)) != 0) \ 522 var |= SERD(sig) | SER(sig); \ 523 else \ 524 var = SERD(sig) | (var & ~SER(sig)); \ 525 } 526 527 int 528 ns8250_bus_attach(struct uart_softc *sc) 529 { 530 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 531 struct uart_bas *bas; 532 unsigned int ivar; 533 #ifdef FDT 534 phandle_t node; 535 pcell_t cell; 536 #endif 537 538 #ifdef FDT 539 /* Check whether uart has a broken txfifo. */ 540 node = ofw_bus_get_node(sc->sc_dev); 541 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 542 broken_txfifo = cell ? 1 : 0; 543 #endif 544 545 bas = &sc->sc_bas; 546 547 ns8250->busy_detect = bas->busy_detect; 548 ns8250->mcr = uart_getreg(bas, REG_MCR); 549 ns8250->fcr = FCR_ENABLE; 550 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 551 &ivar)) { 552 if (UART_FLAGS_FCR_RX_LOW(ivar)) 553 ns8250->fcr |= FCR_RX_LOW; 554 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 555 ns8250->fcr |= FCR_RX_MEDL; 556 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 557 ns8250->fcr |= FCR_RX_HIGH; 558 else 559 ns8250->fcr |= FCR_RX_MEDH; 560 } else 561 ns8250->fcr |= FCR_RX_MEDH; 562 563 /* Get IER mask */ 564 ivar = 0xf0; 565 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 566 &ivar); 567 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 568 569 /* Get IER RX interrupt bits */ 570 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 571 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 572 &ivar); 573 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 574 575 uart_setreg(bas, REG_FCR, ns8250->fcr); 576 uart_barrier(bas); 577 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 578 579 if (ns8250->mcr & MCR_DTR) 580 sc->sc_hwsig |= SER_DTR; 581 if (ns8250->mcr & MCR_RTS) 582 sc->sc_hwsig |= SER_RTS; 583 ns8250_bus_getsig(sc); 584 585 ns8250_clrint(bas); 586 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 587 ns8250->ier |= ns8250->ier_rxbits; 588 uart_setreg(bas, REG_IER, ns8250->ier); 589 uart_barrier(bas); 590 591 /* 592 * Timing of the H/W access was changed with r253161 of uart_core.c 593 * It has been observed that an ITE IT8513E would signal a break 594 * condition with pretty much every character it received, unless 595 * it had enough time to settle between ns8250_bus_attach() and 596 * ns8250_bus_ipend() -- which it accidentally had before r253161. 597 * It's not understood why the UART chip behaves this way and it 598 * could very well be that the DELAY make the H/W work in the same 599 * accidental manner as before. More analysis is warranted, but 600 * at least now we fixed a known regression. 601 */ 602 DELAY(200); 603 return (0); 604 } 605 606 int 607 ns8250_bus_detach(struct uart_softc *sc) 608 { 609 struct ns8250_softc *ns8250; 610 struct uart_bas *bas; 611 u_char ier; 612 613 ns8250 = (struct ns8250_softc *)sc; 614 bas = &sc->sc_bas; 615 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 616 uart_setreg(bas, REG_IER, ier); 617 uart_barrier(bas); 618 ns8250_clrint(bas); 619 return (0); 620 } 621 622 int 623 ns8250_bus_flush(struct uart_softc *sc, int what) 624 { 625 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 626 struct uart_bas *bas; 627 int error; 628 629 bas = &sc->sc_bas; 630 uart_lock(sc->sc_hwmtx); 631 if (sc->sc_rxfifosz > 1) { 632 ns8250_flush(bas, what); 633 uart_setreg(bas, REG_FCR, ns8250->fcr); 634 uart_barrier(bas); 635 error = 0; 636 } else 637 error = ns8250_drain(bas, what); 638 uart_unlock(sc->sc_hwmtx); 639 return (error); 640 } 641 642 int 643 ns8250_bus_getsig(struct uart_softc *sc) 644 { 645 uint32_t old, sig; 646 uint8_t msr; 647 648 /* 649 * The delta bits are reputed to be broken on some hardware, so use 650 * software delta detection by default. Use the hardware delta bits 651 * when capturing PPS pulses which are too narrow for software detection 652 * to see the edges. Hardware delta for RI doesn't work like the 653 * others, so always use software for it. Other threads may be changing 654 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 655 * update without other changes happening. Note that the SIGCHGxx() 656 * macros carefully preserve the delta bits when we have to loop several 657 * times and a signal transitions between iterations. 658 */ 659 do { 660 old = sc->sc_hwsig; 661 sig = old; 662 uart_lock(sc->sc_hwmtx); 663 msr = uart_getreg(&sc->sc_bas, REG_MSR); 664 uart_unlock(sc->sc_hwmtx); 665 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 666 SIGCHGHW(sig, msr, DSR); 667 SIGCHGHW(sig, msr, CTS); 668 SIGCHGHW(sig, msr, DCD); 669 } else { 670 SIGCHGSW(sig, msr, DSR); 671 SIGCHGSW(sig, msr, CTS); 672 SIGCHGSW(sig, msr, DCD); 673 } 674 SIGCHGSW(sig, msr, RI); 675 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 676 return (sig); 677 } 678 679 int 680 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 681 { 682 struct uart_bas *bas; 683 int baudrate, divisor, error; 684 uint8_t efr, lcr; 685 686 bas = &sc->sc_bas; 687 error = 0; 688 uart_lock(sc->sc_hwmtx); 689 switch (request) { 690 case UART_IOCTL_BREAK: 691 lcr = uart_getreg(bas, REG_LCR); 692 if (data) 693 lcr |= LCR_SBREAK; 694 else 695 lcr &= ~LCR_SBREAK; 696 uart_setreg(bas, REG_LCR, lcr); 697 uart_barrier(bas); 698 break; 699 case UART_IOCTL_IFLOW: 700 lcr = uart_getreg(bas, REG_LCR); 701 uart_barrier(bas); 702 uart_setreg(bas, REG_LCR, 0xbf); 703 uart_barrier(bas); 704 efr = uart_getreg(bas, REG_EFR); 705 if (data) 706 efr |= EFR_RTS; 707 else 708 efr &= ~EFR_RTS; 709 uart_setreg(bas, REG_EFR, efr); 710 uart_barrier(bas); 711 uart_setreg(bas, REG_LCR, lcr); 712 uart_barrier(bas); 713 break; 714 case UART_IOCTL_OFLOW: 715 lcr = uart_getreg(bas, REG_LCR); 716 uart_barrier(bas); 717 uart_setreg(bas, REG_LCR, 0xbf); 718 uart_barrier(bas); 719 efr = uart_getreg(bas, REG_EFR); 720 if (data) 721 efr |= EFR_CTS; 722 else 723 efr &= ~EFR_CTS; 724 uart_setreg(bas, REG_EFR, efr); 725 uart_barrier(bas); 726 uart_setreg(bas, REG_LCR, lcr); 727 uart_barrier(bas); 728 break; 729 case UART_IOCTL_BAUD: 730 lcr = uart_getreg(bas, REG_LCR); 731 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 732 uart_barrier(bas); 733 divisor = uart_getreg(bas, REG_DLL) | 734 (uart_getreg(bas, REG_DLH) << 8); 735 uart_barrier(bas); 736 uart_setreg(bas, REG_LCR, lcr); 737 uart_barrier(bas); 738 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 739 if (baudrate > 0) 740 *(int*)data = baudrate; 741 else 742 error = ENXIO; 743 break; 744 default: 745 error = EINVAL; 746 break; 747 } 748 uart_unlock(sc->sc_hwmtx); 749 return (error); 750 } 751 752 int 753 ns8250_bus_ipend(struct uart_softc *sc) 754 { 755 struct uart_bas *bas; 756 struct ns8250_softc *ns8250; 757 int ipend; 758 uint8_t iir, lsr; 759 760 ns8250 = (struct ns8250_softc *)sc; 761 bas = &sc->sc_bas; 762 uart_lock(sc->sc_hwmtx); 763 iir = uart_getreg(bas, REG_IIR); 764 765 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 766 (void)uart_getreg(bas, DW_REG_USR); 767 uart_unlock(sc->sc_hwmtx); 768 return (0); 769 } 770 if (iir & IIR_NOPEND) { 771 uart_unlock(sc->sc_hwmtx); 772 return (0); 773 } 774 ipend = 0; 775 if (iir & IIR_RXRDY) { 776 lsr = uart_getreg(bas, REG_LSR); 777 if (lsr & LSR_OE) 778 ipend |= SER_INT_OVERRUN; 779 if (lsr & LSR_BI) 780 ipend |= SER_INT_BREAK; 781 if (lsr & LSR_RXRDY) 782 ipend |= SER_INT_RXREADY; 783 } else { 784 if (iir & IIR_TXRDY) { 785 ipend |= SER_INT_TXIDLE; 786 ns8250->ier &= ~IER_ETXRDY; 787 uart_setreg(bas, REG_IER, ns8250->ier); 788 uart_barrier(bas); 789 } else 790 ipend |= SER_INT_SIGCHG; 791 } 792 if (ipend == 0) 793 ns8250_clrint(bas); 794 uart_unlock(sc->sc_hwmtx); 795 return (ipend); 796 } 797 798 int 799 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 800 int stopbits, int parity) 801 { 802 struct ns8250_softc *ns8250; 803 struct uart_bas *bas; 804 int error, limit; 805 806 ns8250 = (struct ns8250_softc*)sc; 807 bas = &sc->sc_bas; 808 uart_lock(sc->sc_hwmtx); 809 /* 810 * When using DW UART with BUSY detection it is necessary to wait 811 * until all serial transfers are finished before manipulating the 812 * line control. LCR will not be affected when UART is busy. 813 */ 814 if (ns8250->busy_detect != 0) { 815 /* 816 * Pick an arbitrary high limit to avoid getting stuck in 817 * an infinite loop in case when the hardware is broken. 818 */ 819 limit = 10 * 1024; 820 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 821 --limit) 822 DELAY(4); 823 824 if (limit <= 0) { 825 /* UART appears to be stuck */ 826 uart_unlock(sc->sc_hwmtx); 827 return (EIO); 828 } 829 } 830 831 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 832 uart_unlock(sc->sc_hwmtx); 833 return (error); 834 } 835 836 int 837 ns8250_bus_probe(struct uart_softc *sc) 838 { 839 struct uart_bas *bas; 840 int count, delay, error, limit; 841 uint8_t lsr, mcr, ier; 842 843 bas = &sc->sc_bas; 844 845 error = ns8250_probe(bas); 846 if (error) 847 return (error); 848 849 mcr = MCR_IE; 850 if (sc->sc_sysdev == NULL) { 851 /* By using ns8250_init() we also set DTR and RTS. */ 852 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 853 } else 854 mcr |= MCR_DTR | MCR_RTS; 855 856 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 857 if (error) 858 return (error); 859 860 /* 861 * Set loopback mode. This avoids having garbage on the wire and 862 * also allows us send and receive data. We set DTR and RTS to 863 * avoid the possibility that automatic flow-control prevents 864 * any data from being sent. 865 */ 866 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 867 uart_barrier(bas); 868 869 /* 870 * Enable FIFOs. And check that the UART has them. If not, we're 871 * done. Since this is the first time we enable the FIFOs, we reset 872 * them. 873 */ 874 uart_setreg(bas, REG_FCR, FCR_ENABLE); 875 uart_barrier(bas); 876 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 877 /* 878 * NS16450 or INS8250. We don't bother to differentiate 879 * between them. They're too old to be interesting. 880 */ 881 uart_setreg(bas, REG_MCR, mcr); 882 uart_barrier(bas); 883 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 884 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 885 return (0); 886 } 887 888 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 889 uart_barrier(bas); 890 891 count = 0; 892 delay = ns8250_delay(bas); 893 894 /* We have FIFOs. Drain the transmitter and receiver. */ 895 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 896 if (error) { 897 uart_setreg(bas, REG_MCR, mcr); 898 uart_setreg(bas, REG_FCR, 0); 899 uart_barrier(bas); 900 goto describe; 901 } 902 903 /* 904 * We should have a sufficiently clean "pipe" to determine the 905 * size of the FIFOs. We send as much characters as is reasonable 906 * and wait for the overflow bit in the LSR register to be 907 * asserted, counting the characters as we send them. Based on 908 * that count we know the FIFO size. 909 */ 910 do { 911 uart_setreg(bas, REG_DATA, 0); 912 uart_barrier(bas); 913 count++; 914 915 limit = 30; 916 lsr = 0; 917 /* 918 * LSR bits are cleared upon read, so we must accumulate 919 * them to be able to test LSR_OE below. 920 */ 921 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 922 --limit) 923 DELAY(delay); 924 if (limit == 0) { 925 /* See the comment in ns8250_init(). */ 926 ier = uart_getreg(bas, REG_IER) & 0xe0; 927 uart_setreg(bas, REG_IER, ier); 928 uart_setreg(bas, REG_MCR, mcr); 929 uart_setreg(bas, REG_FCR, 0); 930 uart_barrier(bas); 931 count = 0; 932 goto describe; 933 } 934 } while ((lsr & LSR_OE) == 0 && count < 260); 935 count--; 936 937 uart_setreg(bas, REG_MCR, mcr); 938 939 /* Reset FIFOs. */ 940 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 941 942 describe: 943 if (count >= 14 && count <= 16) { 944 sc->sc_rxfifosz = 16; 945 device_set_desc(sc->sc_dev, "16550 or compatible"); 946 } else if (count >= 28 && count <= 32) { 947 sc->sc_rxfifosz = 32; 948 device_set_desc(sc->sc_dev, "16650 or compatible"); 949 } else if (count >= 56 && count <= 64) { 950 sc->sc_rxfifosz = 64; 951 device_set_desc(sc->sc_dev, "16750 or compatible"); 952 } else if (count >= 112 && count <= 128) { 953 sc->sc_rxfifosz = 128; 954 device_set_desc(sc->sc_dev, "16950 or compatible"); 955 } else if (count >= 224 && count <= 256) { 956 sc->sc_rxfifosz = 256; 957 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 958 } else { 959 sc->sc_rxfifosz = 16; 960 device_set_desc(sc->sc_dev, 961 "Non-standard ns8250 class UART with FIFOs"); 962 } 963 964 /* 965 * Force the Tx FIFO size to 16 bytes for now. We don't program the 966 * Tx trigger. Also, we assume that all data has been sent when the 967 * interrupt happens. 968 */ 969 sc->sc_txfifosz = 16; 970 971 #if 0 972 /* 973 * XXX there are some issues related to hardware flow control and 974 * it's likely that uart(4) is the cause. This basically needs more 975 * investigation, but we avoid using for hardware flow control 976 * until then. 977 */ 978 /* 16650s or higher have automatic flow control. */ 979 if (sc->sc_rxfifosz > 16) { 980 sc->sc_hwiflow = 1; 981 sc->sc_hwoflow = 1; 982 } 983 #endif 984 985 return (0); 986 } 987 988 int 989 ns8250_bus_receive(struct uart_softc *sc) 990 { 991 struct uart_bas *bas; 992 int xc; 993 uint8_t lsr; 994 995 bas = &sc->sc_bas; 996 uart_lock(sc->sc_hwmtx); 997 lsr = uart_getreg(bas, REG_LSR); 998 while (lsr & LSR_RXRDY) { 999 if (uart_rx_full(sc)) { 1000 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1001 break; 1002 } 1003 xc = uart_getreg(bas, REG_DATA); 1004 if (lsr & LSR_FE) 1005 xc |= UART_STAT_FRAMERR; 1006 if (lsr & LSR_PE) 1007 xc |= UART_STAT_PARERR; 1008 uart_rx_put(sc, xc); 1009 lsr = uart_getreg(bas, REG_LSR); 1010 } 1011 /* Discard everything left in the Rx FIFO. */ 1012 while (lsr & LSR_RXRDY) { 1013 (void)uart_getreg(bas, REG_DATA); 1014 uart_barrier(bas); 1015 lsr = uart_getreg(bas, REG_LSR); 1016 } 1017 uart_unlock(sc->sc_hwmtx); 1018 return (0); 1019 } 1020 1021 int 1022 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1023 { 1024 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1025 struct uart_bas *bas; 1026 uint32_t new, old; 1027 1028 bas = &sc->sc_bas; 1029 do { 1030 old = sc->sc_hwsig; 1031 new = old; 1032 if (sig & SER_DDTR) { 1033 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1034 } 1035 if (sig & SER_DRTS) { 1036 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1037 } 1038 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1039 uart_lock(sc->sc_hwmtx); 1040 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1041 if (new & SER_DTR) 1042 ns8250->mcr |= MCR_DTR; 1043 if (new & SER_RTS) 1044 ns8250->mcr |= MCR_RTS; 1045 uart_setreg(bas, REG_MCR, ns8250->mcr); 1046 uart_barrier(bas); 1047 uart_unlock(sc->sc_hwmtx); 1048 return (0); 1049 } 1050 1051 int 1052 ns8250_bus_transmit(struct uart_softc *sc) 1053 { 1054 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1055 struct uart_bas *bas; 1056 int i; 1057 1058 bas = &sc->sc_bas; 1059 uart_lock(sc->sc_hwmtx); 1060 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1061 DELAY(4); 1062 for (i = 0; i < sc->sc_txdatasz; i++) { 1063 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1064 uart_barrier(bas); 1065 } 1066 if (!broken_txfifo) 1067 ns8250->ier |= IER_ETXRDY; 1068 uart_setreg(bas, REG_IER, ns8250->ier); 1069 uart_barrier(bas); 1070 if (broken_txfifo) 1071 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1072 else 1073 sc->sc_txbusy = 1; 1074 uart_unlock(sc->sc_hwmtx); 1075 if (broken_txfifo) 1076 uart_sched_softih(sc, SER_INT_TXIDLE); 1077 return (0); 1078 } 1079 1080 bool 1081 ns8250_bus_txbusy(struct uart_softc *sc) 1082 { 1083 struct uart_bas *bas = &sc->sc_bas; 1084 1085 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) != 1086 (LSR_TEMT | LSR_THRE)) 1087 return (true); 1088 return (false); 1089 } 1090 1091 void 1092 ns8250_bus_grab(struct uart_softc *sc) 1093 { 1094 struct uart_bas *bas = &sc->sc_bas; 1095 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1096 u_char ier; 1097 1098 /* 1099 * turn off all interrupts to enter polling mode. Leave the 1100 * saved mask alone. We'll restore whatever it was in ungrab. 1101 * All pending interrupt signals are reset when IER is set to 0. 1102 */ 1103 uart_lock(sc->sc_hwmtx); 1104 ier = uart_getreg(bas, REG_IER); 1105 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1106 uart_barrier(bas); 1107 uart_unlock(sc->sc_hwmtx); 1108 } 1109 1110 void 1111 ns8250_bus_ungrab(struct uart_softc *sc) 1112 { 1113 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1114 struct uart_bas *bas = &sc->sc_bas; 1115 1116 /* 1117 * Restore previous interrupt mask 1118 */ 1119 uart_lock(sc->sc_hwmtx); 1120 uart_setreg(bas, REG_IER, ns8250->ier); 1121 uart_barrier(bas); 1122 uart_unlock(sc->sc_hwmtx); 1123 } 1124