xref: /freebsd/sys/dev/uart/uart_dev_ns8250.c (revision 839529caa9c35f92b638dbe074655598e7a6bb6f)
1 /*-
2  * Copyright (c) 2003 Marcel Moolenaar
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include "opt_platform.h"
28 #include "opt_uart.h"
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40 
41 #ifdef FDT
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #endif
46 
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #ifdef FDT
50 #include <dev/uart/uart_cpu_fdt.h>
51 #endif
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
55 
56 #include <dev/ic/ns16550.h>
57 
58 #include "uart_if.h"
59 
60 #define	DEFAULT_RCLK	1843200
61 
62 /*
63  * Set the default baudrate tolerance to 3.0%.
64  *
65  * Some embedded boards have odd reference clocks (eg 25MHz)
66  * and we need to handle higher variances in the target baud rate.
67  */
68 #ifndef	UART_DEV_TOLERANCE_PCT
69 #define	UART_DEV_TOLERANCE_PCT	30
70 #endif	/* UART_DEV_TOLERANCE_PCT */
71 
72 static int broken_txfifo = 0;
73 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
74 	&broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
75 
76 /*
77  * Clear pending interrupts. THRE is cleared by reading IIR. Data
78  * that may have been received gets lost here.
79  */
80 static void
81 ns8250_clrint(struct uart_bas *bas)
82 {
83 	uint8_t iir, lsr;
84 
85 	iir = uart_getreg(bas, REG_IIR);
86 	while ((iir & IIR_NOPEND) == 0) {
87 		iir &= IIR_IMASK;
88 		if (iir == IIR_RLS) {
89 			lsr = uart_getreg(bas, REG_LSR);
90 			if (lsr & (LSR_BI|LSR_FE|LSR_PE))
91 				(void)uart_getreg(bas, REG_DATA);
92 		} else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
93 			(void)uart_getreg(bas, REG_DATA);
94 		else if (iir == IIR_MLSC)
95 			(void)uart_getreg(bas, REG_MSR);
96 		uart_barrier(bas);
97 		iir = uart_getreg(bas, REG_IIR);
98 	}
99 }
100 
101 static int
102 ns8250_delay(struct uart_bas *bas)
103 {
104 	int divisor;
105 	u_char lcr;
106 
107 	lcr = uart_getreg(bas, REG_LCR);
108 	uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
109 	uart_barrier(bas);
110 	divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
111 	uart_barrier(bas);
112 	uart_setreg(bas, REG_LCR, lcr);
113 	uart_barrier(bas);
114 
115 	/* 1/10th the time to transmit 1 character (estimate). */
116 	if (divisor <= 134)
117 		return (16000000 * divisor / bas->rclk);
118 	return (16000 * divisor / (bas->rclk / 1000));
119 }
120 
121 static int
122 ns8250_divisor(int rclk, int baudrate)
123 {
124 	int actual_baud, divisor;
125 	int error;
126 
127 	if (baudrate == 0)
128 		return (0);
129 
130 	divisor = (rclk / (baudrate << 3) + 1) >> 1;
131 	if (divisor == 0 || divisor >= 65536)
132 		return (0);
133 	actual_baud = rclk / (divisor << 4);
134 
135 	/* 10 times error in percent: */
136 	error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
137 
138 	/* enforce maximum error tolerance: */
139 	if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
140 		return (0);
141 
142 	return (divisor);
143 }
144 
145 static int
146 ns8250_drain(struct uart_bas *bas, int what)
147 {
148 	int delay, limit;
149 
150 	delay = ns8250_delay(bas);
151 
152 	if (what & UART_DRAIN_TRANSMITTER) {
153 		/*
154 		 * Pick an arbitrary high limit to avoid getting stuck in
155 		 * an infinite loop when the hardware is broken. Make the
156 		 * limit high enough to handle large FIFOs.
157 		 */
158 		limit = 10*1024;
159 		while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
160 			DELAY(delay);
161 		if (limit == 0) {
162 			/* printf("ns8250: transmitter appears stuck... "); */
163 			return (EIO);
164 		}
165 	}
166 
167 	if (what & UART_DRAIN_RECEIVER) {
168 		/*
169 		 * Pick an arbitrary high limit to avoid getting stuck in
170 		 * an infinite loop when the hardware is broken. Make the
171 		 * limit high enough to handle large FIFOs and integrated
172 		 * UARTs. The HP rx2600 for example has 3 UARTs on the
173 		 * management board that tend to get a lot of data send
174 		 * to it when the UART is first activated.
175 		 */
176 		limit=10*4096;
177 		while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
178 			(void)uart_getreg(bas, REG_DATA);
179 			uart_barrier(bas);
180 			DELAY(delay << 2);
181 		}
182 		if (limit == 0) {
183 			/* printf("ns8250: receiver appears broken... "); */
184 			return (EIO);
185 		}
186 	}
187 
188 	return (0);
189 }
190 
191 /*
192  * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
193  * drained. WARNING: this function clobbers the FIFO setting!
194  */
195 static void
196 ns8250_flush(struct uart_bas *bas, int what)
197 {
198 	uint8_t fcr;
199 
200 	fcr = FCR_ENABLE;
201 	if (what & UART_FLUSH_TRANSMITTER)
202 		fcr |= FCR_XMT_RST;
203 	if (what & UART_FLUSH_RECEIVER)
204 		fcr |= FCR_RCV_RST;
205 	uart_setreg(bas, REG_FCR, fcr);
206 	uart_barrier(bas);
207 }
208 
209 static int
210 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
211     int parity)
212 {
213 	int divisor;
214 	uint8_t lcr;
215 
216 	lcr = 0;
217 	if (databits >= 8)
218 		lcr |= LCR_8BITS;
219 	else if (databits == 7)
220 		lcr |= LCR_7BITS;
221 	else if (databits == 6)
222 		lcr |= LCR_6BITS;
223 	else
224 		lcr |= LCR_5BITS;
225 	if (stopbits > 1)
226 		lcr |= LCR_STOPB;
227 	lcr |= parity << 3;
228 
229 	/* Set baudrate. */
230 	if (baudrate > 0) {
231 		divisor = ns8250_divisor(bas->rclk, baudrate);
232 		if (divisor == 0)
233 			return (EINVAL);
234 		uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
235 		uart_barrier(bas);
236 		uart_setreg(bas, REG_DLL, divisor & 0xff);
237 		uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
238 		uart_barrier(bas);
239 	}
240 
241 	/* Set LCR and clear DLAB. */
242 	uart_setreg(bas, REG_LCR, lcr);
243 	uart_barrier(bas);
244 	return (0);
245 }
246 
247 /*
248  * Low-level UART interface.
249  */
250 static int ns8250_probe(struct uart_bas *bas);
251 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
252 static void ns8250_term(struct uart_bas *bas);
253 static void ns8250_putc(struct uart_bas *bas, int);
254 static int ns8250_rxready(struct uart_bas *bas);
255 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
256 
257 struct uart_ops uart_ns8250_ops = {
258 	.probe = ns8250_probe,
259 	.init = ns8250_init,
260 	.term = ns8250_term,
261 	.putc = ns8250_putc,
262 	.rxready = ns8250_rxready,
263 	.getc = ns8250_getc,
264 };
265 
266 static int
267 ns8250_probe(struct uart_bas *bas)
268 {
269 	u_char val;
270 
271 	/* Check known 0 bits that don't depend on DLAB. */
272 	val = uart_getreg(bas, REG_IIR);
273 	if (val & 0x30)
274 		return (ENXIO);
275 	/*
276 	 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
277 	 * chip, but otherwise doesn't seem to have a function. In
278 	 * other words, uart(4) works regardless. Ignore that bit so
279 	 * the probe succeeds.
280 	 */
281 	val = uart_getreg(bas, REG_MCR);
282 	if (val & 0xa0)
283 		return (ENXIO);
284 
285 	return (0);
286 }
287 
288 static void
289 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
290     int parity)
291 {
292 	u_char	ier;
293 
294 	if (bas->rclk == 0)
295 		bas->rclk = DEFAULT_RCLK;
296 	ns8250_param(bas, baudrate, databits, stopbits, parity);
297 
298 	/* Disable all interrupt sources. */
299 	/*
300 	 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
301 	 * UARTs split the receive time-out interrupt bit out separately as
302 	 * 0x10.  This gets handled by ier_mask and ier_rxbits below.
303 	 */
304 	ier = uart_getreg(bas, REG_IER) & 0xe0;
305 	uart_setreg(bas, REG_IER, ier);
306 	uart_barrier(bas);
307 
308 	/* Disable the FIFO (if present). */
309 	uart_setreg(bas, REG_FCR, 0);
310 	uart_barrier(bas);
311 
312 	/* Set RTS & DTR. */
313 	uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
314 	uart_barrier(bas);
315 
316 	ns8250_clrint(bas);
317 }
318 
319 static void
320 ns8250_term(struct uart_bas *bas)
321 {
322 
323 	/* Clear RTS & DTR. */
324 	uart_setreg(bas, REG_MCR, MCR_IE);
325 	uart_barrier(bas);
326 }
327 
328 static void
329 ns8250_putc(struct uart_bas *bas, int c)
330 {
331 	int limit;
332 
333 	limit = 250000;
334 	while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
335 		DELAY(4);
336 	uart_setreg(bas, REG_DATA, c);
337 	uart_barrier(bas);
338 	limit = 250000;
339 	while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
340 		DELAY(4);
341 }
342 
343 static int
344 ns8250_rxready(struct uart_bas *bas)
345 {
346 
347 	return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
348 }
349 
350 static int
351 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
352 {
353 	int c;
354 
355 	uart_lock(hwmtx);
356 
357 	while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
358 		uart_unlock(hwmtx);
359 		DELAY(4);
360 		uart_lock(hwmtx);
361 	}
362 
363 	c = uart_getreg(bas, REG_DATA);
364 
365 	uart_unlock(hwmtx);
366 
367 	return (c);
368 }
369 
370 static kobj_method_t ns8250_methods[] = {
371 	KOBJMETHOD(uart_attach,		ns8250_bus_attach),
372 	KOBJMETHOD(uart_detach,		ns8250_bus_detach),
373 	KOBJMETHOD(uart_flush,		ns8250_bus_flush),
374 	KOBJMETHOD(uart_getsig,		ns8250_bus_getsig),
375 	KOBJMETHOD(uart_ioctl,		ns8250_bus_ioctl),
376 	KOBJMETHOD(uart_ipend,		ns8250_bus_ipend),
377 	KOBJMETHOD(uart_param,		ns8250_bus_param),
378 	KOBJMETHOD(uart_probe,		ns8250_bus_probe),
379 	KOBJMETHOD(uart_receive,	ns8250_bus_receive),
380 	KOBJMETHOD(uart_setsig,		ns8250_bus_setsig),
381 	KOBJMETHOD(uart_transmit,	ns8250_bus_transmit),
382 	KOBJMETHOD(uart_grab,		ns8250_bus_grab),
383 	KOBJMETHOD(uart_ungrab,		ns8250_bus_ungrab),
384 	{ 0, 0 }
385 };
386 
387 struct uart_class uart_ns8250_class = {
388 	"ns8250",
389 	ns8250_methods,
390 	sizeof(struct ns8250_softc),
391 	.uc_ops = &uart_ns8250_ops,
392 	.uc_range = 8,
393 	.uc_rclk = DEFAULT_RCLK,
394 	.uc_rshift = 0
395 };
396 
397 #ifdef FDT
398 static struct ofw_compat_data compat_data[] = {
399 	{"ns16550",		(uintptr_t)&uart_ns8250_class},
400 	{"snps,dw-apb-uart",	(uintptr_t)&uart_ns8250_class},
401 	{NULL,			(uintptr_t)NULL},
402 };
403 UART_FDT_CLASS_AND_DEVICE(compat_data);
404 #endif
405 
406 /* Use token-pasting to form SER_ and MSR_ named constants. */
407 #define	SER(sig)	SER_##sig
408 #define	SERD(sig)	SER_D##sig
409 #define	MSR(sig)	MSR_##sig
410 #define	MSRD(sig)	MSR_D##sig
411 
412 /*
413  * Detect signal changes using software delta detection.  The previous state of
414  * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
415  * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
416  * new state of both the signal and the delta bits.
417  */
418 #define SIGCHGSW(var, msr, sig)					\
419 	if ((msr) & MSR(sig)) {					\
420 		if ((var & SER(sig)) == 0)			\
421 			var |= SERD(sig) | SER(sig);		\
422 	} else {						\
423 		if ((var & SER(sig)) != 0)			\
424 			var = SERD(sig) | (var & ~SER(sig));	\
425 	}
426 
427 /*
428  * Detect signal changes using the hardware msr delta bits.  This is currently
429  * used only when PPS timing information is being captured using the "narrow
430  * pulse" option.  With a narrow PPS pulse the signal may not still be asserted
431  * by time the interrupt handler is invoked.  The hardware will latch the fact
432  * that it changed in the delta bits.
433  */
434 #define SIGCHGHW(var, msr, sig)					\
435 	if ((msr) & MSRD(sig)) {				\
436 		if (((msr) & MSR(sig)) != 0)			\
437 			var |= SERD(sig) | SER(sig);		\
438 		else						\
439 			var = SERD(sig) | (var & ~SER(sig));	\
440 	}
441 
442 int
443 ns8250_bus_attach(struct uart_softc *sc)
444 {
445 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
446 	struct uart_bas *bas;
447 	unsigned int ivar;
448 #ifdef FDT
449 	phandle_t node;
450 	pcell_t cell;
451 #endif
452 
453 	ns8250->busy_detect = 0;
454 
455 #ifdef FDT
456 	/*
457 	 * Check whether uart requires to read USR reg when IIR_BUSY and
458 	 * has broken txfifo.
459 	 */
460 	ns8250->busy_detect = ofw_bus_is_compatible(sc->sc_dev, "snps,dw-apb-uart");
461 	node = ofw_bus_get_node(sc->sc_dev);
462 	/* XXX: This is kept for a short time for compatibility with older device trees */
463 	if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0
464 	    && cell != 0)
465 		ns8250->busy_detect = 1;
466 	if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
467 		broken_txfifo =  cell ? 1 : 0;
468 #endif
469 
470 	bas = &sc->sc_bas;
471 
472 	ns8250->mcr = uart_getreg(bas, REG_MCR);
473 	ns8250->fcr = FCR_ENABLE;
474 	if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
475 	    &ivar)) {
476 		if (UART_FLAGS_FCR_RX_LOW(ivar))
477 			ns8250->fcr |= FCR_RX_LOW;
478 		else if (UART_FLAGS_FCR_RX_MEDL(ivar))
479 			ns8250->fcr |= FCR_RX_MEDL;
480 		else if (UART_FLAGS_FCR_RX_HIGH(ivar))
481 			ns8250->fcr |= FCR_RX_HIGH;
482 		else
483 			ns8250->fcr |= FCR_RX_MEDH;
484 	} else
485 		ns8250->fcr |= FCR_RX_MEDH;
486 
487 	/* Get IER mask */
488 	ivar = 0xf0;
489 	resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
490 	    &ivar);
491 	ns8250->ier_mask = (uint8_t)(ivar & 0xff);
492 
493 	/* Get IER RX interrupt bits */
494 	ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
495 	resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
496 	    &ivar);
497 	ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
498 
499 	uart_setreg(bas, REG_FCR, ns8250->fcr);
500 	uart_barrier(bas);
501 	ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
502 
503 	if (ns8250->mcr & MCR_DTR)
504 		sc->sc_hwsig |= SER_DTR;
505 	if (ns8250->mcr & MCR_RTS)
506 		sc->sc_hwsig |= SER_RTS;
507 	ns8250_bus_getsig(sc);
508 
509 	ns8250_clrint(bas);
510 	ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
511 	ns8250->ier |= ns8250->ier_rxbits;
512 	uart_setreg(bas, REG_IER, ns8250->ier);
513 	uart_barrier(bas);
514 
515 	/*
516 	 * Timing of the H/W access was changed with r253161 of uart_core.c
517 	 * It has been observed that an ITE IT8513E would signal a break
518 	 * condition with pretty much every character it received, unless
519 	 * it had enough time to settle between ns8250_bus_attach() and
520 	 * ns8250_bus_ipend() -- which it accidentally had before r253161.
521 	 * It's not understood why the UART chip behaves this way and it
522 	 * could very well be that the DELAY make the H/W work in the same
523 	 * accidental manner as before. More analysis is warranted, but
524 	 * at least now we fixed a known regression.
525 	 */
526 	DELAY(200);
527 	return (0);
528 }
529 
530 int
531 ns8250_bus_detach(struct uart_softc *sc)
532 {
533 	struct ns8250_softc *ns8250;
534 	struct uart_bas *bas;
535 	u_char ier;
536 
537 	ns8250 = (struct ns8250_softc *)sc;
538 	bas = &sc->sc_bas;
539 	ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
540 	uart_setreg(bas, REG_IER, ier);
541 	uart_barrier(bas);
542 	ns8250_clrint(bas);
543 	return (0);
544 }
545 
546 int
547 ns8250_bus_flush(struct uart_softc *sc, int what)
548 {
549 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
550 	struct uart_bas *bas;
551 	int error;
552 
553 	bas = &sc->sc_bas;
554 	uart_lock(sc->sc_hwmtx);
555 	if (sc->sc_rxfifosz > 1) {
556 		ns8250_flush(bas, what);
557 		uart_setreg(bas, REG_FCR, ns8250->fcr);
558 		uart_barrier(bas);
559 		error = 0;
560 	} else
561 		error = ns8250_drain(bas, what);
562 	uart_unlock(sc->sc_hwmtx);
563 	return (error);
564 }
565 
566 int
567 ns8250_bus_getsig(struct uart_softc *sc)
568 {
569 	uint32_t old, sig;
570 	uint8_t msr;
571 
572 	/*
573 	 * The delta bits are reputed to be broken on some hardware, so use
574 	 * software delta detection by default.  Use the hardware delta bits
575 	 * when capturing PPS pulses which are too narrow for software detection
576 	 * to see the edges.  Hardware delta for RI doesn't work like the
577 	 * others, so always use software for it.  Other threads may be changing
578 	 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
579 	 * update without other changes happening.  Note that the SIGCHGxx()
580 	 * macros carefully preserve the delta bits when we have to loop several
581 	 * times and a signal transitions between iterations.
582 	 */
583 	do {
584 		old = sc->sc_hwsig;
585 		sig = old;
586 		uart_lock(sc->sc_hwmtx);
587 		msr = uart_getreg(&sc->sc_bas, REG_MSR);
588 		uart_unlock(sc->sc_hwmtx);
589 		if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
590 			SIGCHGHW(sig, msr, DSR);
591 			SIGCHGHW(sig, msr, CTS);
592 			SIGCHGHW(sig, msr, DCD);
593 		} else {
594 			SIGCHGSW(sig, msr, DSR);
595 			SIGCHGSW(sig, msr, CTS);
596 			SIGCHGSW(sig, msr, DCD);
597 		}
598 		SIGCHGSW(sig, msr, RI);
599 	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
600 	return (sig);
601 }
602 
603 int
604 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
605 {
606 	struct uart_bas *bas;
607 	int baudrate, divisor, error;
608 	uint8_t efr, lcr;
609 
610 	bas = &sc->sc_bas;
611 	error = 0;
612 	uart_lock(sc->sc_hwmtx);
613 	switch (request) {
614 	case UART_IOCTL_BREAK:
615 		lcr = uart_getreg(bas, REG_LCR);
616 		if (data)
617 			lcr |= LCR_SBREAK;
618 		else
619 			lcr &= ~LCR_SBREAK;
620 		uart_setreg(bas, REG_LCR, lcr);
621 		uart_barrier(bas);
622 		break;
623 	case UART_IOCTL_IFLOW:
624 		lcr = uart_getreg(bas, REG_LCR);
625 		uart_barrier(bas);
626 		uart_setreg(bas, REG_LCR, 0xbf);
627 		uart_barrier(bas);
628 		efr = uart_getreg(bas, REG_EFR);
629 		if (data)
630 			efr |= EFR_RTS;
631 		else
632 			efr &= ~EFR_RTS;
633 		uart_setreg(bas, REG_EFR, efr);
634 		uart_barrier(bas);
635 		uart_setreg(bas, REG_LCR, lcr);
636 		uart_barrier(bas);
637 		break;
638 	case UART_IOCTL_OFLOW:
639 		lcr = uart_getreg(bas, REG_LCR);
640 		uart_barrier(bas);
641 		uart_setreg(bas, REG_LCR, 0xbf);
642 		uart_barrier(bas);
643 		efr = uart_getreg(bas, REG_EFR);
644 		if (data)
645 			efr |= EFR_CTS;
646 		else
647 			efr &= ~EFR_CTS;
648 		uart_setreg(bas, REG_EFR, efr);
649 		uart_barrier(bas);
650 		uart_setreg(bas, REG_LCR, lcr);
651 		uart_barrier(bas);
652 		break;
653 	case UART_IOCTL_BAUD:
654 		lcr = uart_getreg(bas, REG_LCR);
655 		uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
656 		uart_barrier(bas);
657 		divisor = uart_getreg(bas, REG_DLL) |
658 		    (uart_getreg(bas, REG_DLH) << 8);
659 		uart_barrier(bas);
660 		uart_setreg(bas, REG_LCR, lcr);
661 		uart_barrier(bas);
662 		baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
663 		if (baudrate > 0)
664 			*(int*)data = baudrate;
665 		else
666 			error = ENXIO;
667 		break;
668 	default:
669 		error = EINVAL;
670 		break;
671 	}
672 	uart_unlock(sc->sc_hwmtx);
673 	return (error);
674 }
675 
676 int
677 ns8250_bus_ipend(struct uart_softc *sc)
678 {
679 	struct uart_bas *bas;
680 	struct ns8250_softc *ns8250;
681 	int ipend;
682 	uint8_t iir, lsr;
683 
684 	ns8250 = (struct ns8250_softc *)sc;
685 	bas = &sc->sc_bas;
686 	uart_lock(sc->sc_hwmtx);
687 	iir = uart_getreg(bas, REG_IIR);
688 
689 	if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
690 		(void)uart_getreg(bas, DW_REG_USR);
691 		uart_unlock(sc->sc_hwmtx);
692 		return (0);
693 	}
694 	if (iir & IIR_NOPEND) {
695 		uart_unlock(sc->sc_hwmtx);
696 		return (0);
697 	}
698 	ipend = 0;
699 	if (iir & IIR_RXRDY) {
700 		lsr = uart_getreg(bas, REG_LSR);
701 		if (lsr & LSR_OE)
702 			ipend |= SER_INT_OVERRUN;
703 		if (lsr & LSR_BI)
704 			ipend |= SER_INT_BREAK;
705 		if (lsr & LSR_RXRDY)
706 			ipend |= SER_INT_RXREADY;
707 	} else {
708 		if (iir & IIR_TXRDY) {
709 			ipend |= SER_INT_TXIDLE;
710 			uart_setreg(bas, REG_IER, ns8250->ier);
711 			uart_barrier(bas);
712 		} else
713 			ipend |= SER_INT_SIGCHG;
714 	}
715 	if (ipend == 0)
716 		ns8250_clrint(bas);
717 	uart_unlock(sc->sc_hwmtx);
718 	return (ipend);
719 }
720 
721 int
722 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
723     int stopbits, int parity)
724 {
725 	struct ns8250_softc *ns8250;
726 	struct uart_bas *bas;
727 	int error, limit;
728 
729 	ns8250 = (struct ns8250_softc*)sc;
730 	bas = &sc->sc_bas;
731 	uart_lock(sc->sc_hwmtx);
732 	/*
733 	 * When using DW UART with BUSY detection it is necessary to wait
734 	 * until all serial transfers are finished before manipulating the
735 	 * line control. LCR will not be affected when UART is busy.
736 	 */
737 	if (ns8250->busy_detect != 0) {
738 		/*
739 		 * Pick an arbitrary high limit to avoid getting stuck in
740 		 * an infinite loop in case when the hardware is broken.
741 		 */
742 		limit = 10 * 1024;
743 		while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
744 		    --limit)
745 			DELAY(4);
746 
747 		if (limit <= 0) {
748 			/* UART appears to be stuck */
749 			uart_unlock(sc->sc_hwmtx);
750 			return (EIO);
751 		}
752 	}
753 
754 	error = ns8250_param(bas, baudrate, databits, stopbits, parity);
755 	uart_unlock(sc->sc_hwmtx);
756 	return (error);
757 }
758 
759 int
760 ns8250_bus_probe(struct uart_softc *sc)
761 {
762 	struct ns8250_softc *ns8250;
763 	struct uart_bas *bas;
764 	int count, delay, error, limit;
765 	uint8_t lsr, mcr, ier;
766 
767 	ns8250 = (struct ns8250_softc *)sc;
768 	bas = &sc->sc_bas;
769 
770 	error = ns8250_probe(bas);
771 	if (error)
772 		return (error);
773 
774 	mcr = MCR_IE;
775 	if (sc->sc_sysdev == NULL) {
776 		/* By using ns8250_init() we also set DTR and RTS. */
777 		ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
778 	} else
779 		mcr |= MCR_DTR | MCR_RTS;
780 
781 	error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
782 	if (error)
783 		return (error);
784 
785 	/*
786 	 * Set loopback mode. This avoids having garbage on the wire and
787 	 * also allows us send and receive data. We set DTR and RTS to
788 	 * avoid the possibility that automatic flow-control prevents
789 	 * any data from being sent.
790 	 */
791 	uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
792 	uart_barrier(bas);
793 
794 	/*
795 	 * Enable FIFOs. And check that the UART has them. If not, we're
796 	 * done. Since this is the first time we enable the FIFOs, we reset
797 	 * them.
798 	 */
799 	uart_setreg(bas, REG_FCR, FCR_ENABLE);
800 	uart_barrier(bas);
801 	if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
802 		/*
803 		 * NS16450 or INS8250. We don't bother to differentiate
804 		 * between them. They're too old to be interesting.
805 		 */
806 		uart_setreg(bas, REG_MCR, mcr);
807 		uart_barrier(bas);
808 		sc->sc_rxfifosz = sc->sc_txfifosz = 1;
809 		device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
810 		return (0);
811 	}
812 
813 	uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
814 	uart_barrier(bas);
815 
816 	count = 0;
817 	delay = ns8250_delay(bas);
818 
819 	/* We have FIFOs. Drain the transmitter and receiver. */
820 	error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
821 	if (error) {
822 		uart_setreg(bas, REG_MCR, mcr);
823 		uart_setreg(bas, REG_FCR, 0);
824 		uart_barrier(bas);
825 		goto describe;
826 	}
827 
828 	/*
829 	 * We should have a sufficiently clean "pipe" to determine the
830 	 * size of the FIFOs. We send as much characters as is reasonable
831 	 * and wait for the overflow bit in the LSR register to be
832 	 * asserted, counting the characters as we send them. Based on
833 	 * that count we know the FIFO size.
834 	 */
835 	do {
836 		uart_setreg(bas, REG_DATA, 0);
837 		uart_barrier(bas);
838 		count++;
839 
840 		limit = 30;
841 		lsr = 0;
842 		/*
843 		 * LSR bits are cleared upon read, so we must accumulate
844 		 * them to be able to test LSR_OE below.
845 		 */
846 		while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
847 		    --limit)
848 			DELAY(delay);
849 		if (limit == 0) {
850 			ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
851 			uart_setreg(bas, REG_IER, ier);
852 			uart_setreg(bas, REG_MCR, mcr);
853 			uart_setreg(bas, REG_FCR, 0);
854 			uart_barrier(bas);
855 			count = 0;
856 			goto describe;
857 		}
858 	} while ((lsr & LSR_OE) == 0 && count < 130);
859 	count--;
860 
861 	uart_setreg(bas, REG_MCR, mcr);
862 
863 	/* Reset FIFOs. */
864 	ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
865 
866  describe:
867 	if (count >= 14 && count <= 16) {
868 		sc->sc_rxfifosz = 16;
869 		device_set_desc(sc->sc_dev, "16550 or compatible");
870 	} else if (count >= 28 && count <= 32) {
871 		sc->sc_rxfifosz = 32;
872 		device_set_desc(sc->sc_dev, "16650 or compatible");
873 	} else if (count >= 56 && count <= 64) {
874 		sc->sc_rxfifosz = 64;
875 		device_set_desc(sc->sc_dev, "16750 or compatible");
876 	} else if (count >= 112 && count <= 128) {
877 		sc->sc_rxfifosz = 128;
878 		device_set_desc(sc->sc_dev, "16950 or compatible");
879 	} else {
880 		sc->sc_rxfifosz = 16;
881 		device_set_desc(sc->sc_dev,
882 		    "Non-standard ns8250 class UART with FIFOs");
883 	}
884 
885 	/*
886 	 * Force the Tx FIFO size to 16 bytes for now. We don't program the
887 	 * Tx trigger. Also, we assume that all data has been sent when the
888 	 * interrupt happens.
889 	 */
890 	sc->sc_txfifosz = 16;
891 
892 #if 0
893 	/*
894 	 * XXX there are some issues related to hardware flow control and
895 	 * it's likely that uart(4) is the cause. This basicly needs more
896 	 * investigation, but we avoid using for hardware flow control
897 	 * until then.
898 	 */
899 	/* 16650s or higher have automatic flow control. */
900 	if (sc->sc_rxfifosz > 16) {
901 		sc->sc_hwiflow = 1;
902 		sc->sc_hwoflow = 1;
903 	}
904 #endif
905 
906 	return (0);
907 }
908 
909 int
910 ns8250_bus_receive(struct uart_softc *sc)
911 {
912 	struct uart_bas *bas;
913 	int xc;
914 	uint8_t lsr;
915 
916 	bas = &sc->sc_bas;
917 	uart_lock(sc->sc_hwmtx);
918 	lsr = uart_getreg(bas, REG_LSR);
919 	while (lsr & LSR_RXRDY) {
920 		if (uart_rx_full(sc)) {
921 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
922 			break;
923 		}
924 		xc = uart_getreg(bas, REG_DATA);
925 		if (lsr & LSR_FE)
926 			xc |= UART_STAT_FRAMERR;
927 		if (lsr & LSR_PE)
928 			xc |= UART_STAT_PARERR;
929 		uart_rx_put(sc, xc);
930 		lsr = uart_getreg(bas, REG_LSR);
931 	}
932 	/* Discard everything left in the Rx FIFO. */
933 	while (lsr & LSR_RXRDY) {
934 		(void)uart_getreg(bas, REG_DATA);
935 		uart_barrier(bas);
936 		lsr = uart_getreg(bas, REG_LSR);
937 	}
938 	uart_unlock(sc->sc_hwmtx);
939  	return (0);
940 }
941 
942 int
943 ns8250_bus_setsig(struct uart_softc *sc, int sig)
944 {
945 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
946 	struct uart_bas *bas;
947 	uint32_t new, old;
948 
949 	bas = &sc->sc_bas;
950 	do {
951 		old = sc->sc_hwsig;
952 		new = old;
953 		if (sig & SER_DDTR) {
954 			new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
955 		}
956 		if (sig & SER_DRTS) {
957 			new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
958 		}
959 	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
960 	uart_lock(sc->sc_hwmtx);
961 	ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
962 	if (new & SER_DTR)
963 		ns8250->mcr |= MCR_DTR;
964 	if (new & SER_RTS)
965 		ns8250->mcr |= MCR_RTS;
966 	uart_setreg(bas, REG_MCR, ns8250->mcr);
967 	uart_barrier(bas);
968 	uart_unlock(sc->sc_hwmtx);
969 	return (0);
970 }
971 
972 int
973 ns8250_bus_transmit(struct uart_softc *sc)
974 {
975 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
976 	struct uart_bas *bas;
977 	int i;
978 
979 	bas = &sc->sc_bas;
980 	uart_lock(sc->sc_hwmtx);
981 	while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
982 		;
983 	for (i = 0; i < sc->sc_txdatasz; i++) {
984 		uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
985 		uart_barrier(bas);
986 	}
987 	uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
988 	uart_barrier(bas);
989 	if (broken_txfifo)
990 		ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
991 	else
992 		sc->sc_txbusy = 1;
993 	uart_unlock(sc->sc_hwmtx);
994 	if (broken_txfifo)
995 		uart_sched_softih(sc, SER_INT_TXIDLE);
996 	return (0);
997 }
998 
999 void
1000 ns8250_bus_grab(struct uart_softc *sc)
1001 {
1002 	struct uart_bas *bas = &sc->sc_bas;
1003 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1004 	u_char ier;
1005 
1006 	/*
1007 	 * turn off all interrupts to enter polling mode. Leave the
1008 	 * saved mask alone. We'll restore whatever it was in ungrab.
1009 	 * All pending interupt signals are reset when IER is set to 0.
1010 	 */
1011 	uart_lock(sc->sc_hwmtx);
1012 	ier = uart_getreg(bas, REG_IER);
1013 	uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1014 	uart_barrier(bas);
1015 	uart_unlock(sc->sc_hwmtx);
1016 }
1017 
1018 void
1019 ns8250_bus_ungrab(struct uart_softc *sc)
1020 {
1021 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1022 	struct uart_bas *bas = &sc->sc_bas;
1023 
1024 	/*
1025 	 * Restore previous interrupt mask
1026 	 */
1027 	uart_lock(sc->sc_hwmtx);
1028 	uart_setreg(bas, REG_IER, ns8250->ier);
1029 	uart_barrier(bas);
1030 	uart_unlock(sc->sc_hwmtx);
1031 }
1032