1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 #include "opt_uart.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 56 #include <dev/ic/ns16550.h> 57 58 #include "uart_if.h" 59 60 #define DEFAULT_RCLK 1843200 61 62 /* 63 * Set the default baudrate tolerance to 3.0%. 64 * 65 * Some embedded boards have odd reference clocks (eg 25MHz) 66 * and we need to handle higher variances in the target baud rate. 67 */ 68 #ifndef UART_DEV_TOLERANCE_PCT 69 #define UART_DEV_TOLERANCE_PCT 30 70 #endif /* UART_DEV_TOLERANCE_PCT */ 71 72 static int broken_txfifo = 0; 73 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75 76 /* 77 * Clear pending interrupts. THRE is cleared by reading IIR. Data 78 * that may have been received gets lost here. 79 */ 80 static void 81 ns8250_clrint(struct uart_bas *bas) 82 { 83 uint8_t iir, lsr; 84 85 iir = uart_getreg(bas, REG_IIR); 86 while ((iir & IIR_NOPEND) == 0) { 87 iir &= IIR_IMASK; 88 if (iir == IIR_RLS) { 89 lsr = uart_getreg(bas, REG_LSR); 90 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91 (void)uart_getreg(bas, REG_DATA); 92 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 93 (void)uart_getreg(bas, REG_DATA); 94 else if (iir == IIR_MLSC) 95 (void)uart_getreg(bas, REG_MSR); 96 uart_barrier(bas); 97 iir = uart_getreg(bas, REG_IIR); 98 } 99 } 100 101 static int 102 ns8250_delay(struct uart_bas *bas) 103 { 104 int divisor; 105 u_char lcr; 106 107 lcr = uart_getreg(bas, REG_LCR); 108 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 109 uart_barrier(bas); 110 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 111 uart_barrier(bas); 112 uart_setreg(bas, REG_LCR, lcr); 113 uart_barrier(bas); 114 115 /* 1/10th the time to transmit 1 character (estimate). */ 116 if (divisor <= 134) 117 return (16000000 * divisor / bas->rclk); 118 return (16000 * divisor / (bas->rclk / 1000)); 119 } 120 121 static int 122 ns8250_divisor(int rclk, int baudrate) 123 { 124 int actual_baud, divisor; 125 int error; 126 127 if (baudrate == 0) 128 return (0); 129 130 divisor = (rclk / (baudrate << 3) + 1) >> 1; 131 if (divisor == 0 || divisor >= 65536) 132 return (0); 133 actual_baud = rclk / (divisor << 4); 134 135 /* 10 times error in percent: */ 136 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 137 138 /* enforce maximum error tolerance: */ 139 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 140 return (0); 141 142 return (divisor); 143 } 144 145 static int 146 ns8250_drain(struct uart_bas *bas, int what) 147 { 148 int delay, limit; 149 150 delay = ns8250_delay(bas); 151 152 if (what & UART_DRAIN_TRANSMITTER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs. 157 */ 158 limit = 10*1024; 159 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 160 DELAY(delay); 161 if (limit == 0) { 162 /* printf("ns8250: transmitter appears stuck... "); */ 163 return (EIO); 164 } 165 } 166 167 if (what & UART_DRAIN_RECEIVER) { 168 /* 169 * Pick an arbitrary high limit to avoid getting stuck in 170 * an infinite loop when the hardware is broken. Make the 171 * limit high enough to handle large FIFOs and integrated 172 * UARTs. The HP rx2600 for example has 3 UARTs on the 173 * management board that tend to get a lot of data send 174 * to it when the UART is first activated. 175 */ 176 limit=10*4096; 177 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 178 (void)uart_getreg(bas, REG_DATA); 179 uart_barrier(bas); 180 DELAY(delay << 2); 181 } 182 if (limit == 0) { 183 /* printf("ns8250: receiver appears broken... "); */ 184 return (EIO); 185 } 186 } 187 188 return (0); 189 } 190 191 /* 192 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 193 * drained. WARNING: this function clobbers the FIFO setting! 194 */ 195 static void 196 ns8250_flush(struct uart_bas *bas, int what) 197 { 198 uint8_t fcr; 199 200 fcr = FCR_ENABLE; 201 #ifdef CPU_XBURST 202 fcr |= FCR_UART_ON; 203 #endif 204 if (what & UART_FLUSH_TRANSMITTER) 205 fcr |= FCR_XMT_RST; 206 if (what & UART_FLUSH_RECEIVER) 207 fcr |= FCR_RCV_RST; 208 uart_setreg(bas, REG_FCR, fcr); 209 uart_barrier(bas); 210 } 211 212 static int 213 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 214 int parity) 215 { 216 int divisor; 217 uint8_t lcr; 218 219 lcr = 0; 220 if (databits >= 8) 221 lcr |= LCR_8BITS; 222 else if (databits == 7) 223 lcr |= LCR_7BITS; 224 else if (databits == 6) 225 lcr |= LCR_6BITS; 226 else 227 lcr |= LCR_5BITS; 228 if (stopbits > 1) 229 lcr |= LCR_STOPB; 230 lcr |= parity << 3; 231 232 /* Set baudrate. */ 233 if (baudrate > 0) { 234 divisor = ns8250_divisor(bas->rclk, baudrate); 235 if (divisor == 0) 236 return (EINVAL); 237 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 238 uart_barrier(bas); 239 uart_setreg(bas, REG_DLL, divisor & 0xff); 240 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 241 uart_barrier(bas); 242 } 243 244 /* Set LCR and clear DLAB. */ 245 uart_setreg(bas, REG_LCR, lcr); 246 uart_barrier(bas); 247 return (0); 248 } 249 250 /* 251 * Low-level UART interface. 252 */ 253 static int ns8250_probe(struct uart_bas *bas); 254 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 255 static void ns8250_term(struct uart_bas *bas); 256 static void ns8250_putc(struct uart_bas *bas, int); 257 static int ns8250_rxready(struct uart_bas *bas); 258 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 259 260 struct uart_ops uart_ns8250_ops = { 261 .probe = ns8250_probe, 262 .init = ns8250_init, 263 .term = ns8250_term, 264 .putc = ns8250_putc, 265 .rxready = ns8250_rxready, 266 .getc = ns8250_getc, 267 }; 268 269 static int 270 ns8250_probe(struct uart_bas *bas) 271 { 272 u_char val; 273 274 #ifdef CPU_XBURST 275 uart_setreg(bas, REG_FCR, FCR_UART_ON); 276 #endif 277 278 /* Check known 0 bits that don't depend on DLAB. */ 279 val = uart_getreg(bas, REG_IIR); 280 if (val & 0x30) 281 return (ENXIO); 282 /* 283 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 284 * chip, but otherwise doesn't seem to have a function. In 285 * other words, uart(4) works regardless. Ignore that bit so 286 * the probe succeeds. 287 */ 288 val = uart_getreg(bas, REG_MCR); 289 if (val & 0xa0) 290 return (ENXIO); 291 292 return (0); 293 } 294 295 static void 296 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 297 int parity) 298 { 299 u_char ier, val; 300 301 if (bas->rclk == 0) 302 bas->rclk = DEFAULT_RCLK; 303 ns8250_param(bas, baudrate, databits, stopbits, parity); 304 305 /* Disable all interrupt sources. */ 306 /* 307 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 308 * UARTs split the receive time-out interrupt bit out separately as 309 * 0x10. This gets handled by ier_mask and ier_rxbits below. 310 */ 311 ier = uart_getreg(bas, REG_IER) & 0xe0; 312 uart_setreg(bas, REG_IER, ier); 313 uart_barrier(bas); 314 315 /* Disable the FIFO (if present). */ 316 val = 0; 317 #ifdef CPU_XBURST 318 val = FCR_UART_ON; 319 #endif 320 uart_setreg(bas, REG_FCR, val); 321 uart_barrier(bas); 322 323 /* Set RTS & DTR. */ 324 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 325 uart_barrier(bas); 326 327 ns8250_clrint(bas); 328 } 329 330 static void 331 ns8250_term(struct uart_bas *bas) 332 { 333 334 /* Clear RTS & DTR. */ 335 uart_setreg(bas, REG_MCR, MCR_IE); 336 uart_barrier(bas); 337 } 338 339 static void 340 ns8250_putc(struct uart_bas *bas, int c) 341 { 342 int limit; 343 344 limit = 250000; 345 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 346 DELAY(4); 347 uart_setreg(bas, REG_DATA, c); 348 uart_barrier(bas); 349 limit = 250000; 350 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 351 DELAY(4); 352 } 353 354 static int 355 ns8250_rxready(struct uart_bas *bas) 356 { 357 358 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 359 } 360 361 static int 362 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 363 { 364 int c; 365 366 uart_lock(hwmtx); 367 368 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 369 uart_unlock(hwmtx); 370 DELAY(4); 371 uart_lock(hwmtx); 372 } 373 374 c = uart_getreg(bas, REG_DATA); 375 376 uart_unlock(hwmtx); 377 378 return (c); 379 } 380 381 static kobj_method_t ns8250_methods[] = { 382 KOBJMETHOD(uart_attach, ns8250_bus_attach), 383 KOBJMETHOD(uart_detach, ns8250_bus_detach), 384 KOBJMETHOD(uart_flush, ns8250_bus_flush), 385 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 386 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 387 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 388 KOBJMETHOD(uart_param, ns8250_bus_param), 389 KOBJMETHOD(uart_probe, ns8250_bus_probe), 390 KOBJMETHOD(uart_receive, ns8250_bus_receive), 391 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 392 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 393 KOBJMETHOD(uart_grab, ns8250_bus_grab), 394 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 395 { 0, 0 } 396 }; 397 398 struct uart_class uart_ns8250_class = { 399 "ns8250", 400 ns8250_methods, 401 sizeof(struct ns8250_softc), 402 .uc_ops = &uart_ns8250_ops, 403 .uc_range = 8, 404 .uc_rclk = DEFAULT_RCLK, 405 .uc_rshift = 0 406 }; 407 408 #ifdef FDT 409 static struct ofw_compat_data compat_data[] = { 410 {"ns16550", (uintptr_t)&uart_ns8250_class}, 411 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 412 {NULL, (uintptr_t)NULL}, 413 }; 414 UART_FDT_CLASS_AND_DEVICE(compat_data); 415 #endif 416 417 /* Use token-pasting to form SER_ and MSR_ named constants. */ 418 #define SER(sig) SER_##sig 419 #define SERD(sig) SER_D##sig 420 #define MSR(sig) MSR_##sig 421 #define MSRD(sig) MSR_D##sig 422 423 /* 424 * Detect signal changes using software delta detection. The previous state of 425 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 426 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 427 * new state of both the signal and the delta bits. 428 */ 429 #define SIGCHGSW(var, msr, sig) \ 430 if ((msr) & MSR(sig)) { \ 431 if ((var & SER(sig)) == 0) \ 432 var |= SERD(sig) | SER(sig); \ 433 } else { \ 434 if ((var & SER(sig)) != 0) \ 435 var = SERD(sig) | (var & ~SER(sig)); \ 436 } 437 438 /* 439 * Detect signal changes using the hardware msr delta bits. This is currently 440 * used only when PPS timing information is being captured using the "narrow 441 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 442 * by time the interrupt handler is invoked. The hardware will latch the fact 443 * that it changed in the delta bits. 444 */ 445 #define SIGCHGHW(var, msr, sig) \ 446 if ((msr) & MSRD(sig)) { \ 447 if (((msr) & MSR(sig)) != 0) \ 448 var |= SERD(sig) | SER(sig); \ 449 else \ 450 var = SERD(sig) | (var & ~SER(sig)); \ 451 } 452 453 int 454 ns8250_bus_attach(struct uart_softc *sc) 455 { 456 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 457 struct uart_bas *bas; 458 unsigned int ivar; 459 #ifdef FDT 460 phandle_t node; 461 pcell_t cell; 462 #endif 463 464 #ifdef FDT 465 /* Check whether uart has a broken txfifo. */ 466 node = ofw_bus_get_node(sc->sc_dev); 467 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 468 broken_txfifo = cell ? 1 : 0; 469 #endif 470 471 bas = &sc->sc_bas; 472 473 ns8250->mcr = uart_getreg(bas, REG_MCR); 474 ns8250->fcr = FCR_ENABLE; 475 #ifdef CPU_XBURST 476 ns8250->fcr |= FCR_UART_ON; 477 #endif 478 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 479 &ivar)) { 480 if (UART_FLAGS_FCR_RX_LOW(ivar)) 481 ns8250->fcr |= FCR_RX_LOW; 482 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 483 ns8250->fcr |= FCR_RX_MEDL; 484 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 485 ns8250->fcr |= FCR_RX_HIGH; 486 else 487 ns8250->fcr |= FCR_RX_MEDH; 488 } else 489 ns8250->fcr |= FCR_RX_MEDH; 490 491 /* Get IER mask */ 492 ivar = 0xf0; 493 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 494 &ivar); 495 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 496 497 /* Get IER RX interrupt bits */ 498 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 499 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 500 &ivar); 501 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 502 503 uart_setreg(bas, REG_FCR, ns8250->fcr); 504 uart_barrier(bas); 505 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 506 507 if (ns8250->mcr & MCR_DTR) 508 sc->sc_hwsig |= SER_DTR; 509 if (ns8250->mcr & MCR_RTS) 510 sc->sc_hwsig |= SER_RTS; 511 ns8250_bus_getsig(sc); 512 513 ns8250_clrint(bas); 514 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 515 ns8250->ier |= ns8250->ier_rxbits; 516 uart_setreg(bas, REG_IER, ns8250->ier); 517 uart_barrier(bas); 518 519 /* 520 * Timing of the H/W access was changed with r253161 of uart_core.c 521 * It has been observed that an ITE IT8513E would signal a break 522 * condition with pretty much every character it received, unless 523 * it had enough time to settle between ns8250_bus_attach() and 524 * ns8250_bus_ipend() -- which it accidentally had before r253161. 525 * It's not understood why the UART chip behaves this way and it 526 * could very well be that the DELAY make the H/W work in the same 527 * accidental manner as before. More analysis is warranted, but 528 * at least now we fixed a known regression. 529 */ 530 DELAY(200); 531 return (0); 532 } 533 534 int 535 ns8250_bus_detach(struct uart_softc *sc) 536 { 537 struct ns8250_softc *ns8250; 538 struct uart_bas *bas; 539 u_char ier; 540 541 ns8250 = (struct ns8250_softc *)sc; 542 bas = &sc->sc_bas; 543 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 544 uart_setreg(bas, REG_IER, ier); 545 uart_barrier(bas); 546 ns8250_clrint(bas); 547 return (0); 548 } 549 550 int 551 ns8250_bus_flush(struct uart_softc *sc, int what) 552 { 553 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 554 struct uart_bas *bas; 555 int error; 556 557 bas = &sc->sc_bas; 558 uart_lock(sc->sc_hwmtx); 559 if (sc->sc_rxfifosz > 1) { 560 ns8250_flush(bas, what); 561 uart_setreg(bas, REG_FCR, ns8250->fcr); 562 uart_barrier(bas); 563 error = 0; 564 } else 565 error = ns8250_drain(bas, what); 566 uart_unlock(sc->sc_hwmtx); 567 return (error); 568 } 569 570 int 571 ns8250_bus_getsig(struct uart_softc *sc) 572 { 573 uint32_t old, sig; 574 uint8_t msr; 575 576 /* 577 * The delta bits are reputed to be broken on some hardware, so use 578 * software delta detection by default. Use the hardware delta bits 579 * when capturing PPS pulses which are too narrow for software detection 580 * to see the edges. Hardware delta for RI doesn't work like the 581 * others, so always use software for it. Other threads may be changing 582 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 583 * update without other changes happening. Note that the SIGCHGxx() 584 * macros carefully preserve the delta bits when we have to loop several 585 * times and a signal transitions between iterations. 586 */ 587 do { 588 old = sc->sc_hwsig; 589 sig = old; 590 uart_lock(sc->sc_hwmtx); 591 msr = uart_getreg(&sc->sc_bas, REG_MSR); 592 uart_unlock(sc->sc_hwmtx); 593 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 594 SIGCHGHW(sig, msr, DSR); 595 SIGCHGHW(sig, msr, CTS); 596 SIGCHGHW(sig, msr, DCD); 597 } else { 598 SIGCHGSW(sig, msr, DSR); 599 SIGCHGSW(sig, msr, CTS); 600 SIGCHGSW(sig, msr, DCD); 601 } 602 SIGCHGSW(sig, msr, RI); 603 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 604 return (sig); 605 } 606 607 int 608 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 609 { 610 struct uart_bas *bas; 611 int baudrate, divisor, error; 612 uint8_t efr, lcr; 613 614 bas = &sc->sc_bas; 615 error = 0; 616 uart_lock(sc->sc_hwmtx); 617 switch (request) { 618 case UART_IOCTL_BREAK: 619 lcr = uart_getreg(bas, REG_LCR); 620 if (data) 621 lcr |= LCR_SBREAK; 622 else 623 lcr &= ~LCR_SBREAK; 624 uart_setreg(bas, REG_LCR, lcr); 625 uart_barrier(bas); 626 break; 627 case UART_IOCTL_IFLOW: 628 lcr = uart_getreg(bas, REG_LCR); 629 uart_barrier(bas); 630 uart_setreg(bas, REG_LCR, 0xbf); 631 uart_barrier(bas); 632 efr = uart_getreg(bas, REG_EFR); 633 if (data) 634 efr |= EFR_RTS; 635 else 636 efr &= ~EFR_RTS; 637 uart_setreg(bas, REG_EFR, efr); 638 uart_barrier(bas); 639 uart_setreg(bas, REG_LCR, lcr); 640 uart_barrier(bas); 641 break; 642 case UART_IOCTL_OFLOW: 643 lcr = uart_getreg(bas, REG_LCR); 644 uart_barrier(bas); 645 uart_setreg(bas, REG_LCR, 0xbf); 646 uart_barrier(bas); 647 efr = uart_getreg(bas, REG_EFR); 648 if (data) 649 efr |= EFR_CTS; 650 else 651 efr &= ~EFR_CTS; 652 uart_setreg(bas, REG_EFR, efr); 653 uart_barrier(bas); 654 uart_setreg(bas, REG_LCR, lcr); 655 uart_barrier(bas); 656 break; 657 case UART_IOCTL_BAUD: 658 lcr = uart_getreg(bas, REG_LCR); 659 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 660 uart_barrier(bas); 661 divisor = uart_getreg(bas, REG_DLL) | 662 (uart_getreg(bas, REG_DLH) << 8); 663 uart_barrier(bas); 664 uart_setreg(bas, REG_LCR, lcr); 665 uart_barrier(bas); 666 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 667 if (baudrate > 0) 668 *(int*)data = baudrate; 669 else 670 error = ENXIO; 671 break; 672 default: 673 error = EINVAL; 674 break; 675 } 676 uart_unlock(sc->sc_hwmtx); 677 return (error); 678 } 679 680 int 681 ns8250_bus_ipend(struct uart_softc *sc) 682 { 683 struct uart_bas *bas; 684 struct ns8250_softc *ns8250; 685 int ipend; 686 uint8_t iir, lsr; 687 688 ns8250 = (struct ns8250_softc *)sc; 689 bas = &sc->sc_bas; 690 uart_lock(sc->sc_hwmtx); 691 iir = uart_getreg(bas, REG_IIR); 692 693 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 694 (void)uart_getreg(bas, DW_REG_USR); 695 uart_unlock(sc->sc_hwmtx); 696 return (0); 697 } 698 if (iir & IIR_NOPEND) { 699 uart_unlock(sc->sc_hwmtx); 700 return (0); 701 } 702 ipend = 0; 703 if (iir & IIR_RXRDY) { 704 lsr = uart_getreg(bas, REG_LSR); 705 if (lsr & LSR_OE) 706 ipend |= SER_INT_OVERRUN; 707 if (lsr & LSR_BI) 708 ipend |= SER_INT_BREAK; 709 if (lsr & LSR_RXRDY) 710 ipend |= SER_INT_RXREADY; 711 } else { 712 if (iir & IIR_TXRDY) { 713 ipend |= SER_INT_TXIDLE; 714 uart_setreg(bas, REG_IER, ns8250->ier); 715 uart_barrier(bas); 716 } else 717 ipend |= SER_INT_SIGCHG; 718 } 719 if (ipend == 0) 720 ns8250_clrint(bas); 721 uart_unlock(sc->sc_hwmtx); 722 return (ipend); 723 } 724 725 int 726 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 727 int stopbits, int parity) 728 { 729 struct ns8250_softc *ns8250; 730 struct uart_bas *bas; 731 int error, limit; 732 733 ns8250 = (struct ns8250_softc*)sc; 734 bas = &sc->sc_bas; 735 uart_lock(sc->sc_hwmtx); 736 /* 737 * When using DW UART with BUSY detection it is necessary to wait 738 * until all serial transfers are finished before manipulating the 739 * line control. LCR will not be affected when UART is busy. 740 */ 741 if (ns8250->busy_detect != 0) { 742 /* 743 * Pick an arbitrary high limit to avoid getting stuck in 744 * an infinite loop in case when the hardware is broken. 745 */ 746 limit = 10 * 1024; 747 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 748 --limit) 749 DELAY(4); 750 751 if (limit <= 0) { 752 /* UART appears to be stuck */ 753 uart_unlock(sc->sc_hwmtx); 754 return (EIO); 755 } 756 } 757 758 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 759 uart_unlock(sc->sc_hwmtx); 760 return (error); 761 } 762 763 int 764 ns8250_bus_probe(struct uart_softc *sc) 765 { 766 struct ns8250_softc *ns8250; 767 struct uart_bas *bas; 768 int count, delay, error, limit; 769 uint8_t lsr, mcr, ier; 770 uint8_t val; 771 772 ns8250 = (struct ns8250_softc *)sc; 773 bas = &sc->sc_bas; 774 775 error = ns8250_probe(bas); 776 if (error) 777 return (error); 778 779 mcr = MCR_IE; 780 if (sc->sc_sysdev == NULL) { 781 /* By using ns8250_init() we also set DTR and RTS. */ 782 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 783 } else 784 mcr |= MCR_DTR | MCR_RTS; 785 786 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 787 if (error) 788 return (error); 789 790 /* 791 * Set loopback mode. This avoids having garbage on the wire and 792 * also allows us send and receive data. We set DTR and RTS to 793 * avoid the possibility that automatic flow-control prevents 794 * any data from being sent. 795 */ 796 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 797 uart_barrier(bas); 798 799 /* 800 * Enable FIFOs. And check that the UART has them. If not, we're 801 * done. Since this is the first time we enable the FIFOs, we reset 802 * them. 803 */ 804 val = FCR_ENABLE; 805 #ifdef CPU_XBURST 806 val |= FCR_UART_ON; 807 #endif 808 uart_setreg(bas, REG_FCR, val); 809 uart_barrier(bas); 810 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 811 /* 812 * NS16450 or INS8250. We don't bother to differentiate 813 * between them. They're too old to be interesting. 814 */ 815 uart_setreg(bas, REG_MCR, mcr); 816 uart_barrier(bas); 817 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 818 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 819 return (0); 820 } 821 822 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 823 #ifdef CPU_XBURST 824 val |= FCR_UART_ON; 825 #endif 826 uart_setreg(bas, REG_FCR, val); 827 uart_barrier(bas); 828 829 count = 0; 830 delay = ns8250_delay(bas); 831 832 /* We have FIFOs. Drain the transmitter and receiver. */ 833 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 834 if (error) { 835 uart_setreg(bas, REG_MCR, mcr); 836 val = 0; 837 #ifdef CPU_XBURST 838 val |= FCR_UART_ON; 839 #endif 840 uart_setreg(bas, REG_FCR, val); 841 uart_barrier(bas); 842 goto describe; 843 } 844 845 /* 846 * We should have a sufficiently clean "pipe" to determine the 847 * size of the FIFOs. We send as much characters as is reasonable 848 * and wait for the overflow bit in the LSR register to be 849 * asserted, counting the characters as we send them. Based on 850 * that count we know the FIFO size. 851 */ 852 do { 853 uart_setreg(bas, REG_DATA, 0); 854 uart_barrier(bas); 855 count++; 856 857 limit = 30; 858 lsr = 0; 859 /* 860 * LSR bits are cleared upon read, so we must accumulate 861 * them to be able to test LSR_OE below. 862 */ 863 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 864 --limit) 865 DELAY(delay); 866 if (limit == 0) { 867 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 868 uart_setreg(bas, REG_IER, ier); 869 uart_setreg(bas, REG_MCR, mcr); 870 val = 0; 871 #ifdef CPU_XBURST 872 val |= FCR_UART_ON; 873 #endif 874 uart_setreg(bas, REG_FCR, val); 875 uart_barrier(bas); 876 count = 0; 877 goto describe; 878 } 879 } while ((lsr & LSR_OE) == 0 && count < 130); 880 count--; 881 882 uart_setreg(bas, REG_MCR, mcr); 883 884 /* Reset FIFOs. */ 885 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 886 887 describe: 888 if (count >= 14 && count <= 16) { 889 sc->sc_rxfifosz = 16; 890 device_set_desc(sc->sc_dev, "16550 or compatible"); 891 } else if (count >= 28 && count <= 32) { 892 sc->sc_rxfifosz = 32; 893 device_set_desc(sc->sc_dev, "16650 or compatible"); 894 } else if (count >= 56 && count <= 64) { 895 sc->sc_rxfifosz = 64; 896 device_set_desc(sc->sc_dev, "16750 or compatible"); 897 } else if (count >= 112 && count <= 128) { 898 sc->sc_rxfifosz = 128; 899 device_set_desc(sc->sc_dev, "16950 or compatible"); 900 } else { 901 sc->sc_rxfifosz = 16; 902 device_set_desc(sc->sc_dev, 903 "Non-standard ns8250 class UART with FIFOs"); 904 } 905 906 /* 907 * Force the Tx FIFO size to 16 bytes for now. We don't program the 908 * Tx trigger. Also, we assume that all data has been sent when the 909 * interrupt happens. 910 */ 911 sc->sc_txfifosz = 16; 912 913 #if 0 914 /* 915 * XXX there are some issues related to hardware flow control and 916 * it's likely that uart(4) is the cause. This basically needs more 917 * investigation, but we avoid using for hardware flow control 918 * until then. 919 */ 920 /* 16650s or higher have automatic flow control. */ 921 if (sc->sc_rxfifosz > 16) { 922 sc->sc_hwiflow = 1; 923 sc->sc_hwoflow = 1; 924 } 925 #endif 926 927 return (0); 928 } 929 930 int 931 ns8250_bus_receive(struct uart_softc *sc) 932 { 933 struct uart_bas *bas; 934 int xc; 935 uint8_t lsr; 936 937 bas = &sc->sc_bas; 938 uart_lock(sc->sc_hwmtx); 939 lsr = uart_getreg(bas, REG_LSR); 940 while (lsr & LSR_RXRDY) { 941 if (uart_rx_full(sc)) { 942 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 943 break; 944 } 945 xc = uart_getreg(bas, REG_DATA); 946 if (lsr & LSR_FE) 947 xc |= UART_STAT_FRAMERR; 948 if (lsr & LSR_PE) 949 xc |= UART_STAT_PARERR; 950 uart_rx_put(sc, xc); 951 lsr = uart_getreg(bas, REG_LSR); 952 } 953 /* Discard everything left in the Rx FIFO. */ 954 while (lsr & LSR_RXRDY) { 955 (void)uart_getreg(bas, REG_DATA); 956 uart_barrier(bas); 957 lsr = uart_getreg(bas, REG_LSR); 958 } 959 uart_unlock(sc->sc_hwmtx); 960 return (0); 961 } 962 963 int 964 ns8250_bus_setsig(struct uart_softc *sc, int sig) 965 { 966 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 967 struct uart_bas *bas; 968 uint32_t new, old; 969 970 bas = &sc->sc_bas; 971 do { 972 old = sc->sc_hwsig; 973 new = old; 974 if (sig & SER_DDTR) { 975 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 976 } 977 if (sig & SER_DRTS) { 978 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 979 } 980 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 981 uart_lock(sc->sc_hwmtx); 982 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 983 if (new & SER_DTR) 984 ns8250->mcr |= MCR_DTR; 985 if (new & SER_RTS) 986 ns8250->mcr |= MCR_RTS; 987 uart_setreg(bas, REG_MCR, ns8250->mcr); 988 uart_barrier(bas); 989 uart_unlock(sc->sc_hwmtx); 990 return (0); 991 } 992 993 int 994 ns8250_bus_transmit(struct uart_softc *sc) 995 { 996 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 997 struct uart_bas *bas; 998 int i; 999 1000 bas = &sc->sc_bas; 1001 uart_lock(sc->sc_hwmtx); 1002 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1003 ; 1004 for (i = 0; i < sc->sc_txdatasz; i++) { 1005 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1006 uart_barrier(bas); 1007 } 1008 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 1009 uart_barrier(bas); 1010 if (broken_txfifo) 1011 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1012 else 1013 sc->sc_txbusy = 1; 1014 uart_unlock(sc->sc_hwmtx); 1015 if (broken_txfifo) 1016 uart_sched_softih(sc, SER_INT_TXIDLE); 1017 return (0); 1018 } 1019 1020 void 1021 ns8250_bus_grab(struct uart_softc *sc) 1022 { 1023 struct uart_bas *bas = &sc->sc_bas; 1024 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1025 u_char ier; 1026 1027 /* 1028 * turn off all interrupts to enter polling mode. Leave the 1029 * saved mask alone. We'll restore whatever it was in ungrab. 1030 * All pending interrupt signals are reset when IER is set to 0. 1031 */ 1032 uart_lock(sc->sc_hwmtx); 1033 ier = uart_getreg(bas, REG_IER); 1034 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1035 uart_barrier(bas); 1036 uart_unlock(sc->sc_hwmtx); 1037 } 1038 1039 void 1040 ns8250_bus_ungrab(struct uart_softc *sc) 1041 { 1042 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1043 struct uart_bas *bas = &sc->sc_bas; 1044 1045 /* 1046 * Restore previous interrupt mask 1047 */ 1048 uart_lock(sc->sc_hwmtx); 1049 uart_setreg(bas, REG_IER, ns8250->ier); 1050 uart_barrier(bas); 1051 uart_unlock(sc->sc_hwmtx); 1052 } 1053