1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <machine/bus.h> 41 42 #ifdef FDT 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #endif 47 48 #include <dev/uart/uart.h> 49 #include <dev/uart/uart_cpu.h> 50 #ifdef FDT 51 #include <dev/uart/uart_cpu_fdt.h> 52 #endif 53 #include <dev/uart/uart_bus.h> 54 #include <dev/uart/uart_dev_ns8250.h> 55 #include <dev/uart/uart_ppstypes.h> 56 #ifdef DEV_ACPI 57 #include <dev/uart/uart_cpu_acpi.h> 58 #include <contrib/dev/acpica/include/acpi.h> 59 #endif 60 61 #include <dev/ic/ns16550.h> 62 63 #include "uart_if.h" 64 65 #define DEFAULT_RCLK 1843200 66 67 /* 68 * Set the default baudrate tolerance to 3.0%. 69 * 70 * Some embedded boards have odd reference clocks (eg 25MHz) 71 * and we need to handle higher variances in the target baud rate. 72 */ 73 #ifndef UART_DEV_TOLERANCE_PCT 74 #define UART_DEV_TOLERANCE_PCT 30 75 #endif /* UART_DEV_TOLERANCE_PCT */ 76 77 static int broken_txfifo = 0; 78 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 79 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 80 81 /* 82 * To use early printf on x86, add the following to your kernel config: 83 * 84 * options UART_NS8250_EARLY_PORT=0x3f8 85 * options EARLY_PRINTF 86 */ 87 #if defined(EARLY_PRINTF) && (defined(__amd64__) || defined(__i386__)) 88 static void 89 uart_ns8250_early_putc(int c) 90 { 91 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 92 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 93 int limit = 10000; /* 10ms is plenty of time */ 94 95 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 96 continue; 97 outb(tx, c); 98 } 99 early_putc_t *early_putc = uart_ns8250_early_putc; 100 #endif /* EARLY_PRINTF */ 101 102 /* 103 * Clear pending interrupts. THRE is cleared by reading IIR. Data 104 * that may have been received gets lost here. 105 */ 106 static void 107 ns8250_clrint(struct uart_bas *bas) 108 { 109 uint8_t iir, lsr; 110 111 iir = uart_getreg(bas, REG_IIR); 112 while ((iir & IIR_NOPEND) == 0) { 113 iir &= IIR_IMASK; 114 if (iir == IIR_RLS) { 115 lsr = uart_getreg(bas, REG_LSR); 116 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 117 (void)uart_getreg(bas, REG_DATA); 118 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 119 (void)uart_getreg(bas, REG_DATA); 120 else if (iir == IIR_MLSC) 121 (void)uart_getreg(bas, REG_MSR); 122 uart_barrier(bas); 123 iir = uart_getreg(bas, REG_IIR); 124 } 125 } 126 127 static int 128 ns8250_delay(struct uart_bas *bas) 129 { 130 int divisor; 131 u_char lcr; 132 133 lcr = uart_getreg(bas, REG_LCR); 134 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 135 uart_barrier(bas); 136 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 137 uart_barrier(bas); 138 uart_setreg(bas, REG_LCR, lcr); 139 uart_barrier(bas); 140 141 /* 1/10th the time to transmit 1 character (estimate). */ 142 if (divisor <= 134) 143 return (16000000 * divisor / bas->rclk); 144 return (16000 * divisor / (bas->rclk / 1000)); 145 } 146 147 static int 148 ns8250_divisor(int rclk, int baudrate) 149 { 150 int actual_baud, divisor; 151 int error; 152 153 if (baudrate == 0) 154 return (0); 155 156 divisor = (rclk / (baudrate << 3) + 1) >> 1; 157 if (divisor == 0 || divisor >= 65536) 158 return (0); 159 actual_baud = rclk / (divisor << 4); 160 161 /* 10 times error in percent: */ 162 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 163 164 /* enforce maximum error tolerance: */ 165 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 166 return (0); 167 168 return (divisor); 169 } 170 171 static int 172 ns8250_drain(struct uart_bas *bas, int what) 173 { 174 int delay, limit; 175 176 delay = ns8250_delay(bas); 177 178 if (what & UART_DRAIN_TRANSMITTER) { 179 /* 180 * Pick an arbitrary high limit to avoid getting stuck in 181 * an infinite loop when the hardware is broken. Make the 182 * limit high enough to handle large FIFOs. 183 */ 184 limit = 10*1024; 185 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 186 DELAY(delay); 187 if (limit == 0) { 188 /* printf("ns8250: transmitter appears stuck... "); */ 189 return (EIO); 190 } 191 } 192 193 if (what & UART_DRAIN_RECEIVER) { 194 /* 195 * Pick an arbitrary high limit to avoid getting stuck in 196 * an infinite loop when the hardware is broken. Make the 197 * limit high enough to handle large FIFOs and integrated 198 * UARTs. The HP rx2600 for example has 3 UARTs on the 199 * management board that tend to get a lot of data send 200 * to it when the UART is first activated. Assume that we 201 * have finished draining if LSR_RXRDY is not asserted both 202 * prior to and after a DELAY; but as long as LSR_RXRDY is 203 * asserted, read (and discard) characters as quickly as 204 * possible. 205 */ 206 limit=10*4096; 207 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 208 do { 209 (void)uart_getreg(bas, REG_DATA); 210 uart_barrier(bas); 211 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 212 uart_barrier(bas); 213 DELAY(delay << 2); 214 } 215 if (limit == 0) { 216 /* printf("ns8250: receiver appears broken... "); */ 217 return (EIO); 218 } 219 } 220 221 return (0); 222 } 223 224 /* 225 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 226 * drained. WARNING: this function clobbers the FIFO setting! 227 */ 228 static void 229 ns8250_flush(struct uart_bas *bas, int what) 230 { 231 uint8_t fcr; 232 uint8_t lsr; 233 int drain = 0; 234 235 fcr = FCR_ENABLE; 236 #ifdef CPU_XBURST 237 fcr |= FCR_UART_ON; 238 #endif 239 if (what & UART_FLUSH_TRANSMITTER) 240 fcr |= FCR_XMT_RST; 241 if (what & UART_FLUSH_RECEIVER) 242 fcr |= FCR_RCV_RST; 243 uart_setreg(bas, REG_FCR, fcr); 244 uart_barrier(bas); 245 246 /* 247 * Detect and work around emulated UARTs which don't implement the 248 * FCR register; on these systems we need to drain the FIFO since 249 * the flush we request doesn't happen. One such system is the 250 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 251 * https://github.com/rust-vmm/vm-superio/issues/83 252 */ 253 lsr = uart_getreg(bas, REG_LSR); 254 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 255 drain |= UART_DRAIN_TRANSMITTER; 256 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 257 drain |= UART_DRAIN_RECEIVER; 258 if (drain != 0) { 259 printf("ns8250: UART FCR is broken\n"); 260 ns8250_drain(bas, drain); 261 } 262 } 263 264 static int 265 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 266 int parity) 267 { 268 int divisor; 269 uint8_t lcr; 270 271 /* Don't change settings when running on Hyper-V */ 272 if (vm_guest == VM_GUEST_HV) 273 return (0); 274 275 lcr = 0; 276 if (databits >= 8) 277 lcr |= LCR_8BITS; 278 else if (databits == 7) 279 lcr |= LCR_7BITS; 280 else if (databits == 6) 281 lcr |= LCR_6BITS; 282 else 283 lcr |= LCR_5BITS; 284 if (stopbits > 1) 285 lcr |= LCR_STOPB; 286 lcr |= parity << 3; 287 288 /* Set baudrate. */ 289 if (baudrate > 0) { 290 divisor = ns8250_divisor(bas->rclk, baudrate); 291 if (divisor == 0) 292 return (EINVAL); 293 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 294 uart_barrier(bas); 295 uart_setreg(bas, REG_DLL, divisor & 0xff); 296 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 297 uart_barrier(bas); 298 } 299 300 /* Set LCR and clear DLAB. */ 301 uart_setreg(bas, REG_LCR, lcr); 302 uart_barrier(bas); 303 return (0); 304 } 305 306 /* 307 * Low-level UART interface. 308 */ 309 static int ns8250_probe(struct uart_bas *bas); 310 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 311 static void ns8250_term(struct uart_bas *bas); 312 static void ns8250_putc(struct uart_bas *bas, int); 313 static int ns8250_rxready(struct uart_bas *bas); 314 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 315 316 struct uart_ops uart_ns8250_ops = { 317 .probe = ns8250_probe, 318 .init = ns8250_init, 319 .term = ns8250_term, 320 .putc = ns8250_putc, 321 .rxready = ns8250_rxready, 322 .getc = ns8250_getc, 323 }; 324 325 static int 326 ns8250_probe(struct uart_bas *bas) 327 { 328 u_char val; 329 330 #ifdef CPU_XBURST 331 uart_setreg(bas, REG_FCR, FCR_UART_ON); 332 #endif 333 334 /* Check known 0 bits that don't depend on DLAB. */ 335 val = uart_getreg(bas, REG_IIR); 336 if (val & 0x30) 337 return (ENXIO); 338 /* 339 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 340 * chip, but otherwise doesn't seem to have a function. In 341 * other words, uart(4) works regardless. Ignore that bit so 342 * the probe succeeds. 343 */ 344 val = uart_getreg(bas, REG_MCR); 345 if (val & 0xa0) 346 return (ENXIO); 347 348 return (0); 349 } 350 351 static void 352 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 353 int parity) 354 { 355 u_char ier, val; 356 357 if (bas->rclk == 0) 358 bas->rclk = DEFAULT_RCLK; 359 ns8250_param(bas, baudrate, databits, stopbits, parity); 360 361 /* Disable all interrupt sources. */ 362 /* 363 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 364 * UARTs split the receive time-out interrupt bit out separately as 365 * 0x10. This gets handled by ier_mask and ier_rxbits below. 366 */ 367 ier = uart_getreg(bas, REG_IER) & 0xe0; 368 uart_setreg(bas, REG_IER, ier); 369 uart_barrier(bas); 370 371 /* Disable the FIFO (if present). */ 372 val = 0; 373 #ifdef CPU_XBURST 374 val |= FCR_UART_ON; 375 #endif 376 uart_setreg(bas, REG_FCR, val); 377 uart_barrier(bas); 378 379 /* Set RTS & DTR. */ 380 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 381 uart_barrier(bas); 382 383 ns8250_clrint(bas); 384 } 385 386 static void 387 ns8250_term(struct uart_bas *bas) 388 { 389 390 /* Clear RTS & DTR. */ 391 uart_setreg(bas, REG_MCR, MCR_IE); 392 uart_barrier(bas); 393 } 394 395 static void 396 ns8250_putc(struct uart_bas *bas, int c) 397 { 398 int limit; 399 400 if (vm_guest != VM_GUEST_HV) { 401 limit = 250000; 402 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 403 DELAY(4); 404 } 405 uart_setreg(bas, REG_DATA, c); 406 uart_barrier(bas); 407 } 408 409 static int 410 ns8250_rxready(struct uart_bas *bas) 411 { 412 413 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 414 } 415 416 static int 417 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 418 { 419 int c; 420 421 uart_lock(hwmtx); 422 423 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 424 uart_unlock(hwmtx); 425 DELAY(4); 426 uart_lock(hwmtx); 427 } 428 429 c = uart_getreg(bas, REG_DATA); 430 431 uart_unlock(hwmtx); 432 433 return (c); 434 } 435 436 static kobj_method_t ns8250_methods[] = { 437 KOBJMETHOD(uart_attach, ns8250_bus_attach), 438 KOBJMETHOD(uart_detach, ns8250_bus_detach), 439 KOBJMETHOD(uart_flush, ns8250_bus_flush), 440 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 441 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 442 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 443 KOBJMETHOD(uart_param, ns8250_bus_param), 444 KOBJMETHOD(uart_probe, ns8250_bus_probe), 445 KOBJMETHOD(uart_receive, ns8250_bus_receive), 446 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 447 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 448 KOBJMETHOD(uart_grab, ns8250_bus_grab), 449 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 450 { 0, 0 } 451 }; 452 453 struct uart_class uart_ns8250_class = { 454 "ns8250", 455 ns8250_methods, 456 sizeof(struct ns8250_softc), 457 .uc_ops = &uart_ns8250_ops, 458 .uc_range = 8, 459 .uc_rclk = DEFAULT_RCLK, 460 .uc_rshift = 0 461 }; 462 463 /* 464 * XXX -- refactor out ACPI and FDT ifdefs 465 */ 466 #ifdef DEV_ACPI 467 static struct acpi_uart_compat_data acpi_compat_data[] = { 468 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 469 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 470 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 471 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 472 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 473 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 474 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 475 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 476 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 477 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 478 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 479 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 480 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 481 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 482 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 483 }; 484 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 485 #endif 486 487 #ifdef FDT 488 static struct ofw_compat_data compat_data[] = { 489 {"ns16550", (uintptr_t)&uart_ns8250_class}, 490 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 491 {NULL, (uintptr_t)NULL}, 492 }; 493 UART_FDT_CLASS_AND_DEVICE(compat_data); 494 #endif 495 496 /* Use token-pasting to form SER_ and MSR_ named constants. */ 497 #define SER(sig) SER_##sig 498 #define SERD(sig) SER_D##sig 499 #define MSR(sig) MSR_##sig 500 #define MSRD(sig) MSR_D##sig 501 502 /* 503 * Detect signal changes using software delta detection. The previous state of 504 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 505 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 506 * new state of both the signal and the delta bits. 507 */ 508 #define SIGCHGSW(var, msr, sig) \ 509 if ((msr) & MSR(sig)) { \ 510 if ((var & SER(sig)) == 0) \ 511 var |= SERD(sig) | SER(sig); \ 512 } else { \ 513 if ((var & SER(sig)) != 0) \ 514 var = SERD(sig) | (var & ~SER(sig)); \ 515 } 516 517 /* 518 * Detect signal changes using the hardware msr delta bits. This is currently 519 * used only when PPS timing information is being captured using the "narrow 520 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 521 * by time the interrupt handler is invoked. The hardware will latch the fact 522 * that it changed in the delta bits. 523 */ 524 #define SIGCHGHW(var, msr, sig) \ 525 if ((msr) & MSRD(sig)) { \ 526 if (((msr) & MSR(sig)) != 0) \ 527 var |= SERD(sig) | SER(sig); \ 528 else \ 529 var = SERD(sig) | (var & ~SER(sig)); \ 530 } 531 532 int 533 ns8250_bus_attach(struct uart_softc *sc) 534 { 535 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 536 struct uart_bas *bas; 537 unsigned int ivar; 538 #ifdef FDT 539 phandle_t node; 540 pcell_t cell; 541 #endif 542 543 #ifdef FDT 544 /* Check whether uart has a broken txfifo. */ 545 node = ofw_bus_get_node(sc->sc_dev); 546 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 547 broken_txfifo = cell ? 1 : 0; 548 #endif 549 550 bas = &sc->sc_bas; 551 552 ns8250->busy_detect = bas->busy_detect; 553 ns8250->mcr = uart_getreg(bas, REG_MCR); 554 ns8250->fcr = FCR_ENABLE; 555 #ifdef CPU_XBURST 556 ns8250->fcr |= FCR_UART_ON; 557 #endif 558 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 559 &ivar)) { 560 if (UART_FLAGS_FCR_RX_LOW(ivar)) 561 ns8250->fcr |= FCR_RX_LOW; 562 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 563 ns8250->fcr |= FCR_RX_MEDL; 564 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 565 ns8250->fcr |= FCR_RX_HIGH; 566 else 567 ns8250->fcr |= FCR_RX_MEDH; 568 } else 569 ns8250->fcr |= FCR_RX_MEDH; 570 571 /* Get IER mask */ 572 ivar = 0xf0; 573 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 574 &ivar); 575 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 576 577 /* Get IER RX interrupt bits */ 578 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 579 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 580 &ivar); 581 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 582 583 uart_setreg(bas, REG_FCR, ns8250->fcr); 584 uart_barrier(bas); 585 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 586 587 if (ns8250->mcr & MCR_DTR) 588 sc->sc_hwsig |= SER_DTR; 589 if (ns8250->mcr & MCR_RTS) 590 sc->sc_hwsig |= SER_RTS; 591 ns8250_bus_getsig(sc); 592 593 ns8250_clrint(bas); 594 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 595 ns8250->ier |= ns8250->ier_rxbits; 596 uart_setreg(bas, REG_IER, ns8250->ier); 597 uart_barrier(bas); 598 599 /* 600 * Timing of the H/W access was changed with r253161 of uart_core.c 601 * It has been observed that an ITE IT8513E would signal a break 602 * condition with pretty much every character it received, unless 603 * it had enough time to settle between ns8250_bus_attach() and 604 * ns8250_bus_ipend() -- which it accidentally had before r253161. 605 * It's not understood why the UART chip behaves this way and it 606 * could very well be that the DELAY make the H/W work in the same 607 * accidental manner as before. More analysis is warranted, but 608 * at least now we fixed a known regression. 609 */ 610 DELAY(200); 611 return (0); 612 } 613 614 int 615 ns8250_bus_detach(struct uart_softc *sc) 616 { 617 struct ns8250_softc *ns8250; 618 struct uart_bas *bas; 619 u_char ier; 620 621 ns8250 = (struct ns8250_softc *)sc; 622 bas = &sc->sc_bas; 623 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 624 uart_setreg(bas, REG_IER, ier); 625 uart_barrier(bas); 626 ns8250_clrint(bas); 627 return (0); 628 } 629 630 int 631 ns8250_bus_flush(struct uart_softc *sc, int what) 632 { 633 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 634 struct uart_bas *bas; 635 int error; 636 637 bas = &sc->sc_bas; 638 uart_lock(sc->sc_hwmtx); 639 if (sc->sc_rxfifosz > 1) { 640 ns8250_flush(bas, what); 641 uart_setreg(bas, REG_FCR, ns8250->fcr); 642 uart_barrier(bas); 643 error = 0; 644 } else 645 error = ns8250_drain(bas, what); 646 uart_unlock(sc->sc_hwmtx); 647 return (error); 648 } 649 650 int 651 ns8250_bus_getsig(struct uart_softc *sc) 652 { 653 uint32_t old, sig; 654 uint8_t msr; 655 656 /* 657 * The delta bits are reputed to be broken on some hardware, so use 658 * software delta detection by default. Use the hardware delta bits 659 * when capturing PPS pulses which are too narrow for software detection 660 * to see the edges. Hardware delta for RI doesn't work like the 661 * others, so always use software for it. Other threads may be changing 662 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 663 * update without other changes happening. Note that the SIGCHGxx() 664 * macros carefully preserve the delta bits when we have to loop several 665 * times and a signal transitions between iterations. 666 */ 667 do { 668 old = sc->sc_hwsig; 669 sig = old; 670 uart_lock(sc->sc_hwmtx); 671 msr = uart_getreg(&sc->sc_bas, REG_MSR); 672 uart_unlock(sc->sc_hwmtx); 673 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 674 SIGCHGHW(sig, msr, DSR); 675 SIGCHGHW(sig, msr, CTS); 676 SIGCHGHW(sig, msr, DCD); 677 } else { 678 SIGCHGSW(sig, msr, DSR); 679 SIGCHGSW(sig, msr, CTS); 680 SIGCHGSW(sig, msr, DCD); 681 } 682 SIGCHGSW(sig, msr, RI); 683 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 684 return (sig); 685 } 686 687 int 688 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 689 { 690 struct uart_bas *bas; 691 int baudrate, divisor, error; 692 uint8_t efr, lcr; 693 694 bas = &sc->sc_bas; 695 error = 0; 696 uart_lock(sc->sc_hwmtx); 697 switch (request) { 698 case UART_IOCTL_BREAK: 699 lcr = uart_getreg(bas, REG_LCR); 700 if (data) 701 lcr |= LCR_SBREAK; 702 else 703 lcr &= ~LCR_SBREAK; 704 uart_setreg(bas, REG_LCR, lcr); 705 uart_barrier(bas); 706 break; 707 case UART_IOCTL_IFLOW: 708 lcr = uart_getreg(bas, REG_LCR); 709 uart_barrier(bas); 710 uart_setreg(bas, REG_LCR, 0xbf); 711 uart_barrier(bas); 712 efr = uart_getreg(bas, REG_EFR); 713 if (data) 714 efr |= EFR_RTS; 715 else 716 efr &= ~EFR_RTS; 717 uart_setreg(bas, REG_EFR, efr); 718 uart_barrier(bas); 719 uart_setreg(bas, REG_LCR, lcr); 720 uart_barrier(bas); 721 break; 722 case UART_IOCTL_OFLOW: 723 lcr = uart_getreg(bas, REG_LCR); 724 uart_barrier(bas); 725 uart_setreg(bas, REG_LCR, 0xbf); 726 uart_barrier(bas); 727 efr = uart_getreg(bas, REG_EFR); 728 if (data) 729 efr |= EFR_CTS; 730 else 731 efr &= ~EFR_CTS; 732 uart_setreg(bas, REG_EFR, efr); 733 uart_barrier(bas); 734 uart_setreg(bas, REG_LCR, lcr); 735 uart_barrier(bas); 736 break; 737 case UART_IOCTL_BAUD: 738 lcr = uart_getreg(bas, REG_LCR); 739 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 740 uart_barrier(bas); 741 divisor = uart_getreg(bas, REG_DLL) | 742 (uart_getreg(bas, REG_DLH) << 8); 743 uart_barrier(bas); 744 uart_setreg(bas, REG_LCR, lcr); 745 uart_barrier(bas); 746 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 747 if (baudrate > 0) 748 *(int*)data = baudrate; 749 else 750 error = ENXIO; 751 break; 752 default: 753 error = EINVAL; 754 break; 755 } 756 uart_unlock(sc->sc_hwmtx); 757 return (error); 758 } 759 760 int 761 ns8250_bus_ipend(struct uart_softc *sc) 762 { 763 struct uart_bas *bas; 764 struct ns8250_softc *ns8250; 765 int ipend; 766 uint8_t iir, lsr; 767 768 ns8250 = (struct ns8250_softc *)sc; 769 bas = &sc->sc_bas; 770 uart_lock(sc->sc_hwmtx); 771 iir = uart_getreg(bas, REG_IIR); 772 773 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 774 (void)uart_getreg(bas, DW_REG_USR); 775 uart_unlock(sc->sc_hwmtx); 776 return (0); 777 } 778 if (iir & IIR_NOPEND) { 779 uart_unlock(sc->sc_hwmtx); 780 return (0); 781 } 782 ipend = 0; 783 if (iir & IIR_RXRDY) { 784 lsr = uart_getreg(bas, REG_LSR); 785 if (lsr & LSR_OE) 786 ipend |= SER_INT_OVERRUN; 787 if (lsr & LSR_BI) 788 ipend |= SER_INT_BREAK; 789 if (lsr & LSR_RXRDY) 790 ipend |= SER_INT_RXREADY; 791 } else { 792 if (iir & IIR_TXRDY) { 793 ipend |= SER_INT_TXIDLE; 794 ns8250->ier &= ~IER_ETXRDY; 795 uart_setreg(bas, REG_IER, ns8250->ier); 796 uart_barrier(bas); 797 } else 798 ipend |= SER_INT_SIGCHG; 799 } 800 if (ipend == 0) 801 ns8250_clrint(bas); 802 uart_unlock(sc->sc_hwmtx); 803 return (ipend); 804 } 805 806 int 807 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 808 int stopbits, int parity) 809 { 810 struct ns8250_softc *ns8250; 811 struct uart_bas *bas; 812 int error, limit; 813 814 ns8250 = (struct ns8250_softc*)sc; 815 bas = &sc->sc_bas; 816 uart_lock(sc->sc_hwmtx); 817 /* 818 * When using DW UART with BUSY detection it is necessary to wait 819 * until all serial transfers are finished before manipulating the 820 * line control. LCR will not be affected when UART is busy. 821 */ 822 if (ns8250->busy_detect != 0) { 823 /* 824 * Pick an arbitrary high limit to avoid getting stuck in 825 * an infinite loop in case when the hardware is broken. 826 */ 827 limit = 10 * 1024; 828 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 829 --limit) 830 DELAY(4); 831 832 if (limit <= 0) { 833 /* UART appears to be stuck */ 834 uart_unlock(sc->sc_hwmtx); 835 return (EIO); 836 } 837 } 838 839 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 840 uart_unlock(sc->sc_hwmtx); 841 return (error); 842 } 843 844 int 845 ns8250_bus_probe(struct uart_softc *sc) 846 { 847 struct uart_bas *bas; 848 int count, delay, error, limit; 849 uint8_t lsr, mcr, ier; 850 uint8_t val; 851 852 bas = &sc->sc_bas; 853 854 error = ns8250_probe(bas); 855 if (error) 856 return (error); 857 858 mcr = MCR_IE; 859 if (sc->sc_sysdev == NULL) { 860 /* By using ns8250_init() we also set DTR and RTS. */ 861 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 862 } else 863 mcr |= MCR_DTR | MCR_RTS; 864 865 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 866 if (error) 867 return (error); 868 869 /* 870 * Set loopback mode. This avoids having garbage on the wire and 871 * also allows us send and receive data. We set DTR and RTS to 872 * avoid the possibility that automatic flow-control prevents 873 * any data from being sent. 874 */ 875 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 876 uart_barrier(bas); 877 878 /* 879 * Enable FIFOs. And check that the UART has them. If not, we're 880 * done. Since this is the first time we enable the FIFOs, we reset 881 * them. 882 */ 883 val = FCR_ENABLE; 884 #ifdef CPU_XBURST 885 val |= FCR_UART_ON; 886 #endif 887 uart_setreg(bas, REG_FCR, val); 888 uart_barrier(bas); 889 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 890 /* 891 * NS16450 or INS8250. We don't bother to differentiate 892 * between them. They're too old to be interesting. 893 */ 894 uart_setreg(bas, REG_MCR, mcr); 895 uart_barrier(bas); 896 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 897 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 898 return (0); 899 } 900 901 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 902 #ifdef CPU_XBURST 903 val |= FCR_UART_ON; 904 #endif 905 uart_setreg(bas, REG_FCR, val); 906 uart_barrier(bas); 907 908 count = 0; 909 delay = ns8250_delay(bas); 910 911 /* We have FIFOs. Drain the transmitter and receiver. */ 912 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 913 if (error) { 914 uart_setreg(bas, REG_MCR, mcr); 915 val = 0; 916 #ifdef CPU_XBURST 917 val |= FCR_UART_ON; 918 #endif 919 uart_setreg(bas, REG_FCR, val); 920 uart_barrier(bas); 921 goto describe; 922 } 923 924 /* 925 * We should have a sufficiently clean "pipe" to determine the 926 * size of the FIFOs. We send as much characters as is reasonable 927 * and wait for the overflow bit in the LSR register to be 928 * asserted, counting the characters as we send them. Based on 929 * that count we know the FIFO size. 930 */ 931 do { 932 uart_setreg(bas, REG_DATA, 0); 933 uart_barrier(bas); 934 count++; 935 936 limit = 30; 937 lsr = 0; 938 /* 939 * LSR bits are cleared upon read, so we must accumulate 940 * them to be able to test LSR_OE below. 941 */ 942 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 943 --limit) 944 DELAY(delay); 945 if (limit == 0) { 946 /* See the comment in ns8250_init(). */ 947 ier = uart_getreg(bas, REG_IER) & 0xe0; 948 uart_setreg(bas, REG_IER, ier); 949 uart_setreg(bas, REG_MCR, mcr); 950 val = 0; 951 #ifdef CPU_XBURST 952 val |= FCR_UART_ON; 953 #endif 954 uart_setreg(bas, REG_FCR, val); 955 uart_barrier(bas); 956 count = 0; 957 goto describe; 958 } 959 } while ((lsr & LSR_OE) == 0 && count < 260); 960 count--; 961 962 uart_setreg(bas, REG_MCR, mcr); 963 964 /* Reset FIFOs. */ 965 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 966 967 describe: 968 if (count >= 14 && count <= 16) { 969 sc->sc_rxfifosz = 16; 970 device_set_desc(sc->sc_dev, "16550 or compatible"); 971 } else if (count >= 28 && count <= 32) { 972 sc->sc_rxfifosz = 32; 973 device_set_desc(sc->sc_dev, "16650 or compatible"); 974 } else if (count >= 56 && count <= 64) { 975 sc->sc_rxfifosz = 64; 976 device_set_desc(sc->sc_dev, "16750 or compatible"); 977 } else if (count >= 112 && count <= 128) { 978 sc->sc_rxfifosz = 128; 979 device_set_desc(sc->sc_dev, "16950 or compatible"); 980 } else if (count >= 224 && count <= 256) { 981 sc->sc_rxfifosz = 256; 982 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 983 } else { 984 sc->sc_rxfifosz = 16; 985 device_set_desc(sc->sc_dev, 986 "Non-standard ns8250 class UART with FIFOs"); 987 } 988 989 /* 990 * Force the Tx FIFO size to 16 bytes for now. We don't program the 991 * Tx trigger. Also, we assume that all data has been sent when the 992 * interrupt happens. 993 */ 994 sc->sc_txfifosz = 16; 995 996 #if 0 997 /* 998 * XXX there are some issues related to hardware flow control and 999 * it's likely that uart(4) is the cause. This basically needs more 1000 * investigation, but we avoid using for hardware flow control 1001 * until then. 1002 */ 1003 /* 16650s or higher have automatic flow control. */ 1004 if (sc->sc_rxfifosz > 16) { 1005 sc->sc_hwiflow = 1; 1006 sc->sc_hwoflow = 1; 1007 } 1008 #endif 1009 1010 return (0); 1011 } 1012 1013 int 1014 ns8250_bus_receive(struct uart_softc *sc) 1015 { 1016 struct uart_bas *bas; 1017 int xc; 1018 uint8_t lsr; 1019 1020 bas = &sc->sc_bas; 1021 uart_lock(sc->sc_hwmtx); 1022 lsr = uart_getreg(bas, REG_LSR); 1023 while (lsr & LSR_RXRDY) { 1024 if (uart_rx_full(sc)) { 1025 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1026 break; 1027 } 1028 xc = uart_getreg(bas, REG_DATA); 1029 if (lsr & LSR_FE) 1030 xc |= UART_STAT_FRAMERR; 1031 if (lsr & LSR_PE) 1032 xc |= UART_STAT_PARERR; 1033 uart_rx_put(sc, xc); 1034 lsr = uart_getreg(bas, REG_LSR); 1035 } 1036 /* Discard everything left in the Rx FIFO. */ 1037 while (lsr & LSR_RXRDY) { 1038 (void)uart_getreg(bas, REG_DATA); 1039 uart_barrier(bas); 1040 lsr = uart_getreg(bas, REG_LSR); 1041 } 1042 uart_unlock(sc->sc_hwmtx); 1043 return (0); 1044 } 1045 1046 int 1047 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1048 { 1049 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1050 struct uart_bas *bas; 1051 uint32_t new, old; 1052 1053 bas = &sc->sc_bas; 1054 do { 1055 old = sc->sc_hwsig; 1056 new = old; 1057 if (sig & SER_DDTR) { 1058 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1059 } 1060 if (sig & SER_DRTS) { 1061 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1062 } 1063 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1064 uart_lock(sc->sc_hwmtx); 1065 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1066 if (new & SER_DTR) 1067 ns8250->mcr |= MCR_DTR; 1068 if (new & SER_RTS) 1069 ns8250->mcr |= MCR_RTS; 1070 uart_setreg(bas, REG_MCR, ns8250->mcr); 1071 uart_barrier(bas); 1072 uart_unlock(sc->sc_hwmtx); 1073 return (0); 1074 } 1075 1076 int 1077 ns8250_bus_transmit(struct uart_softc *sc) 1078 { 1079 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1080 struct uart_bas *bas; 1081 int i; 1082 1083 bas = &sc->sc_bas; 1084 uart_lock(sc->sc_hwmtx); 1085 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1086 DELAY(4); 1087 for (i = 0; i < sc->sc_txdatasz; i++) { 1088 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1089 uart_barrier(bas); 1090 } 1091 if (!broken_txfifo) 1092 ns8250->ier |= IER_ETXRDY; 1093 uart_setreg(bas, REG_IER, ns8250->ier); 1094 uart_barrier(bas); 1095 if (broken_txfifo) 1096 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1097 else 1098 sc->sc_txbusy = 1; 1099 uart_unlock(sc->sc_hwmtx); 1100 if (broken_txfifo) 1101 uart_sched_softih(sc, SER_INT_TXIDLE); 1102 return (0); 1103 } 1104 1105 void 1106 ns8250_bus_grab(struct uart_softc *sc) 1107 { 1108 struct uart_bas *bas = &sc->sc_bas; 1109 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1110 u_char ier; 1111 1112 /* 1113 * turn off all interrupts to enter polling mode. Leave the 1114 * saved mask alone. We'll restore whatever it was in ungrab. 1115 * All pending interrupt signals are reset when IER is set to 0. 1116 */ 1117 uart_lock(sc->sc_hwmtx); 1118 ier = uart_getreg(bas, REG_IER); 1119 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1120 uart_barrier(bas); 1121 uart_unlock(sc->sc_hwmtx); 1122 } 1123 1124 void 1125 ns8250_bus_ungrab(struct uart_softc *sc) 1126 { 1127 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1128 struct uart_bas *bas = &sc->sc_bas; 1129 1130 /* 1131 * Restore previous interrupt mask 1132 */ 1133 uart_lock(sc->sc_hwmtx); 1134 uart_setreg(bas, REG_IER, ns8250->ier); 1135 uart_barrier(bas); 1136 uart_unlock(sc->sc_hwmtx); 1137 } 1138