1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_platform.h" 30 #include "opt_uart.h" 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/kernel.h> 40 #include <sys/sysctl.h> 41 #include <machine/bus.h> 42 43 #ifdef FDT 44 #include <dev/fdt/fdt_common.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 #endif 48 49 #include <dev/uart/uart.h> 50 #include <dev/uart/uart_cpu.h> 51 #ifdef FDT 52 #include <dev/uart/uart_cpu_fdt.h> 53 #endif 54 #include <dev/uart/uart_bus.h> 55 #include <dev/uart/uart_dev_ns8250.h> 56 #include <dev/uart/uart_ppstypes.h> 57 58 #include <dev/ic/ns16550.h> 59 60 #include "uart_if.h" 61 62 #define DEFAULT_RCLK 1843200 63 64 /* 65 * Set the default baudrate tolerance to 3.0%. 66 * 67 * Some embedded boards have odd reference clocks (eg 25MHz) 68 * and we need to handle higher variances in the target baud rate. 69 */ 70 #ifndef UART_DEV_TOLERANCE_PCT 71 #define UART_DEV_TOLERANCE_PCT 30 72 #endif /* UART_DEV_TOLERANCE_PCT */ 73 74 static int broken_txfifo = 0; 75 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 76 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 77 78 /* 79 * Clear pending interrupts. THRE is cleared by reading IIR. Data 80 * that may have been received gets lost here. 81 */ 82 static void 83 ns8250_clrint(struct uart_bas *bas) 84 { 85 uint8_t iir, lsr; 86 87 iir = uart_getreg(bas, REG_IIR); 88 while ((iir & IIR_NOPEND) == 0) { 89 iir &= IIR_IMASK; 90 if (iir == IIR_RLS) { 91 lsr = uart_getreg(bas, REG_LSR); 92 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 93 (void)uart_getreg(bas, REG_DATA); 94 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 95 (void)uart_getreg(bas, REG_DATA); 96 else if (iir == IIR_MLSC) 97 (void)uart_getreg(bas, REG_MSR); 98 uart_barrier(bas); 99 iir = uart_getreg(bas, REG_IIR); 100 } 101 } 102 103 static int 104 ns8250_delay(struct uart_bas *bas) 105 { 106 int divisor; 107 u_char lcr; 108 109 lcr = uart_getreg(bas, REG_LCR); 110 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 111 uart_barrier(bas); 112 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 113 uart_barrier(bas); 114 uart_setreg(bas, REG_LCR, lcr); 115 uart_barrier(bas); 116 117 /* 1/10th the time to transmit 1 character (estimate). */ 118 if (divisor <= 134) 119 return (16000000 * divisor / bas->rclk); 120 return (16000 * divisor / (bas->rclk / 1000)); 121 } 122 123 static int 124 ns8250_divisor(int rclk, int baudrate) 125 { 126 int actual_baud, divisor; 127 int error; 128 129 if (baudrate == 0) 130 return (0); 131 132 divisor = (rclk / (baudrate << 3) + 1) >> 1; 133 if (divisor == 0 || divisor >= 65536) 134 return (0); 135 actual_baud = rclk / (divisor << 4); 136 137 /* 10 times error in percent: */ 138 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 139 140 /* enforce maximum error tolerance: */ 141 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 142 return (0); 143 144 return (divisor); 145 } 146 147 static int 148 ns8250_drain(struct uart_bas *bas, int what) 149 { 150 int delay, limit; 151 152 delay = ns8250_delay(bas); 153 154 if (what & UART_DRAIN_TRANSMITTER) { 155 /* 156 * Pick an arbitrary high limit to avoid getting stuck in 157 * an infinite loop when the hardware is broken. Make the 158 * limit high enough to handle large FIFOs. 159 */ 160 limit = 10*1024; 161 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 162 DELAY(delay); 163 if (limit == 0) { 164 /* printf("ns8250: transmitter appears stuck... "); */ 165 return (EIO); 166 } 167 } 168 169 if (what & UART_DRAIN_RECEIVER) { 170 /* 171 * Pick an arbitrary high limit to avoid getting stuck in 172 * an infinite loop when the hardware is broken. Make the 173 * limit high enough to handle large FIFOs and integrated 174 * UARTs. The HP rx2600 for example has 3 UARTs on the 175 * management board that tend to get a lot of data send 176 * to it when the UART is first activated. 177 */ 178 limit=10*4096; 179 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 180 (void)uart_getreg(bas, REG_DATA); 181 uart_barrier(bas); 182 DELAY(delay << 2); 183 } 184 if (limit == 0) { 185 /* printf("ns8250: receiver appears broken... "); */ 186 return (EIO); 187 } 188 } 189 190 return (0); 191 } 192 193 /* 194 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 195 * drained. WARNING: this function clobbers the FIFO setting! 196 */ 197 static void 198 ns8250_flush(struct uart_bas *bas, int what) 199 { 200 uint8_t fcr; 201 202 fcr = FCR_ENABLE; 203 #ifdef CPU_XBURST 204 fcr |= FCR_UART_ON; 205 #endif 206 if (what & UART_FLUSH_TRANSMITTER) 207 fcr |= FCR_XMT_RST; 208 if (what & UART_FLUSH_RECEIVER) 209 fcr |= FCR_RCV_RST; 210 uart_setreg(bas, REG_FCR, fcr); 211 uart_barrier(bas); 212 } 213 214 static int 215 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 216 int parity) 217 { 218 int divisor; 219 uint8_t lcr; 220 221 lcr = 0; 222 if (databits >= 8) 223 lcr |= LCR_8BITS; 224 else if (databits == 7) 225 lcr |= LCR_7BITS; 226 else if (databits == 6) 227 lcr |= LCR_6BITS; 228 else 229 lcr |= LCR_5BITS; 230 if (stopbits > 1) 231 lcr |= LCR_STOPB; 232 lcr |= parity << 3; 233 234 /* Set baudrate. */ 235 if (baudrate > 0) { 236 divisor = ns8250_divisor(bas->rclk, baudrate); 237 if (divisor == 0) 238 return (EINVAL); 239 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 240 uart_barrier(bas); 241 uart_setreg(bas, REG_DLL, divisor & 0xff); 242 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 243 uart_barrier(bas); 244 } 245 246 /* Set LCR and clear DLAB. */ 247 uart_setreg(bas, REG_LCR, lcr); 248 uart_barrier(bas); 249 return (0); 250 } 251 252 /* 253 * Low-level UART interface. 254 */ 255 static int ns8250_probe(struct uart_bas *bas); 256 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 257 static void ns8250_term(struct uart_bas *bas); 258 static void ns8250_putc(struct uart_bas *bas, int); 259 static int ns8250_rxready(struct uart_bas *bas); 260 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 261 262 struct uart_ops uart_ns8250_ops = { 263 .probe = ns8250_probe, 264 .init = ns8250_init, 265 .term = ns8250_term, 266 .putc = ns8250_putc, 267 .rxready = ns8250_rxready, 268 .getc = ns8250_getc, 269 }; 270 271 static int 272 ns8250_probe(struct uart_bas *bas) 273 { 274 u_char val; 275 276 #ifdef CPU_XBURST 277 uart_setreg(bas, REG_FCR, FCR_UART_ON); 278 #endif 279 280 /* Check known 0 bits that don't depend on DLAB. */ 281 val = uart_getreg(bas, REG_IIR); 282 if (val & 0x30) 283 return (ENXIO); 284 /* 285 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 286 * chip, but otherwise doesn't seem to have a function. In 287 * other words, uart(4) works regardless. Ignore that bit so 288 * the probe succeeds. 289 */ 290 val = uart_getreg(bas, REG_MCR); 291 if (val & 0xa0) 292 return (ENXIO); 293 294 return (0); 295 } 296 297 static void 298 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 299 int parity) 300 { 301 u_char ier, val; 302 303 if (bas->rclk == 0) 304 bas->rclk = DEFAULT_RCLK; 305 ns8250_param(bas, baudrate, databits, stopbits, parity); 306 307 /* Disable all interrupt sources. */ 308 /* 309 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 310 * UARTs split the receive time-out interrupt bit out separately as 311 * 0x10. This gets handled by ier_mask and ier_rxbits below. 312 */ 313 ier = uart_getreg(bas, REG_IER) & 0xe0; 314 uart_setreg(bas, REG_IER, ier); 315 uart_barrier(bas); 316 317 /* Disable the FIFO (if present). */ 318 val = 0; 319 #ifdef CPU_XBURST 320 val |= FCR_UART_ON; 321 #endif 322 uart_setreg(bas, REG_FCR, val); 323 uart_barrier(bas); 324 325 /* Set RTS & DTR. */ 326 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 327 uart_barrier(bas); 328 329 ns8250_clrint(bas); 330 } 331 332 static void 333 ns8250_term(struct uart_bas *bas) 334 { 335 336 /* Clear RTS & DTR. */ 337 uart_setreg(bas, REG_MCR, MCR_IE); 338 uart_barrier(bas); 339 } 340 341 static void 342 ns8250_putc(struct uart_bas *bas, int c) 343 { 344 int limit; 345 346 limit = 250000; 347 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 348 DELAY(4); 349 uart_setreg(bas, REG_DATA, c); 350 uart_barrier(bas); 351 } 352 353 static int 354 ns8250_rxready(struct uart_bas *bas) 355 { 356 357 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 358 } 359 360 static int 361 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 362 { 363 int c; 364 365 uart_lock(hwmtx); 366 367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 368 uart_unlock(hwmtx); 369 DELAY(4); 370 uart_lock(hwmtx); 371 } 372 373 c = uart_getreg(bas, REG_DATA); 374 375 uart_unlock(hwmtx); 376 377 return (c); 378 } 379 380 static kobj_method_t ns8250_methods[] = { 381 KOBJMETHOD(uart_attach, ns8250_bus_attach), 382 KOBJMETHOD(uart_detach, ns8250_bus_detach), 383 KOBJMETHOD(uart_flush, ns8250_bus_flush), 384 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 385 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 386 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 387 KOBJMETHOD(uart_param, ns8250_bus_param), 388 KOBJMETHOD(uart_probe, ns8250_bus_probe), 389 KOBJMETHOD(uart_receive, ns8250_bus_receive), 390 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 391 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 392 KOBJMETHOD(uart_grab, ns8250_bus_grab), 393 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 394 { 0, 0 } 395 }; 396 397 struct uart_class uart_ns8250_class = { 398 "ns8250", 399 ns8250_methods, 400 sizeof(struct ns8250_softc), 401 .uc_ops = &uart_ns8250_ops, 402 .uc_range = 8, 403 .uc_rclk = DEFAULT_RCLK, 404 .uc_rshift = 0 405 }; 406 407 #ifdef FDT 408 static struct ofw_compat_data compat_data[] = { 409 {"ns16550", (uintptr_t)&uart_ns8250_class}, 410 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 411 {NULL, (uintptr_t)NULL}, 412 }; 413 UART_FDT_CLASS_AND_DEVICE(compat_data); 414 #endif 415 416 /* Use token-pasting to form SER_ and MSR_ named constants. */ 417 #define SER(sig) SER_##sig 418 #define SERD(sig) SER_D##sig 419 #define MSR(sig) MSR_##sig 420 #define MSRD(sig) MSR_D##sig 421 422 /* 423 * Detect signal changes using software delta detection. The previous state of 424 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 425 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 426 * new state of both the signal and the delta bits. 427 */ 428 #define SIGCHGSW(var, msr, sig) \ 429 if ((msr) & MSR(sig)) { \ 430 if ((var & SER(sig)) == 0) \ 431 var |= SERD(sig) | SER(sig); \ 432 } else { \ 433 if ((var & SER(sig)) != 0) \ 434 var = SERD(sig) | (var & ~SER(sig)); \ 435 } 436 437 /* 438 * Detect signal changes using the hardware msr delta bits. This is currently 439 * used only when PPS timing information is being captured using the "narrow 440 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 441 * by time the interrupt handler is invoked. The hardware will latch the fact 442 * that it changed in the delta bits. 443 */ 444 #define SIGCHGHW(var, msr, sig) \ 445 if ((msr) & MSRD(sig)) { \ 446 if (((msr) & MSR(sig)) != 0) \ 447 var |= SERD(sig) | SER(sig); \ 448 else \ 449 var = SERD(sig) | (var & ~SER(sig)); \ 450 } 451 452 int 453 ns8250_bus_attach(struct uart_softc *sc) 454 { 455 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 456 struct uart_bas *bas; 457 unsigned int ivar; 458 #ifdef FDT 459 phandle_t node; 460 pcell_t cell; 461 #endif 462 463 #ifdef FDT 464 /* Check whether uart has a broken txfifo. */ 465 node = ofw_bus_get_node(sc->sc_dev); 466 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 467 broken_txfifo = cell ? 1 : 0; 468 #endif 469 470 bas = &sc->sc_bas; 471 472 ns8250->mcr = uart_getreg(bas, REG_MCR); 473 ns8250->fcr = FCR_ENABLE; 474 #ifdef CPU_XBURST 475 ns8250->fcr |= FCR_UART_ON; 476 #endif 477 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 478 &ivar)) { 479 if (UART_FLAGS_FCR_RX_LOW(ivar)) 480 ns8250->fcr |= FCR_RX_LOW; 481 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 482 ns8250->fcr |= FCR_RX_MEDL; 483 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 484 ns8250->fcr |= FCR_RX_HIGH; 485 else 486 ns8250->fcr |= FCR_RX_MEDH; 487 } else 488 ns8250->fcr |= FCR_RX_MEDH; 489 490 /* Get IER mask */ 491 ivar = 0xf0; 492 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 493 &ivar); 494 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 495 496 /* Get IER RX interrupt bits */ 497 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 498 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 499 &ivar); 500 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 501 502 uart_setreg(bas, REG_FCR, ns8250->fcr); 503 uart_barrier(bas); 504 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 505 506 if (ns8250->mcr & MCR_DTR) 507 sc->sc_hwsig |= SER_DTR; 508 if (ns8250->mcr & MCR_RTS) 509 sc->sc_hwsig |= SER_RTS; 510 ns8250_bus_getsig(sc); 511 512 ns8250_clrint(bas); 513 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 514 ns8250->ier |= ns8250->ier_rxbits; 515 uart_setreg(bas, REG_IER, ns8250->ier); 516 uart_barrier(bas); 517 518 /* 519 * Timing of the H/W access was changed with r253161 of uart_core.c 520 * It has been observed that an ITE IT8513E would signal a break 521 * condition with pretty much every character it received, unless 522 * it had enough time to settle between ns8250_bus_attach() and 523 * ns8250_bus_ipend() -- which it accidentally had before r253161. 524 * It's not understood why the UART chip behaves this way and it 525 * could very well be that the DELAY make the H/W work in the same 526 * accidental manner as before. More analysis is warranted, but 527 * at least now we fixed a known regression. 528 */ 529 DELAY(200); 530 return (0); 531 } 532 533 int 534 ns8250_bus_detach(struct uart_softc *sc) 535 { 536 struct ns8250_softc *ns8250; 537 struct uart_bas *bas; 538 u_char ier; 539 540 ns8250 = (struct ns8250_softc *)sc; 541 bas = &sc->sc_bas; 542 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 543 uart_setreg(bas, REG_IER, ier); 544 uart_barrier(bas); 545 ns8250_clrint(bas); 546 return (0); 547 } 548 549 int 550 ns8250_bus_flush(struct uart_softc *sc, int what) 551 { 552 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 553 struct uart_bas *bas; 554 int error; 555 556 bas = &sc->sc_bas; 557 uart_lock(sc->sc_hwmtx); 558 if (sc->sc_rxfifosz > 1) { 559 ns8250_flush(bas, what); 560 uart_setreg(bas, REG_FCR, ns8250->fcr); 561 uart_barrier(bas); 562 error = 0; 563 } else 564 error = ns8250_drain(bas, what); 565 uart_unlock(sc->sc_hwmtx); 566 return (error); 567 } 568 569 int 570 ns8250_bus_getsig(struct uart_softc *sc) 571 { 572 uint32_t old, sig; 573 uint8_t msr; 574 575 /* 576 * The delta bits are reputed to be broken on some hardware, so use 577 * software delta detection by default. Use the hardware delta bits 578 * when capturing PPS pulses which are too narrow for software detection 579 * to see the edges. Hardware delta for RI doesn't work like the 580 * others, so always use software for it. Other threads may be changing 581 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 582 * update without other changes happening. Note that the SIGCHGxx() 583 * macros carefully preserve the delta bits when we have to loop several 584 * times and a signal transitions between iterations. 585 */ 586 do { 587 old = sc->sc_hwsig; 588 sig = old; 589 uart_lock(sc->sc_hwmtx); 590 msr = uart_getreg(&sc->sc_bas, REG_MSR); 591 uart_unlock(sc->sc_hwmtx); 592 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 593 SIGCHGHW(sig, msr, DSR); 594 SIGCHGHW(sig, msr, CTS); 595 SIGCHGHW(sig, msr, DCD); 596 } else { 597 SIGCHGSW(sig, msr, DSR); 598 SIGCHGSW(sig, msr, CTS); 599 SIGCHGSW(sig, msr, DCD); 600 } 601 SIGCHGSW(sig, msr, RI); 602 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 603 return (sig); 604 } 605 606 int 607 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 608 { 609 struct uart_bas *bas; 610 int baudrate, divisor, error; 611 uint8_t efr, lcr; 612 613 bas = &sc->sc_bas; 614 error = 0; 615 uart_lock(sc->sc_hwmtx); 616 switch (request) { 617 case UART_IOCTL_BREAK: 618 lcr = uart_getreg(bas, REG_LCR); 619 if (data) 620 lcr |= LCR_SBREAK; 621 else 622 lcr &= ~LCR_SBREAK; 623 uart_setreg(bas, REG_LCR, lcr); 624 uart_barrier(bas); 625 break; 626 case UART_IOCTL_IFLOW: 627 lcr = uart_getreg(bas, REG_LCR); 628 uart_barrier(bas); 629 uart_setreg(bas, REG_LCR, 0xbf); 630 uart_barrier(bas); 631 efr = uart_getreg(bas, REG_EFR); 632 if (data) 633 efr |= EFR_RTS; 634 else 635 efr &= ~EFR_RTS; 636 uart_setreg(bas, REG_EFR, efr); 637 uart_barrier(bas); 638 uart_setreg(bas, REG_LCR, lcr); 639 uart_barrier(bas); 640 break; 641 case UART_IOCTL_OFLOW: 642 lcr = uart_getreg(bas, REG_LCR); 643 uart_barrier(bas); 644 uart_setreg(bas, REG_LCR, 0xbf); 645 uart_barrier(bas); 646 efr = uart_getreg(bas, REG_EFR); 647 if (data) 648 efr |= EFR_CTS; 649 else 650 efr &= ~EFR_CTS; 651 uart_setreg(bas, REG_EFR, efr); 652 uart_barrier(bas); 653 uart_setreg(bas, REG_LCR, lcr); 654 uart_barrier(bas); 655 break; 656 case UART_IOCTL_BAUD: 657 lcr = uart_getreg(bas, REG_LCR); 658 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 659 uart_barrier(bas); 660 divisor = uart_getreg(bas, REG_DLL) | 661 (uart_getreg(bas, REG_DLH) << 8); 662 uart_barrier(bas); 663 uart_setreg(bas, REG_LCR, lcr); 664 uart_barrier(bas); 665 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 666 if (baudrate > 0) 667 *(int*)data = baudrate; 668 else 669 error = ENXIO; 670 break; 671 default: 672 error = EINVAL; 673 break; 674 } 675 uart_unlock(sc->sc_hwmtx); 676 return (error); 677 } 678 679 int 680 ns8250_bus_ipend(struct uart_softc *sc) 681 { 682 struct uart_bas *bas; 683 struct ns8250_softc *ns8250; 684 int ipend; 685 uint8_t iir, lsr; 686 687 ns8250 = (struct ns8250_softc *)sc; 688 bas = &sc->sc_bas; 689 uart_lock(sc->sc_hwmtx); 690 iir = uart_getreg(bas, REG_IIR); 691 692 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 693 (void)uart_getreg(bas, DW_REG_USR); 694 uart_unlock(sc->sc_hwmtx); 695 return (0); 696 } 697 if (iir & IIR_NOPEND) { 698 uart_unlock(sc->sc_hwmtx); 699 return (0); 700 } 701 ipend = 0; 702 if (iir & IIR_RXRDY) { 703 lsr = uart_getreg(bas, REG_LSR); 704 if (lsr & LSR_OE) 705 ipend |= SER_INT_OVERRUN; 706 if (lsr & LSR_BI) 707 ipend |= SER_INT_BREAK; 708 if (lsr & LSR_RXRDY) 709 ipend |= SER_INT_RXREADY; 710 } else { 711 if (iir & IIR_TXRDY) { 712 ipend |= SER_INT_TXIDLE; 713 uart_setreg(bas, REG_IER, ns8250->ier); 714 uart_barrier(bas); 715 } else 716 ipend |= SER_INT_SIGCHG; 717 } 718 if (ipend == 0) 719 ns8250_clrint(bas); 720 uart_unlock(sc->sc_hwmtx); 721 return (ipend); 722 } 723 724 int 725 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 726 int stopbits, int parity) 727 { 728 struct ns8250_softc *ns8250; 729 struct uart_bas *bas; 730 int error, limit; 731 732 ns8250 = (struct ns8250_softc*)sc; 733 bas = &sc->sc_bas; 734 uart_lock(sc->sc_hwmtx); 735 /* 736 * When using DW UART with BUSY detection it is necessary to wait 737 * until all serial transfers are finished before manipulating the 738 * line control. LCR will not be affected when UART is busy. 739 */ 740 if (ns8250->busy_detect != 0) { 741 /* 742 * Pick an arbitrary high limit to avoid getting stuck in 743 * an infinite loop in case when the hardware is broken. 744 */ 745 limit = 10 * 1024; 746 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 747 --limit) 748 DELAY(4); 749 750 if (limit <= 0) { 751 /* UART appears to be stuck */ 752 uart_unlock(sc->sc_hwmtx); 753 return (EIO); 754 } 755 } 756 757 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 758 uart_unlock(sc->sc_hwmtx); 759 return (error); 760 } 761 762 int 763 ns8250_bus_probe(struct uart_softc *sc) 764 { 765 struct ns8250_softc *ns8250; 766 struct uart_bas *bas; 767 int count, delay, error, limit; 768 uint8_t lsr, mcr, ier; 769 uint8_t val; 770 771 ns8250 = (struct ns8250_softc *)sc; 772 bas = &sc->sc_bas; 773 774 error = ns8250_probe(bas); 775 if (error) 776 return (error); 777 778 mcr = MCR_IE; 779 if (sc->sc_sysdev == NULL) { 780 /* By using ns8250_init() we also set DTR and RTS. */ 781 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 782 } else 783 mcr |= MCR_DTR | MCR_RTS; 784 785 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 786 if (error) 787 return (error); 788 789 /* 790 * Set loopback mode. This avoids having garbage on the wire and 791 * also allows us send and receive data. We set DTR and RTS to 792 * avoid the possibility that automatic flow-control prevents 793 * any data from being sent. 794 */ 795 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 796 uart_barrier(bas); 797 798 /* 799 * Enable FIFOs. And check that the UART has them. If not, we're 800 * done. Since this is the first time we enable the FIFOs, we reset 801 * them. 802 */ 803 val = FCR_ENABLE; 804 #ifdef CPU_XBURST 805 val |= FCR_UART_ON; 806 #endif 807 uart_setreg(bas, REG_FCR, val); 808 uart_barrier(bas); 809 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 810 /* 811 * NS16450 or INS8250. We don't bother to differentiate 812 * between them. They're too old to be interesting. 813 */ 814 uart_setreg(bas, REG_MCR, mcr); 815 uart_barrier(bas); 816 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 817 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 818 return (0); 819 } 820 821 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 822 #ifdef CPU_XBURST 823 val |= FCR_UART_ON; 824 #endif 825 uart_setreg(bas, REG_FCR, val); 826 uart_barrier(bas); 827 828 count = 0; 829 delay = ns8250_delay(bas); 830 831 /* We have FIFOs. Drain the transmitter and receiver. */ 832 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 833 if (error) { 834 uart_setreg(bas, REG_MCR, mcr); 835 val = 0; 836 #ifdef CPU_XBURST 837 val |= FCR_UART_ON; 838 #endif 839 uart_setreg(bas, REG_FCR, val); 840 uart_barrier(bas); 841 goto describe; 842 } 843 844 /* 845 * We should have a sufficiently clean "pipe" to determine the 846 * size of the FIFOs. We send as much characters as is reasonable 847 * and wait for the overflow bit in the LSR register to be 848 * asserted, counting the characters as we send them. Based on 849 * that count we know the FIFO size. 850 */ 851 do { 852 uart_setreg(bas, REG_DATA, 0); 853 uart_barrier(bas); 854 count++; 855 856 limit = 30; 857 lsr = 0; 858 /* 859 * LSR bits are cleared upon read, so we must accumulate 860 * them to be able to test LSR_OE below. 861 */ 862 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 863 --limit) 864 DELAY(delay); 865 if (limit == 0) { 866 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 867 uart_setreg(bas, REG_IER, ier); 868 uart_setreg(bas, REG_MCR, mcr); 869 val = 0; 870 #ifdef CPU_XBURST 871 val |= FCR_UART_ON; 872 #endif 873 uart_setreg(bas, REG_FCR, val); 874 uart_barrier(bas); 875 count = 0; 876 goto describe; 877 } 878 } while ((lsr & LSR_OE) == 0 && count < 260); 879 count--; 880 881 uart_setreg(bas, REG_MCR, mcr); 882 883 /* Reset FIFOs. */ 884 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 885 886 describe: 887 if (count >= 14 && count <= 16) { 888 sc->sc_rxfifosz = 16; 889 device_set_desc(sc->sc_dev, "16550 or compatible"); 890 } else if (count >= 28 && count <= 32) { 891 sc->sc_rxfifosz = 32; 892 device_set_desc(sc->sc_dev, "16650 or compatible"); 893 } else if (count >= 56 && count <= 64) { 894 sc->sc_rxfifosz = 64; 895 device_set_desc(sc->sc_dev, "16750 or compatible"); 896 } else if (count >= 112 && count <= 128) { 897 sc->sc_rxfifosz = 128; 898 device_set_desc(sc->sc_dev, "16950 or compatible"); 899 } else if (count >= 224 && count <= 256) { 900 sc->sc_rxfifosz = 256; 901 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 902 } else { 903 sc->sc_rxfifosz = 16; 904 device_set_desc(sc->sc_dev, 905 "Non-standard ns8250 class UART with FIFOs"); 906 } 907 908 /* 909 * Force the Tx FIFO size to 16 bytes for now. We don't program the 910 * Tx trigger. Also, we assume that all data has been sent when the 911 * interrupt happens. 912 */ 913 sc->sc_txfifosz = 16; 914 915 #if 0 916 /* 917 * XXX there are some issues related to hardware flow control and 918 * it's likely that uart(4) is the cause. This basically needs more 919 * investigation, but we avoid using for hardware flow control 920 * until then. 921 */ 922 /* 16650s or higher have automatic flow control. */ 923 if (sc->sc_rxfifosz > 16) { 924 sc->sc_hwiflow = 1; 925 sc->sc_hwoflow = 1; 926 } 927 #endif 928 929 return (0); 930 } 931 932 int 933 ns8250_bus_receive(struct uart_softc *sc) 934 { 935 struct uart_bas *bas; 936 int xc; 937 uint8_t lsr; 938 939 bas = &sc->sc_bas; 940 uart_lock(sc->sc_hwmtx); 941 lsr = uart_getreg(bas, REG_LSR); 942 while (lsr & LSR_RXRDY) { 943 if (uart_rx_full(sc)) { 944 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 945 break; 946 } 947 xc = uart_getreg(bas, REG_DATA); 948 if (lsr & LSR_FE) 949 xc |= UART_STAT_FRAMERR; 950 if (lsr & LSR_PE) 951 xc |= UART_STAT_PARERR; 952 uart_rx_put(sc, xc); 953 lsr = uart_getreg(bas, REG_LSR); 954 } 955 /* Discard everything left in the Rx FIFO. */ 956 while (lsr & LSR_RXRDY) { 957 (void)uart_getreg(bas, REG_DATA); 958 uart_barrier(bas); 959 lsr = uart_getreg(bas, REG_LSR); 960 } 961 uart_unlock(sc->sc_hwmtx); 962 return (0); 963 } 964 965 int 966 ns8250_bus_setsig(struct uart_softc *sc, int sig) 967 { 968 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 969 struct uart_bas *bas; 970 uint32_t new, old; 971 972 bas = &sc->sc_bas; 973 do { 974 old = sc->sc_hwsig; 975 new = old; 976 if (sig & SER_DDTR) { 977 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 978 } 979 if (sig & SER_DRTS) { 980 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 981 } 982 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 983 uart_lock(sc->sc_hwmtx); 984 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 985 if (new & SER_DTR) 986 ns8250->mcr |= MCR_DTR; 987 if (new & SER_RTS) 988 ns8250->mcr |= MCR_RTS; 989 uart_setreg(bas, REG_MCR, ns8250->mcr); 990 uart_barrier(bas); 991 uart_unlock(sc->sc_hwmtx); 992 return (0); 993 } 994 995 int 996 ns8250_bus_transmit(struct uart_softc *sc) 997 { 998 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 999 struct uart_bas *bas; 1000 int i; 1001 1002 bas = &sc->sc_bas; 1003 uart_lock(sc->sc_hwmtx); 1004 if (sc->sc_txdatasz > 1) { 1005 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 1006 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1007 } else { 1008 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1009 DELAY(4); 1010 } 1011 for (i = 0; i < sc->sc_txdatasz; i++) { 1012 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1013 uart_barrier(bas); 1014 } 1015 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 1016 uart_barrier(bas); 1017 if (broken_txfifo) 1018 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1019 else 1020 sc->sc_txbusy = 1; 1021 uart_unlock(sc->sc_hwmtx); 1022 if (broken_txfifo) 1023 uart_sched_softih(sc, SER_INT_TXIDLE); 1024 return (0); 1025 } 1026 1027 void 1028 ns8250_bus_grab(struct uart_softc *sc) 1029 { 1030 struct uart_bas *bas = &sc->sc_bas; 1031 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1032 u_char ier; 1033 1034 /* 1035 * turn off all interrupts to enter polling mode. Leave the 1036 * saved mask alone. We'll restore whatever it was in ungrab. 1037 * All pending interrupt signals are reset when IER is set to 0. 1038 */ 1039 uart_lock(sc->sc_hwmtx); 1040 ier = uart_getreg(bas, REG_IER); 1041 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1042 uart_barrier(bas); 1043 uart_unlock(sc->sc_hwmtx); 1044 } 1045 1046 void 1047 ns8250_bus_ungrab(struct uart_softc *sc) 1048 { 1049 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1050 struct uart_bas *bas = &sc->sc_bas; 1051 1052 /* 1053 * Restore previous interrupt mask 1054 */ 1055 uart_lock(sc->sc_hwmtx); 1056 uart_setreg(bas, REG_IER, ns8250->ier); 1057 uart_barrier(bas); 1058 uart_unlock(sc->sc_hwmtx); 1059 } 1060