1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/ns16550.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 1843200 45 46 /* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50 static void 51 ns8250_clrint(struct uart_bas *bas) 52 { 53 uint8_t iir; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) 59 (void)uart_getreg(bas, REG_LSR); 60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61 (void)uart_getreg(bas, REG_DATA); 62 else if (iir == IIR_MLSC) 63 (void)uart_getreg(bas, REG_MSR); 64 uart_barrier(bas); 65 iir = uart_getreg(bas, REG_IIR); 66 } 67 } 68 69 static int 70 ns8250_delay(struct uart_bas *bas) 71 { 72 int divisor; 73 u_char lcr; 74 75 lcr = uart_getreg(bas, REG_LCR); 76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77 uart_barrier(bas); 78 divisor = uart_getdreg(bas, REG_DL); 79 uart_barrier(bas); 80 uart_setreg(bas, REG_LCR, lcr); 81 uart_barrier(bas); 82 83 /* 1/10th the time to transmit 1 character (estimate). */ 84 return (16000000 * divisor / bas->rclk); 85 } 86 87 static int 88 ns8250_divisor(int rclk, int baudrate) 89 { 90 int actual_baud, divisor; 91 int error; 92 93 if (baudrate == 0) 94 return (0); 95 96 divisor = (rclk / (baudrate << 3) + 1) >> 1; 97 if (divisor == 0 || divisor >= 65536) 98 return (0); 99 actual_baud = rclk / (divisor << 4); 100 101 /* 10 times error in percent: */ 102 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 103 104 /* 3.0% maximum error tolerance: */ 105 if (error < -30 || error > 30) 106 return (0); 107 108 return (divisor); 109 } 110 111 static int 112 ns8250_drain(struct uart_bas *bas, int what) 113 { 114 int delay, limit; 115 116 delay = ns8250_delay(bas); 117 118 if (what & UART_DRAIN_TRANSMITTER) { 119 /* 120 * Pick an arbitrary high limit to avoid getting stuck in 121 * an infinite loop when the hardware is broken. Make the 122 * limit high enough to handle large FIFOs. 123 */ 124 limit = 10*1024; 125 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 126 DELAY(delay); 127 if (limit == 0) { 128 /* printf("ns8250: transmitter appears stuck... "); */ 129 return (EIO); 130 } 131 } 132 133 if (what & UART_DRAIN_RECEIVER) { 134 /* 135 * Pick an arbitrary high limit to avoid getting stuck in 136 * an infinite loop when the hardware is broken. Make the 137 * limit high enough to handle large FIFOs and integrated 138 * UARTs. The HP rx2600 for example has 3 UARTs on the 139 * management board that tend to get a lot of data send 140 * to it when the UART is first activated. 141 */ 142 limit=10*4096; 143 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 144 (void)uart_getreg(bas, REG_DATA); 145 uart_barrier(bas); 146 DELAY(delay << 2); 147 } 148 if (limit == 0) { 149 /* printf("ns8250: receiver appears broken... "); */ 150 return (EIO); 151 } 152 } 153 154 return (0); 155 } 156 157 /* 158 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 159 * drained. WARNING: this function clobbers the FIFO setting! 160 */ 161 static void 162 ns8250_flush(struct uart_bas *bas, int what) 163 { 164 uint8_t fcr; 165 166 fcr = FCR_ENABLE; 167 if (what & UART_FLUSH_TRANSMITTER) 168 fcr |= FCR_XMT_RST; 169 if (what & UART_FLUSH_RECEIVER) 170 fcr |= FCR_RCV_RST; 171 uart_setreg(bas, REG_FCR, fcr); 172 uart_barrier(bas); 173 } 174 175 static int 176 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 177 int parity) 178 { 179 int divisor; 180 uint8_t lcr; 181 182 lcr = 0; 183 if (databits >= 8) 184 lcr |= LCR_8BITS; 185 else if (databits == 7) 186 lcr |= LCR_7BITS; 187 else if (databits == 6) 188 lcr |= LCR_6BITS; 189 else 190 lcr |= LCR_5BITS; 191 if (stopbits > 1) 192 lcr |= LCR_STOPB; 193 lcr |= parity << 3; 194 195 /* Set baudrate. */ 196 if (baudrate > 0) { 197 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 198 uart_barrier(bas); 199 divisor = ns8250_divisor(bas->rclk, baudrate); 200 if (divisor == 0) 201 return (EINVAL); 202 uart_setdreg(bas, REG_DL, divisor); 203 uart_barrier(bas); 204 } 205 206 /* Set LCR and clear DLAB. */ 207 uart_setreg(bas, REG_LCR, lcr); 208 uart_barrier(bas); 209 return (0); 210 } 211 212 /* 213 * Low-level UART interface. 214 */ 215 static int ns8250_probe(struct uart_bas *bas); 216 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 217 static void ns8250_term(struct uart_bas *bas); 218 static void ns8250_putc(struct uart_bas *bas, int); 219 static int ns8250_poll(struct uart_bas *bas); 220 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 221 222 struct uart_ops uart_ns8250_ops = { 223 .probe = ns8250_probe, 224 .init = ns8250_init, 225 .term = ns8250_term, 226 .putc = ns8250_putc, 227 .poll = ns8250_poll, 228 .getc = ns8250_getc, 229 }; 230 231 static int 232 ns8250_probe(struct uart_bas *bas) 233 { 234 u_char lcr, val; 235 236 /* Check known 0 bits that don't depend on DLAB. */ 237 val = uart_getreg(bas, REG_IIR); 238 if (val & 0x30) 239 return (ENXIO); 240 val = uart_getreg(bas, REG_MCR); 241 if (val & 0xe0) 242 return (ENXIO); 243 244 lcr = uart_getreg(bas, REG_LCR); 245 uart_setreg(bas, REG_LCR, lcr & ~LCR_DLAB); 246 uart_barrier(bas); 247 248 /* Check known 0 bits that depend on !DLAB. */ 249 val = uart_getreg(bas, REG_IER); 250 if (val & 0xf0) 251 goto fail; 252 253 uart_setreg(bas, REG_LCR, lcr); 254 uart_barrier(bas); 255 return (0); 256 257 fail: 258 uart_setreg(bas, REG_LCR, lcr); 259 uart_barrier(bas); 260 return (ENXIO); 261 } 262 263 static void 264 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 265 int parity) 266 { 267 268 if (bas->rclk == 0) 269 bas->rclk = DEFAULT_RCLK; 270 ns8250_param(bas, baudrate, databits, stopbits, parity); 271 272 /* Disable all interrupt sources. */ 273 uart_setreg(bas, REG_IER, 0); 274 uart_barrier(bas); 275 276 /* Disable the FIFO (if present). */ 277 uart_setreg(bas, REG_FCR, 0); 278 uart_barrier(bas); 279 280 /* Set RTS & DTR. */ 281 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 282 uart_barrier(bas); 283 284 ns8250_clrint(bas); 285 } 286 287 static void 288 ns8250_term(struct uart_bas *bas) 289 { 290 291 /* Clear RTS & DTR. */ 292 uart_setreg(bas, REG_MCR, MCR_IE); 293 uart_barrier(bas); 294 } 295 296 static void 297 ns8250_putc(struct uart_bas *bas, int c) 298 { 299 int delay, limit; 300 301 /* 1/10th the time to transmit 1 character (estimate). */ 302 delay = ns8250_delay(bas); 303 304 limit = 20; 305 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 306 DELAY(delay); 307 uart_setreg(bas, REG_DATA, c); 308 uart_barrier(bas); 309 limit = 40; 310 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 311 DELAY(delay); 312 } 313 314 static int 315 ns8250_poll(struct uart_bas *bas) 316 { 317 318 if (uart_getreg(bas, REG_LSR) & LSR_RXRDY) 319 return (uart_getreg(bas, REG_DATA)); 320 return (-1); 321 } 322 323 static int 324 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 325 { 326 int c, delay; 327 328 uart_lock(hwmtx); 329 330 /* 1/10th the time to transmit 1 character (estimate). */ 331 delay = ns8250_delay(bas); 332 333 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 334 uart_unlock(hwmtx); 335 DELAY(delay); 336 uart_lock(hwmtx); 337 } 338 339 c = uart_getreg(bas, REG_DATA); 340 341 uart_unlock(hwmtx); 342 343 return (c); 344 } 345 346 /* 347 * High-level UART interface. 348 */ 349 struct ns8250_softc { 350 struct uart_softc base; 351 uint8_t fcr; 352 uint8_t ier; 353 uint8_t mcr; 354 }; 355 356 static int ns8250_bus_attach(struct uart_softc *); 357 static int ns8250_bus_detach(struct uart_softc *); 358 static int ns8250_bus_flush(struct uart_softc *, int); 359 static int ns8250_bus_getsig(struct uart_softc *); 360 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 361 static int ns8250_bus_ipend(struct uart_softc *); 362 static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 363 static int ns8250_bus_probe(struct uart_softc *); 364 static int ns8250_bus_receive(struct uart_softc *); 365 static int ns8250_bus_setsig(struct uart_softc *, int); 366 static int ns8250_bus_transmit(struct uart_softc *); 367 368 static kobj_method_t ns8250_methods[] = { 369 KOBJMETHOD(uart_attach, ns8250_bus_attach), 370 KOBJMETHOD(uart_detach, ns8250_bus_detach), 371 KOBJMETHOD(uart_flush, ns8250_bus_flush), 372 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 373 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 374 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 375 KOBJMETHOD(uart_param, ns8250_bus_param), 376 KOBJMETHOD(uart_probe, ns8250_bus_probe), 377 KOBJMETHOD(uart_receive, ns8250_bus_receive), 378 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 379 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 380 { 0, 0 } 381 }; 382 383 struct uart_class uart_ns8250_class = { 384 "ns8250 class", 385 ns8250_methods, 386 sizeof(struct ns8250_softc), 387 .uc_range = 8, 388 .uc_rclk = DEFAULT_RCLK 389 }; 390 391 #define SIGCHG(c, i, s, d) \ 392 if (c) { \ 393 i |= (i & s) ? s : s | d; \ 394 } else { \ 395 i = (i & s) ? (i & ~s) | d : i; \ 396 } 397 398 static int 399 ns8250_bus_attach(struct uart_softc *sc) 400 { 401 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 402 struct uart_bas *bas; 403 404 bas = &sc->sc_bas; 405 406 ns8250->mcr = uart_getreg(bas, REG_MCR); 407 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 408 uart_setreg(bas, REG_FCR, ns8250->fcr); 409 uart_barrier(bas); 410 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 411 412 if (ns8250->mcr & MCR_DTR) 413 sc->sc_hwsig |= SER_DTR; 414 if (ns8250->mcr & MCR_RTS) 415 sc->sc_hwsig |= SER_RTS; 416 ns8250_bus_getsig(sc); 417 418 ns8250_clrint(bas); 419 ns8250->ier = IER_EMSC | IER_ERLS | IER_ERXRDY; 420 uart_setreg(bas, REG_IER, ns8250->ier); 421 uart_barrier(bas); 422 return (0); 423 } 424 425 static int 426 ns8250_bus_detach(struct uart_softc *sc) 427 { 428 struct uart_bas *bas; 429 430 bas = &sc->sc_bas; 431 uart_setreg(bas, REG_IER, 0); 432 uart_barrier(bas); 433 ns8250_clrint(bas); 434 return (0); 435 } 436 437 static int 438 ns8250_bus_flush(struct uart_softc *sc, int what) 439 { 440 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 441 struct uart_bas *bas; 442 int error; 443 444 bas = &sc->sc_bas; 445 uart_lock(sc->sc_hwmtx); 446 if (sc->sc_rxfifosz > 1) { 447 ns8250_flush(bas, what); 448 uart_setreg(bas, REG_FCR, ns8250->fcr); 449 uart_barrier(bas); 450 error = 0; 451 } else 452 error = ns8250_drain(bas, what); 453 uart_unlock(sc->sc_hwmtx); 454 return (error); 455 } 456 457 static int 458 ns8250_bus_getsig(struct uart_softc *sc) 459 { 460 uint32_t new, old, sig; 461 uint8_t msr; 462 463 do { 464 old = sc->sc_hwsig; 465 sig = old; 466 uart_lock(sc->sc_hwmtx); 467 msr = uart_getreg(&sc->sc_bas, REG_MSR); 468 uart_unlock(sc->sc_hwmtx); 469 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 470 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 471 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 472 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 473 new = sig & ~SER_MASK_DELTA; 474 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 475 return (sig); 476 } 477 478 static int 479 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 480 { 481 struct uart_bas *bas; 482 int baudrate, divisor, error; 483 uint8_t efr, lcr; 484 485 bas = &sc->sc_bas; 486 error = 0; 487 uart_lock(sc->sc_hwmtx); 488 switch (request) { 489 case UART_IOCTL_BREAK: 490 lcr = uart_getreg(bas, REG_LCR); 491 if (data) 492 lcr |= LCR_SBREAK; 493 else 494 lcr &= ~LCR_SBREAK; 495 uart_setreg(bas, REG_LCR, lcr); 496 uart_barrier(bas); 497 break; 498 case UART_IOCTL_IFLOW: 499 lcr = uart_getreg(bas, REG_LCR); 500 uart_barrier(bas); 501 uart_setreg(bas, REG_LCR, 0xbf); 502 uart_barrier(bas); 503 efr = uart_getreg(bas, REG_EFR); 504 if (data) 505 efr |= EFR_RTS; 506 else 507 efr &= ~EFR_RTS; 508 uart_setreg(bas, REG_EFR, efr); 509 uart_barrier(bas); 510 uart_setreg(bas, REG_LCR, lcr); 511 uart_barrier(bas); 512 break; 513 case UART_IOCTL_OFLOW: 514 lcr = uart_getreg(bas, REG_LCR); 515 uart_barrier(bas); 516 uart_setreg(bas, REG_LCR, 0xbf); 517 uart_barrier(bas); 518 efr = uart_getreg(bas, REG_EFR); 519 if (data) 520 efr |= EFR_CTS; 521 else 522 efr &= ~EFR_CTS; 523 uart_setreg(bas, REG_EFR, efr); 524 uart_barrier(bas); 525 uart_setreg(bas, REG_LCR, lcr); 526 uart_barrier(bas); 527 break; 528 case UART_IOCTL_BAUD: 529 lcr = uart_getreg(bas, REG_LCR); 530 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 531 uart_barrier(bas); 532 divisor = uart_getdreg(bas, REG_DL); 533 uart_barrier(bas); 534 uart_setreg(bas, REG_LCR, lcr); 535 uart_barrier(bas); 536 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 537 if (baudrate > 0) 538 *(int*)data = baudrate; 539 else 540 error = ENXIO; 541 break; 542 default: 543 error = EINVAL; 544 break; 545 } 546 uart_unlock(sc->sc_hwmtx); 547 return (error); 548 } 549 550 static int 551 ns8250_bus_ipend(struct uart_softc *sc) 552 { 553 struct uart_bas *bas; 554 int ipend; 555 uint8_t iir, lsr; 556 557 bas = &sc->sc_bas; 558 uart_lock(sc->sc_hwmtx); 559 iir = uart_getreg(bas, REG_IIR); 560 if (iir & IIR_NOPEND) { 561 uart_unlock(sc->sc_hwmtx); 562 return (0); 563 } 564 ipend = 0; 565 if (iir & IIR_RXRDY) { 566 lsr = uart_getreg(bas, REG_LSR); 567 uart_unlock(sc->sc_hwmtx); 568 if (lsr & LSR_OE) 569 ipend |= SER_INT_OVERRUN; 570 if (lsr & LSR_BI) 571 ipend |= SER_INT_BREAK; 572 if (lsr & LSR_RXRDY) 573 ipend |= SER_INT_RXREADY; 574 } else { 575 uart_unlock(sc->sc_hwmtx); 576 if (iir & IIR_TXRDY) 577 ipend |= SER_INT_TXIDLE; 578 else 579 ipend |= SER_INT_SIGCHG; 580 } 581 return ((sc->sc_leaving) ? 0 : ipend); 582 } 583 584 static int 585 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 586 int stopbits, int parity) 587 { 588 struct uart_bas *bas; 589 int error; 590 591 bas = &sc->sc_bas; 592 uart_lock(sc->sc_hwmtx); 593 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 594 uart_unlock(sc->sc_hwmtx); 595 return (error); 596 } 597 598 static int 599 ns8250_bus_probe(struct uart_softc *sc) 600 { 601 struct uart_bas *bas; 602 int count, delay, error, limit; 603 uint8_t lsr, mcr; 604 605 bas = &sc->sc_bas; 606 607 error = ns8250_probe(bas); 608 if (error) 609 return (error); 610 611 mcr = MCR_IE; 612 if (sc->sc_sysdev == NULL) { 613 /* By using ns8250_init() we also set DTR and RTS. */ 614 ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE); 615 } else 616 mcr |= MCR_DTR | MCR_RTS; 617 618 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 619 if (error) 620 return (error); 621 622 /* 623 * Set loopback mode. This avoids having garbage on the wire and 624 * also allows us send and receive data. We set DTR and RTS to 625 * avoid the possibility that automatic flow-control prevents 626 * any data from being sent. 627 */ 628 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 629 uart_barrier(bas); 630 631 /* 632 * Enable FIFOs. And check that the UART has them. If not, we're 633 * done. Since this is the first time we enable the FIFOs, we reset 634 * them. 635 */ 636 uart_setreg(bas, REG_FCR, FCR_ENABLE); 637 uart_barrier(bas); 638 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 639 /* 640 * NS16450 or INS8250. We don't bother to differentiate 641 * between them. They're too old to be interesting. 642 */ 643 uart_setreg(bas, REG_MCR, mcr); 644 uart_barrier(bas); 645 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 646 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 647 return (0); 648 } 649 650 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 651 uart_barrier(bas); 652 653 count = 0; 654 delay = ns8250_delay(bas); 655 656 /* We have FIFOs. Drain the transmitter and receiver. */ 657 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 658 if (error) { 659 uart_setreg(bas, REG_MCR, mcr); 660 uart_setreg(bas, REG_FCR, 0); 661 uart_barrier(bas); 662 goto describe; 663 } 664 665 /* 666 * We should have a sufficiently clean "pipe" to determine the 667 * size of the FIFOs. We send as much characters as is reasonable 668 * and wait for the the overflow bit in the LSR register to be 669 * asserted, counting the characters as we send them. Based on 670 * that count we know the FIFO size. 671 */ 672 do { 673 uart_setreg(bas, REG_DATA, 0); 674 uart_barrier(bas); 675 count++; 676 677 limit = 30; 678 lsr = 0; 679 /* 680 * LSR bits are cleared upon read, so we must accumulate 681 * them to be able to test LSR_OE below. 682 */ 683 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 684 --limit) 685 DELAY(delay); 686 if (limit == 0) { 687 uart_setreg(bas, REG_IER, 0); 688 uart_setreg(bas, REG_MCR, mcr); 689 uart_setreg(bas, REG_FCR, 0); 690 uart_barrier(bas); 691 count = 0; 692 goto describe; 693 } 694 } while ((lsr & LSR_OE) == 0 && count < 130); 695 count--; 696 697 uart_setreg(bas, REG_MCR, mcr); 698 699 /* Reset FIFOs. */ 700 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 701 702 describe: 703 if (count >= 14 && count <= 16) { 704 sc->sc_rxfifosz = 16; 705 device_set_desc(sc->sc_dev, "16550 or compatible"); 706 } else if (count >= 28 && count <= 32) { 707 sc->sc_rxfifosz = 32; 708 device_set_desc(sc->sc_dev, "16650 or compatible"); 709 } else if (count >= 56 && count <= 64) { 710 sc->sc_rxfifosz = 64; 711 device_set_desc(sc->sc_dev, "16750 or compatible"); 712 } else if (count >= 112 && count <= 128) { 713 sc->sc_rxfifosz = 128; 714 device_set_desc(sc->sc_dev, "16950 or compatible"); 715 } else { 716 sc->sc_rxfifosz = 16; 717 device_set_desc(sc->sc_dev, 718 "Non-standard ns8250 class UART with FIFOs"); 719 } 720 721 /* 722 * Force the Tx FIFO size to 16 bytes for now. We don't program the 723 * Tx trigger. Also, we assume that all data has been sent when the 724 * interrupt happens. 725 */ 726 sc->sc_txfifosz = 16; 727 728 #if 0 729 /* 730 * XXX there are some issues related to hardware flow control and 731 * it's likely that uart(4) is the cause. This basicly needs more 732 * investigation, but we avoid using for hardware flow control 733 * until then. 734 */ 735 /* 16650s or higher have automatic flow control. */ 736 if (sc->sc_rxfifosz > 16) { 737 sc->sc_hwiflow = 1; 738 sc->sc_hwoflow = 1; 739 } 740 #endif 741 742 return (0); 743 } 744 745 static int 746 ns8250_bus_receive(struct uart_softc *sc) 747 { 748 struct uart_bas *bas; 749 int xc; 750 uint8_t lsr; 751 752 bas = &sc->sc_bas; 753 uart_lock(sc->sc_hwmtx); 754 lsr = uart_getreg(bas, REG_LSR); 755 while (lsr & LSR_RXRDY) { 756 if (uart_rx_full(sc)) { 757 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 758 break; 759 } 760 xc = uart_getreg(bas, REG_DATA); 761 if (lsr & LSR_FE) 762 xc |= UART_STAT_FRAMERR; 763 if (lsr & LSR_PE) 764 xc |= UART_STAT_PARERR; 765 uart_rx_put(sc, xc); 766 lsr = uart_getreg(bas, REG_LSR); 767 } 768 /* Discard everything left in the Rx FIFO. */ 769 while (lsr & LSR_RXRDY) { 770 (void)uart_getreg(bas, REG_DATA); 771 uart_barrier(bas); 772 lsr = uart_getreg(bas, REG_LSR); 773 } 774 uart_unlock(sc->sc_hwmtx); 775 return (0); 776 } 777 778 static int 779 ns8250_bus_setsig(struct uart_softc *sc, int sig) 780 { 781 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 782 struct uart_bas *bas; 783 uint32_t new, old; 784 785 bas = &sc->sc_bas; 786 do { 787 old = sc->sc_hwsig; 788 new = old; 789 if (sig & SER_DDTR) { 790 SIGCHG(sig & SER_DTR, new, SER_DTR, 791 SER_DDTR); 792 } 793 if (sig & SER_DRTS) { 794 SIGCHG(sig & SER_RTS, new, SER_RTS, 795 SER_DRTS); 796 } 797 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 798 uart_lock(sc->sc_hwmtx); 799 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 800 if (new & SER_DTR) 801 ns8250->mcr |= MCR_DTR; 802 if (new & SER_RTS) 803 ns8250->mcr |= MCR_RTS; 804 uart_setreg(bas, REG_MCR, ns8250->mcr); 805 uart_barrier(bas); 806 uart_unlock(sc->sc_hwmtx); 807 return (0); 808 } 809 810 static int 811 ns8250_bus_transmit(struct uart_softc *sc) 812 { 813 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 814 struct uart_bas *bas; 815 int i; 816 817 bas = &sc->sc_bas; 818 uart_lock(sc->sc_hwmtx); 819 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 820 ; 821 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 822 uart_barrier(bas); 823 for (i = 0; i < sc->sc_txdatasz; i++) { 824 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 825 uart_barrier(bas); 826 } 827 sc->sc_txbusy = 1; 828 uart_unlock(sc->sc_hwmtx); 829 return (0); 830 } 831