1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/sysctl.h> 38 #include <machine/bus.h> 39 40 #ifdef FDT 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #endif 45 46 #include <dev/uart/uart.h> 47 #include <dev/uart/uart_cpu.h> 48 #include <dev/uart/uart_bus.h> 49 #include <dev/uart/uart_dev_ns8250.h> 50 51 #include <dev/ic/ns16550.h> 52 53 #include "uart_if.h" 54 55 #define DEFAULT_RCLK 1843200 56 57 static int broken_txfifo = 0; 58 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60 61 /* 62 * Clear pending interrupts. THRE is cleared by reading IIR. Data 63 * that may have been received gets lost here. 64 */ 65 static void 66 ns8250_clrint(struct uart_bas *bas) 67 { 68 uint8_t iir, lsr; 69 70 iir = uart_getreg(bas, REG_IIR); 71 while ((iir & IIR_NOPEND) == 0) { 72 iir &= IIR_IMASK; 73 if (iir == IIR_RLS) { 74 lsr = uart_getreg(bas, REG_LSR); 75 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 76 (void)uart_getreg(bas, REG_DATA); 77 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 78 (void)uart_getreg(bas, REG_DATA); 79 else if (iir == IIR_MLSC) 80 (void)uart_getreg(bas, REG_MSR); 81 uart_barrier(bas); 82 iir = uart_getreg(bas, REG_IIR); 83 } 84 } 85 86 static int 87 ns8250_delay(struct uart_bas *bas) 88 { 89 int divisor; 90 u_char lcr; 91 92 lcr = uart_getreg(bas, REG_LCR); 93 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 94 uart_barrier(bas); 95 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 96 uart_barrier(bas); 97 uart_setreg(bas, REG_LCR, lcr); 98 uart_barrier(bas); 99 100 /* 1/10th the time to transmit 1 character (estimate). */ 101 if (divisor <= 134) 102 return (16000000 * divisor / bas->rclk); 103 return (16000 * divisor / (bas->rclk / 1000)); 104 } 105 106 static int 107 ns8250_divisor(int rclk, int baudrate) 108 { 109 int actual_baud, divisor; 110 int error; 111 112 if (baudrate == 0) 113 return (0); 114 115 divisor = (rclk / (baudrate << 3) + 1) >> 1; 116 if (divisor == 0 || divisor >= 65536) 117 return (0); 118 actual_baud = rclk / (divisor << 4); 119 120 /* 10 times error in percent: */ 121 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 122 123 /* 3.0% maximum error tolerance: */ 124 if (error < -30 || error > 30) 125 return (0); 126 127 return (divisor); 128 } 129 130 static int 131 ns8250_drain(struct uart_bas *bas, int what) 132 { 133 int delay, limit; 134 135 delay = ns8250_delay(bas); 136 137 if (what & UART_DRAIN_TRANSMITTER) { 138 /* 139 * Pick an arbitrary high limit to avoid getting stuck in 140 * an infinite loop when the hardware is broken. Make the 141 * limit high enough to handle large FIFOs. 142 */ 143 limit = 10*1024; 144 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 145 DELAY(delay); 146 if (limit == 0) { 147 /* printf("ns8250: transmitter appears stuck... "); */ 148 return (EIO); 149 } 150 } 151 152 if (what & UART_DRAIN_RECEIVER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs and integrated 157 * UARTs. The HP rx2600 for example has 3 UARTs on the 158 * management board that tend to get a lot of data send 159 * to it when the UART is first activated. 160 */ 161 limit=10*4096; 162 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 163 (void)uart_getreg(bas, REG_DATA); 164 uart_barrier(bas); 165 DELAY(delay << 2); 166 } 167 if (limit == 0) { 168 /* printf("ns8250: receiver appears broken... "); */ 169 return (EIO); 170 } 171 } 172 173 return (0); 174 } 175 176 /* 177 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 178 * drained. WARNING: this function clobbers the FIFO setting! 179 */ 180 static void 181 ns8250_flush(struct uart_bas *bas, int what) 182 { 183 uint8_t fcr; 184 185 fcr = FCR_ENABLE; 186 if (what & UART_FLUSH_TRANSMITTER) 187 fcr |= FCR_XMT_RST; 188 if (what & UART_FLUSH_RECEIVER) 189 fcr |= FCR_RCV_RST; 190 uart_setreg(bas, REG_FCR, fcr); 191 uart_barrier(bas); 192 } 193 194 static int 195 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 196 int parity) 197 { 198 int divisor; 199 uint8_t lcr; 200 201 lcr = 0; 202 if (databits >= 8) 203 lcr |= LCR_8BITS; 204 else if (databits == 7) 205 lcr |= LCR_7BITS; 206 else if (databits == 6) 207 lcr |= LCR_6BITS; 208 else 209 lcr |= LCR_5BITS; 210 if (stopbits > 1) 211 lcr |= LCR_STOPB; 212 lcr |= parity << 3; 213 214 /* Set baudrate. */ 215 if (baudrate > 0) { 216 divisor = ns8250_divisor(bas->rclk, baudrate); 217 if (divisor == 0) 218 return (EINVAL); 219 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 220 uart_barrier(bas); 221 uart_setreg(bas, REG_DLL, divisor & 0xff); 222 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 223 uart_barrier(bas); 224 } 225 226 /* Set LCR and clear DLAB. */ 227 uart_setreg(bas, REG_LCR, lcr); 228 uart_barrier(bas); 229 return (0); 230 } 231 232 /* 233 * Low-level UART interface. 234 */ 235 static int ns8250_probe(struct uart_bas *bas); 236 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 237 static void ns8250_term(struct uart_bas *bas); 238 static void ns8250_putc(struct uart_bas *bas, int); 239 static int ns8250_rxready(struct uart_bas *bas); 240 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 241 242 struct uart_ops uart_ns8250_ops = { 243 .probe = ns8250_probe, 244 .init = ns8250_init, 245 .term = ns8250_term, 246 .putc = ns8250_putc, 247 .rxready = ns8250_rxready, 248 .getc = ns8250_getc, 249 }; 250 251 static int 252 ns8250_probe(struct uart_bas *bas) 253 { 254 u_char val; 255 256 /* Check known 0 bits that don't depend on DLAB. */ 257 val = uart_getreg(bas, REG_IIR); 258 if (val & 0x30) 259 return (ENXIO); 260 /* 261 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 262 * chip, but otherwise doesn't seem to have a function. In 263 * other words, uart(4) works regardless. Ignore that bit so 264 * the probe succeeds. 265 */ 266 val = uart_getreg(bas, REG_MCR); 267 if (val & 0xa0) 268 return (ENXIO); 269 270 return (0); 271 } 272 273 static void 274 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 275 int parity) 276 { 277 u_char ier; 278 279 if (bas->rclk == 0) 280 bas->rclk = DEFAULT_RCLK; 281 ns8250_param(bas, baudrate, databits, stopbits, parity); 282 283 /* Disable all interrupt sources. */ 284 /* 285 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 286 * UARTs split the receive time-out interrupt bit out separately as 287 * 0x10. This gets handled by ier_mask and ier_rxbits below. 288 */ 289 ier = uart_getreg(bas, REG_IER) & 0xe0; 290 uart_setreg(bas, REG_IER, ier); 291 uart_barrier(bas); 292 293 /* Disable the FIFO (if present). */ 294 uart_setreg(bas, REG_FCR, 0); 295 uart_barrier(bas); 296 297 /* Set RTS & DTR. */ 298 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 299 uart_barrier(bas); 300 301 ns8250_clrint(bas); 302 } 303 304 static void 305 ns8250_term(struct uart_bas *bas) 306 { 307 308 /* Clear RTS & DTR. */ 309 uart_setreg(bas, REG_MCR, MCR_IE); 310 uart_barrier(bas); 311 } 312 313 static void 314 ns8250_putc(struct uart_bas *bas, int c) 315 { 316 int limit; 317 318 limit = 250000; 319 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 320 DELAY(4); 321 uart_setreg(bas, REG_DATA, c); 322 uart_barrier(bas); 323 limit = 250000; 324 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 325 DELAY(4); 326 } 327 328 static int 329 ns8250_rxready(struct uart_bas *bas) 330 { 331 332 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 333 } 334 335 static int 336 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 337 { 338 int c; 339 340 uart_lock(hwmtx); 341 342 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 343 uart_unlock(hwmtx); 344 DELAY(4); 345 uart_lock(hwmtx); 346 } 347 348 c = uart_getreg(bas, REG_DATA); 349 350 uart_unlock(hwmtx); 351 352 return (c); 353 } 354 355 static kobj_method_t ns8250_methods[] = { 356 KOBJMETHOD(uart_attach, ns8250_bus_attach), 357 KOBJMETHOD(uart_detach, ns8250_bus_detach), 358 KOBJMETHOD(uart_flush, ns8250_bus_flush), 359 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 360 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 361 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 362 KOBJMETHOD(uart_param, ns8250_bus_param), 363 KOBJMETHOD(uart_probe, ns8250_bus_probe), 364 KOBJMETHOD(uart_receive, ns8250_bus_receive), 365 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 366 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 367 KOBJMETHOD(uart_grab, ns8250_bus_grab), 368 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 369 { 0, 0 } 370 }; 371 372 struct uart_class uart_ns8250_class = { 373 "ns8250", 374 ns8250_methods, 375 sizeof(struct ns8250_softc), 376 .uc_ops = &uart_ns8250_ops, 377 .uc_range = 8, 378 .uc_rclk = DEFAULT_RCLK 379 }; 380 381 #define SIGCHG(c, i, s, d) \ 382 if (c) { \ 383 i |= (i & s) ? s : s | d; \ 384 } else { \ 385 i = (i & s) ? (i & ~s) | d : i; \ 386 } 387 388 int 389 ns8250_bus_attach(struct uart_softc *sc) 390 { 391 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 392 struct uart_bas *bas; 393 unsigned int ivar; 394 #ifdef FDT 395 phandle_t node; 396 pcell_t cell; 397 #endif 398 399 ns8250->busy_detect = 0; 400 401 #ifdef FDT 402 /* 403 * Check whether uart requires to read USR reg when IIR_BUSY and 404 * has broken txfifo. 405 */ 406 node = ofw_bus_get_node(sc->sc_dev); 407 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 408 ns8250->busy_detect = 1; 409 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 410 broken_txfifo = 1; 411 #endif 412 413 bas = &sc->sc_bas; 414 415 ns8250->mcr = uart_getreg(bas, REG_MCR); 416 ns8250->fcr = FCR_ENABLE; 417 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 418 &ivar)) { 419 if (UART_FLAGS_FCR_RX_LOW(ivar)) 420 ns8250->fcr |= FCR_RX_LOW; 421 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 422 ns8250->fcr |= FCR_RX_MEDL; 423 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 424 ns8250->fcr |= FCR_RX_HIGH; 425 else 426 ns8250->fcr |= FCR_RX_MEDH; 427 } else 428 ns8250->fcr |= FCR_RX_MEDH; 429 430 /* Get IER mask */ 431 ivar = 0xf0; 432 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 433 &ivar); 434 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 435 436 /* Get IER RX interrupt bits */ 437 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 438 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 439 &ivar); 440 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 441 442 uart_setreg(bas, REG_FCR, ns8250->fcr); 443 uart_barrier(bas); 444 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 445 446 if (ns8250->mcr & MCR_DTR) 447 sc->sc_hwsig |= SER_DTR; 448 if (ns8250->mcr & MCR_RTS) 449 sc->sc_hwsig |= SER_RTS; 450 ns8250_bus_getsig(sc); 451 452 ns8250_clrint(bas); 453 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 454 ns8250->ier |= ns8250->ier_rxbits; 455 uart_setreg(bas, REG_IER, ns8250->ier); 456 uart_barrier(bas); 457 458 /* 459 * Timing of the H/W access was changed with r253161 of uart_core.c 460 * It has been observed that an ITE IT8513E would signal a break 461 * condition with pretty much every character it received, unless 462 * it had enough time to settle between ns8250_bus_attach() and 463 * ns8250_bus_ipend() -- which it accidentally had before r253161. 464 * It's not understood why the UART chip behaves this way and it 465 * could very well be that the DELAY make the H/W work in the same 466 * accidental manner as before. More analysis is warranted, but 467 * at least now we fixed a known regression. 468 */ 469 DELAY(200); 470 return (0); 471 } 472 473 int 474 ns8250_bus_detach(struct uart_softc *sc) 475 { 476 struct ns8250_softc *ns8250; 477 struct uart_bas *bas; 478 u_char ier; 479 480 ns8250 = (struct ns8250_softc *)sc; 481 bas = &sc->sc_bas; 482 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 483 uart_setreg(bas, REG_IER, ier); 484 uart_barrier(bas); 485 ns8250_clrint(bas); 486 return (0); 487 } 488 489 int 490 ns8250_bus_flush(struct uart_softc *sc, int what) 491 { 492 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 493 struct uart_bas *bas; 494 int error; 495 496 bas = &sc->sc_bas; 497 uart_lock(sc->sc_hwmtx); 498 if (sc->sc_rxfifosz > 1) { 499 ns8250_flush(bas, what); 500 uart_setreg(bas, REG_FCR, ns8250->fcr); 501 uart_barrier(bas); 502 error = 0; 503 } else 504 error = ns8250_drain(bas, what); 505 uart_unlock(sc->sc_hwmtx); 506 return (error); 507 } 508 509 int 510 ns8250_bus_getsig(struct uart_softc *sc) 511 { 512 uint32_t new, old, sig; 513 uint8_t msr; 514 515 do { 516 old = sc->sc_hwsig; 517 sig = old; 518 uart_lock(sc->sc_hwmtx); 519 msr = uart_getreg(&sc->sc_bas, REG_MSR); 520 uart_unlock(sc->sc_hwmtx); 521 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 522 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 523 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 524 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 525 new = sig & ~SER_MASK_DELTA; 526 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 527 return (sig); 528 } 529 530 int 531 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 532 { 533 struct uart_bas *bas; 534 int baudrate, divisor, error; 535 uint8_t efr, lcr; 536 537 bas = &sc->sc_bas; 538 error = 0; 539 uart_lock(sc->sc_hwmtx); 540 switch (request) { 541 case UART_IOCTL_BREAK: 542 lcr = uart_getreg(bas, REG_LCR); 543 if (data) 544 lcr |= LCR_SBREAK; 545 else 546 lcr &= ~LCR_SBREAK; 547 uart_setreg(bas, REG_LCR, lcr); 548 uart_barrier(bas); 549 break; 550 case UART_IOCTL_IFLOW: 551 lcr = uart_getreg(bas, REG_LCR); 552 uart_barrier(bas); 553 uart_setreg(bas, REG_LCR, 0xbf); 554 uart_barrier(bas); 555 efr = uart_getreg(bas, REG_EFR); 556 if (data) 557 efr |= EFR_RTS; 558 else 559 efr &= ~EFR_RTS; 560 uart_setreg(bas, REG_EFR, efr); 561 uart_barrier(bas); 562 uart_setreg(bas, REG_LCR, lcr); 563 uart_barrier(bas); 564 break; 565 case UART_IOCTL_OFLOW: 566 lcr = uart_getreg(bas, REG_LCR); 567 uart_barrier(bas); 568 uart_setreg(bas, REG_LCR, 0xbf); 569 uart_barrier(bas); 570 efr = uart_getreg(bas, REG_EFR); 571 if (data) 572 efr |= EFR_CTS; 573 else 574 efr &= ~EFR_CTS; 575 uart_setreg(bas, REG_EFR, efr); 576 uart_barrier(bas); 577 uart_setreg(bas, REG_LCR, lcr); 578 uart_barrier(bas); 579 break; 580 case UART_IOCTL_BAUD: 581 lcr = uart_getreg(bas, REG_LCR); 582 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 583 uart_barrier(bas); 584 divisor = uart_getreg(bas, REG_DLL) | 585 (uart_getreg(bas, REG_DLH) << 8); 586 uart_barrier(bas); 587 uart_setreg(bas, REG_LCR, lcr); 588 uart_barrier(bas); 589 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 590 if (baudrate > 0) 591 *(int*)data = baudrate; 592 else 593 error = ENXIO; 594 break; 595 default: 596 error = EINVAL; 597 break; 598 } 599 uart_unlock(sc->sc_hwmtx); 600 return (error); 601 } 602 603 int 604 ns8250_bus_ipend(struct uart_softc *sc) 605 { 606 struct uart_bas *bas; 607 struct ns8250_softc *ns8250; 608 int ipend; 609 uint8_t iir, lsr; 610 611 ns8250 = (struct ns8250_softc *)sc; 612 bas = &sc->sc_bas; 613 uart_lock(sc->sc_hwmtx); 614 iir = uart_getreg(bas, REG_IIR); 615 616 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 617 (void)uart_getreg(bas, DW_REG_USR); 618 uart_unlock(sc->sc_hwmtx); 619 return (0); 620 } 621 if (iir & IIR_NOPEND) { 622 uart_unlock(sc->sc_hwmtx); 623 return (0); 624 } 625 ipend = 0; 626 if (iir & IIR_RXRDY) { 627 lsr = uart_getreg(bas, REG_LSR); 628 if (lsr & LSR_OE) 629 ipend |= SER_INT_OVERRUN; 630 if (lsr & LSR_BI) 631 ipend |= SER_INT_BREAK; 632 if (lsr & LSR_RXRDY) 633 ipend |= SER_INT_RXREADY; 634 } else { 635 if (iir & IIR_TXRDY) { 636 ipend |= SER_INT_TXIDLE; 637 uart_setreg(bas, REG_IER, ns8250->ier); 638 } else 639 ipend |= SER_INT_SIGCHG; 640 } 641 if (ipend == 0) 642 ns8250_clrint(bas); 643 uart_unlock(sc->sc_hwmtx); 644 return (ipend); 645 } 646 647 int 648 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 649 int stopbits, int parity) 650 { 651 struct ns8250_softc *ns8250; 652 struct uart_bas *bas; 653 int error, limit; 654 655 ns8250 = (struct ns8250_softc*)sc; 656 bas = &sc->sc_bas; 657 uart_lock(sc->sc_hwmtx); 658 /* 659 * When using DW UART with BUSY detection it is necessary to wait 660 * until all serial transfers are finished before manipulating the 661 * line control. LCR will not be affected when UART is busy. 662 */ 663 if (ns8250->busy_detect != 0) { 664 /* 665 * Pick an arbitrary high limit to avoid getting stuck in 666 * an infinite loop in case when the hardware is broken. 667 */ 668 limit = 10 * 1024; 669 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 670 --limit) 671 DELAY(4); 672 673 if (limit <= 0) { 674 /* UART appears to be stuck */ 675 uart_unlock(sc->sc_hwmtx); 676 return (EIO); 677 } 678 } 679 680 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 681 uart_unlock(sc->sc_hwmtx); 682 return (error); 683 } 684 685 int 686 ns8250_bus_probe(struct uart_softc *sc) 687 { 688 struct ns8250_softc *ns8250; 689 struct uart_bas *bas; 690 int count, delay, error, limit; 691 uint8_t lsr, mcr, ier; 692 693 ns8250 = (struct ns8250_softc *)sc; 694 bas = &sc->sc_bas; 695 696 error = ns8250_probe(bas); 697 if (error) 698 return (error); 699 700 mcr = MCR_IE; 701 if (sc->sc_sysdev == NULL) { 702 /* By using ns8250_init() we also set DTR and RTS. */ 703 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 704 } else 705 mcr |= MCR_DTR | MCR_RTS; 706 707 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 708 if (error) 709 return (error); 710 711 /* 712 * Set loopback mode. This avoids having garbage on the wire and 713 * also allows us send and receive data. We set DTR and RTS to 714 * avoid the possibility that automatic flow-control prevents 715 * any data from being sent. 716 */ 717 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 718 uart_barrier(bas); 719 720 /* 721 * Enable FIFOs. And check that the UART has them. If not, we're 722 * done. Since this is the first time we enable the FIFOs, we reset 723 * them. 724 */ 725 uart_setreg(bas, REG_FCR, FCR_ENABLE); 726 uart_barrier(bas); 727 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 728 /* 729 * NS16450 or INS8250. We don't bother to differentiate 730 * between them. They're too old to be interesting. 731 */ 732 uart_setreg(bas, REG_MCR, mcr); 733 uart_barrier(bas); 734 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 735 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 736 return (0); 737 } 738 739 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 740 uart_barrier(bas); 741 742 count = 0; 743 delay = ns8250_delay(bas); 744 745 /* We have FIFOs. Drain the transmitter and receiver. */ 746 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 747 if (error) { 748 uart_setreg(bas, REG_MCR, mcr); 749 uart_setreg(bas, REG_FCR, 0); 750 uart_barrier(bas); 751 goto describe; 752 } 753 754 /* 755 * We should have a sufficiently clean "pipe" to determine the 756 * size of the FIFOs. We send as much characters as is reasonable 757 * and wait for the overflow bit in the LSR register to be 758 * asserted, counting the characters as we send them. Based on 759 * that count we know the FIFO size. 760 */ 761 do { 762 uart_setreg(bas, REG_DATA, 0); 763 uart_barrier(bas); 764 count++; 765 766 limit = 30; 767 lsr = 0; 768 /* 769 * LSR bits are cleared upon read, so we must accumulate 770 * them to be able to test LSR_OE below. 771 */ 772 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 773 --limit) 774 DELAY(delay); 775 if (limit == 0) { 776 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 777 uart_setreg(bas, REG_IER, ier); 778 uart_setreg(bas, REG_MCR, mcr); 779 uart_setreg(bas, REG_FCR, 0); 780 uart_barrier(bas); 781 count = 0; 782 goto describe; 783 } 784 } while ((lsr & LSR_OE) == 0 && count < 130); 785 count--; 786 787 uart_setreg(bas, REG_MCR, mcr); 788 789 /* Reset FIFOs. */ 790 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 791 792 describe: 793 if (count >= 14 && count <= 16) { 794 sc->sc_rxfifosz = 16; 795 device_set_desc(sc->sc_dev, "16550 or compatible"); 796 } else if (count >= 28 && count <= 32) { 797 sc->sc_rxfifosz = 32; 798 device_set_desc(sc->sc_dev, "16650 or compatible"); 799 } else if (count >= 56 && count <= 64) { 800 sc->sc_rxfifosz = 64; 801 device_set_desc(sc->sc_dev, "16750 or compatible"); 802 } else if (count >= 112 && count <= 128) { 803 sc->sc_rxfifosz = 128; 804 device_set_desc(sc->sc_dev, "16950 or compatible"); 805 } else { 806 sc->sc_rxfifosz = 16; 807 device_set_desc(sc->sc_dev, 808 "Non-standard ns8250 class UART with FIFOs"); 809 } 810 811 /* 812 * Force the Tx FIFO size to 16 bytes for now. We don't program the 813 * Tx trigger. Also, we assume that all data has been sent when the 814 * interrupt happens. 815 */ 816 sc->sc_txfifosz = 16; 817 818 #if 0 819 /* 820 * XXX there are some issues related to hardware flow control and 821 * it's likely that uart(4) is the cause. This basicly needs more 822 * investigation, but we avoid using for hardware flow control 823 * until then. 824 */ 825 /* 16650s or higher have automatic flow control. */ 826 if (sc->sc_rxfifosz > 16) { 827 sc->sc_hwiflow = 1; 828 sc->sc_hwoflow = 1; 829 } 830 #endif 831 832 return (0); 833 } 834 835 int 836 ns8250_bus_receive(struct uart_softc *sc) 837 { 838 struct uart_bas *bas; 839 int xc; 840 uint8_t lsr; 841 842 bas = &sc->sc_bas; 843 uart_lock(sc->sc_hwmtx); 844 lsr = uart_getreg(bas, REG_LSR); 845 while (lsr & LSR_RXRDY) { 846 if (uart_rx_full(sc)) { 847 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 848 break; 849 } 850 xc = uart_getreg(bas, REG_DATA); 851 if (lsr & LSR_FE) 852 xc |= UART_STAT_FRAMERR; 853 if (lsr & LSR_PE) 854 xc |= UART_STAT_PARERR; 855 uart_rx_put(sc, xc); 856 lsr = uart_getreg(bas, REG_LSR); 857 } 858 /* Discard everything left in the Rx FIFO. */ 859 while (lsr & LSR_RXRDY) { 860 (void)uart_getreg(bas, REG_DATA); 861 uart_barrier(bas); 862 lsr = uart_getreg(bas, REG_LSR); 863 } 864 uart_unlock(sc->sc_hwmtx); 865 return (0); 866 } 867 868 int 869 ns8250_bus_setsig(struct uart_softc *sc, int sig) 870 { 871 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 872 struct uart_bas *bas; 873 uint32_t new, old; 874 875 bas = &sc->sc_bas; 876 do { 877 old = sc->sc_hwsig; 878 new = old; 879 if (sig & SER_DDTR) { 880 SIGCHG(sig & SER_DTR, new, SER_DTR, 881 SER_DDTR); 882 } 883 if (sig & SER_DRTS) { 884 SIGCHG(sig & SER_RTS, new, SER_RTS, 885 SER_DRTS); 886 } 887 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 888 uart_lock(sc->sc_hwmtx); 889 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 890 if (new & SER_DTR) 891 ns8250->mcr |= MCR_DTR; 892 if (new & SER_RTS) 893 ns8250->mcr |= MCR_RTS; 894 uart_setreg(bas, REG_MCR, ns8250->mcr); 895 uart_barrier(bas); 896 uart_unlock(sc->sc_hwmtx); 897 return (0); 898 } 899 900 int 901 ns8250_bus_transmit(struct uart_softc *sc) 902 { 903 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 904 struct uart_bas *bas; 905 int i; 906 907 bas = &sc->sc_bas; 908 uart_lock(sc->sc_hwmtx); 909 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 910 ; 911 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 912 uart_barrier(bas); 913 for (i = 0; i < sc->sc_txdatasz; i++) { 914 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 915 uart_barrier(bas); 916 } 917 if (broken_txfifo) 918 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 919 else 920 sc->sc_txbusy = 1; 921 uart_unlock(sc->sc_hwmtx); 922 if (broken_txfifo) 923 uart_sched_softih(sc, SER_INT_TXIDLE); 924 return (0); 925 } 926 927 void 928 ns8250_bus_grab(struct uart_softc *sc) 929 { 930 struct uart_bas *bas = &sc->sc_bas; 931 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 932 u_char ier; 933 934 /* 935 * turn off all interrupts to enter polling mode. Leave the 936 * saved mask alone. We'll restore whatever it was in ungrab. 937 * All pending interupt signals are reset when IER is set to 0. 938 */ 939 uart_lock(sc->sc_hwmtx); 940 ier = uart_getreg(bas, REG_IER); 941 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 942 uart_barrier(bas); 943 uart_unlock(sc->sc_hwmtx); 944 } 945 946 void 947 ns8250_bus_ungrab(struct uart_softc *sc) 948 { 949 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 950 struct uart_bas *bas = &sc->sc_bas; 951 952 /* 953 * Restore previous interrupt mask 954 */ 955 uart_lock(sc->sc_hwmtx); 956 uart_setreg(bas, REG_IER, ns8250->ier); 957 uart_barrier(bas); 958 uart_unlock(sc->sc_hwmtx); 959 } 960