1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/cdefs.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/sysctl.h> 40 #include <machine/bus.h> 41 42 #ifdef FDT 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #endif 47 48 #include <dev/uart/uart.h> 49 #include <dev/uart/uart_cpu.h> 50 #ifdef FDT 51 #include <dev/uart/uart_cpu_fdt.h> 52 #endif 53 #include <dev/uart/uart_bus.h> 54 #include <dev/uart/uart_dev_ns8250.h> 55 #include <dev/uart/uart_ppstypes.h> 56 #ifdef DEV_ACPI 57 #include <dev/uart/uart_cpu_acpi.h> 58 #include <contrib/dev/acpica/include/acpi.h> 59 #endif 60 61 #include <dev/ic/ns16550.h> 62 63 #include "uart_if.h" 64 65 #define DEFAULT_RCLK 1843200 66 67 /* 68 * Set the default baudrate tolerance to 3.0%. 69 * 70 * Some embedded boards have odd reference clocks (eg 25MHz) 71 * and we need to handle higher variances in the target baud rate. 72 */ 73 #ifndef UART_DEV_TOLERANCE_PCT 74 #define UART_DEV_TOLERANCE_PCT 30 75 #endif /* UART_DEV_TOLERANCE_PCT */ 76 77 static int broken_txfifo = 0; 78 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 79 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 80 81 /* 82 * Clear pending interrupts. THRE is cleared by reading IIR. Data 83 * that may have been received gets lost here. 84 */ 85 static void 86 ns8250_clrint(struct uart_bas *bas) 87 { 88 uint8_t iir, lsr; 89 90 iir = uart_getreg(bas, REG_IIR); 91 while ((iir & IIR_NOPEND) == 0) { 92 iir &= IIR_IMASK; 93 if (iir == IIR_RLS) { 94 lsr = uart_getreg(bas, REG_LSR); 95 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 96 (void)uart_getreg(bas, REG_DATA); 97 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 98 (void)uart_getreg(bas, REG_DATA); 99 else if (iir == IIR_MLSC) 100 (void)uart_getreg(bas, REG_MSR); 101 uart_barrier(bas); 102 iir = uart_getreg(bas, REG_IIR); 103 } 104 } 105 106 static int 107 ns8250_delay(struct uart_bas *bas) 108 { 109 int divisor; 110 u_char lcr; 111 112 lcr = uart_getreg(bas, REG_LCR); 113 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 114 uart_barrier(bas); 115 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 116 uart_barrier(bas); 117 uart_setreg(bas, REG_LCR, lcr); 118 uart_barrier(bas); 119 120 /* 1/10th the time to transmit 1 character (estimate). */ 121 if (divisor <= 134) 122 return (16000000 * divisor / bas->rclk); 123 return (16000 * divisor / (bas->rclk / 1000)); 124 } 125 126 static int 127 ns8250_divisor(int rclk, int baudrate) 128 { 129 int actual_baud, divisor; 130 int error; 131 132 if (baudrate == 0) 133 return (0); 134 135 divisor = (rclk / (baudrate << 3) + 1) >> 1; 136 if (divisor == 0 || divisor >= 65536) 137 return (0); 138 actual_baud = rclk / (divisor << 4); 139 140 /* 10 times error in percent: */ 141 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 142 143 /* enforce maximum error tolerance: */ 144 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 145 return (0); 146 147 return (divisor); 148 } 149 150 static int 151 ns8250_drain(struct uart_bas *bas, int what) 152 { 153 int delay, limit; 154 155 delay = ns8250_delay(bas); 156 157 if (what & UART_DRAIN_TRANSMITTER) { 158 /* 159 * Pick an arbitrary high limit to avoid getting stuck in 160 * an infinite loop when the hardware is broken. Make the 161 * limit high enough to handle large FIFOs. 162 */ 163 limit = 10*1024; 164 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 165 DELAY(delay); 166 if (limit == 0) { 167 /* printf("ns8250: transmitter appears stuck... "); */ 168 return (EIO); 169 } 170 } 171 172 if (what & UART_DRAIN_RECEIVER) { 173 /* 174 * Pick an arbitrary high limit to avoid getting stuck in 175 * an infinite loop when the hardware is broken. Make the 176 * limit high enough to handle large FIFOs and integrated 177 * UARTs. The HP rx2600 for example has 3 UARTs on the 178 * management board that tend to get a lot of data send 179 * to it when the UART is first activated. Assume that we 180 * have finished draining if LSR_RXRDY is not asserted both 181 * prior to and after a DELAY; but as long as LSR_RXRDY is 182 * asserted, read (and discard) characters as quickly as 183 * possible. 184 */ 185 limit=10*4096; 186 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 187 do { 188 (void)uart_getreg(bas, REG_DATA); 189 uart_barrier(bas); 190 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 191 uart_barrier(bas); 192 DELAY(delay << 2); 193 } 194 if (limit == 0) { 195 /* printf("ns8250: receiver appears broken... "); */ 196 return (EIO); 197 } 198 } 199 200 return (0); 201 } 202 203 /* 204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 205 * drained. WARNING: this function clobbers the FIFO setting! 206 */ 207 static void 208 ns8250_flush(struct uart_bas *bas, int what) 209 { 210 uint8_t fcr; 211 uint8_t lsr; 212 int drain = 0; 213 214 fcr = FCR_ENABLE; 215 #ifdef CPU_XBURST 216 fcr |= FCR_UART_ON; 217 #endif 218 if (what & UART_FLUSH_TRANSMITTER) 219 fcr |= FCR_XMT_RST; 220 if (what & UART_FLUSH_RECEIVER) 221 fcr |= FCR_RCV_RST; 222 uart_setreg(bas, REG_FCR, fcr); 223 uart_barrier(bas); 224 225 /* 226 * Detect and work around emulated UARTs which don't implement the 227 * FCR register; on these systems we need to drain the FIFO since 228 * the flush we request doesn't happen. One such system is the 229 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 230 * https://github.com/rust-vmm/vm-superio/issues/83 231 */ 232 lsr = uart_getreg(bas, REG_LSR); 233 if (((lsr & LSR_TEMT) == 0) && (what & UART_FLUSH_TRANSMITTER)) 234 drain |= UART_DRAIN_TRANSMITTER; 235 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 236 drain |= UART_DRAIN_RECEIVER; 237 if (drain != 0) { 238 printf("ns8250: UART FCR is broken\n"); 239 ns8250_drain(bas, drain); 240 } 241 } 242 243 static int 244 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 245 int parity) 246 { 247 int divisor; 248 uint8_t lcr; 249 250 /* Don't change settings when running on Hyper-V */ 251 if (vm_guest == VM_GUEST_HV) 252 return (0); 253 254 lcr = 0; 255 if (databits >= 8) 256 lcr |= LCR_8BITS; 257 else if (databits == 7) 258 lcr |= LCR_7BITS; 259 else if (databits == 6) 260 lcr |= LCR_6BITS; 261 else 262 lcr |= LCR_5BITS; 263 if (stopbits > 1) 264 lcr |= LCR_STOPB; 265 lcr |= parity << 3; 266 267 /* Set baudrate. */ 268 if (baudrate > 0) { 269 divisor = ns8250_divisor(bas->rclk, baudrate); 270 if (divisor == 0) 271 return (EINVAL); 272 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 273 uart_barrier(bas); 274 uart_setreg(bas, REG_DLL, divisor & 0xff); 275 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 276 uart_barrier(bas); 277 } 278 279 /* Set LCR and clear DLAB. */ 280 uart_setreg(bas, REG_LCR, lcr); 281 uart_barrier(bas); 282 return (0); 283 } 284 285 /* 286 * Low-level UART interface. 287 */ 288 static int ns8250_probe(struct uart_bas *bas); 289 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 290 static void ns8250_term(struct uart_bas *bas); 291 static void ns8250_putc(struct uart_bas *bas, int); 292 static int ns8250_rxready(struct uart_bas *bas); 293 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 294 295 struct uart_ops uart_ns8250_ops = { 296 .probe = ns8250_probe, 297 .init = ns8250_init, 298 .term = ns8250_term, 299 .putc = ns8250_putc, 300 .rxready = ns8250_rxready, 301 .getc = ns8250_getc, 302 }; 303 304 static int 305 ns8250_probe(struct uart_bas *bas) 306 { 307 u_char val; 308 309 #ifdef CPU_XBURST 310 uart_setreg(bas, REG_FCR, FCR_UART_ON); 311 #endif 312 313 /* Check known 0 bits that don't depend on DLAB. */ 314 val = uart_getreg(bas, REG_IIR); 315 if (val & 0x30) 316 return (ENXIO); 317 /* 318 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 319 * chip, but otherwise doesn't seem to have a function. In 320 * other words, uart(4) works regardless. Ignore that bit so 321 * the probe succeeds. 322 */ 323 val = uart_getreg(bas, REG_MCR); 324 if (val & 0xa0) 325 return (ENXIO); 326 327 return (0); 328 } 329 330 static void 331 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 332 int parity) 333 { 334 u_char ier, val; 335 336 if (bas->rclk == 0) 337 bas->rclk = DEFAULT_RCLK; 338 ns8250_param(bas, baudrate, databits, stopbits, parity); 339 340 /* Disable all interrupt sources. */ 341 /* 342 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 343 * UARTs split the receive time-out interrupt bit out separately as 344 * 0x10. This gets handled by ier_mask and ier_rxbits below. 345 */ 346 ier = uart_getreg(bas, REG_IER) & 0xe0; 347 uart_setreg(bas, REG_IER, ier); 348 uart_barrier(bas); 349 350 /* Disable the FIFO (if present). */ 351 val = 0; 352 #ifdef CPU_XBURST 353 val |= FCR_UART_ON; 354 #endif 355 uart_setreg(bas, REG_FCR, val); 356 uart_barrier(bas); 357 358 /* Set RTS & DTR. */ 359 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 360 uart_barrier(bas); 361 362 ns8250_clrint(bas); 363 } 364 365 static void 366 ns8250_term(struct uart_bas *bas) 367 { 368 369 /* Clear RTS & DTR. */ 370 uart_setreg(bas, REG_MCR, MCR_IE); 371 uart_barrier(bas); 372 } 373 374 static void 375 ns8250_putc(struct uart_bas *bas, int c) 376 { 377 int limit; 378 379 if (vm_guest != VM_GUEST_HV) { 380 limit = 250000; 381 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 382 DELAY(4); 383 } 384 uart_setreg(bas, REG_DATA, c); 385 uart_barrier(bas); 386 } 387 388 static int 389 ns8250_rxready(struct uart_bas *bas) 390 { 391 392 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 393 } 394 395 static int 396 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 397 { 398 int c; 399 400 uart_lock(hwmtx); 401 402 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 403 uart_unlock(hwmtx); 404 DELAY(4); 405 uart_lock(hwmtx); 406 } 407 408 c = uart_getreg(bas, REG_DATA); 409 410 uart_unlock(hwmtx); 411 412 return (c); 413 } 414 415 static kobj_method_t ns8250_methods[] = { 416 KOBJMETHOD(uart_attach, ns8250_bus_attach), 417 KOBJMETHOD(uart_detach, ns8250_bus_detach), 418 KOBJMETHOD(uart_flush, ns8250_bus_flush), 419 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 420 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 421 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 422 KOBJMETHOD(uart_param, ns8250_bus_param), 423 KOBJMETHOD(uart_probe, ns8250_bus_probe), 424 KOBJMETHOD(uart_receive, ns8250_bus_receive), 425 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 426 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 427 KOBJMETHOD(uart_grab, ns8250_bus_grab), 428 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 429 { 0, 0 } 430 }; 431 432 struct uart_class uart_ns8250_class = { 433 "ns8250", 434 ns8250_methods, 435 sizeof(struct ns8250_softc), 436 .uc_ops = &uart_ns8250_ops, 437 .uc_range = 8, 438 .uc_rclk = DEFAULT_RCLK, 439 .uc_rshift = 0 440 }; 441 442 /* 443 * XXX -- refactor out ACPI and FDT ifdefs 444 */ 445 #ifdef DEV_ACPI 446 static struct acpi_uart_compat_data acpi_compat_data[] = { 447 {"AMD0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 448 {"AMDI0020", &uart_ns8250_class, 0, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 449 {"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 450 {"SCX0006", &uart_ns8250_class, 0, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 451 {"HISI0031", &uart_ns8250_class, 0, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 452 {"NXP0018", &uart_ns8250_class, 0, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 453 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, 0, "Standard PC COM port"}, 454 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, 0, "16550A-compatible COM port"}, 455 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 456 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 457 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 458 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 459 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 460 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 461 {NULL, NULL, 0, 0 , 0, 0, 0, NULL}, 462 }; 463 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 464 #endif 465 466 #ifdef FDT 467 static struct ofw_compat_data compat_data[] = { 468 {"ns16550", (uintptr_t)&uart_ns8250_class}, 469 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 470 {NULL, (uintptr_t)NULL}, 471 }; 472 UART_FDT_CLASS_AND_DEVICE(compat_data); 473 #endif 474 475 /* Use token-pasting to form SER_ and MSR_ named constants. */ 476 #define SER(sig) SER_##sig 477 #define SERD(sig) SER_D##sig 478 #define MSR(sig) MSR_##sig 479 #define MSRD(sig) MSR_D##sig 480 481 /* 482 * Detect signal changes using software delta detection. The previous state of 483 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 484 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 485 * new state of both the signal and the delta bits. 486 */ 487 #define SIGCHGSW(var, msr, sig) \ 488 if ((msr) & MSR(sig)) { \ 489 if ((var & SER(sig)) == 0) \ 490 var |= SERD(sig) | SER(sig); \ 491 } else { \ 492 if ((var & SER(sig)) != 0) \ 493 var = SERD(sig) | (var & ~SER(sig)); \ 494 } 495 496 /* 497 * Detect signal changes using the hardware msr delta bits. This is currently 498 * used only when PPS timing information is being captured using the "narrow 499 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 500 * by time the interrupt handler is invoked. The hardware will latch the fact 501 * that it changed in the delta bits. 502 */ 503 #define SIGCHGHW(var, msr, sig) \ 504 if ((msr) & MSRD(sig)) { \ 505 if (((msr) & MSR(sig)) != 0) \ 506 var |= SERD(sig) | SER(sig); \ 507 else \ 508 var = SERD(sig) | (var & ~SER(sig)); \ 509 } 510 511 int 512 ns8250_bus_attach(struct uart_softc *sc) 513 { 514 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 515 struct uart_bas *bas; 516 unsigned int ivar; 517 #ifdef FDT 518 phandle_t node; 519 pcell_t cell; 520 #endif 521 522 #ifdef FDT 523 /* Check whether uart has a broken txfifo. */ 524 node = ofw_bus_get_node(sc->sc_dev); 525 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 526 broken_txfifo = cell ? 1 : 0; 527 #endif 528 529 bas = &sc->sc_bas; 530 531 ns8250->busy_detect = bas->busy_detect; 532 ns8250->mcr = uart_getreg(bas, REG_MCR); 533 ns8250->fcr = FCR_ENABLE; 534 #ifdef CPU_XBURST 535 ns8250->fcr |= FCR_UART_ON; 536 #endif 537 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 538 &ivar)) { 539 if (UART_FLAGS_FCR_RX_LOW(ivar)) 540 ns8250->fcr |= FCR_RX_LOW; 541 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 542 ns8250->fcr |= FCR_RX_MEDL; 543 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 544 ns8250->fcr |= FCR_RX_HIGH; 545 else 546 ns8250->fcr |= FCR_RX_MEDH; 547 } else 548 ns8250->fcr |= FCR_RX_MEDH; 549 550 /* Get IER mask */ 551 ivar = 0xf0; 552 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 553 &ivar); 554 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 555 556 /* Get IER RX interrupt bits */ 557 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 558 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 559 &ivar); 560 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 561 562 uart_setreg(bas, REG_FCR, ns8250->fcr); 563 uart_barrier(bas); 564 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 565 566 if (ns8250->mcr & MCR_DTR) 567 sc->sc_hwsig |= SER_DTR; 568 if (ns8250->mcr & MCR_RTS) 569 sc->sc_hwsig |= SER_RTS; 570 ns8250_bus_getsig(sc); 571 572 ns8250_clrint(bas); 573 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 574 ns8250->ier |= ns8250->ier_rxbits; 575 uart_setreg(bas, REG_IER, ns8250->ier); 576 uart_barrier(bas); 577 578 /* 579 * Timing of the H/W access was changed with r253161 of uart_core.c 580 * It has been observed that an ITE IT8513E would signal a break 581 * condition with pretty much every character it received, unless 582 * it had enough time to settle between ns8250_bus_attach() and 583 * ns8250_bus_ipend() -- which it accidentally had before r253161. 584 * It's not understood why the UART chip behaves this way and it 585 * could very well be that the DELAY make the H/W work in the same 586 * accidental manner as before. More analysis is warranted, but 587 * at least now we fixed a known regression. 588 */ 589 DELAY(200); 590 return (0); 591 } 592 593 int 594 ns8250_bus_detach(struct uart_softc *sc) 595 { 596 struct ns8250_softc *ns8250; 597 struct uart_bas *bas; 598 u_char ier; 599 600 ns8250 = (struct ns8250_softc *)sc; 601 bas = &sc->sc_bas; 602 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 603 uart_setreg(bas, REG_IER, ier); 604 uart_barrier(bas); 605 ns8250_clrint(bas); 606 return (0); 607 } 608 609 int 610 ns8250_bus_flush(struct uart_softc *sc, int what) 611 { 612 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 613 struct uart_bas *bas; 614 int error; 615 616 bas = &sc->sc_bas; 617 uart_lock(sc->sc_hwmtx); 618 if (sc->sc_rxfifosz > 1) { 619 ns8250_flush(bas, what); 620 uart_setreg(bas, REG_FCR, ns8250->fcr); 621 uart_barrier(bas); 622 error = 0; 623 } else 624 error = ns8250_drain(bas, what); 625 uart_unlock(sc->sc_hwmtx); 626 return (error); 627 } 628 629 int 630 ns8250_bus_getsig(struct uart_softc *sc) 631 { 632 uint32_t old, sig; 633 uint8_t msr; 634 635 /* 636 * The delta bits are reputed to be broken on some hardware, so use 637 * software delta detection by default. Use the hardware delta bits 638 * when capturing PPS pulses which are too narrow for software detection 639 * to see the edges. Hardware delta for RI doesn't work like the 640 * others, so always use software for it. Other threads may be changing 641 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 642 * update without other changes happening. Note that the SIGCHGxx() 643 * macros carefully preserve the delta bits when we have to loop several 644 * times and a signal transitions between iterations. 645 */ 646 do { 647 old = sc->sc_hwsig; 648 sig = old; 649 uart_lock(sc->sc_hwmtx); 650 msr = uart_getreg(&sc->sc_bas, REG_MSR); 651 uart_unlock(sc->sc_hwmtx); 652 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 653 SIGCHGHW(sig, msr, DSR); 654 SIGCHGHW(sig, msr, CTS); 655 SIGCHGHW(sig, msr, DCD); 656 } else { 657 SIGCHGSW(sig, msr, DSR); 658 SIGCHGSW(sig, msr, CTS); 659 SIGCHGSW(sig, msr, DCD); 660 } 661 SIGCHGSW(sig, msr, RI); 662 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 663 return (sig); 664 } 665 666 int 667 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 668 { 669 struct uart_bas *bas; 670 int baudrate, divisor, error; 671 uint8_t efr, lcr; 672 673 bas = &sc->sc_bas; 674 error = 0; 675 uart_lock(sc->sc_hwmtx); 676 switch (request) { 677 case UART_IOCTL_BREAK: 678 lcr = uart_getreg(bas, REG_LCR); 679 if (data) 680 lcr |= LCR_SBREAK; 681 else 682 lcr &= ~LCR_SBREAK; 683 uart_setreg(bas, REG_LCR, lcr); 684 uart_barrier(bas); 685 break; 686 case UART_IOCTL_IFLOW: 687 lcr = uart_getreg(bas, REG_LCR); 688 uart_barrier(bas); 689 uart_setreg(bas, REG_LCR, 0xbf); 690 uart_barrier(bas); 691 efr = uart_getreg(bas, REG_EFR); 692 if (data) 693 efr |= EFR_RTS; 694 else 695 efr &= ~EFR_RTS; 696 uart_setreg(bas, REG_EFR, efr); 697 uart_barrier(bas); 698 uart_setreg(bas, REG_LCR, lcr); 699 uart_barrier(bas); 700 break; 701 case UART_IOCTL_OFLOW: 702 lcr = uart_getreg(bas, REG_LCR); 703 uart_barrier(bas); 704 uart_setreg(bas, REG_LCR, 0xbf); 705 uart_barrier(bas); 706 efr = uart_getreg(bas, REG_EFR); 707 if (data) 708 efr |= EFR_CTS; 709 else 710 efr &= ~EFR_CTS; 711 uart_setreg(bas, REG_EFR, efr); 712 uart_barrier(bas); 713 uart_setreg(bas, REG_LCR, lcr); 714 uart_barrier(bas); 715 break; 716 case UART_IOCTL_BAUD: 717 lcr = uart_getreg(bas, REG_LCR); 718 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 719 uart_barrier(bas); 720 divisor = uart_getreg(bas, REG_DLL) | 721 (uart_getreg(bas, REG_DLH) << 8); 722 uart_barrier(bas); 723 uart_setreg(bas, REG_LCR, lcr); 724 uart_barrier(bas); 725 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 726 if (baudrate > 0) 727 *(int*)data = baudrate; 728 else 729 error = ENXIO; 730 break; 731 default: 732 error = EINVAL; 733 break; 734 } 735 uart_unlock(sc->sc_hwmtx); 736 return (error); 737 } 738 739 int 740 ns8250_bus_ipend(struct uart_softc *sc) 741 { 742 struct uart_bas *bas; 743 struct ns8250_softc *ns8250; 744 int ipend; 745 uint8_t iir, lsr; 746 747 ns8250 = (struct ns8250_softc *)sc; 748 bas = &sc->sc_bas; 749 uart_lock(sc->sc_hwmtx); 750 iir = uart_getreg(bas, REG_IIR); 751 752 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 753 (void)uart_getreg(bas, DW_REG_USR); 754 uart_unlock(sc->sc_hwmtx); 755 return (0); 756 } 757 if (iir & IIR_NOPEND) { 758 uart_unlock(sc->sc_hwmtx); 759 return (0); 760 } 761 ipend = 0; 762 if (iir & IIR_RXRDY) { 763 lsr = uart_getreg(bas, REG_LSR); 764 if (lsr & LSR_OE) 765 ipend |= SER_INT_OVERRUN; 766 if (lsr & LSR_BI) 767 ipend |= SER_INT_BREAK; 768 if (lsr & LSR_RXRDY) 769 ipend |= SER_INT_RXREADY; 770 } else { 771 if (iir & IIR_TXRDY) { 772 ipend |= SER_INT_TXIDLE; 773 ns8250->ier &= ~IER_ETXRDY; 774 uart_setreg(bas, REG_IER, ns8250->ier); 775 uart_barrier(bas); 776 } else 777 ipend |= SER_INT_SIGCHG; 778 } 779 if (ipend == 0) 780 ns8250_clrint(bas); 781 uart_unlock(sc->sc_hwmtx); 782 return (ipend); 783 } 784 785 int 786 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 787 int stopbits, int parity) 788 { 789 struct ns8250_softc *ns8250; 790 struct uart_bas *bas; 791 int error, limit; 792 793 ns8250 = (struct ns8250_softc*)sc; 794 bas = &sc->sc_bas; 795 uart_lock(sc->sc_hwmtx); 796 /* 797 * When using DW UART with BUSY detection it is necessary to wait 798 * until all serial transfers are finished before manipulating the 799 * line control. LCR will not be affected when UART is busy. 800 */ 801 if (ns8250->busy_detect != 0) { 802 /* 803 * Pick an arbitrary high limit to avoid getting stuck in 804 * an infinite loop in case when the hardware is broken. 805 */ 806 limit = 10 * 1024; 807 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 808 --limit) 809 DELAY(4); 810 811 if (limit <= 0) { 812 /* UART appears to be stuck */ 813 uart_unlock(sc->sc_hwmtx); 814 return (EIO); 815 } 816 } 817 818 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 819 uart_unlock(sc->sc_hwmtx); 820 return (error); 821 } 822 823 int 824 ns8250_bus_probe(struct uart_softc *sc) 825 { 826 struct uart_bas *bas; 827 int count, delay, error, limit; 828 uint8_t lsr, mcr, ier; 829 uint8_t val; 830 831 bas = &sc->sc_bas; 832 833 error = ns8250_probe(bas); 834 if (error) 835 return (error); 836 837 mcr = MCR_IE; 838 if (sc->sc_sysdev == NULL) { 839 /* By using ns8250_init() we also set DTR and RTS. */ 840 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 841 } else 842 mcr |= MCR_DTR | MCR_RTS; 843 844 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 845 if (error) 846 return (error); 847 848 /* 849 * Set loopback mode. This avoids having garbage on the wire and 850 * also allows us send and receive data. We set DTR and RTS to 851 * avoid the possibility that automatic flow-control prevents 852 * any data from being sent. 853 */ 854 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 855 uart_barrier(bas); 856 857 /* 858 * Enable FIFOs. And check that the UART has them. If not, we're 859 * done. Since this is the first time we enable the FIFOs, we reset 860 * them. 861 */ 862 val = FCR_ENABLE; 863 #ifdef CPU_XBURST 864 val |= FCR_UART_ON; 865 #endif 866 uart_setreg(bas, REG_FCR, val); 867 uart_barrier(bas); 868 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 869 /* 870 * NS16450 or INS8250. We don't bother to differentiate 871 * between them. They're too old to be interesting. 872 */ 873 uart_setreg(bas, REG_MCR, mcr); 874 uart_barrier(bas); 875 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 876 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 877 return (0); 878 } 879 880 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 881 #ifdef CPU_XBURST 882 val |= FCR_UART_ON; 883 #endif 884 uart_setreg(bas, REG_FCR, val); 885 uart_barrier(bas); 886 887 count = 0; 888 delay = ns8250_delay(bas); 889 890 /* We have FIFOs. Drain the transmitter and receiver. */ 891 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 892 if (error) { 893 uart_setreg(bas, REG_MCR, mcr); 894 val = 0; 895 #ifdef CPU_XBURST 896 val |= FCR_UART_ON; 897 #endif 898 uart_setreg(bas, REG_FCR, val); 899 uart_barrier(bas); 900 goto describe; 901 } 902 903 /* 904 * We should have a sufficiently clean "pipe" to determine the 905 * size of the FIFOs. We send as much characters as is reasonable 906 * and wait for the overflow bit in the LSR register to be 907 * asserted, counting the characters as we send them. Based on 908 * that count we know the FIFO size. 909 */ 910 do { 911 uart_setreg(bas, REG_DATA, 0); 912 uart_barrier(bas); 913 count++; 914 915 limit = 30; 916 lsr = 0; 917 /* 918 * LSR bits are cleared upon read, so we must accumulate 919 * them to be able to test LSR_OE below. 920 */ 921 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 922 --limit) 923 DELAY(delay); 924 if (limit == 0) { 925 /* See the comment in ns8250_init(). */ 926 ier = uart_getreg(bas, REG_IER) & 0xe0; 927 uart_setreg(bas, REG_IER, ier); 928 uart_setreg(bas, REG_MCR, mcr); 929 val = 0; 930 #ifdef CPU_XBURST 931 val |= FCR_UART_ON; 932 #endif 933 uart_setreg(bas, REG_FCR, val); 934 uart_barrier(bas); 935 count = 0; 936 goto describe; 937 } 938 } while ((lsr & LSR_OE) == 0 && count < 260); 939 count--; 940 941 uart_setreg(bas, REG_MCR, mcr); 942 943 /* Reset FIFOs. */ 944 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 945 946 describe: 947 if (count >= 14 && count <= 16) { 948 sc->sc_rxfifosz = 16; 949 device_set_desc(sc->sc_dev, "16550 or compatible"); 950 } else if (count >= 28 && count <= 32) { 951 sc->sc_rxfifosz = 32; 952 device_set_desc(sc->sc_dev, "16650 or compatible"); 953 } else if (count >= 56 && count <= 64) { 954 sc->sc_rxfifosz = 64; 955 device_set_desc(sc->sc_dev, "16750 or compatible"); 956 } else if (count >= 112 && count <= 128) { 957 sc->sc_rxfifosz = 128; 958 device_set_desc(sc->sc_dev, "16950 or compatible"); 959 } else if (count >= 224 && count <= 256) { 960 sc->sc_rxfifosz = 256; 961 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 962 } else { 963 sc->sc_rxfifosz = 16; 964 device_set_desc(sc->sc_dev, 965 "Non-standard ns8250 class UART with FIFOs"); 966 } 967 968 /* 969 * Force the Tx FIFO size to 16 bytes for now. We don't program the 970 * Tx trigger. Also, we assume that all data has been sent when the 971 * interrupt happens. 972 */ 973 sc->sc_txfifosz = 16; 974 975 #if 0 976 /* 977 * XXX there are some issues related to hardware flow control and 978 * it's likely that uart(4) is the cause. This basically needs more 979 * investigation, but we avoid using for hardware flow control 980 * until then. 981 */ 982 /* 16650s or higher have automatic flow control. */ 983 if (sc->sc_rxfifosz > 16) { 984 sc->sc_hwiflow = 1; 985 sc->sc_hwoflow = 1; 986 } 987 #endif 988 989 return (0); 990 } 991 992 int 993 ns8250_bus_receive(struct uart_softc *sc) 994 { 995 struct uart_bas *bas; 996 int xc; 997 uint8_t lsr; 998 999 bas = &sc->sc_bas; 1000 uart_lock(sc->sc_hwmtx); 1001 lsr = uart_getreg(bas, REG_LSR); 1002 while (lsr & LSR_RXRDY) { 1003 if (uart_rx_full(sc)) { 1004 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1005 break; 1006 } 1007 xc = uart_getreg(bas, REG_DATA); 1008 if (lsr & LSR_FE) 1009 xc |= UART_STAT_FRAMERR; 1010 if (lsr & LSR_PE) 1011 xc |= UART_STAT_PARERR; 1012 uart_rx_put(sc, xc); 1013 lsr = uart_getreg(bas, REG_LSR); 1014 } 1015 /* Discard everything left in the Rx FIFO. */ 1016 while (lsr & LSR_RXRDY) { 1017 (void)uart_getreg(bas, REG_DATA); 1018 uart_barrier(bas); 1019 lsr = uart_getreg(bas, REG_LSR); 1020 } 1021 uart_unlock(sc->sc_hwmtx); 1022 return (0); 1023 } 1024 1025 int 1026 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1027 { 1028 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1029 struct uart_bas *bas; 1030 uint32_t new, old; 1031 1032 bas = &sc->sc_bas; 1033 do { 1034 old = sc->sc_hwsig; 1035 new = old; 1036 if (sig & SER_DDTR) { 1037 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1038 } 1039 if (sig & SER_DRTS) { 1040 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1041 } 1042 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1043 uart_lock(sc->sc_hwmtx); 1044 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1045 if (new & SER_DTR) 1046 ns8250->mcr |= MCR_DTR; 1047 if (new & SER_RTS) 1048 ns8250->mcr |= MCR_RTS; 1049 uart_setreg(bas, REG_MCR, ns8250->mcr); 1050 uart_barrier(bas); 1051 uart_unlock(sc->sc_hwmtx); 1052 return (0); 1053 } 1054 1055 int 1056 ns8250_bus_transmit(struct uart_softc *sc) 1057 { 1058 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1059 struct uart_bas *bas; 1060 int i; 1061 1062 bas = &sc->sc_bas; 1063 uart_lock(sc->sc_hwmtx); 1064 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1065 DELAY(4); 1066 for (i = 0; i < sc->sc_txdatasz; i++) { 1067 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1068 uart_barrier(bas); 1069 } 1070 if (!broken_txfifo) 1071 ns8250->ier |= IER_ETXRDY; 1072 uart_setreg(bas, REG_IER, ns8250->ier); 1073 uart_barrier(bas); 1074 if (broken_txfifo) 1075 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1076 else 1077 sc->sc_txbusy = 1; 1078 uart_unlock(sc->sc_hwmtx); 1079 if (broken_txfifo) 1080 uart_sched_softih(sc, SER_INT_TXIDLE); 1081 return (0); 1082 } 1083 1084 void 1085 ns8250_bus_grab(struct uart_softc *sc) 1086 { 1087 struct uart_bas *bas = &sc->sc_bas; 1088 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1089 u_char ier; 1090 1091 /* 1092 * turn off all interrupts to enter polling mode. Leave the 1093 * saved mask alone. We'll restore whatever it was in ungrab. 1094 * All pending interrupt signals are reset when IER is set to 0. 1095 */ 1096 uart_lock(sc->sc_hwmtx); 1097 ier = uart_getreg(bas, REG_IER); 1098 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1099 uart_barrier(bas); 1100 uart_unlock(sc->sc_hwmtx); 1101 } 1102 1103 void 1104 ns8250_bus_ungrab(struct uart_softc *sc) 1105 { 1106 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1107 struct uart_bas *bas = &sc->sc_bas; 1108 1109 /* 1110 * Restore previous interrupt mask 1111 */ 1112 uart_lock(sc->sc_hwmtx); 1113 uart_setreg(bas, REG_IER, ns8250->ier); 1114 uart_barrier(bas); 1115 uart_unlock(sc->sc_hwmtx); 1116 } 1117