1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/ns16550.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 1843200 45 46 /* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50 static void 51 ns8250_clrint(struct uart_bas *bas) 52 { 53 uint8_t iir; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) 59 (void)uart_getreg(bas, REG_LSR); 60 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 61 (void)uart_getreg(bas, REG_DATA); 62 else if (iir == IIR_MLSC) 63 (void)uart_getreg(bas, REG_MSR); 64 uart_barrier(bas); 65 iir = uart_getreg(bas, REG_IIR); 66 } 67 } 68 69 static int 70 ns8250_delay(struct uart_bas *bas) 71 { 72 int divisor; 73 u_char lcr; 74 75 lcr = uart_getreg(bas, REG_LCR); 76 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 77 uart_barrier(bas); 78 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 79 uart_barrier(bas); 80 uart_setreg(bas, REG_LCR, lcr); 81 uart_barrier(bas); 82 83 /* 1/10th the time to transmit 1 character (estimate). */ 84 if (divisor <= 134) 85 return (16000000 * divisor / bas->rclk); 86 return (16000 * divisor / (bas->rclk / 1000)); 87 } 88 89 static int 90 ns8250_divisor(int rclk, int baudrate) 91 { 92 int actual_baud, divisor; 93 int error; 94 95 if (baudrate == 0) 96 return (0); 97 98 divisor = (rclk / (baudrate << 3) + 1) >> 1; 99 if (divisor == 0 || divisor >= 65536) 100 return (0); 101 actual_baud = rclk / (divisor << 4); 102 103 /* 10 times error in percent: */ 104 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 105 106 /* 3.0% maximum error tolerance: */ 107 if (error < -30 || error > 30) 108 return (0); 109 110 return (divisor); 111 } 112 113 static int 114 ns8250_drain(struct uart_bas *bas, int what) 115 { 116 int delay, limit; 117 118 delay = ns8250_delay(bas); 119 120 if (what & UART_DRAIN_TRANSMITTER) { 121 /* 122 * Pick an arbitrary high limit to avoid getting stuck in 123 * an infinite loop when the hardware is broken. Make the 124 * limit high enough to handle large FIFOs. 125 */ 126 limit = 10*1024; 127 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 128 DELAY(delay); 129 if (limit == 0) { 130 /* printf("ns8250: transmitter appears stuck... "); */ 131 return (EIO); 132 } 133 } 134 135 if (what & UART_DRAIN_RECEIVER) { 136 /* 137 * Pick an arbitrary high limit to avoid getting stuck in 138 * an infinite loop when the hardware is broken. Make the 139 * limit high enough to handle large FIFOs and integrated 140 * UARTs. The HP rx2600 for example has 3 UARTs on the 141 * management board that tend to get a lot of data send 142 * to it when the UART is first activated. 143 */ 144 limit=10*4096; 145 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 146 (void)uart_getreg(bas, REG_DATA); 147 uart_barrier(bas); 148 DELAY(delay << 2); 149 } 150 if (limit == 0) { 151 /* printf("ns8250: receiver appears broken... "); */ 152 return (EIO); 153 } 154 } 155 156 return (0); 157 } 158 159 /* 160 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 161 * drained. WARNING: this function clobbers the FIFO setting! 162 */ 163 static void 164 ns8250_flush(struct uart_bas *bas, int what) 165 { 166 uint8_t fcr; 167 168 fcr = FCR_ENABLE; 169 if (what & UART_FLUSH_TRANSMITTER) 170 fcr |= FCR_XMT_RST; 171 if (what & UART_FLUSH_RECEIVER) 172 fcr |= FCR_RCV_RST; 173 uart_setreg(bas, REG_FCR, fcr); 174 uart_barrier(bas); 175 } 176 177 static int 178 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 179 int parity) 180 { 181 int divisor; 182 uint8_t lcr; 183 184 lcr = 0; 185 if (databits >= 8) 186 lcr |= LCR_8BITS; 187 else if (databits == 7) 188 lcr |= LCR_7BITS; 189 else if (databits == 6) 190 lcr |= LCR_6BITS; 191 else 192 lcr |= LCR_5BITS; 193 if (stopbits > 1) 194 lcr |= LCR_STOPB; 195 lcr |= parity << 3; 196 197 /* Set baudrate. */ 198 if (baudrate > 0) { 199 divisor = ns8250_divisor(bas->rclk, baudrate); 200 if (divisor == 0) 201 return (EINVAL); 202 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 203 uart_barrier(bas); 204 uart_setreg(bas, REG_DLL, divisor & 0xff); 205 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 206 uart_barrier(bas); 207 } 208 209 /* Set LCR and clear DLAB. */ 210 uart_setreg(bas, REG_LCR, lcr); 211 uart_barrier(bas); 212 return (0); 213 } 214 215 /* 216 * Low-level UART interface. 217 */ 218 static int ns8250_probe(struct uart_bas *bas); 219 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 220 static void ns8250_term(struct uart_bas *bas); 221 static void ns8250_putc(struct uart_bas *bas, int); 222 static int ns8250_rxready(struct uart_bas *bas); 223 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 224 225 static struct uart_ops uart_ns8250_ops = { 226 .probe = ns8250_probe, 227 .init = ns8250_init, 228 .term = ns8250_term, 229 .putc = ns8250_putc, 230 .rxready = ns8250_rxready, 231 .getc = ns8250_getc, 232 }; 233 234 static int 235 ns8250_probe(struct uart_bas *bas) 236 { 237 u_char val; 238 239 /* Check known 0 bits that don't depend on DLAB. */ 240 val = uart_getreg(bas, REG_IIR); 241 if (val & 0x30) 242 return (ENXIO); 243 val = uart_getreg(bas, REG_MCR); 244 if (val & 0xe0) 245 return (ENXIO); 246 247 return (0); 248 } 249 250 static void 251 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 252 int parity) 253 { 254 u_char ier; 255 256 if (bas->rclk == 0) 257 bas->rclk = DEFAULT_RCLK; 258 ns8250_param(bas, baudrate, databits, stopbits, parity); 259 260 /* Disable all interrupt sources. */ 261 ier = uart_getreg(bas, REG_IER) & 0xf0; 262 uart_setreg(bas, REG_IER, ier); 263 uart_barrier(bas); 264 265 /* Disable the FIFO (if present). */ 266 uart_setreg(bas, REG_FCR, 0); 267 uart_barrier(bas); 268 269 /* Set RTS & DTR. */ 270 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 271 uart_barrier(bas); 272 273 ns8250_clrint(bas); 274 } 275 276 static void 277 ns8250_term(struct uart_bas *bas) 278 { 279 280 /* Clear RTS & DTR. */ 281 uart_setreg(bas, REG_MCR, MCR_IE); 282 uart_barrier(bas); 283 } 284 285 static void 286 ns8250_putc(struct uart_bas *bas, int c) 287 { 288 int limit; 289 290 limit = 250000; 291 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 292 DELAY(4); 293 uart_setreg(bas, REG_DATA, c); 294 uart_barrier(bas); 295 limit = 250000; 296 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 297 DELAY(4); 298 } 299 300 static int 301 ns8250_rxready(struct uart_bas *bas) 302 { 303 304 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 305 } 306 307 static int 308 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 309 { 310 int c; 311 312 uart_lock(hwmtx); 313 314 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 315 uart_unlock(hwmtx); 316 DELAY(4); 317 uart_lock(hwmtx); 318 } 319 320 c = uart_getreg(bas, REG_DATA); 321 322 uart_unlock(hwmtx); 323 324 return (c); 325 } 326 327 /* 328 * High-level UART interface. 329 */ 330 struct ns8250_softc { 331 struct uart_softc base; 332 uint8_t fcr; 333 uint8_t ier; 334 uint8_t mcr; 335 }; 336 337 static int ns8250_bus_attach(struct uart_softc *); 338 static int ns8250_bus_detach(struct uart_softc *); 339 static int ns8250_bus_flush(struct uart_softc *, int); 340 static int ns8250_bus_getsig(struct uart_softc *); 341 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 342 static int ns8250_bus_ipend(struct uart_softc *); 343 static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 344 static int ns8250_bus_probe(struct uart_softc *); 345 static int ns8250_bus_receive(struct uart_softc *); 346 static int ns8250_bus_setsig(struct uart_softc *, int); 347 static int ns8250_bus_transmit(struct uart_softc *); 348 349 static kobj_method_t ns8250_methods[] = { 350 KOBJMETHOD(uart_attach, ns8250_bus_attach), 351 KOBJMETHOD(uart_detach, ns8250_bus_detach), 352 KOBJMETHOD(uart_flush, ns8250_bus_flush), 353 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 354 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 355 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 356 KOBJMETHOD(uart_param, ns8250_bus_param), 357 KOBJMETHOD(uart_probe, ns8250_bus_probe), 358 KOBJMETHOD(uart_receive, ns8250_bus_receive), 359 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 360 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 361 { 0, 0 } 362 }; 363 364 struct uart_class uart_ns8250_class = { 365 "ns8250", 366 ns8250_methods, 367 sizeof(struct ns8250_softc), 368 .uc_ops = &uart_ns8250_ops, 369 .uc_range = 8, 370 .uc_rclk = DEFAULT_RCLK 371 }; 372 373 #define SIGCHG(c, i, s, d) \ 374 if (c) { \ 375 i |= (i & s) ? s : s | d; \ 376 } else { \ 377 i = (i & s) ? (i & ~s) | d : i; \ 378 } 379 380 static int 381 ns8250_bus_attach(struct uart_softc *sc) 382 { 383 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 384 struct uart_bas *bas; 385 386 bas = &sc->sc_bas; 387 388 ns8250->mcr = uart_getreg(bas, REG_MCR); 389 ns8250->fcr = FCR_ENABLE | FCR_RX_MEDH; 390 uart_setreg(bas, REG_FCR, ns8250->fcr); 391 uart_barrier(bas); 392 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 393 394 if (ns8250->mcr & MCR_DTR) 395 sc->sc_hwsig |= SER_DTR; 396 if (ns8250->mcr & MCR_RTS) 397 sc->sc_hwsig |= SER_RTS; 398 ns8250_bus_getsig(sc); 399 400 ns8250_clrint(bas); 401 ns8250->ier = uart_getreg(bas, REG_IER) & 0xf0; 402 ns8250->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; 403 uart_setreg(bas, REG_IER, ns8250->ier); 404 uart_barrier(bas); 405 return (0); 406 } 407 408 static int 409 ns8250_bus_detach(struct uart_softc *sc) 410 { 411 struct uart_bas *bas; 412 u_char ier; 413 414 bas = &sc->sc_bas; 415 ier = uart_getreg(bas, REG_IER) & 0xf0; 416 uart_setreg(bas, REG_IER, ier); 417 uart_barrier(bas); 418 ns8250_clrint(bas); 419 return (0); 420 } 421 422 static int 423 ns8250_bus_flush(struct uart_softc *sc, int what) 424 { 425 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 426 struct uart_bas *bas; 427 int error; 428 429 bas = &sc->sc_bas; 430 uart_lock(sc->sc_hwmtx); 431 if (sc->sc_rxfifosz > 1) { 432 ns8250_flush(bas, what); 433 uart_setreg(bas, REG_FCR, ns8250->fcr); 434 uart_barrier(bas); 435 error = 0; 436 } else 437 error = ns8250_drain(bas, what); 438 uart_unlock(sc->sc_hwmtx); 439 return (error); 440 } 441 442 static int 443 ns8250_bus_getsig(struct uart_softc *sc) 444 { 445 uint32_t new, old, sig; 446 uint8_t msr; 447 448 do { 449 old = sc->sc_hwsig; 450 sig = old; 451 uart_lock(sc->sc_hwmtx); 452 msr = uart_getreg(&sc->sc_bas, REG_MSR); 453 uart_unlock(sc->sc_hwmtx); 454 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 455 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 456 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 457 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 458 new = sig & ~SER_MASK_DELTA; 459 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 460 return (sig); 461 } 462 463 static int 464 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 465 { 466 struct uart_bas *bas; 467 int baudrate, divisor, error; 468 uint8_t efr, lcr; 469 470 bas = &sc->sc_bas; 471 error = 0; 472 uart_lock(sc->sc_hwmtx); 473 switch (request) { 474 case UART_IOCTL_BREAK: 475 lcr = uart_getreg(bas, REG_LCR); 476 if (data) 477 lcr |= LCR_SBREAK; 478 else 479 lcr &= ~LCR_SBREAK; 480 uart_setreg(bas, REG_LCR, lcr); 481 uart_barrier(bas); 482 break; 483 case UART_IOCTL_IFLOW: 484 lcr = uart_getreg(bas, REG_LCR); 485 uart_barrier(bas); 486 uart_setreg(bas, REG_LCR, 0xbf); 487 uart_barrier(bas); 488 efr = uart_getreg(bas, REG_EFR); 489 if (data) 490 efr |= EFR_RTS; 491 else 492 efr &= ~EFR_RTS; 493 uart_setreg(bas, REG_EFR, efr); 494 uart_barrier(bas); 495 uart_setreg(bas, REG_LCR, lcr); 496 uart_barrier(bas); 497 break; 498 case UART_IOCTL_OFLOW: 499 lcr = uart_getreg(bas, REG_LCR); 500 uart_barrier(bas); 501 uart_setreg(bas, REG_LCR, 0xbf); 502 uart_barrier(bas); 503 efr = uart_getreg(bas, REG_EFR); 504 if (data) 505 efr |= EFR_CTS; 506 else 507 efr &= ~EFR_CTS; 508 uart_setreg(bas, REG_EFR, efr); 509 uart_barrier(bas); 510 uart_setreg(bas, REG_LCR, lcr); 511 uart_barrier(bas); 512 break; 513 case UART_IOCTL_BAUD: 514 lcr = uart_getreg(bas, REG_LCR); 515 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 516 uart_barrier(bas); 517 divisor = uart_getreg(bas, REG_DLL) | 518 (uart_getreg(bas, REG_DLH) << 8); 519 uart_barrier(bas); 520 uart_setreg(bas, REG_LCR, lcr); 521 uart_barrier(bas); 522 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 523 if (baudrate > 0) 524 *(int*)data = baudrate; 525 else 526 error = ENXIO; 527 break; 528 default: 529 error = EINVAL; 530 break; 531 } 532 uart_unlock(sc->sc_hwmtx); 533 return (error); 534 } 535 536 static int 537 ns8250_bus_ipend(struct uart_softc *sc) 538 { 539 struct uart_bas *bas; 540 int ipend; 541 uint8_t iir, lsr; 542 543 bas = &sc->sc_bas; 544 uart_lock(sc->sc_hwmtx); 545 iir = uart_getreg(bas, REG_IIR); 546 if (iir & IIR_NOPEND) { 547 uart_unlock(sc->sc_hwmtx); 548 return (0); 549 } 550 ipend = 0; 551 if (iir & IIR_RXRDY) { 552 lsr = uart_getreg(bas, REG_LSR); 553 uart_unlock(sc->sc_hwmtx); 554 if (lsr & LSR_OE) 555 ipend |= SER_INT_OVERRUN; 556 if (lsr & LSR_BI) 557 ipend |= SER_INT_BREAK; 558 if (lsr & LSR_RXRDY) 559 ipend |= SER_INT_RXREADY; 560 } else { 561 uart_unlock(sc->sc_hwmtx); 562 if (iir & IIR_TXRDY) 563 ipend |= SER_INT_TXIDLE; 564 else 565 ipend |= SER_INT_SIGCHG; 566 } 567 return ((sc->sc_leaving) ? 0 : ipend); 568 } 569 570 static int 571 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 572 int stopbits, int parity) 573 { 574 struct uart_bas *bas; 575 int error; 576 577 bas = &sc->sc_bas; 578 uart_lock(sc->sc_hwmtx); 579 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 580 uart_unlock(sc->sc_hwmtx); 581 return (error); 582 } 583 584 static int 585 ns8250_bus_probe(struct uart_softc *sc) 586 { 587 struct uart_bas *bas; 588 int count, delay, error, limit; 589 uint8_t lsr, mcr, ier; 590 591 bas = &sc->sc_bas; 592 593 error = ns8250_probe(bas); 594 if (error) 595 return (error); 596 597 mcr = MCR_IE; 598 if (sc->sc_sysdev == NULL) { 599 /* By using ns8250_init() we also set DTR and RTS. */ 600 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 601 } else 602 mcr |= MCR_DTR | MCR_RTS; 603 604 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 605 if (error) 606 return (error); 607 608 /* 609 * Set loopback mode. This avoids having garbage on the wire and 610 * also allows us send and receive data. We set DTR and RTS to 611 * avoid the possibility that automatic flow-control prevents 612 * any data from being sent. 613 */ 614 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 615 uart_barrier(bas); 616 617 /* 618 * Enable FIFOs. And check that the UART has them. If not, we're 619 * done. Since this is the first time we enable the FIFOs, we reset 620 * them. 621 */ 622 uart_setreg(bas, REG_FCR, FCR_ENABLE); 623 uart_barrier(bas); 624 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 625 /* 626 * NS16450 or INS8250. We don't bother to differentiate 627 * between them. They're too old to be interesting. 628 */ 629 uart_setreg(bas, REG_MCR, mcr); 630 uart_barrier(bas); 631 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 632 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 633 return (0); 634 } 635 636 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 637 uart_barrier(bas); 638 639 count = 0; 640 delay = ns8250_delay(bas); 641 642 /* We have FIFOs. Drain the transmitter and receiver. */ 643 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 644 if (error) { 645 uart_setreg(bas, REG_MCR, mcr); 646 uart_setreg(bas, REG_FCR, 0); 647 uart_barrier(bas); 648 goto describe; 649 } 650 651 /* 652 * We should have a sufficiently clean "pipe" to determine the 653 * size of the FIFOs. We send as much characters as is reasonable 654 * and wait for the the overflow bit in the LSR register to be 655 * asserted, counting the characters as we send them. Based on 656 * that count we know the FIFO size. 657 */ 658 do { 659 uart_setreg(bas, REG_DATA, 0); 660 uart_barrier(bas); 661 count++; 662 663 limit = 30; 664 lsr = 0; 665 /* 666 * LSR bits are cleared upon read, so we must accumulate 667 * them to be able to test LSR_OE below. 668 */ 669 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 670 --limit) 671 DELAY(delay); 672 if (limit == 0) { 673 ier = uart_getreg(bas, REG_IER) & 0xf0; 674 uart_setreg(bas, REG_IER, ier); 675 uart_setreg(bas, REG_MCR, mcr); 676 uart_setreg(bas, REG_FCR, 0); 677 uart_barrier(bas); 678 count = 0; 679 goto describe; 680 } 681 } while ((lsr & LSR_OE) == 0 && count < 130); 682 count--; 683 684 uart_setreg(bas, REG_MCR, mcr); 685 686 /* Reset FIFOs. */ 687 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 688 689 describe: 690 if (count >= 14 && count <= 16) { 691 sc->sc_rxfifosz = 16; 692 device_set_desc(sc->sc_dev, "16550 or compatible"); 693 } else if (count >= 28 && count <= 32) { 694 sc->sc_rxfifosz = 32; 695 device_set_desc(sc->sc_dev, "16650 or compatible"); 696 } else if (count >= 56 && count <= 64) { 697 sc->sc_rxfifosz = 64; 698 device_set_desc(sc->sc_dev, "16750 or compatible"); 699 } else if (count >= 112 && count <= 128) { 700 sc->sc_rxfifosz = 128; 701 device_set_desc(sc->sc_dev, "16950 or compatible"); 702 } else { 703 sc->sc_rxfifosz = 16; 704 device_set_desc(sc->sc_dev, 705 "Non-standard ns8250 class UART with FIFOs"); 706 } 707 708 /* 709 * Force the Tx FIFO size to 16 bytes for now. We don't program the 710 * Tx trigger. Also, we assume that all data has been sent when the 711 * interrupt happens. 712 */ 713 sc->sc_txfifosz = 16; 714 715 #if 0 716 /* 717 * XXX there are some issues related to hardware flow control and 718 * it's likely that uart(4) is the cause. This basicly needs more 719 * investigation, but we avoid using for hardware flow control 720 * until then. 721 */ 722 /* 16650s or higher have automatic flow control. */ 723 if (sc->sc_rxfifosz > 16) { 724 sc->sc_hwiflow = 1; 725 sc->sc_hwoflow = 1; 726 } 727 #endif 728 729 return (0); 730 } 731 732 static int 733 ns8250_bus_receive(struct uart_softc *sc) 734 { 735 struct uart_bas *bas; 736 int xc; 737 uint8_t lsr; 738 739 bas = &sc->sc_bas; 740 uart_lock(sc->sc_hwmtx); 741 lsr = uart_getreg(bas, REG_LSR); 742 while (lsr & LSR_RXRDY) { 743 if (uart_rx_full(sc)) { 744 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 745 break; 746 } 747 xc = uart_getreg(bas, REG_DATA); 748 if (lsr & LSR_FE) 749 xc |= UART_STAT_FRAMERR; 750 if (lsr & LSR_PE) 751 xc |= UART_STAT_PARERR; 752 uart_rx_put(sc, xc); 753 lsr = uart_getreg(bas, REG_LSR); 754 } 755 /* Discard everything left in the Rx FIFO. */ 756 while (lsr & LSR_RXRDY) { 757 (void)uart_getreg(bas, REG_DATA); 758 uart_barrier(bas); 759 lsr = uart_getreg(bas, REG_LSR); 760 } 761 uart_unlock(sc->sc_hwmtx); 762 return (0); 763 } 764 765 static int 766 ns8250_bus_setsig(struct uart_softc *sc, int sig) 767 { 768 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 769 struct uart_bas *bas; 770 uint32_t new, old; 771 772 bas = &sc->sc_bas; 773 do { 774 old = sc->sc_hwsig; 775 new = old; 776 if (sig & SER_DDTR) { 777 SIGCHG(sig & SER_DTR, new, SER_DTR, 778 SER_DDTR); 779 } 780 if (sig & SER_DRTS) { 781 SIGCHG(sig & SER_RTS, new, SER_RTS, 782 SER_DRTS); 783 } 784 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 785 uart_lock(sc->sc_hwmtx); 786 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 787 if (new & SER_DTR) 788 ns8250->mcr |= MCR_DTR; 789 if (new & SER_RTS) 790 ns8250->mcr |= MCR_RTS; 791 uart_setreg(bas, REG_MCR, ns8250->mcr); 792 uart_barrier(bas); 793 uart_unlock(sc->sc_hwmtx); 794 return (0); 795 } 796 797 static int 798 ns8250_bus_transmit(struct uart_softc *sc) 799 { 800 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 801 struct uart_bas *bas; 802 int i; 803 804 bas = &sc->sc_bas; 805 uart_lock(sc->sc_hwmtx); 806 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 807 ; 808 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 809 uart_barrier(bas); 810 for (i = 0; i < sc->sc_txdatasz; i++) { 811 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 812 uart_barrier(bas); 813 } 814 sc->sc_txbusy = 1; 815 uart_unlock(sc->sc_hwmtx); 816 return (0); 817 } 818