1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_acpi.h" 30 #include "opt_platform.h" 31 #include "opt_uart.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 #ifdef DEV_ACPI 56 #include <dev/uart/uart_cpu_acpi.h> 57 #include <contrib/dev/acpica/include/acpi.h> 58 #endif 59 60 #include <dev/ic/ns16550.h> 61 62 #include "uart_if.h" 63 64 #define DEFAULT_RCLK 1843200 65 66 /* 67 * Set the default baudrate tolerance to 3.0%. 68 * 69 * Some embedded boards have odd reference clocks (eg 25MHz) 70 * and we need to handle higher variances in the target baud rate. 71 */ 72 #ifndef UART_DEV_TOLERANCE_PCT 73 #define UART_DEV_TOLERANCE_PCT 30 74 #endif /* UART_DEV_TOLERANCE_PCT */ 75 76 static int broken_txfifo = 0; 77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 79 80 static int uart_noise_threshold = 0; 81 SYSCTL_INT(_hw, OID_AUTO, uart_noise_threshold, CTLFLAG_RWTUN, 82 &uart_noise_threshold, 0, 83 "Number of UART RX interrupts where TX is not ready, before data is discarded"); 84 85 /* 86 * To use early printf on x86, add the following to your kernel config: 87 * 88 * options UART_NS8250_EARLY_PORT=0x3f8 89 * options EARLY_PRINTF=ns8250 90 */ 91 #if CHECK_EARLY_PRINTF(ns8250) 92 #if !(defined(__amd64__) || defined(__i386__)) 93 #error ns8250 early putc is x86 specific as it uses inb/outb 94 #endif 95 static void 96 uart_ns8250_early_putc(int c) 97 { 98 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR; 99 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA; 100 int limit = 10000; /* 10ms is plenty of time */ 101 102 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0) 103 continue; 104 outb(tx, c); 105 } 106 early_putc_t *early_putc = uart_ns8250_early_putc; 107 #endif /* EARLY_PRINTF */ 108 109 /* 110 * Clear pending interrupts. THRE is cleared by reading IIR. Data 111 * that may have been received gets lost here. 112 */ 113 static void 114 ns8250_clrint(struct uart_bas *bas) 115 { 116 uint8_t iir, lsr; 117 118 iir = uart_getreg(bas, REG_IIR); 119 while ((iir & IIR_NOPEND) == 0) { 120 iir &= IIR_IMASK; 121 if (iir == IIR_RLS) { 122 lsr = uart_getreg(bas, REG_LSR); 123 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 124 (void)uart_getreg(bas, REG_DATA); 125 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 126 (void)uart_getreg(bas, REG_DATA); 127 else if (iir == IIR_MLSC) 128 (void)uart_getreg(bas, REG_MSR); 129 uart_barrier(bas); 130 iir = uart_getreg(bas, REG_IIR); 131 } 132 } 133 134 static uint32_t 135 ns8250_get_divisor(struct uart_bas *bas) 136 { 137 uint32_t divisor; 138 uint8_t lcr; 139 140 lcr = uart_getreg(bas, REG_LCR); 141 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 142 uart_barrier(bas); 143 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 144 uart_barrier(bas); 145 uart_setreg(bas, REG_LCR, lcr); 146 uart_barrier(bas); 147 148 return (divisor); 149 } 150 151 static int 152 ns8250_delay(struct uart_bas *bas) 153 { 154 int divisor; 155 156 divisor = ns8250_get_divisor(bas); 157 158 /* 1/10th the time to transmit 1 character (estimate). */ 159 if (divisor <= 134) 160 return (16000000 * divisor / bas->rclk); 161 return (16000 * divisor / (bas->rclk / 1000)); 162 } 163 164 static int 165 ns8250_divisor(int rclk, int baudrate) 166 { 167 int actual_baud, divisor; 168 int error; 169 170 if (baudrate == 0) 171 return (0); 172 173 divisor = (rclk / (baudrate << 3) + 1) >> 1; 174 if (divisor == 0 || divisor >= 65536) 175 return (0); 176 actual_baud = rclk / (divisor << 4); 177 178 /* 10 times error in percent: */ 179 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2; 180 181 /* enforce maximum error tolerance: */ 182 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 183 return (0); 184 185 return (divisor); 186 } 187 188 static int 189 ns8250_drain(struct uart_bas *bas, int what) 190 { 191 int delay, limit; 192 193 delay = ns8250_delay(bas); 194 195 if (what & UART_DRAIN_TRANSMITTER) { 196 /* 197 * Pick an arbitrary high limit to avoid getting stuck in 198 * an infinite loop when the hardware is broken. Make the 199 * limit high enough to handle large FIFOs. 200 */ 201 limit = 10*1024; 202 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 203 DELAY(delay); 204 if (limit == 0) { 205 /* printf("uart: ns8250: transmitter appears stuck... "); */ 206 return (EIO); 207 } 208 } 209 210 if (what & UART_DRAIN_RECEIVER) { 211 /* 212 * Pick an arbitrary high limit to avoid getting stuck in 213 * an infinite loop when the hardware is broken. Make the 214 * limit high enough to handle large FIFOs and integrated 215 * UARTs. The HP rx2600 for example has 3 UARTs on the 216 * management board that tend to get a lot of data send 217 * to it when the UART is first activated. Assume that we 218 * have finished draining if LSR_RXRDY is not asserted both 219 * prior to and after a DELAY; but as long as LSR_RXRDY is 220 * asserted, read (and discard) characters as quickly as 221 * possible. 222 */ 223 limit=10*4096; 224 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 225 do { 226 (void)uart_getreg(bas, REG_DATA); 227 uart_barrier(bas); 228 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit); 229 uart_barrier(bas); 230 DELAY(delay << 2); 231 } 232 if (limit == 0) { 233 /* printf("uart: ns8250: receiver appears broken... "); */ 234 return (EIO); 235 } 236 } 237 238 return (0); 239 } 240 241 /* 242 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 243 * drained. WARNING: this function clobbers the FIFO setting! 244 */ 245 static void 246 ns8250_flush(struct uart_bas *bas, int what) 247 { 248 uint8_t fcr; 249 uint8_t lsr; 250 int drain = 0; 251 252 fcr = FCR_ENABLE; 253 if (what & UART_FLUSH_TRANSMITTER) 254 fcr |= FCR_XMT_RST; 255 if (what & UART_FLUSH_RECEIVER) 256 fcr |= FCR_RCV_RST; 257 uart_setreg(bas, REG_FCR, fcr); 258 uart_barrier(bas); 259 260 /* 261 * Detect and work around emulated UARTs which don't implement the 262 * FCR register; on these systems we need to drain the FIFO since 263 * the flush we request doesn't happen. One such system is the 264 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code: 265 * https://github.com/rust-vmm/vm-superio/issues/83 266 */ 267 lsr = uart_getreg(bas, REG_LSR); 268 if (((lsr & LSR_THRE) == 0) && (what & UART_FLUSH_TRANSMITTER)) 269 drain |= UART_DRAIN_TRANSMITTER; 270 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER)) 271 drain |= UART_DRAIN_RECEIVER; 272 if (drain != 0) { 273 printf("uart: ns8250: UART FCR is broken (%#x)\n", drain); 274 ns8250_drain(bas, drain); 275 } 276 } 277 278 static int 279 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 280 int parity) 281 { 282 int divisor; 283 uint8_t lcr; 284 285 /* Don't change settings when running on Hyper-V */ 286 if (vm_guest == VM_GUEST_HV) 287 return (0); 288 289 lcr = 0; 290 if (databits >= 8) 291 lcr |= LCR_8BITS; 292 else if (databits == 7) 293 lcr |= LCR_7BITS; 294 else if (databits == 6) 295 lcr |= LCR_6BITS; 296 else 297 lcr |= LCR_5BITS; 298 if (stopbits > 1) 299 lcr |= LCR_STOPB; 300 lcr |= parity << 3; 301 302 /* Set baudrate if we know a rclk and both are not 0. */ 303 if (baudrate > 0 && bas->rclk > 0) { 304 divisor = ns8250_divisor(bas->rclk, baudrate); 305 if (divisor == 0) 306 return (EINVAL); 307 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 308 uart_barrier(bas); 309 uart_setreg(bas, REG_DLL, divisor & 0xff); 310 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 311 uart_barrier(bas); 312 } 313 314 /* Set LCR and clear DLAB. */ 315 uart_setreg(bas, REG_LCR, lcr); 316 uart_barrier(bas); 317 return (0); 318 } 319 320 /* 321 * Low-level UART interface. 322 */ 323 static int ns8250_probe(struct uart_bas *bas); 324 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 325 static void ns8250_term(struct uart_bas *bas); 326 static void ns8250_putc(struct uart_bas *bas, int); 327 static int ns8250_rxready(struct uart_bas *bas); 328 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 329 330 struct uart_ops uart_ns8250_ops = { 331 .probe = ns8250_probe, 332 .init = ns8250_init, 333 .term = ns8250_term, 334 .putc = ns8250_putc, 335 .rxready = ns8250_rxready, 336 .getc = ns8250_getc, 337 }; 338 339 static int 340 ns8250_probe(struct uart_bas *bas) 341 { 342 u_char val; 343 344 /* Check known 0 bits that don't depend on DLAB. */ 345 val = uart_getreg(bas, REG_IIR); 346 if (val & 0x30) 347 return (ENXIO); 348 /* 349 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 350 * chip, but otherwise doesn't seem to have a function. In 351 * other words, uart(4) works regardless. Ignore that bit so 352 * the probe succeeds. 353 */ 354 val = uart_getreg(bas, REG_MCR); 355 if (val & 0xa0) 356 return (ENXIO); 357 358 return (0); 359 } 360 361 static void 362 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 363 int parity) 364 { 365 u_char ier; 366 367 /* Disable all interrupt sources. */ 368 /* 369 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 370 * UARTs split the receive time-out interrupt bit out separately as 371 * 0x10. This gets handled by ier_mask and ier_rxbits below. 372 */ 373 ier = uart_getreg(bas, REG_IER) & 0xe0; 374 uart_setreg(bas, REG_IER, ier); 375 uart_barrier(bas); 376 377 /* 378 * Loader tells us to infer the rclk when it sets xo to 0 in 379 * hw.uart.console. We know the baudrate was set by the firmware, so 380 * calculate rclk from baudrate and the divisor register. If 'div' is 381 * actually 0, the resulting 0 value will have us fall back to other 382 * rclk methods. 383 */ 384 if (bas->rclk_guess && bas->rclk == 0 && baudrate != 0) { 385 uint32_t div; 386 387 div = ns8250_get_divisor(bas); 388 bas->rclk = baudrate * div * 16; 389 } 390 391 /* 392 * Pick a default because we just don't know. This likely needs future 393 * refinement, but that's hard outside of consoles to know what to use. 394 * But defer as long as possible if there's no defined baud rate. 395 */ 396 if (bas->rclk == 0 && baudrate != 0) 397 bas->rclk = DEFAULT_RCLK; 398 399 ns8250_param(bas, baudrate, databits, stopbits, parity); 400 401 /* Disable the FIFO (if present). */ 402 uart_setreg(bas, REG_FCR, 0); 403 uart_barrier(bas); 404 405 /* Set RTS & DTR. */ 406 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 407 uart_barrier(bas); 408 409 ns8250_clrint(bas); 410 } 411 412 static void 413 ns8250_term(struct uart_bas *bas) 414 { 415 416 /* Clear RTS & DTR. */ 417 uart_setreg(bas, REG_MCR, MCR_IE); 418 uart_barrier(bas); 419 } 420 421 static void 422 ns8250_putc(struct uart_bas *bas, int c) 423 { 424 int limit; 425 426 if (vm_guest != VM_GUEST_HV) { 427 limit = 250000; 428 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 429 DELAY(4); 430 } 431 uart_setreg(bas, REG_DATA, c); 432 uart_barrier(bas); 433 } 434 435 static int 436 ns8250_rxready(struct uart_bas *bas) 437 { 438 439 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 440 } 441 442 static int 443 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 444 { 445 int c; 446 447 uart_lock(hwmtx); 448 449 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 450 uart_unlock(hwmtx); 451 DELAY(4); 452 uart_lock(hwmtx); 453 } 454 455 c = uart_getreg(bas, REG_DATA); 456 457 uart_unlock(hwmtx); 458 459 return (c); 460 } 461 462 static kobj_method_t ns8250_methods[] = { 463 KOBJMETHOD(uart_attach, ns8250_bus_attach), 464 KOBJMETHOD(uart_detach, ns8250_bus_detach), 465 KOBJMETHOD(uart_flush, ns8250_bus_flush), 466 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 467 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 468 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 469 KOBJMETHOD(uart_param, ns8250_bus_param), 470 KOBJMETHOD(uart_probe, ns8250_bus_probe), 471 KOBJMETHOD(uart_receive, ns8250_bus_receive), 472 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 473 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 474 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy), 475 KOBJMETHOD(uart_grab, ns8250_bus_grab), 476 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 477 KOBJMETHOD_END 478 }; 479 480 struct uart_class uart_ns8250_class = { 481 "ns8250", 482 ns8250_methods, 483 sizeof(struct ns8250_softc), 484 .uc_ops = &uart_ns8250_ops, 485 .uc_range = 8, 486 .uc_rclk = DEFAULT_RCLK, 487 .uc_rshift = 0 488 }; 489 UART_CLASS(uart_ns8250_class); 490 491 /* 492 * XXX -- refactor out ACPI and FDT ifdefs 493 */ 494 #ifdef DEV_ACPI 495 static struct acpi_spcr_compat_data acpi_spcr_compat_data[] = { 496 { &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE }, 497 { &uart_ns8250_class, ACPI_DBG2_16550_SUBSET }, 498 { &uart_ns8250_class, ACPI_DBG2_16550_WITH_GAS }, 499 { NULL, 0 }, 500 }; 501 UART_ACPI_SPCR_CLASS(acpi_spcr_compat_data); 502 503 static struct acpi_uart_compat_data acpi_compat_data[] = { 504 {"AMD0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 505 {"AMDI0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, 506 {"APMC0D08", &uart_ns8250_class, 2, 4, 0, 0, "APM compatible UART"}, 507 {"MRVL0001", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, 508 {"SCX0006", &uart_ns8250_class, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, 509 {"HISI0031", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, 510 {"INTC1006", &uart_ns8250_class, 2, 0, 25000000, 0, "Intel ARM64 UART"}, 511 {"NXP0018", &uart_ns8250_class, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, 512 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, "Standard PC COM port"}, 513 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, "16550A-compatible COM port"}, 514 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, 515 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 516 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, 517 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, 518 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, 519 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, 520 {NULL, NULL, 0 , 0, 0, 0, NULL}, 521 }; 522 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); 523 #endif 524 525 #ifdef FDT 526 static struct ofw_compat_data compat_data[] = { 527 {"ns16550", (uintptr_t)&uart_ns8250_class}, 528 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 529 {NULL, (uintptr_t)NULL}, 530 }; 531 UART_FDT_CLASS_AND_DEVICE(compat_data); 532 #endif 533 534 /* Use token-pasting to form SER_ and MSR_ named constants. */ 535 #define SER(sig) SER_##sig 536 #define SERD(sig) SER_D##sig 537 #define MSR(sig) MSR_##sig 538 #define MSRD(sig) MSR_D##sig 539 540 /* 541 * Detect signal changes using software delta detection. The previous state of 542 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 543 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 544 * new state of both the signal and the delta bits. 545 */ 546 #define SIGCHGSW(var, msr, sig) \ 547 if ((msr) & MSR(sig)) { \ 548 if ((var & SER(sig)) == 0) \ 549 var |= SERD(sig) | SER(sig); \ 550 } else { \ 551 if ((var & SER(sig)) != 0) \ 552 var = SERD(sig) | (var & ~SER(sig)); \ 553 } 554 555 /* 556 * Detect signal changes using the hardware msr delta bits. This is currently 557 * used only when PPS timing information is being captured using the "narrow 558 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 559 * by time the interrupt handler is invoked. The hardware will latch the fact 560 * that it changed in the delta bits. 561 */ 562 #define SIGCHGHW(var, msr, sig) \ 563 if ((msr) & MSRD(sig)) { \ 564 if (((msr) & MSR(sig)) != 0) \ 565 var |= SERD(sig) | SER(sig); \ 566 else \ 567 var = SERD(sig) | (var & ~SER(sig)); \ 568 } 569 570 int 571 ns8250_bus_attach(struct uart_softc *sc) 572 { 573 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 574 struct uart_bas *bas; 575 unsigned int ivar; 576 #ifdef FDT 577 phandle_t node; 578 pcell_t cell; 579 #endif 580 581 #ifdef FDT 582 /* Check whether uart has a broken txfifo. */ 583 node = ofw_bus_get_node(sc->sc_dev); 584 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 585 broken_txfifo = cell ? 1 : 0; 586 #endif 587 588 bas = &sc->sc_bas; 589 590 ns8250->busy_detect = bas->busy_detect; 591 ns8250->mcr = uart_getreg(bas, REG_MCR); 592 ns8250->fcr = FCR_ENABLE; 593 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 594 &ivar)) { 595 if (UART_FLAGS_FCR_RX_LOW(ivar)) 596 ns8250->fcr |= FCR_RX_LOW; 597 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 598 ns8250->fcr |= FCR_RX_MEDL; 599 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 600 ns8250->fcr |= FCR_RX_HIGH; 601 else 602 ns8250->fcr |= FCR_RX_MEDH; 603 } else 604 ns8250->fcr |= FCR_RX_MEDH; 605 606 /* Get IER mask */ 607 ivar = 0xf0; 608 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 609 &ivar); 610 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 611 612 /* Get IER RX interrupt bits */ 613 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 614 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 615 &ivar); 616 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 617 618 uart_setreg(bas, REG_FCR, ns8250->fcr); 619 uart_barrier(bas); 620 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 621 622 if (ns8250->mcr & MCR_DTR) 623 sc->sc_hwsig |= SER_DTR; 624 if (ns8250->mcr & MCR_RTS) 625 sc->sc_hwsig |= SER_RTS; 626 ns8250_bus_getsig(sc); 627 628 ns8250_clrint(bas); 629 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 630 ns8250->ier |= ns8250->ier_rxbits; 631 uart_setreg(bas, REG_IER, ns8250->ier); 632 uart_barrier(bas); 633 634 /* 635 * Timing of the H/W access was changed with r253161 of uart_core.c 636 * It has been observed that an ITE IT8513E would signal a break 637 * condition with pretty much every character it received, unless 638 * it had enough time to settle between ns8250_bus_attach() and 639 * ns8250_bus_ipend() -- which it accidentally had before r253161. 640 * It's not understood why the UART chip behaves this way and it 641 * could very well be that the DELAY make the H/W work in the same 642 * accidental manner as before. More analysis is warranted, but 643 * at least now we fixed a known regression. 644 */ 645 DELAY(200); 646 return (0); 647 } 648 649 int 650 ns8250_bus_detach(struct uart_softc *sc) 651 { 652 struct ns8250_softc *ns8250; 653 struct uart_bas *bas; 654 u_char ier; 655 656 ns8250 = (struct ns8250_softc *)sc; 657 bas = &sc->sc_bas; 658 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 659 uart_setreg(bas, REG_IER, ier); 660 uart_barrier(bas); 661 ns8250_clrint(bas); 662 return (0); 663 } 664 665 int 666 ns8250_bus_flush(struct uart_softc *sc, int what) 667 { 668 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 669 struct uart_bas *bas; 670 int error; 671 672 bas = &sc->sc_bas; 673 uart_lock(sc->sc_hwmtx); 674 if (sc->sc_rxfifosz > 1) { 675 ns8250_flush(bas, what); 676 uart_setreg(bas, REG_FCR, ns8250->fcr); 677 uart_barrier(bas); 678 error = 0; 679 } else 680 error = ns8250_drain(bas, what); 681 uart_unlock(sc->sc_hwmtx); 682 return (error); 683 } 684 685 int 686 ns8250_bus_getsig(struct uart_softc *sc) 687 { 688 uint32_t old, sig; 689 uint8_t msr; 690 691 /* 692 * The delta bits are reputed to be broken on some hardware, so use 693 * software delta detection by default. Use the hardware delta bits 694 * when capturing PPS pulses which are too narrow for software detection 695 * to see the edges. Hardware delta for RI doesn't work like the 696 * others, so always use software for it. Other threads may be changing 697 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 698 * update without other changes happening. Note that the SIGCHGxx() 699 * macros carefully preserve the delta bits when we have to loop several 700 * times and a signal transitions between iterations. 701 */ 702 do { 703 old = sc->sc_hwsig; 704 sig = old; 705 uart_lock(sc->sc_hwmtx); 706 msr = uart_getreg(&sc->sc_bas, REG_MSR); 707 uart_unlock(sc->sc_hwmtx); 708 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 709 SIGCHGHW(sig, msr, DSR); 710 SIGCHGHW(sig, msr, CTS); 711 SIGCHGHW(sig, msr, DCD); 712 } else { 713 SIGCHGSW(sig, msr, DSR); 714 SIGCHGSW(sig, msr, CTS); 715 SIGCHGSW(sig, msr, DCD); 716 } 717 SIGCHGSW(sig, msr, RI); 718 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 719 return (sig); 720 } 721 722 int 723 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 724 { 725 struct uart_bas *bas; 726 int baudrate, divisor, error; 727 uint8_t efr, lcr; 728 729 bas = &sc->sc_bas; 730 error = 0; 731 uart_lock(sc->sc_hwmtx); 732 switch (request) { 733 case UART_IOCTL_BREAK: 734 lcr = uart_getreg(bas, REG_LCR); 735 if (data) 736 lcr |= LCR_SBREAK; 737 else 738 lcr &= ~LCR_SBREAK; 739 uart_setreg(bas, REG_LCR, lcr); 740 uart_barrier(bas); 741 break; 742 case UART_IOCTL_IFLOW: 743 lcr = uart_getreg(bas, REG_LCR); 744 uart_barrier(bas); 745 uart_setreg(bas, REG_LCR, 0xbf); 746 uart_barrier(bas); 747 efr = uart_getreg(bas, REG_EFR); 748 if (data) 749 efr |= EFR_RTS; 750 else 751 efr &= ~EFR_RTS; 752 uart_setreg(bas, REG_EFR, efr); 753 uart_barrier(bas); 754 uart_setreg(bas, REG_LCR, lcr); 755 uart_barrier(bas); 756 break; 757 case UART_IOCTL_OFLOW: 758 lcr = uart_getreg(bas, REG_LCR); 759 uart_barrier(bas); 760 uart_setreg(bas, REG_LCR, 0xbf); 761 uart_barrier(bas); 762 efr = uart_getreg(bas, REG_EFR); 763 if (data) 764 efr |= EFR_CTS; 765 else 766 efr &= ~EFR_CTS; 767 uart_setreg(bas, REG_EFR, efr); 768 uart_barrier(bas); 769 uart_setreg(bas, REG_LCR, lcr); 770 uart_barrier(bas); 771 break; 772 case UART_IOCTL_BAUD: 773 divisor = ns8250_get_divisor(bas); 774 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 775 if (baudrate > 0) 776 *(int*)data = baudrate; 777 else 778 error = ENXIO; 779 break; 780 default: 781 error = EINVAL; 782 break; 783 } 784 uart_unlock(sc->sc_hwmtx); 785 return (error); 786 } 787 788 int 789 ns8250_bus_ipend(struct uart_softc *sc) 790 { 791 struct uart_bas *bas; 792 struct ns8250_softc *ns8250; 793 int ipend; 794 uint8_t iir, lsr; 795 796 ns8250 = (struct ns8250_softc *)sc; 797 bas = &sc->sc_bas; 798 uart_lock(sc->sc_hwmtx); 799 iir = uart_getreg(bas, REG_IIR); 800 801 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 802 (void)uart_getreg(bas, DW_REG_USR); 803 uart_unlock(sc->sc_hwmtx); 804 return (0); 805 } 806 if (iir & IIR_NOPEND) { 807 uart_unlock(sc->sc_hwmtx); 808 return (0); 809 } 810 ipend = 0; 811 if (iir & IIR_RXRDY) { 812 lsr = uart_getreg(bas, REG_LSR); 813 if (lsr & LSR_OE) 814 ipend |= SER_INT_OVERRUN; 815 if (lsr & LSR_BI) 816 ipend |= SER_INT_BREAK; 817 if (lsr & LSR_RXRDY) 818 ipend |= SER_INT_RXREADY; 819 } else { 820 if (iir & IIR_TXRDY) { 821 ipend |= SER_INT_TXIDLE; 822 ns8250->ier &= ~IER_ETXRDY; 823 uart_setreg(bas, REG_IER, ns8250->ier); 824 uart_barrier(bas); 825 } else 826 ipend |= SER_INT_SIGCHG; 827 } 828 if (ipend == 0) 829 ns8250_clrint(bas); 830 uart_unlock(sc->sc_hwmtx); 831 return (ipend); 832 } 833 834 int 835 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 836 int stopbits, int parity) 837 { 838 struct ns8250_softc *ns8250; 839 struct uart_bas *bas; 840 int error, limit; 841 842 ns8250 = (struct ns8250_softc*)sc; 843 bas = &sc->sc_bas; 844 uart_lock(sc->sc_hwmtx); 845 /* 846 * When using DW UART with BUSY detection it is necessary to wait 847 * until all serial transfers are finished before manipulating the 848 * line control. LCR will not be affected when UART is busy. 849 */ 850 if (ns8250->busy_detect != 0) { 851 /* 852 * Pick an arbitrary high limit to avoid getting stuck in 853 * an infinite loop in case when the hardware is broken. 854 */ 855 limit = 10 * 1024; 856 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 857 --limit) 858 DELAY(4); 859 860 if (limit <= 0) { 861 /* UART appears to be stuck */ 862 uart_unlock(sc->sc_hwmtx); 863 return (EIO); 864 } 865 } 866 867 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 868 uart_unlock(sc->sc_hwmtx); 869 return (error); 870 } 871 872 int 873 ns8250_bus_probe(struct uart_softc *sc) 874 { 875 struct uart_bas *bas; 876 int count, delay, error, limit; 877 uint8_t lsr, mcr, ier; 878 879 bas = &sc->sc_bas; 880 881 error = ns8250_probe(bas); 882 if (error) 883 return (error); 884 885 mcr = MCR_IE; 886 if (sc->sc_sysdev == NULL) { 887 /* By using ns8250_init() we also set DTR and RTS. */ 888 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 889 } else 890 mcr |= MCR_DTR | MCR_RTS; 891 892 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 893 if (error) 894 return (error); 895 896 /* 897 * Set loopback mode. This avoids having garbage on the wire and 898 * also allows us send and receive data. We set DTR and RTS to 899 * avoid the possibility that automatic flow-control prevents 900 * any data from being sent. 901 */ 902 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 903 uart_barrier(bas); 904 905 /* 906 * Enable FIFOs. And check that the UART has them. If not, we're 907 * done. Since this is the first time we enable the FIFOs, we reset 908 * them. 909 */ 910 uart_setreg(bas, REG_FCR, FCR_ENABLE); 911 uart_barrier(bas); 912 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 913 /* 914 * NS16450 or INS8250. We don't bother to differentiate 915 * between them. They're too old to be interesting. 916 */ 917 uart_setreg(bas, REG_MCR, mcr); 918 uart_barrier(bas); 919 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 920 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 921 return (0); 922 } 923 924 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 925 uart_barrier(bas); 926 927 count = 0; 928 delay = ns8250_delay(bas); 929 930 /* We have FIFOs. Drain the transmitter and receiver. */ 931 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 932 if (error) { 933 uart_setreg(bas, REG_MCR, mcr); 934 uart_setreg(bas, REG_FCR, 0); 935 uart_barrier(bas); 936 goto describe; 937 } 938 939 /* 940 * We should have a sufficiently clean "pipe" to determine the 941 * size of the FIFOs. We send as much characters as is reasonable 942 * and wait for the overflow bit in the LSR register to be 943 * asserted, counting the characters as we send them. Based on 944 * that count we know the FIFO size. 945 */ 946 do { 947 uart_setreg(bas, REG_DATA, 0); 948 uart_barrier(bas); 949 count++; 950 951 limit = 30; 952 lsr = 0; 953 /* 954 * LSR bits are cleared upon read, so we must accumulate 955 * them to be able to test LSR_OE below. 956 */ 957 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 958 --limit) 959 DELAY(delay); 960 if (limit == 0) { 961 /* See the comment in ns8250_init(). */ 962 ier = uart_getreg(bas, REG_IER) & 0xe0; 963 uart_setreg(bas, REG_IER, ier); 964 uart_setreg(bas, REG_MCR, mcr); 965 uart_setreg(bas, REG_FCR, 0); 966 uart_barrier(bas); 967 count = 0; 968 goto describe; 969 } 970 } while ((lsr & LSR_OE) == 0 && count < 260); 971 count--; 972 973 uart_setreg(bas, REG_MCR, mcr); 974 975 /* Reset FIFOs. */ 976 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 977 978 describe: 979 if (count >= 14 && count <= 16) { 980 sc->sc_rxfifosz = 16; 981 device_set_desc(sc->sc_dev, "16550 or compatible"); 982 } else if (count >= 28 && count <= 32) { 983 sc->sc_rxfifosz = 32; 984 device_set_desc(sc->sc_dev, "16650 or compatible"); 985 } else if (count >= 56 && count <= 64) { 986 sc->sc_rxfifosz = 64; 987 device_set_desc(sc->sc_dev, "16750 or compatible"); 988 } else if (count >= 112 && count <= 128) { 989 sc->sc_rxfifosz = 128; 990 device_set_desc(sc->sc_dev, "16950 or compatible"); 991 } else if (count >= 224 && count <= 256) { 992 sc->sc_rxfifosz = 256; 993 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO"); 994 } else { 995 sc->sc_rxfifosz = 16; 996 device_set_desc(sc->sc_dev, 997 "Non-standard ns8250 class UART with FIFOs"); 998 } 999 1000 /* 1001 * Force the Tx FIFO size to 16 bytes for now. We don't program the 1002 * Tx trigger. Also, we assume that all data has been sent when the 1003 * interrupt happens. 1004 */ 1005 sc->sc_txfifosz = 16; 1006 1007 #if 0 1008 /* 1009 * XXX there are some issues related to hardware flow control and 1010 * it's likely that uart(4) is the cause. This basically needs more 1011 * investigation, but we avoid using for hardware flow control 1012 * until then. 1013 */ 1014 /* 16650s or higher have automatic flow control. */ 1015 if (sc->sc_rxfifosz > 16) { 1016 sc->sc_hwiflow = 1; 1017 sc->sc_hwoflow = 1; 1018 } 1019 #endif 1020 1021 return (0); 1022 } 1023 1024 int 1025 ns8250_bus_receive(struct uart_softc *sc) 1026 { 1027 struct uart_bas *bas; 1028 struct ns8250_softc *ns8250 = (struct ns8250_softc *)sc; 1029 int xc; 1030 uint8_t lsr; 1031 1032 bas = &sc->sc_bas; 1033 uart_lock(sc->sc_hwmtx); 1034 lsr = uart_getreg(bas, REG_LSR); 1035 while (lsr & LSR_RXRDY) { 1036 if (uart_rx_full(sc)) { 1037 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 1038 break; 1039 } 1040 /* Filter out possible noise on the line. 1041 * Expect that the device should be able to transmit as well as 1042 * receive, so if we receive too many characters before transmit 1043 * is ready, it's probably noise. 1044 */ 1045 if ((lsr & (LSR_TXRDY | LSR_TEMT)) == 0 && 1046 uart_noise_threshold > 0) { 1047 if (++ns8250->noise_count >= uart_noise_threshold) 1048 break; 1049 } else 1050 ns8250->noise_count = 0; 1051 xc = uart_getreg(bas, REG_DATA); 1052 if (lsr & LSR_FE) 1053 xc |= UART_STAT_FRAMERR; 1054 if (lsr & LSR_PE) 1055 xc |= UART_STAT_PARERR; 1056 uart_rx_put(sc, xc); 1057 lsr = uart_getreg(bas, REG_LSR); 1058 } 1059 /* Discard everything left in the Rx FIFO. */ 1060 while (lsr & LSR_RXRDY) { 1061 (void)uart_getreg(bas, REG_DATA); 1062 uart_barrier(bas); 1063 lsr = uart_getreg(bas, REG_LSR); 1064 } 1065 uart_unlock(sc->sc_hwmtx); 1066 return (0); 1067 } 1068 1069 int 1070 ns8250_bus_setsig(struct uart_softc *sc, int sig) 1071 { 1072 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1073 struct uart_bas *bas; 1074 uint32_t new, old; 1075 1076 bas = &sc->sc_bas; 1077 do { 1078 old = sc->sc_hwsig; 1079 new = old; 1080 if (sig & SER_DDTR) { 1081 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 1082 } 1083 if (sig & SER_DRTS) { 1084 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 1085 } 1086 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 1087 uart_lock(sc->sc_hwmtx); 1088 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 1089 if (new & SER_DTR) 1090 ns8250->mcr |= MCR_DTR; 1091 if (new & SER_RTS) 1092 ns8250->mcr |= MCR_RTS; 1093 uart_setreg(bas, REG_MCR, ns8250->mcr); 1094 uart_barrier(bas); 1095 uart_unlock(sc->sc_hwmtx); 1096 return (0); 1097 } 1098 1099 int 1100 ns8250_bus_transmit(struct uart_softc *sc) 1101 { 1102 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1103 struct uart_bas *bas; 1104 int i; 1105 1106 bas = &sc->sc_bas; 1107 uart_lock(sc->sc_hwmtx); 1108 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1109 DELAY(4); 1110 for (i = 0; i < sc->sc_txdatasz; i++) { 1111 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1112 uart_barrier(bas); 1113 } 1114 if (!broken_txfifo) 1115 ns8250->ier |= IER_ETXRDY; 1116 uart_setreg(bas, REG_IER, ns8250->ier); 1117 uart_barrier(bas); 1118 if (broken_txfifo) 1119 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1120 else 1121 sc->sc_txbusy = 1; 1122 uart_unlock(sc->sc_hwmtx); 1123 if (broken_txfifo) 1124 uart_sched_softih(sc, SER_INT_TXIDLE); 1125 return (0); 1126 } 1127 1128 bool 1129 ns8250_bus_txbusy(struct uart_softc *sc) 1130 { 1131 struct uart_bas *bas = &sc->sc_bas; 1132 1133 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) != 1134 (LSR_TEMT | LSR_THRE)) 1135 return (true); 1136 return (false); 1137 } 1138 1139 void 1140 ns8250_bus_grab(struct uart_softc *sc) 1141 { 1142 struct uart_bas *bas = &sc->sc_bas; 1143 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1144 u_char ier; 1145 1146 /* 1147 * turn off all interrupts to enter polling mode. Leave the 1148 * saved mask alone. We'll restore whatever it was in ungrab. 1149 * All pending interrupt signals are reset when IER is set to 0. 1150 */ 1151 uart_lock(sc->sc_hwmtx); 1152 ier = uart_getreg(bas, REG_IER); 1153 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1154 uart_barrier(bas); 1155 uart_unlock(sc->sc_hwmtx); 1156 } 1157 1158 void 1159 ns8250_bus_ungrab(struct uart_softc *sc) 1160 { 1161 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1162 struct uart_bas *bas = &sc->sc_bas; 1163 1164 /* 1165 * Restore previous interrupt mask 1166 */ 1167 uart_lock(sc->sc_hwmtx); 1168 uart_setreg(bas, REG_IER, ns8250->ier); 1169 uart_barrier(bas); 1170 uart_unlock(sc->sc_hwmtx); 1171 } 1172