1 /*- 2 * Copyright (c) 2017 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/bus.h> 29 #include <sys/conf.h> 30 #include <sys/kernel.h> 31 #include <sys/sysctl.h> 32 #include <sys/systm.h> 33 34 #include <machine/bus.h> 35 36 #include <dev/ofw/ofw_bus_subr.h> 37 #include <dev/uart/uart.h> 38 #include <dev/uart/uart_bus.h> 39 #include <dev/uart/uart_cpu.h> 40 #include <dev/uart/uart_cpu_fdt.h> 41 42 #include "uart_if.h" 43 44 #define UART_RBR 0x00 /* Receiver Buffer */ 45 #define RBR_BRK_DET (1 << 15) /* Break Detect */ 46 #define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */ 47 #define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */ 48 #define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */ 49 50 #define UART_TSH 0x04 /* Transmitter Holding Register */ 51 52 #define UART_CTRL 0x08 /* Control Register */ 53 #define CTRL_SOFT_RST (1 << 31) /* Soft Reset */ 54 #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */ 55 #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */ 56 #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */ 57 #define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */ 58 #define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */ 59 #define CTRL_PAR_EN (1 << 10) /* Parity Enable */ 60 #define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */ 61 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */ 62 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */ 63 #define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */ 64 #define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */ 65 #define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */ 66 #define CTRL_BRK_DET_INT (1 << 3) /* Break Detect Interrupt Enable */ 67 #define CTRL_FRM_ERR_INT (1 << 2) /* Frame Error Interrupt Enable */ 68 #define CTRL_PAR_ERR_INT (1 << 1) /* Parity Error Interrupt Enable */ 69 #define CTRL_OVR_ERR_INT (1 << 0) /* Overrun Error Interrupt Enable */ 70 #define CTRL_INTR_MASK 0x1ff 71 #define CTRL_TX_IDLE_INT CTRL_TX_RDY_INT 72 #define CTRL_IPEND_MASK (CTRL_OVR_ERR_INT | CTRL_BRK_DET_INT | \ 73 CTRL_RX_RDY_INT) 74 75 #define UART_STAT 0x0c /* Status Register */ 76 #define STAT_TX_FIFO_EMPT (1 << 13) /* TX FIFO Empty */ 77 #define STAT_RX_FIFO_EMPT (1 << 12) /* RX FIFO Empty */ 78 #define STAT_TX_FIFO_FULL (1 << 11) /* TX FIFO Full */ 79 #define STAT_TX_FIFO_HALF (1 << 10) /* TX FIFO Half Full */ 80 #define STAT_RX_TOGL (1 << 9) /* RX Toogled */ 81 #define STAT_RX_FIFO_FULL (1 << 8) /* RX FIFO Full */ 82 #define STAT_RX_FIFO_HALF (1 << 7) /* RX FIFO Half Full */ 83 #define STAT_TX_EMPT (1 << 6) /* TX Empty */ 84 #define STAT_TX_RDY (1 << 5) /* TX Ready */ 85 #define STAT_RX_RDY (1 << 4) /* RX Ready */ 86 #define STAT_BRK_DET (1 << 3) /* Break Detect */ 87 #define STAT_FRM_ERR (1 << 2) /* Frame Error */ 88 #define STAT_PAR_ERR (1 << 1) /* Parity Error */ 89 #define STAT_OVR_ERR (1 << 0) /* Overrun Error */ 90 #define STAT_TX_IDLE STAT_TX_RDY 91 #define STAT_TRANS_MASK (STAT_OVR_ERR | STAT_BRK_DET | STAT_RX_RDY) 92 93 #define UART_CCR 0x10 /* Clock Control Register */ 94 #define CCR_BAUDRATE_DIV 0x3ff /* Baud Rate Divisor */ 95 96 #define DEFAULT_RCLK 25804800 97 #define ONE_FRAME_TIME 87 98 99 #define stat_ipend_trans(i) ( \ 100 (i & STAT_OVR_ERR) << 16 | \ 101 (i & STAT_BRK_DET) << 14 | \ 102 (i & STAT_RX_RDY) << 14) 103 104 /* 105 * For debugging purposes 106 */ 107 #if 0 108 #ifdef EARLY_PRINTF 109 #if defined(SOCDEV_PA) && defined(SOCDEV_VA) 110 #define UART_REG_OFFSET 0x12000 111 static void 112 uart_mvebu_early_putc(int c) 113 { 114 volatile uint32_t *tsh; 115 volatile uint32_t *stat; 116 117 tsh = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_TSH); 118 stat = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_STAT); 119 120 while(!(*stat & STAT_TX_RDY)) 121 ; 122 123 *tsh = c & 0xff; 124 } 125 126 early_putc_t *early_putc = uart_mvebu_early_putc; 127 #endif 128 #endif 129 #endif 130 131 /* 132 * Low-level UART interface. 133 */ 134 static int uart_mvebu_probe(struct uart_bas *); 135 static void uart_mvebu_init(struct uart_bas *, int, int, int, int); 136 static void uart_mvebu_putc(struct uart_bas *, int); 137 static int uart_mvebu_rxready(struct uart_bas *); 138 static int uart_mvebu_getc(struct uart_bas *, struct mtx *); 139 140 static struct uart_ops uart_mvebu_ops = { 141 .probe = uart_mvebu_probe, 142 .init = uart_mvebu_init, 143 .term = NULL, 144 .putc = uart_mvebu_putc, 145 .rxready = uart_mvebu_rxready, 146 .getc = uart_mvebu_getc, 147 }; 148 149 static int 150 uart_mvebu_probe(struct uart_bas *bas) 151 { 152 153 return (0); 154 } 155 156 static int 157 uart_mvebu_divisor(int rclk, int baudrate) 158 { 159 int divisor; 160 161 if (baudrate == 0) 162 return (0); 163 164 divisor = (rclk >> 4) / baudrate; 165 if (divisor <= 1 || divisor >= 1024) 166 return (0); 167 168 return (divisor); 169 } 170 171 static int 172 uart_mvebu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 173 int parity) 174 { 175 uint32_t ctrl = 0; 176 uint32_t ccr; 177 int divisor, ret = 0; 178 179 /* Reset UART */ 180 ctrl = uart_getreg(bas, UART_CTRL); 181 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | 182 CTRL_LPBK_EN); 183 uart_barrier(bas); 184 185 switch (stopbits) { 186 case 2: 187 ctrl |= CTRL_TWO_STOP; 188 break; 189 case 1: 190 default: 191 ctrl &=~ CTRL_TWO_STOP; 192 } 193 194 switch (parity) { 195 case 3: /* Even parity bit */ 196 ctrl |= CTRL_PAR_EN; 197 break; 198 default: 199 ctrl &=~ CTRL_PAR_EN; 200 } 201 202 /* Set baudrate. */ 203 if (baudrate > 0) { 204 divisor = uart_mvebu_divisor(bas->rclk, baudrate); 205 if (divisor == 0) { 206 ret = EINVAL; 207 } else { 208 ccr = uart_getreg(bas, UART_CCR); 209 ccr &=~CCR_BAUDRATE_DIV; 210 211 uart_setreg(bas, UART_CCR, ccr | divisor); 212 uart_barrier(bas); 213 } 214 } 215 216 /* Set mirroring of status bits */ 217 ctrl |= CTRL_ST_MIRR_EN; 218 219 uart_setreg(bas, UART_CTRL, ctrl); 220 uart_barrier(bas); 221 222 return (ret); 223 } 224 225 static void 226 uart_mvebu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 227 int parity) 228 { 229 /* Set default frequency */ 230 bas->rclk = DEFAULT_RCLK; 231 232 /* Mask interrupts */ 233 uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) & 234 ~CTRL_INTR_MASK); 235 uart_barrier(bas); 236 237 uart_mvebu_param(bas, baudrate, databits, stopbits, parity); 238 } 239 240 static void 241 uart_mvebu_putc(struct uart_bas *bas, int c) 242 { 243 while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL) 244 ; 245 uart_setreg(bas, UART_TSH, c & 0xff); 246 } 247 248 static int 249 uart_mvebu_rxready(struct uart_bas *bas) 250 { 251 if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY) 252 return 1; 253 return 0; 254 } 255 256 static int 257 uart_mvebu_getc(struct uart_bas *bas, struct mtx *hwmtx) 258 { 259 int c; 260 261 uart_lock(hwmtx); 262 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY)) 263 ; 264 265 c = uart_getreg(bas, UART_RBR) & 0xff; 266 uart_unlock(hwmtx); 267 268 return c; 269 } 270 271 /* 272 * UART driver methods implementation. 273 */ 274 struct uart_mvebu_softc { 275 struct uart_softc base; 276 uint16_t intrm; 277 }; 278 279 static int uart_mvebu_bus_attach(struct uart_softc *); 280 static int uart_mvebu_bus_detach(struct uart_softc *); 281 static int uart_mvebu_bus_flush(struct uart_softc *, int); 282 static int uart_mvebu_bus_getsig(struct uart_softc *); 283 static int uart_mvebu_bus_ioctl(struct uart_softc *, int, intptr_t); 284 static int uart_mvebu_bus_ipend(struct uart_softc *); 285 static int uart_mvebu_bus_param(struct uart_softc *, int, int, int, int); 286 static int uart_mvebu_bus_probe(struct uart_softc *); 287 static int uart_mvebu_bus_receive(struct uart_softc *); 288 static int uart_mvebu_bus_setsig(struct uart_softc *, int); 289 static int uart_mvebu_bus_transmit(struct uart_softc *); 290 static void uart_mvebu_bus_grab(struct uart_softc *); 291 static void uart_mvebu_bus_ungrab(struct uart_softc *); 292 293 static kobj_method_t uart_mvebu_methods[] = { 294 KOBJMETHOD(uart_attach, uart_mvebu_bus_attach), 295 KOBJMETHOD(uart_detach, uart_mvebu_bus_detach), 296 KOBJMETHOD(uart_flush, uart_mvebu_bus_flush), 297 KOBJMETHOD(uart_getsig, uart_mvebu_bus_getsig), 298 KOBJMETHOD(uart_ioctl, uart_mvebu_bus_ioctl), 299 KOBJMETHOD(uart_ipend, uart_mvebu_bus_ipend), 300 KOBJMETHOD(uart_param, uart_mvebu_bus_param), 301 KOBJMETHOD(uart_probe, uart_mvebu_bus_probe), 302 KOBJMETHOD(uart_receive, uart_mvebu_bus_receive), 303 KOBJMETHOD(uart_setsig, uart_mvebu_bus_setsig), 304 KOBJMETHOD(uart_transmit, uart_mvebu_bus_transmit), 305 KOBJMETHOD(uart_grab, uart_mvebu_bus_grab), 306 KOBJMETHOD(uart_ungrab, uart_mvebu_bus_ungrab), 307 { 0, 0 } 308 }; 309 310 struct uart_class uart_mvebu_class = { 311 "mvebu-uart", 312 uart_mvebu_methods, 313 sizeof(struct uart_mvebu_softc), 314 .uc_ops = &uart_mvebu_ops, 315 .uc_range = 0x14, 316 .uc_rclk = DEFAULT_RCLK, 317 .uc_rshift = 0, 318 .uc_riowidth = 4 319 }; 320 321 static struct ofw_compat_data compat_data[] = { 322 {"marvell,armada-3700-uart", (uintptr_t)&uart_mvebu_class}, 323 {NULL, (uintptr_t)NULL}, 324 }; 325 UART_FDT_CLASS_AND_DEVICE(compat_data); 326 327 static int 328 uart_mvebu_bus_attach(struct uart_softc *sc) 329 { 330 struct uart_bas *bas; 331 int ctrl; 332 333 bas = &sc->sc_bas; 334 uart_lock(sc->sc_hwmtx); 335 336 ctrl = uart_getreg(bas, UART_CTRL); 337 338 /* Enable interrupts */ 339 ctrl &=~ CTRL_INTR_MASK; 340 ctrl |= CTRL_IPEND_MASK; 341 342 /* Set interrupts */ 343 uart_setreg(bas, UART_CTRL, ctrl); 344 uart_barrier(bas); 345 346 uart_unlock(sc->sc_hwmtx); 347 348 return (0); 349 } 350 351 static int 352 uart_mvebu_bus_detach(struct uart_softc *sc) 353 { 354 355 return (0); 356 } 357 358 static int 359 uart_mvebu_bus_flush(struct uart_softc *sc, int what) 360 { 361 struct uart_bas *bas; 362 int ctrl, ret = 0; 363 364 bas = &sc->sc_bas; 365 uart_lock(sc->sc_hwmtx); 366 ctrl = uart_getreg(bas, UART_CTRL); 367 368 switch (what) { 369 case UART_FLUSH_RECEIVER: 370 uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST); 371 uart_barrier(bas); 372 break; 373 374 case UART_FLUSH_TRANSMITTER: 375 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST); 376 uart_barrier(bas); 377 break; 378 379 default: 380 ret = EINVAL; 381 break; 382 } 383 384 /* Back to normal operation */ 385 if (!ret) { 386 uart_setreg(bas, UART_CTRL, ctrl); 387 uart_barrier(bas); 388 } 389 390 uart_unlock(sc->sc_hwmtx); 391 return (ret); 392 } 393 394 static int 395 uart_mvebu_bus_getsig(struct uart_softc *sc) 396 { 397 398 return (0); 399 } 400 401 static int 402 uart_mvebu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 403 { 404 struct uart_bas *bas; 405 int ctrl, ret = 0; 406 int divisor, baudrate; 407 408 bas = &sc->sc_bas; 409 uart_lock(sc->sc_hwmtx); 410 switch (request) { 411 case UART_IOCTL_BREAK: 412 ctrl = uart_getreg(bas, UART_CTRL); 413 if (data) 414 ctrl |= CTRL_SND_BRK_SEQ; 415 else 416 ctrl &=~ CTRL_SND_BRK_SEQ; 417 uart_setreg(bas, UART_CTRL, ctrl); 418 uart_barrier(bas); 419 break; 420 421 case UART_IOCTL_BAUD: 422 divisor = uart_getreg(bas, UART_CCR) & CCR_BAUDRATE_DIV; 423 baudrate = bas->rclk/(divisor * 16); 424 *(int *)data = baudrate; 425 break; 426 427 default: 428 ret = ENOTTY; 429 break; 430 } 431 uart_unlock(sc->sc_hwmtx); 432 433 return (ret); 434 } 435 436 static int 437 uart_mvebu_bus_ipend(struct uart_softc *sc) 438 { 439 struct uart_bas *bas; 440 int ipend, ctrl, ret = 0; 441 442 bas = &sc->sc_bas; 443 uart_lock(sc->sc_hwmtx); 444 ipend = uart_getreg(bas, UART_STAT); 445 ctrl = uart_getreg(bas, UART_CTRL); 446 447 if (((ipend & STAT_TX_IDLE) == STAT_TX_IDLE) && 448 (ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) { 449 /* Disable TX IDLE Interrupt generation */ 450 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT); 451 uart_barrier(bas); 452 453 /* SER_INT_TXIDLE means empty TX FIFO. Wait until it cleans */ 454 while(!(uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_EMPT)) 455 DELAY(ONE_FRAME_TIME/2); 456 457 ret |= SER_INT_TXIDLE; 458 } 459 460 ret |= stat_ipend_trans(ipend & STAT_TRANS_MASK); 461 462 uart_unlock(sc->sc_hwmtx); 463 464 return (ret); 465 } 466 467 static int 468 uart_mvebu_bus_param(struct uart_softc *sc, int baudrate, int databits, 469 int stopbits, int parity) 470 { 471 int ret; 472 473 uart_lock(sc->sc_hwmtx); 474 ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 475 uart_unlock(sc->sc_hwmtx); 476 477 return (ret); 478 } 479 480 static int 481 uart_mvebu_bus_probe(struct uart_softc *sc) 482 { 483 if (!ofw_bus_status_okay(sc->sc_dev)) 484 return (ENXIO); 485 486 if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data) 487 return (ENXIO); 488 489 device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART"); 490 491 sc->sc_txfifosz = 32; 492 sc->sc_rxfifosz = 64; 493 sc->sc_hwiflow = 0; 494 sc->sc_hwoflow = 0; 495 496 return (0); 497 } 498 499 int 500 uart_mvebu_bus_receive(struct uart_softc *sc) 501 { 502 struct uart_bas *bas; 503 uint32_t xc; 504 int rx, er; 505 506 bas = &sc->sc_bas; 507 uart_lock(sc->sc_hwmtx); 508 509 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) { 510 if (uart_rx_full(sc)) { 511 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 512 break; 513 } 514 515 xc = uart_getreg(bas, UART_RBR); 516 rx = xc & 0xff; 517 er = xc & 0xf000; 518 /* 519 * Formula which translates marvell error bits 520 * Only valid when CTRL_ST_MIRR_EN is set 521 */ 522 er = (er & RBR_BRK_DET) >> 7 | 523 (er & RBR_FRM_ERR_DET) >> 5 | 524 (er & RBR_PAR_ERR_DET) >> 2 | 525 (er & RBR_OVR_ERR_DET) >> 2; 526 527 uart_rx_put(sc, rx | er); 528 uart_barrier(bas); 529 } 530 /* 531 * uart_if.m says that receive interrupt 532 * should be cleared, so we need to reset 533 * RX FIFO 534 */ 535 536 if (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) { 537 uart_mvebu_bus_flush(sc, UART_FLUSH_RECEIVER); 538 } 539 540 uart_unlock(sc->sc_hwmtx); 541 return (0); 542 } 543 544 static int 545 uart_mvebu_bus_setsig(struct uart_softc *sc, int sig) 546 { 547 /* Not supported by hardware */ 548 return (0); 549 } 550 551 int 552 uart_mvebu_bus_transmit(struct uart_softc *sc) 553 { 554 struct uart_bas *bas; 555 int i, ctrl; 556 557 bas = &sc->sc_bas; 558 uart_lock(sc->sc_hwmtx); 559 560 /* Turn off all interrupts during send */ 561 ctrl = uart_getreg(bas, UART_CTRL); 562 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); 563 uart_barrier(bas); 564 565 for (i = 0; i < sc->sc_txdatasz; i++) { 566 uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff); 567 uart_barrier(bas); 568 } 569 570 /* 571 * Make sure that interrupt is generated 572 * when FIFO can get more data. 573 */ 574 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT); 575 uart_barrier(bas); 576 577 /* Mark busy */ 578 sc->sc_txbusy = 1; 579 580 uart_unlock(sc->sc_hwmtx); 581 return (0); 582 } 583 584 static void 585 uart_mvebu_bus_grab(struct uart_softc *sc) 586 { 587 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc; 588 struct uart_bas *bas = &sc->sc_bas; 589 uint32_t ctrl; 590 591 /* Mask all interrupts */ 592 uart_lock(sc->sc_hwmtx); 593 ctrl = uart_getreg(bas, UART_CTRL); 594 msc->intrm = ctrl & CTRL_INTR_MASK; 595 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); 596 uart_barrier(bas); 597 uart_unlock(sc->sc_hwmtx); 598 } 599 600 static void 601 uart_mvebu_bus_ungrab(struct uart_softc *sc) 602 { 603 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc; 604 struct uart_bas *bas = &sc->sc_bas; 605 uint32_t ctrl; 606 607 /* Restore interrupts */ 608 uart_lock(sc->sc_hwmtx); 609 ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK; 610 uart_setreg(bas, UART_CTRL, ctrl | msc->intrm); 611 uart_barrier(bas); 612 uart_unlock(sc->sc_hwmtx); 613 } 614