1 /*- 2 * Copyright (c) 2017 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/conf.h> 31 #include <sys/kernel.h> 32 #include <sys/sysctl.h> 33 #include <sys/systm.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/ofw/ofw_bus_subr.h> 38 #include <dev/uart/uart.h> 39 #include <dev/uart/uart_bus.h> 40 #include <dev/uart/uart_cpu.h> 41 #include <dev/uart/uart_cpu_fdt.h> 42 43 #include "uart_if.h" 44 45 #define UART_RBR 0x00 /* Receiver Buffer */ 46 #define RBR_BRK_DET (1 << 15) /* Break Detect */ 47 #define RBR_FRM_ERR_DET (1 << 14) /* Frame Error Detect */ 48 #define RBR_PAR_ERR_DET (1 << 13) /* Parity Error Detect */ 49 #define RBR_OVR_ERR_DET (1 << 12) /* Overrun Error */ 50 51 #define UART_TSH 0x04 /* Transmitter Holding Register */ 52 53 #define UART_CTRL 0x08 /* Control Register */ 54 #define CTRL_SOFT_RST (1 << 31) /* Soft Reset */ 55 #define CTRL_TX_FIFO_RST (1 << 15) /* TX FIFO Reset */ 56 #define CTRL_RX_FIFO_RST (1 << 14) /* RX FIFO Reset */ 57 #define CTRL_ST_MIRR_EN (1 << 13) /* Status Mirror Enable */ 58 #define CTRL_LPBK_EN (1 << 12) /* Loopback Mode Enable */ 59 #define CTRL_SND_BRK_SEQ (1 << 11) /* Send Break Sequence */ 60 #define CTRL_PAR_EN (1 << 10) /* Parity Enable */ 61 #define CTRL_TWO_STOP (1 << 9) /* Two Stop Bits */ 62 #define CTRL_TX_HALF_INT (1 << 8) /* TX Half-Full Interrupt Enable */ 63 #define CTRL_RX_HALF_INT (1 << 7) /* RX Half-Full Interrupt Enable */ 64 #define CTRL_TX_EMPT_INT (1 << 6) /* TX Empty Interrupt Enable */ 65 #define CTRL_TX_RDY_INT (1 << 5) /* TX Ready Interrupt Enable */ 66 #define CTRL_RX_RDY_INT (1 << 4) /* RX Ready Interrupt Enable */ 67 #define CTRL_BRK_DET_INT (1 << 3) /* Break Detect Interrupt Enable */ 68 #define CTRL_FRM_ERR_INT (1 << 2) /* Frame Error Interrupt Enable */ 69 #define CTRL_PAR_ERR_INT (1 << 1) /* Parity Error Interrupt Enable */ 70 #define CTRL_OVR_ERR_INT (1 << 0) /* Overrun Error Interrupt Enable */ 71 #define CTRL_INTR_MASK 0x1ff 72 #define CTRL_TX_IDLE_INT CTRL_TX_RDY_INT 73 #define CTRL_IPEND_MASK (CTRL_OVR_ERR_INT | CTRL_BRK_DET_INT | \ 74 CTRL_RX_RDY_INT) 75 76 #define UART_STAT 0x0c /* Status Register */ 77 #define STAT_TX_FIFO_EMPT (1 << 13) /* TX FIFO Empty */ 78 #define STAT_RX_FIFO_EMPT (1 << 12) /* RX FIFO Empty */ 79 #define STAT_TX_FIFO_FULL (1 << 11) /* TX FIFO Full */ 80 #define STAT_TX_FIFO_HALF (1 << 10) /* TX FIFO Half Full */ 81 #define STAT_RX_TOGL (1 << 9) /* RX Toogled */ 82 #define STAT_RX_FIFO_FULL (1 << 8) /* RX FIFO Full */ 83 #define STAT_RX_FIFO_HALF (1 << 7) /* RX FIFO Half Full */ 84 #define STAT_TX_EMPT (1 << 6) /* TX Empty */ 85 #define STAT_TX_RDY (1 << 5) /* TX Ready */ 86 #define STAT_RX_RDY (1 << 4) /* RX Ready */ 87 #define STAT_BRK_DET (1 << 3) /* Break Detect */ 88 #define STAT_FRM_ERR (1 << 2) /* Frame Error */ 89 #define STAT_PAR_ERR (1 << 1) /* Parity Error */ 90 #define STAT_OVR_ERR (1 << 0) /* Overrun Error */ 91 #define STAT_TX_IDLE STAT_TX_RDY 92 #define STAT_TRANS_MASK (STAT_OVR_ERR | STAT_BRK_DET | STAT_RX_RDY) 93 94 #define UART_CCR 0x10 /* Clock Control Register */ 95 #define CCR_BAUDRATE_DIV 0x3ff /* Baud Rate Divisor */ 96 97 #define DEFAULT_RCLK 25804800 98 #define ONE_FRAME_TIME 87 99 100 #define stat_ipend_trans(i) ( \ 101 (i & STAT_OVR_ERR) << 16 | \ 102 (i & STAT_BRK_DET) << 14 | \ 103 (i & STAT_RX_RDY) << 14) 104 105 /* 106 * For debugging purposes 107 */ 108 #if 0 109 #ifdef EARLY_PRINTF 110 #if defined(SOCDEV_PA) && defined(SOCDEV_VA) 111 #define UART_REG_OFFSET 0x12000 112 static void 113 uart_mvebu_early_putc(int c) 114 { 115 volatile uint32_t *tsh; 116 volatile uint32_t *stat; 117 118 tsh = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_TSH); 119 stat = (uint32_t *)(SOCDEV_VA + UART_REG_OFFSET + UART_STAT); 120 121 while(!(*stat & STAT_TX_RDY)) 122 ; 123 124 *tsh = c & 0xff; 125 } 126 127 early_putc_t *early_putc = uart_mvebu_early_putc; 128 #endif 129 #endif 130 #endif 131 132 /* 133 * Low-level UART interface. 134 */ 135 static int uart_mvebu_probe(struct uart_bas *); 136 static void uart_mvebu_init(struct uart_bas *, int, int, int, int); 137 static void uart_mvebu_putc(struct uart_bas *, int); 138 static int uart_mvebu_rxready(struct uart_bas *); 139 static int uart_mvebu_getc(struct uart_bas *, struct mtx *); 140 141 static struct uart_ops uart_mvebu_ops = { 142 .probe = uart_mvebu_probe, 143 .init = uart_mvebu_init, 144 .term = NULL, 145 .putc = uart_mvebu_putc, 146 .rxready = uart_mvebu_rxready, 147 .getc = uart_mvebu_getc, 148 }; 149 150 static int 151 uart_mvebu_probe(struct uart_bas *bas) 152 { 153 154 return (0); 155 } 156 157 static int 158 uart_mvebu_divisor(int rclk, int baudrate) 159 { 160 int divisor; 161 162 if (baudrate == 0) 163 return (0); 164 165 divisor = (rclk >> 4) / baudrate; 166 if (divisor <= 1 || divisor >= 1024) 167 return (0); 168 169 return (divisor); 170 } 171 172 static int 173 uart_mvebu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 174 int parity) 175 { 176 uint32_t ctrl = 0; 177 uint32_t ccr; 178 int divisor, ret = 0; 179 180 /* Reset UART */ 181 ctrl = uart_getreg(bas, UART_CTRL); 182 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | 183 CTRL_LPBK_EN); 184 uart_barrier(bas); 185 186 switch (stopbits) { 187 case 2: 188 ctrl |= CTRL_TWO_STOP; 189 break; 190 case 1: 191 default: 192 ctrl &=~ CTRL_TWO_STOP; 193 } 194 195 switch (parity) { 196 case 3: /* Even parity bit */ 197 ctrl |= CTRL_PAR_EN; 198 break; 199 default: 200 ctrl &=~ CTRL_PAR_EN; 201 } 202 203 /* Set baudrate. */ 204 if (baudrate > 0) { 205 divisor = uart_mvebu_divisor(bas->rclk, baudrate); 206 if (divisor == 0) { 207 ret = EINVAL; 208 } else { 209 ccr = uart_getreg(bas, UART_CCR); 210 ccr &=~CCR_BAUDRATE_DIV; 211 212 uart_setreg(bas, UART_CCR, ccr | divisor); 213 uart_barrier(bas); 214 } 215 } 216 217 /* Set mirroring of status bits */ 218 ctrl |= CTRL_ST_MIRR_EN; 219 220 uart_setreg(bas, UART_CTRL, ctrl); 221 uart_barrier(bas); 222 223 return (ret); 224 } 225 226 static void 227 uart_mvebu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 228 int parity) 229 { 230 /* Set default frequency */ 231 bas->rclk = DEFAULT_RCLK; 232 233 /* Mask interrupts */ 234 uart_setreg(bas, UART_CTRL, uart_getreg(bas, UART_CTRL) & 235 ~CTRL_INTR_MASK); 236 uart_barrier(bas); 237 238 uart_mvebu_param(bas, baudrate, databits, stopbits, parity); 239 } 240 241 static void 242 uart_mvebu_putc(struct uart_bas *bas, int c) 243 { 244 while (uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_FULL) 245 ; 246 uart_setreg(bas, UART_TSH, c & 0xff); 247 } 248 249 static int 250 uart_mvebu_rxready(struct uart_bas *bas) 251 { 252 if (uart_getreg(bas, UART_STAT) & STAT_RX_RDY) 253 return 1; 254 return 0; 255 } 256 257 static int 258 uart_mvebu_getc(struct uart_bas *bas, struct mtx *hwmtx) 259 { 260 int c; 261 262 uart_lock(hwmtx); 263 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_RDY)) 264 ; 265 266 c = uart_getreg(bas, UART_RBR) & 0xff; 267 uart_unlock(hwmtx); 268 269 return c; 270 } 271 272 /* 273 * UART driver methods implementation. 274 */ 275 struct uart_mvebu_softc { 276 struct uart_softc base; 277 uint16_t intrm; 278 }; 279 280 static int uart_mvebu_bus_attach(struct uart_softc *); 281 static int uart_mvebu_bus_detach(struct uart_softc *); 282 static int uart_mvebu_bus_flush(struct uart_softc *, int); 283 static int uart_mvebu_bus_getsig(struct uart_softc *); 284 static int uart_mvebu_bus_ioctl(struct uart_softc *, int, intptr_t); 285 static int uart_mvebu_bus_ipend(struct uart_softc *); 286 static int uart_mvebu_bus_param(struct uart_softc *, int, int, int, int); 287 static int uart_mvebu_bus_probe(struct uart_softc *); 288 static int uart_mvebu_bus_receive(struct uart_softc *); 289 static int uart_mvebu_bus_setsig(struct uart_softc *, int); 290 static int uart_mvebu_bus_transmit(struct uart_softc *); 291 static void uart_mvebu_bus_grab(struct uart_softc *); 292 static void uart_mvebu_bus_ungrab(struct uart_softc *); 293 294 static kobj_method_t uart_mvebu_methods[] = { 295 KOBJMETHOD(uart_attach, uart_mvebu_bus_attach), 296 KOBJMETHOD(uart_detach, uart_mvebu_bus_detach), 297 KOBJMETHOD(uart_flush, uart_mvebu_bus_flush), 298 KOBJMETHOD(uart_getsig, uart_mvebu_bus_getsig), 299 KOBJMETHOD(uart_ioctl, uart_mvebu_bus_ioctl), 300 KOBJMETHOD(uart_ipend, uart_mvebu_bus_ipend), 301 KOBJMETHOD(uart_param, uart_mvebu_bus_param), 302 KOBJMETHOD(uart_probe, uart_mvebu_bus_probe), 303 KOBJMETHOD(uart_receive, uart_mvebu_bus_receive), 304 KOBJMETHOD(uart_setsig, uart_mvebu_bus_setsig), 305 KOBJMETHOD(uart_transmit, uart_mvebu_bus_transmit), 306 KOBJMETHOD(uart_grab, uart_mvebu_bus_grab), 307 KOBJMETHOD(uart_ungrab, uart_mvebu_bus_ungrab), 308 { 0, 0 } 309 }; 310 311 struct uart_class uart_mvebu_class = { 312 "mvebu-uart", 313 uart_mvebu_methods, 314 sizeof(struct uart_mvebu_softc), 315 .uc_ops = &uart_mvebu_ops, 316 .uc_range = 0x14, 317 .uc_rclk = DEFAULT_RCLK, 318 .uc_rshift = 0, 319 .uc_riowidth = 4 320 }; 321 322 static struct ofw_compat_data compat_data[] = { 323 {"marvell,armada-3700-uart", (uintptr_t)&uart_mvebu_class}, 324 {NULL, (uintptr_t)NULL}, 325 }; 326 UART_FDT_CLASS_AND_DEVICE(compat_data); 327 328 static int 329 uart_mvebu_bus_attach(struct uart_softc *sc) 330 { 331 struct uart_bas *bas; 332 int ctrl; 333 334 bas = &sc->sc_bas; 335 uart_lock(sc->sc_hwmtx); 336 337 ctrl = uart_getreg(bas, UART_CTRL); 338 339 /* Enable interrupts */ 340 ctrl &=~ CTRL_INTR_MASK; 341 ctrl |= CTRL_IPEND_MASK; 342 343 /* Set interrupts */ 344 uart_setreg(bas, UART_CTRL, ctrl); 345 uart_barrier(bas); 346 347 uart_unlock(sc->sc_hwmtx); 348 349 return (0); 350 } 351 352 static int 353 uart_mvebu_bus_detach(struct uart_softc *sc) 354 { 355 356 return (0); 357 } 358 359 static int 360 uart_mvebu_bus_flush(struct uart_softc *sc, int what) 361 { 362 struct uart_bas *bas; 363 int ctrl, ret = 0; 364 365 bas = &sc->sc_bas; 366 uart_lock(sc->sc_hwmtx); 367 ctrl = uart_getreg(bas, UART_CTRL); 368 369 switch (what) { 370 case UART_FLUSH_RECEIVER: 371 uart_setreg(bas, UART_CTRL, ctrl | CTRL_RX_FIFO_RST); 372 uart_barrier(bas); 373 break; 374 375 case UART_FLUSH_TRANSMITTER: 376 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_FIFO_RST); 377 uart_barrier(bas); 378 break; 379 380 default: 381 ret = EINVAL; 382 break; 383 } 384 385 /* Back to normal operation */ 386 if (!ret) { 387 uart_setreg(bas, UART_CTRL, ctrl); 388 uart_barrier(bas); 389 } 390 391 uart_unlock(sc->sc_hwmtx); 392 return (ret); 393 } 394 395 static int 396 uart_mvebu_bus_getsig(struct uart_softc *sc) 397 { 398 399 return (0); 400 } 401 402 static int 403 uart_mvebu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 404 { 405 struct uart_bas *bas; 406 int ctrl, ret = 0; 407 int divisor, baudrate; 408 409 bas = &sc->sc_bas; 410 uart_lock(sc->sc_hwmtx); 411 switch (request) { 412 case UART_IOCTL_BREAK: 413 ctrl = uart_getreg(bas, UART_CTRL); 414 if (data) 415 ctrl |= CTRL_SND_BRK_SEQ; 416 else 417 ctrl &=~ CTRL_SND_BRK_SEQ; 418 uart_setreg(bas, UART_CTRL, ctrl); 419 uart_barrier(bas); 420 break; 421 422 case UART_IOCTL_BAUD: 423 divisor = uart_getreg(bas, UART_CCR) & CCR_BAUDRATE_DIV; 424 baudrate = bas->rclk/(divisor * 16); 425 *(int *)data = baudrate; 426 break; 427 428 default: 429 ret = ENOTTY; 430 break; 431 } 432 uart_unlock(sc->sc_hwmtx); 433 434 return (ret); 435 } 436 437 static int 438 uart_mvebu_bus_ipend(struct uart_softc *sc) 439 { 440 struct uart_bas *bas; 441 int ipend, ctrl, ret = 0; 442 443 bas = &sc->sc_bas; 444 uart_lock(sc->sc_hwmtx); 445 ipend = uart_getreg(bas, UART_STAT); 446 ctrl = uart_getreg(bas, UART_CTRL); 447 448 if (((ipend & STAT_TX_IDLE) == STAT_TX_IDLE) && 449 (ctrl & CTRL_TX_IDLE_INT) == CTRL_TX_IDLE_INT) { 450 /* Disable TX IDLE Interrupt generation */ 451 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_TX_IDLE_INT); 452 uart_barrier(bas); 453 454 /* SER_INT_TXIDLE means empty TX FIFO. Wait until it cleans */ 455 while(!(uart_getreg(bas, UART_STAT) & STAT_TX_FIFO_EMPT)) 456 DELAY(ONE_FRAME_TIME/2); 457 458 ret |= SER_INT_TXIDLE; 459 } 460 461 ret |= stat_ipend_trans(ipend & STAT_TRANS_MASK); 462 463 uart_unlock(sc->sc_hwmtx); 464 465 return (ret); 466 } 467 468 static int 469 uart_mvebu_bus_param(struct uart_softc *sc, int baudrate, int databits, 470 int stopbits, int parity) 471 { 472 int ret; 473 474 uart_lock(sc->sc_hwmtx); 475 ret = uart_mvebu_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 476 uart_unlock(sc->sc_hwmtx); 477 478 return (ret); 479 } 480 481 static int 482 uart_mvebu_bus_probe(struct uart_softc *sc) 483 { 484 if (!ofw_bus_status_okay(sc->sc_dev)) 485 return (ENXIO); 486 487 if (!ofw_bus_search_compatible(sc->sc_dev, compat_data)->ocd_data) 488 return (ENXIO); 489 490 device_set_desc(sc->sc_dev, "Marvell Armada 3700 UART"); 491 492 sc->sc_txfifosz = 32; 493 sc->sc_rxfifosz = 64; 494 sc->sc_hwiflow = 0; 495 sc->sc_hwoflow = 0; 496 497 return (0); 498 } 499 500 int 501 uart_mvebu_bus_receive(struct uart_softc *sc) 502 { 503 struct uart_bas *bas; 504 uint32_t xc; 505 int rx, er; 506 507 bas = &sc->sc_bas; 508 uart_lock(sc->sc_hwmtx); 509 510 while (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) { 511 if (uart_rx_full(sc)) { 512 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 513 break; 514 } 515 516 xc = uart_getreg(bas, UART_RBR); 517 rx = xc & 0xff; 518 er = xc & 0xf000; 519 /* 520 * Formula which translates marvell error bits 521 * Only valid when CTRL_ST_MIRR_EN is set 522 */ 523 er = (er & RBR_BRK_DET) >> 7 | 524 (er & RBR_FRM_ERR_DET) >> 5 | 525 (er & RBR_PAR_ERR_DET) >> 2 | 526 (er & RBR_OVR_ERR_DET) >> 2; 527 528 uart_rx_put(sc, rx | er); 529 uart_barrier(bas); 530 } 531 /* 532 * uart_if.m says that receive interrupt 533 * should be cleared, so we need to reset 534 * RX FIFO 535 */ 536 537 if (!(uart_getreg(bas, UART_STAT) & STAT_RX_FIFO_EMPT)) { 538 uart_mvebu_bus_flush(sc, UART_FLUSH_RECEIVER); 539 } 540 541 uart_unlock(sc->sc_hwmtx); 542 return (0); 543 } 544 545 static int 546 uart_mvebu_bus_setsig(struct uart_softc *sc, int sig) 547 { 548 /* Not supported by hardware */ 549 return (0); 550 } 551 552 int 553 uart_mvebu_bus_transmit(struct uart_softc *sc) 554 { 555 struct uart_bas *bas; 556 int i, ctrl; 557 558 bas = &sc->sc_bas; 559 uart_lock(sc->sc_hwmtx); 560 561 /* Turn off all interrupts during send */ 562 ctrl = uart_getreg(bas, UART_CTRL); 563 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); 564 uart_barrier(bas); 565 566 for (i = 0; i < sc->sc_txdatasz; i++) { 567 uart_setreg(bas, UART_TSH, sc->sc_txbuf[i] & 0xff); 568 uart_barrier(bas); 569 } 570 571 /* 572 * Make sure that interrupt is generated 573 * when FIFO can get more data. 574 */ 575 uart_setreg(bas, UART_CTRL, ctrl | CTRL_TX_IDLE_INT); 576 uart_barrier(bas); 577 578 /* Mark busy */ 579 sc->sc_txbusy = 1; 580 581 uart_unlock(sc->sc_hwmtx); 582 return (0); 583 } 584 585 static void 586 uart_mvebu_bus_grab(struct uart_softc *sc) 587 { 588 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc; 589 struct uart_bas *bas = &sc->sc_bas; 590 uint32_t ctrl; 591 592 /* Mask all interrupts */ 593 uart_lock(sc->sc_hwmtx); 594 ctrl = uart_getreg(bas, UART_CTRL); 595 msc->intrm = ctrl & CTRL_INTR_MASK; 596 uart_setreg(bas, UART_CTRL, ctrl & ~CTRL_INTR_MASK); 597 uart_barrier(bas); 598 uart_unlock(sc->sc_hwmtx); 599 } 600 601 static void 602 uart_mvebu_bus_ungrab(struct uart_softc *sc) 603 { 604 struct uart_mvebu_softc *msc = (struct uart_mvebu_softc *)sc; 605 struct uart_bas *bas = &sc->sc_bas; 606 uint32_t ctrl; 607 608 /* Restore interrupts */ 609 uart_lock(sc->sc_hwmtx); 610 ctrl = uart_getreg(bas, UART_CTRL) & ~CTRL_INTR_MASK; 611 uart_setreg(bas, UART_CTRL, ctrl | msc->intrm); 612 uart_barrier(bas); 613 uart_unlock(sc->sc_hwmtx); 614 } 615