1 /*- 2 * Copyright (c) 2018 Diane Bruce 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * Based on uart_dev_pl011.c 28 * Copyright (c) 2012 Semihalf. 29 * All rights reserved. 30 */ 31 /* 32 * The mini Uart has the following features: 33 * - 7 or 8 bit operation. 34 * - 1 start and 1 stop bit. 35 * - No parities. 36 * - Break generation. 37 * - 8 symbols deep FIFOs for receive and transmit. 38 * - SW controlled RTS, SW readable CTS. 39 * - Auto flow control with programmable FIFO level. 40 * - 16550 like registers. 41 * - Baudrate derived from system clock. 42 * This is a mini UART and it does NOT have the following capabilities: 43 * - Break detection 44 * - Framing errors detection. 45 * - Parity bit 46 * - Receive Time-out interrupt 47 * - DCD, DSR, DTR or RI signals. 48 * The implemented UART is not a 16650 compatible UART However as far 49 * as possible the first 8 control and status registers are laid out 50 * like a 16550 UART. All 16550 register bits which are not supported can 51 * be written but will be ignored and read back as 0. All control bits 52 * for simple UART receive/transmit operations are available. 53 */ 54 55 #include "opt_acpi.h" 56 #include "opt_platform.h" 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/kernel.h> 61 #include <sys/bus.h> 62 63 #include <machine/bus.h> 64 #include <machine/machdep.h> 65 #include <machine/pcpu.h> 66 67 #include <dev/uart/uart.h> 68 #include <dev/uart/uart_cpu.h> 69 #ifdef FDT 70 #include <dev/uart/uart_cpu_fdt.h> 71 #include <dev/ofw/ofw_bus.h> 72 #endif 73 #include <dev/uart/uart_bus.h> 74 #include "uart_if.h" 75 76 /* BCM2835 Micro UART registers and masks*/ 77 #define AUX_MU_IO_REG 0x00 /* I/O register */ 78 79 /* 80 * According to errata bits 1 and 2 are swapped, 81 * Also bits 2 and 3 are required to enable interrupts. 82 */ 83 #define AUX_MU_IER_REG 0x01 84 #define IER_RXENABLE (1) 85 #define IER_TXENABLE (1<<1) 86 #define IER_REQUIRED (3<<2) 87 #define IER_MASK_ALL (IER_TXENABLE|IER_RXENABLE) 88 89 #define AUX_MU_IIR_REG 0x02 90 #define IIR_READY (1) 91 #define IIR_TXREADY (1<<1) 92 #define IIR_RXREADY (1<<2) 93 #define IIR_CLEAR (3<<1) 94 95 #define AUX_MU_LCR_REG 0x03 96 #define LCR_WLEN7 (0) 97 #define LCR_WLEN8 (3) 98 99 #define AUX_MU_MCR_REG 0x04 100 #define AUX_MCR_RTS (1<<1) 101 102 #define AUX_MU_LSR_REG 0x05 103 #define LSR_RXREADY (1) 104 #define LSR_OVRRUN (1<<1) 105 #define LSR_TXEMPTY (1<<5) 106 #define LSR_TXIDLE (1<<6) 107 108 #define AUX_MU_MSR_REG 0x06 109 #define MSR_CTS (1<<5) 110 111 #define AUX_MU_SCRATCH_REG 0x07 112 113 #define AUX_MU_CNTL_REG 0x08 114 #define CNTL_RXENAB (1) 115 #define CNTL_TXENAB (1<<1) 116 117 #define AUX_MU_STAT_REG 0x09 118 #define STAT_TX_SA (1<<1) 119 #define STAT_RX_SA (1) 120 121 #define AUX_MU_BAUD_REG 0x0a 122 123 /* 124 * FIXME: actual register size is SoC-dependent, we need to handle it 125 */ 126 #define __uart_getreg(bas, reg) \ 127 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 128 #define __uart_setreg(bas, reg, value) \ 129 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 130 131 /* 132 * Low-level UART interface. 133 */ 134 static int uart_mu_probe(struct uart_bas *bas); 135 static void uart_mu_init(struct uart_bas *bas, int, int, int, int); 136 static void uart_mu_term(struct uart_bas *bas); 137 static void uart_mu_putc(struct uart_bas *bas, int); 138 static int uart_mu_rxready(struct uart_bas *bas); 139 static int uart_mu_getc(struct uart_bas *bas, struct mtx *); 140 141 static struct uart_ops uart_mu_ops = { 142 .probe = uart_mu_probe, 143 .init = uart_mu_init, 144 .term = uart_mu_term, 145 .putc = uart_mu_putc, 146 .rxready = uart_mu_rxready, 147 .getc = uart_mu_getc, 148 }; 149 150 static int 151 uart_mu_probe(struct uart_bas *bas) 152 { 153 154 return (0); 155 } 156 157 /* 158 * According to the docs, the cpu clock is locked to 250Mhz when 159 * the micro-uart is used 160 */ 161 #define CPU_CLOCK 250000000 162 163 static void 164 uart_mu_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 165 int parity) 166 { 167 uint32_t line; 168 uint32_t baud; 169 170 /* 171 * Zero all settings to make sure 172 * UART is disabled and not configured 173 */ 174 line = 0x0; 175 __uart_setreg(bas, AUX_MU_CNTL_REG, line); 176 177 /* As I know UART is disabled I can setup the line */ 178 switch (databits) { 179 case 7: 180 line |= LCR_WLEN7; 181 break; 182 case 6: 183 case 8: 184 default: 185 line |= LCR_WLEN8; 186 break; 187 } 188 189 __uart_setreg(bas, AUX_MU_LCR_REG, line); 190 191 /* See 2.2.1 BCM2835-ARM-Peripherals baudrate */ 192 if (baudrate != 0) { 193 baud = CPU_CLOCK / (8 * baudrate); 194 /* XXX 195 * baud = cpu_clock() / (8 * baudrate); 196 */ 197 __uart_setreg(bas, AUX_MU_BAUD_REG, ((uint32_t)(baud & 0xFFFF))); 198 } 199 200 /* re-enable UART */ 201 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB); 202 } 203 204 static void 205 uart_mu_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 206 int parity) 207 { 208 209 /* Mask all interrupts */ 210 __uart_setreg(bas, AUX_MU_IER_REG, 0); 211 uart_mu_param(bas, baudrate, databits, stopbits, parity); 212 } 213 214 static void 215 uart_mu_term(struct uart_bas *bas) 216 { 217 } 218 219 static void 220 uart_mu_putc(struct uart_bas *bas, int c) 221 { 222 223 /* Wait when TX FIFO full. Push character otherwise. */ 224 while ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXEMPTY) == 0) 225 ; 226 __uart_setreg(bas, AUX_MU_IO_REG, c & 0xff); 227 } 228 229 static int 230 uart_mu_rxready(struct uart_bas *bas) 231 { 232 233 return ((__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_RXREADY) != 0); 234 } 235 236 static int 237 uart_mu_getc(struct uart_bas *bas, struct mtx *hwmtx) 238 { 239 int c; 240 241 while(!uart_mu_rxready(bas)) 242 ; 243 c = __uart_getreg(bas, AUX_MU_IO_REG) & 0xff; 244 return (c); 245 } 246 247 /* 248 * High-level UART interface. 249 */ 250 struct uart_mu_softc { 251 struct uart_softc bas; 252 uint16_t aux_ier; /* Interrupt mask */ 253 }; 254 255 static int uart_mu_bus_attach(struct uart_softc *); 256 static int uart_mu_bus_detach(struct uart_softc *); 257 static int uart_mu_bus_flush(struct uart_softc *, int); 258 static int uart_mu_bus_getsig(struct uart_softc *); 259 static int uart_mu_bus_ioctl(struct uart_softc *, int, intptr_t); 260 static int uart_mu_bus_ipend(struct uart_softc *); 261 static int uart_mu_bus_param(struct uart_softc *, int, int, int, int); 262 static int uart_mu_bus_probe(struct uart_softc *); 263 static int uart_mu_bus_receive(struct uart_softc *); 264 static int uart_mu_bus_setsig(struct uart_softc *, int); 265 static int uart_mu_bus_transmit(struct uart_softc *); 266 static void uart_mu_bus_grab(struct uart_softc *); 267 static void uart_mu_bus_ungrab(struct uart_softc *); 268 269 static kobj_method_t uart_mu_methods[] = { 270 KOBJMETHOD(uart_attach, uart_mu_bus_attach), 271 KOBJMETHOD(uart_detach, uart_mu_bus_detach), 272 KOBJMETHOD(uart_flush, uart_mu_bus_flush), 273 KOBJMETHOD(uart_getsig, uart_mu_bus_getsig), 274 KOBJMETHOD(uart_ioctl, uart_mu_bus_ioctl), 275 KOBJMETHOD(uart_ipend, uart_mu_bus_ipend), 276 KOBJMETHOD(uart_param, uart_mu_bus_param), 277 KOBJMETHOD(uart_probe, uart_mu_bus_probe), 278 KOBJMETHOD(uart_receive, uart_mu_bus_receive), 279 KOBJMETHOD(uart_setsig, uart_mu_bus_setsig), 280 KOBJMETHOD(uart_transmit, uart_mu_bus_transmit), 281 KOBJMETHOD(uart_grab, uart_mu_bus_grab), 282 KOBJMETHOD(uart_ungrab, uart_mu_bus_ungrab), 283 { 0, 0 } 284 }; 285 286 static struct uart_class uart_mu_class = { 287 "aux-uart", 288 uart_mu_methods, 289 sizeof(struct uart_mu_softc), 290 .uc_ops = &uart_mu_ops, 291 .uc_range = 0x48, 292 .uc_rclk = 0, 293 .uc_rshift = 2 294 }; 295 296 #ifdef FDT 297 static struct ofw_compat_data fdt_compat_data[] = { 298 {"brcm,bcm2835-aux-uart" , (uintptr_t)&uart_mu_class}, 299 {NULL, (uintptr_t)NULL}, 300 }; 301 UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); 302 #endif 303 304 static int 305 uart_mu_bus_attach(struct uart_softc *sc) 306 { 307 struct uart_mu_softc *psc; 308 struct uart_bas *bas; 309 310 psc = (struct uart_mu_softc *)sc; 311 bas = &sc->sc_bas; 312 /* Clear interrupts */ 313 __uart_setreg(bas, AUX_MU_IIR_REG, IIR_CLEAR); 314 /* Enable interrupts */ 315 psc->aux_ier = (IER_RXENABLE|IER_TXENABLE|IER_REQUIRED); 316 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); 317 sc->sc_txbusy = 0; 318 319 return (0); 320 } 321 322 static int 323 uart_mu_bus_detach(struct uart_softc *sc) 324 { 325 326 return (0); 327 } 328 329 static int 330 uart_mu_bus_flush(struct uart_softc *sc, int what) 331 { 332 333 return (0); 334 } 335 336 static int 337 uart_mu_bus_getsig(struct uart_softc *sc) 338 { 339 340 return (0); 341 } 342 343 static int 344 uart_mu_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 345 { 346 int error; 347 348 error = 0; 349 uart_lock(sc->sc_hwmtx); 350 switch (request) { 351 case UART_IOCTL_BREAK: 352 break; 353 case UART_IOCTL_BAUD: 354 *(int*)data = 115200; 355 break; 356 default: 357 error = EINVAL; 358 break; 359 } 360 uart_unlock(sc->sc_hwmtx); 361 362 return (error); 363 } 364 365 static int 366 uart_mu_bus_ipend(struct uart_softc *sc) 367 { 368 struct uart_mu_softc *psc; 369 struct uart_bas *bas; 370 uint32_t ints; 371 int ipend; 372 373 psc = (struct uart_mu_softc *)sc; 374 bas = &sc->sc_bas; 375 376 uart_lock(sc->sc_hwmtx); 377 ints = __uart_getreg(bas, AUX_MU_IIR_REG); 378 ipend = 0; 379 380 /* 381 * According to docs only one of IIR_RXREADY 382 * or IIR_TXREADY are valid eg. Only one or the other. 383 */ 384 if (ints & IIR_RXREADY) { 385 ipend |= SER_INT_RXREADY; 386 } else if (ints & IIR_TXREADY) { 387 if (__uart_getreg(bas, AUX_MU_LSR_REG) & LSR_TXIDLE) { 388 if (sc->sc_txbusy) 389 ipend |= SER_INT_TXIDLE; 390 391 /* Disable TX interrupt */ 392 __uart_setreg(bas, AUX_MU_IER_REG, 393 psc->aux_ier & ~IER_TXENABLE); 394 } 395 } 396 397 uart_unlock(sc->sc_hwmtx); 398 399 return (ipend); 400 } 401 402 static int 403 uart_mu_bus_param(struct uart_softc *sc, int baudrate, int databits, 404 int stopbits, int parity) 405 { 406 407 uart_lock(sc->sc_hwmtx); 408 uart_mu_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 409 uart_unlock(sc->sc_hwmtx); 410 411 return (0); 412 } 413 414 static int 415 uart_mu_bus_probe(struct uart_softc *sc) 416 { 417 418 /* MU always has 8 byte deep fifo */ 419 sc->sc_rxfifosz = 8; 420 sc->sc_txfifosz = 8; 421 device_set_desc(sc->sc_dev, "BCM2835 Mini-UART"); 422 423 return (0); 424 } 425 426 static int 427 uart_mu_bus_receive(struct uart_softc *sc) 428 { 429 struct uart_bas *bas; 430 uint32_t lsr, xc; 431 int rx; 432 433 bas = &sc->sc_bas; 434 uart_lock(sc->sc_hwmtx); 435 436 lsr = __uart_getreg(bas, AUX_MU_LSR_REG); 437 while (lsr & LSR_RXREADY) { 438 xc = __uart_getreg(bas, AUX_MU_IO_REG); 439 rx = xc & 0xff; 440 if (uart_rx_full(sc)) { 441 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 442 break; 443 } 444 uart_rx_put(sc, rx); 445 lsr = __uart_getreg(bas, AUX_MU_LSR_REG); 446 } 447 uart_unlock(sc->sc_hwmtx); 448 449 return (0); 450 } 451 452 static int 453 uart_mu_bus_setsig(struct uart_softc *sc, int sig) 454 { 455 456 return (0); 457 } 458 459 static int 460 uart_mu_bus_transmit(struct uart_softc *sc) 461 { 462 struct uart_mu_softc *psc; 463 struct uart_bas *bas; 464 int i; 465 466 psc = (struct uart_mu_softc *)sc; 467 bas = &sc->sc_bas; 468 uart_lock(sc->sc_hwmtx); 469 470 for (i = 0; i < sc->sc_txdatasz; i++) { 471 __uart_setreg(bas, AUX_MU_IO_REG, sc->sc_txbuf[i] & 0xff); 472 uart_barrier(bas); 473 } 474 475 /* Mark busy and enable TX interrupt */ 476 sc->sc_txbusy = 1; 477 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); 478 479 uart_unlock(sc->sc_hwmtx); 480 481 return (0); 482 } 483 484 static void 485 uart_mu_bus_grab(struct uart_softc *sc) 486 { 487 struct uart_mu_softc *psc; 488 struct uart_bas *bas; 489 490 psc = (struct uart_mu_softc *)sc; 491 bas = &sc->sc_bas; 492 493 /* Disable interrupts on switch to polling */ 494 uart_lock(sc->sc_hwmtx); 495 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier &~IER_MASK_ALL); 496 uart_unlock(sc->sc_hwmtx); 497 } 498 499 static void 500 uart_mu_bus_ungrab(struct uart_softc *sc) 501 { 502 struct uart_mu_softc *psc; 503 struct uart_bas *bas; 504 505 psc = (struct uart_mu_softc *)sc; 506 bas = &sc->sc_bas; 507 508 /* Switch to using interrupts while not grabbed */ 509 uart_lock(sc->sc_hwmtx); 510 __uart_setreg(bas, AUX_MU_CNTL_REG, CNTL_RXENAB|CNTL_TXENAB); 511 __uart_setreg(bas, AUX_MU_IER_REG, psc->aux_ier); 512 uart_unlock(sc->sc_hwmtx); 513 } 514