1 /*- 2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _UART_DM_H_ 30 #define _UART_DM_H_ 31 32 #define UART_DM_EXTR_BITS(value, start_pos, end_pos) \ 33 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) 34 35 /* UART Parity Mode */ 36 enum UART_DM_PARITY_MODE { 37 UART_DM_NO_PARITY, 38 UART_DM_ODD_PARITY, 39 UART_DM_EVEN_PARITY, 40 UART_DM_SPACE_PARITY 41 }; 42 43 /* UART Stop Bit Length */ 44 enum UART_DM_STOP_BIT_LEN { 45 UART_DM_SBL_9_16, 46 UART_DM_SBL_1, 47 UART_DM_SBL_1_9_16, 48 UART_DM_SBL_2 49 }; 50 51 /* UART Bits per Char */ 52 enum UART_DM_BITS_PER_CHAR { 53 UART_DM_5_BPS, 54 UART_DM_6_BPS, 55 UART_DM_7_BPS, 56 UART_DM_8_BPS 57 }; 58 59 /* 8-N-1 Configuration */ 60 #define UART_DM_8_N_1_MODE (UART_DM_NO_PARITY | \ 61 (UART_DM_SBL_1 << 2) | \ 62 (UART_DM_8_BPS << 4)) 63 64 /* UART_DM Registers */ 65 66 /* UART Operational Mode Registers (HSUART) */ 67 #define UART_DM_MR1 0x00 68 #define UART_DM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00 69 #define UART_DM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f 70 #define UART_DM_MR1_CTS_CTL_BMSK 0x40 71 #define UART_DM_MR1_RX_RDY_CTL_BMSK 0x80 72 73 #define UART_DM_MR2 0x04 74 #define UART_DM_MR2_ERROR_MODE_BMSK 0x40 75 #define UART_DM_MR2_BITS_PER_CHAR_BMSK 0x30 76 #define UART_DM_MR2_STOP_BIT_LEN_BMSK 0x0c 77 #define UART_DM_MR2_PARITY_MODE_BMSK 0x03 78 #define UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) 79 #define UART_DM_LOOPBACK (1 << 7) 80 81 /* UART Clock Selection Register, write only */ 82 #define UART_DM_CSR 0x08 83 84 /* UART DM TX FIFO Registers - 4, write only */ 85 #define UART_DM_TF(x) (0x70 + (4 * (x))) 86 87 /* UART Command Register, write only */ 88 #define UART_DM_CR 0x10 89 #define UART_DM_CR_RX_ENABLE (1 << 0) 90 #define UART_DM_CR_RX_DISABLE (1 << 1) 91 #define UART_DM_CR_TX_ENABLE (1 << 2) 92 #define UART_DM_CR_TX_DISABLE (1 << 3) 93 94 /* UART_DM_CR channel command bit value (register field is bits 8:4) */ 95 #define UART_DM_RESET_RX 0x10 96 #define UART_DM_RESET_TX 0x20 97 #define UART_DM_RESET_ERROR_STATUS 0x30 98 #define UART_DM_RESET_BREAK_INT 0x40 99 #define UART_DM_START_BREAK 0x50 100 #define UART_DM_STOP_BREAK 0x60 101 #define UART_DM_RESET_CTS 0x70 102 #define UART_DM_RESET_STALE_INT 0x80 103 #define UART_DM_RFR_LOW 0xD0 104 #define UART_DM_RFR_HIGH 0xE0 105 #define UART_DM_CR_PROTECTION_EN 0x100 106 #define UART_DM_STALE_EVENT_ENABLE 0x500 107 #define UART_DM_STALE_EVENT_DISABLE 0x600 108 #define UART_DM_FORCE_STALE_EVENT 0x400 109 #define UART_DM_CLEAR_TX_READY 0x300 110 #define UART_DM_RESET_TX_ERROR 0x800 111 #define UART_DM_RESET_TX_DONE 0x810 112 113 /* UART Interrupt Mask Register */ 114 #define UART_DM_IMR 0x14 115 /* these can be used for both ISR and IMR registers */ 116 #define UART_DM_TXLEV (1 << 0) 117 #define UART_DM_RXHUNT (1 << 1) 118 #define UART_DM_RXBRK_CHNG (1 << 2) 119 #define UART_DM_RXSTALE (1 << 3) 120 #define UART_DM_RXLEV (1 << 4) 121 #define UART_DM_DELTA_CTS (1 << 5) 122 #define UART_DM_CURRENT_CTS (1 << 6) 123 #define UART_DM_TX_READY (1 << 7) 124 #define UART_DM_TX_ERROR (1 << 8) 125 #define UART_DM_TX_DONE (1 << 9) 126 #define UART_DM_RXBREAK_START (1 << 10) 127 #define UART_DM_RXBREAK_END (1 << 11) 128 #define UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) 129 130 #define UART_DM_IMR_ENABLED (UART_DM_TX_READY | \ 131 UART_DM_TXLEV | \ 132 UART_DM_RXLEV | \ 133 UART_DM_RXSTALE) 134 135 /* UART Interrupt Programming Register */ 136 #define UART_DM_IPR 0x18 137 #define UART_DM_STALE_TIMEOUT_LSB 0x0f 138 #define UART_DM_STALE_TIMEOUT_MSB 0x00 139 #define UART_DM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80 140 #define UART_DM_IPR_STALE_LSB_BMSK 0x1f 141 142 /* UART Transmit/Receive FIFO Watermark Register */ 143 #define UART_DM_TFWR 0x1c 144 /* Interrupt is generated when FIFO level is less than or equal to this value */ 145 #define UART_DM_TFW_VALUE 0 146 147 #define UART_DM_RFWR 0x20 148 /* Interrupt generated when no of words in RX FIFO is greater than this value */ 149 #define UART_DM_RFW_VALUE 0 150 151 /* UART Hunt Character Register */ 152 #define UART_DM_HCR 0x24 153 154 /* Used for RX transfer initialization */ 155 #define UART_DM_DMRX 0x34 156 /* Default DMRX value - any value bigger than FIFO size would be fine */ 157 #define UART_DM_DMRX_DEF_VALUE 0x220 158 159 /* Register to enable IRDA function */ 160 #define UART_DM_IRDA 0x38 161 162 /* UART Data Mover Enable Register */ 163 #define UART_DM_DMEN 0x3c 164 /* 165 * Single-Character mode for RX channel (every character received 166 * is zero-padded into a word). 167 */ 168 #define UART_DM_DMEN_RX_SC_ENABLE (1 << 5) 169 170 /* Number of characters for Transmission */ 171 #define UART_DM_NO_CHARS_FOR_TX 0x40 172 173 /* UART RX FIFO Base Address */ 174 #define UART_DM_BADR 0x44 175 176 #define UART_DM_SIM_CFG_ADDR 0x80 177 178 /* Read only registers */ 179 /* UART Status Register */ 180 #define UART_DM_SR 0x08 181 /* register field mask mapping */ 182 #define UART_DM_SR_RXRDY (1 << 0) 183 #define UART_DM_SR_RXFULL (1 << 1) 184 #define UART_DM_SR_TXRDY (1 << 2) 185 #define UART_DM_SR_TXEMT (1 << 3) 186 #define UART_DM_SR_UART_OVERRUN (1 << 4) 187 #define UART_DM_SR_PAR_FRAME_ERR (1 << 5) 188 #define UART_DM_RX_BREAK (1 << 6) 189 #define UART_DM_HUNT_CHAR (1 << 7) 190 #define UART_DM_RX_BRK_START_LAST (1 << 8) 191 192 /* UART Receive FIFO Registers - 4 in numbers */ 193 #define UART_DM_RF(x) (0x70 + (4 * (x))) 194 195 /* UART Masked Interrupt Status Register */ 196 #define UART_DM_MISR 0x10 197 198 /* UART Interrupt Status Register */ 199 #define UART_DM_ISR 0x14 200 201 /* Number of characters received since the end of last RX transfer */ 202 #define UART_DM_RX_TOTAL_SNAP 0x38 203 204 /* UART TX FIFO Status Register */ 205 #define UART_DM_TXFS 0x4c 206 #define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) 207 #define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) 208 #define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) 209 #define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) 210 211 /* UART RX FIFO Status Register */ 212 #define UART_DM_RXFS 0x50 213 #define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) 214 #define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) 215 #define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) 216 #define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) 217 218 #endif /* _UART_DM_H_ */ 219