1 /*- 2 * Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _UART_DM_H_ 28 #define _UART_DM_H_ 29 30 #define UART_DM_EXTR_BITS(value, start_pos, end_pos) \ 31 ((value << (32 - end_pos)) >> (32 - (end_pos - start_pos))) 32 33 /* UART Parity Mode */ 34 enum UART_DM_PARITY_MODE { 35 UART_DM_NO_PARITY, 36 UART_DM_ODD_PARITY, 37 UART_DM_EVEN_PARITY, 38 UART_DM_SPACE_PARITY 39 }; 40 41 /* UART Stop Bit Length */ 42 enum UART_DM_STOP_BIT_LEN { 43 UART_DM_SBL_9_16, 44 UART_DM_SBL_1, 45 UART_DM_SBL_1_9_16, 46 UART_DM_SBL_2 47 }; 48 49 /* UART Bits per Char */ 50 enum UART_DM_BITS_PER_CHAR { 51 UART_DM_5_BPS, 52 UART_DM_6_BPS, 53 UART_DM_7_BPS, 54 UART_DM_8_BPS 55 }; 56 57 /* 8-N-1 Configuration */ 58 #define UART_DM_8_N_1_MODE (UART_DM_NO_PARITY | \ 59 (UART_DM_SBL_1 << 2) | \ 60 (UART_DM_8_BPS << 4)) 61 62 /* UART_DM Registers */ 63 64 /* UART Operational Mode Registers (HSUART) */ 65 #define UART_DM_MR1 0x00 66 #define UART_DM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00 67 #define UART_DM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f 68 #define UART_DM_MR1_CTS_CTL_BMSK 0x40 69 #define UART_DM_MR1_RX_RDY_CTL_BMSK 0x80 70 71 #define UART_DM_MR2 0x04 72 #define UART_DM_MR2_ERROR_MODE_BMSK 0x40 73 #define UART_DM_MR2_BITS_PER_CHAR_BMSK 0x30 74 #define UART_DM_MR2_STOP_BIT_LEN_BMSK 0x0c 75 #define UART_DM_MR2_PARITY_MODE_BMSK 0x03 76 #define UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8) 77 #define UART_DM_LOOPBACK (1 << 7) 78 79 /* UART Clock Selection Register, write only */ 80 #define UART_DM_CSR 0x08 81 82 /* UART DM TX FIFO Registers - 4, write only */ 83 #define UART_DM_TF(x) (0x70 + (4 * (x))) 84 85 /* UART Command Register, write only */ 86 #define UART_DM_CR 0x10 87 #define UART_DM_CR_RX_ENABLE (1 << 0) 88 #define UART_DM_CR_RX_DISABLE (1 << 1) 89 #define UART_DM_CR_TX_ENABLE (1 << 2) 90 #define UART_DM_CR_TX_DISABLE (1 << 3) 91 92 /* UART_DM_CR channel command bit value (register field is bits 8:4) */ 93 #define UART_DM_RESET_RX 0x10 94 #define UART_DM_RESET_TX 0x20 95 #define UART_DM_RESET_ERROR_STATUS 0x30 96 #define UART_DM_RESET_BREAK_INT 0x40 97 #define UART_DM_START_BREAK 0x50 98 #define UART_DM_STOP_BREAK 0x60 99 #define UART_DM_RESET_CTS 0x70 100 #define UART_DM_RESET_STALE_INT 0x80 101 #define UART_DM_RFR_LOW 0xD0 102 #define UART_DM_RFR_HIGH 0xE0 103 #define UART_DM_CR_PROTECTION_EN 0x100 104 #define UART_DM_STALE_EVENT_ENABLE 0x500 105 #define UART_DM_STALE_EVENT_DISABLE 0x600 106 #define UART_DM_FORCE_STALE_EVENT 0x400 107 #define UART_DM_CLEAR_TX_READY 0x300 108 #define UART_DM_RESET_TX_ERROR 0x800 109 #define UART_DM_RESET_TX_DONE 0x810 110 111 /* UART Interrupt Mask Register */ 112 #define UART_DM_IMR 0x14 113 /* these can be used for both ISR and IMR registers */ 114 #define UART_DM_TXLEV (1 << 0) 115 #define UART_DM_RXHUNT (1 << 1) 116 #define UART_DM_RXBRK_CHNG (1 << 2) 117 #define UART_DM_RXSTALE (1 << 3) 118 #define UART_DM_RXLEV (1 << 4) 119 #define UART_DM_DELTA_CTS (1 << 5) 120 #define UART_DM_CURRENT_CTS (1 << 6) 121 #define UART_DM_TX_READY (1 << 7) 122 #define UART_DM_TX_ERROR (1 << 8) 123 #define UART_DM_TX_DONE (1 << 9) 124 #define UART_DM_RXBREAK_START (1 << 10) 125 #define UART_DM_RXBREAK_END (1 << 11) 126 #define UART_DM_PAR_FRAME_ERR_IRQ (1 << 12) 127 128 #define UART_DM_IMR_ENABLED (UART_DM_TX_READY | \ 129 UART_DM_TXLEV | \ 130 UART_DM_RXLEV | \ 131 UART_DM_RXSTALE) 132 133 /* UART Interrupt Programming Register */ 134 #define UART_DM_IPR 0x18 135 #define UART_DM_STALE_TIMEOUT_LSB 0x0f 136 #define UART_DM_STALE_TIMEOUT_MSB 0x00 137 #define UART_DM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80 138 #define UART_DM_IPR_STALE_LSB_BMSK 0x1f 139 140 /* UART Transmit/Receive FIFO Watermark Register */ 141 #define UART_DM_TFWR 0x1c 142 /* Interrupt is generated when FIFO level is less than or equal to this value */ 143 #define UART_DM_TFW_VALUE 0 144 145 #define UART_DM_RFWR 0x20 146 /* Interrupt generated when no of words in RX FIFO is greater than this value */ 147 #define UART_DM_RFW_VALUE 0 148 149 /* UART Hunt Character Register */ 150 #define UART_DM_HCR 0x24 151 152 /* Used for RX transfer initialization */ 153 #define UART_DM_DMRX 0x34 154 /* Default DMRX value - any value bigger than FIFO size would be fine */ 155 #define UART_DM_DMRX_DEF_VALUE 0x220 156 157 /* Register to enable IRDA function */ 158 #define UART_DM_IRDA 0x38 159 160 /* UART Data Mover Enable Register */ 161 #define UART_DM_DMEN 0x3c 162 /* 163 * Single-Character mode for RX channel (every character received 164 * is zero-padded into a word). 165 */ 166 #define UART_DM_DMEN_RX_SC_ENABLE (1 << 5) 167 168 /* Number of characters for Transmission */ 169 #define UART_DM_NO_CHARS_FOR_TX 0x40 170 171 /* UART RX FIFO Base Address */ 172 #define UART_DM_BADR 0x44 173 174 #define UART_DM_SIM_CFG_ADDR 0x80 175 176 /* Read only registers */ 177 /* UART Status Register */ 178 #define UART_DM_SR 0x08 179 /* register field mask mapping */ 180 #define UART_DM_SR_RXRDY (1 << 0) 181 #define UART_DM_SR_RXFULL (1 << 1) 182 #define UART_DM_SR_TXRDY (1 << 2) 183 #define UART_DM_SR_TXEMT (1 << 3) 184 #define UART_DM_SR_UART_OVERRUN (1 << 4) 185 #define UART_DM_SR_PAR_FRAME_ERR (1 << 5) 186 #define UART_DM_RX_BREAK (1 << 6) 187 #define UART_DM_HUNT_CHAR (1 << 7) 188 #define UART_DM_RX_BRK_START_LAST (1 << 8) 189 190 /* UART Receive FIFO Registers - 4 in numbers */ 191 #define UART_DM_RF(x) (0x70 + (4 * (x))) 192 193 /* UART Masked Interrupt Status Register */ 194 #define UART_DM_MISR 0x10 195 196 /* UART Interrupt Status Register */ 197 #define UART_DM_ISR 0x14 198 199 /* Number of characters received since the end of last RX transfer */ 200 #define UART_DM_RX_TOTAL_SNAP 0x38 201 202 /* UART TX FIFO Status Register */ 203 #define UART_DM_TXFS 0x4c 204 #define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) 205 #define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) 206 #define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) 207 #define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) 208 209 /* UART RX FIFO Status Register */ 210 #define UART_DM_RXFS 0x50 211 #define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6) 212 #define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31) 213 #define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9) 214 #define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13) 215 216 #endif /* _UART_DM_H_ */ 217