1 /*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * 4 * This software was developed by Oleksandr Rybalko under sponsorship 5 * from the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _UART_DEV_IMX5XX_H 30 #define _UART_DEV_IMX5XX_H 31 32 #define IMXUART_URXD_REG 0x0000 /* UART Receiver Register */ 33 #define IMXUART_URXD_CHARRDY (1 << 15) 34 #define IMXUART_URXD_ERR (1 << 14) 35 #define IMXUART_URXD_OVRRUN (1 << 13) 36 #define IMXUART_URXD_FRMERR (1 << 12) 37 #define IMXUART_URXD_BRK (1 << 11) 38 #define IMXUART_URXD_PRERR (1 << 10) 39 #define IMXUART_URXD_RX_DATA_MASK 0xff 40 41 #define IMXUART_UTXD_REG 0x0040 /* UART Transmitter Register */ 42 #define IMXUART_UTXD_TX_DATA_MASK 0xff 43 44 #define IMXUART_UCR1_REG 0x0080 /* UART Control Register 1 */ 45 #define IMXUART_UCR1_ADEN (1 << 15) 46 #define IMXUART_UCR1_ADBR (1 << 14) 47 #define IMXUART_UCR1_TRDYEN (1 << 13) 48 #define IMXUART_UCR1_IDEN (1 << 12) 49 #define IMXUART_UCR1_ICD_MASK (3 << 10) 50 #define IMXUART_UCR1_ICD_IDLE4 (0 << 10) 51 #define IMXUART_UCR1_ICD_IDLE8 (1 << 10) 52 #define IMXUART_UCR1_ICD_IDLE16 (2 << 10) 53 #define IMXUART_UCR1_ICD_IDLE32 (3 << 10) 54 #define IMXUART_UCR1_RRDYEN (1 << 9) 55 #define IMXUART_UCR1_RXDMAEN (1 << 8) 56 #define IMXUART_UCR1_IREN (1 << 7) 57 #define IMXUART_UCR1_TXMPTYEN (1 << 6) 58 #define IMXUART_UCR1_RTSDEN (1 << 5) 59 #define IMXUART_UCR1_SNDBRK (1 << 4) 60 #define IMXUART_UCR1_TXDMAEN (1 << 3) 61 #define IMXUART_UCR1_ATDMAEN (1 << 2) 62 #define IMXUART_UCR1_DOZE (1 << 1) 63 #define IMXUART_UCR1_UARTEN (1 << 0) 64 65 #define IMXUART_UCR2_REG 0x0084 /* UART Control Register 2 */ 66 #define IMXUART_UCR2_ESCI (1 << 15) 67 #define IMXUART_UCR2_IRTS (1 << 14) 68 #define IMXUART_UCR2_CTSC (1 << 13) 69 #define IMXUART_UCR2_CTS (1 << 12) 70 #define IMXUART_UCR2_ESCEN (1 << 11) 71 #define IMXUART_UCR2_RTEC_MASK (3 << 9) 72 #define IMXUART_UCR2_RTEC_REDGE (0 << 9) 73 #define IMXUART_UCR2_RTEC_FEDGE (1 << 9) 74 #define IMXUART_UCR2_RTEC_EDGE (2 << 9) 75 #define IMXUART_UCR2_PREN (1 << 8) 76 #define IMXUART_UCR2_PROE (1 << 7) 77 #define IMXUART_UCR2_STPB (1 << 6) 78 #define IMXUART_UCR2_WS (1 << 5) 79 #define IMXUART_UCR2_RTSEN (1 << 4) 80 #define IMXUART_UCR2_ATEN (1 << 3) 81 #define IMXUART_UCR2_TXEN (1 << 2) 82 #define IMXUART_UCR2_RXEN (1 << 1) 83 #define IMXUART_UCR2_N_SRST (1 << 0) 84 85 #define IMXUART_UCR3_REG 0x0088 /* UART Control Register 3 */ 86 #define IMXUART_UCR3_DPEC_MASK (3 << 14) 87 #define IMXUART_UCR3_DPEC_REDGE (0 << 14) 88 #define IMXUART_UCR3_DPEC_FEDGE (1 << 14) 89 #define IMXUART_UCR3_DPEC_EDGE (2 << 14) 90 #define IMXUART_UCR3_DTREN (1 << 13) 91 #define IMXUART_UCR3_PARERREN (1 << 12) 92 #define IMXUART_UCR3_FRAERREN (1 << 11) 93 #define IMXUART_UCR3_DSR (1 << 10) 94 #define IMXUART_UCR3_DCD (1 << 9) 95 #define IMXUART_UCR3_RI (1 << 8) 96 #define IMXUART_UCR3_ADNIMP (1 << 7) 97 #define IMXUART_UCR3_RXDSEN (1 << 6) 98 #define IMXUART_UCR3_AIRINTEN (1 << 5) 99 #define IMXUART_UCR3_AWAKEN (1 << 4) 100 #define IMXUART_UCR3_DTRDEN (1 << 3) 101 #define IMXUART_UCR3_RXDMUXSEL (1 << 2) 102 #define IMXUART_UCR3_INVT (1 << 1) 103 #define IMXUART_UCR3_ACIEN (1 << 0) 104 105 #define IMXUART_UCR4_REG 0x008c /* UART Control Register 4 */ 106 #define IMXUART_UCR4_CTSTL_MASK (0x3f << 10) 107 #define IMXUART_UCR4_CTSTL_SHIFT 10 108 #define IMXUART_UCR4_INVR (1 << 9) 109 #define IMXUART_UCR4_ENIRI (1 << 8) 110 #define IMXUART_UCR4_WKEN (1 << 7) 111 #define IMXUART_UCR4_IDDMAEN (1 << 6) 112 #define IMXUART_UCR4_IRSC (1 << 5) 113 #define IMXUART_UCR4_LPBYP (1 << 4) 114 #define IMXUART_UCR4_TCEN (1 << 3) 115 #define IMXUART_UCR4_BKEN (1 << 2) 116 #define IMXUART_UCR4_OREN (1 << 1) 117 #define IMXUART_UCR4_DREN (1 << 0) 118 119 #define IMXUART_UFCR_REG 0x0090 /* UART FIFO Control Register */ 120 #define IMXUART_UFCR_TXTL_MASK (0x3f << 10) 121 #define IMXUART_UFCR_TXTL_SHIFT 10 122 #define IMXUART_UFCR_RFDIV_MASK (0x07 << 7) 123 #define IMXUART_UFCR_RFDIV_SHIFT 7 124 #define IMXUART_UFCR_RFDIV_DIV6 (0 << 7) 125 #define IMXUART_UFCR_RFDIV_DIV5 (1 << 7) 126 #define IMXUART_UFCR_RFDIV_DIV4 (2 << 7) 127 #define IMXUART_UFCR_RFDIV_DIV3 (3 << 7) 128 #define IMXUART_UFCR_RFDIV_DIV2 (4 << 7) 129 #define IMXUART_UFCR_RFDIV_DIV1 (5 << 7) 130 #define IMXUART_UFCR_RFDIV_DIV7 (6 << 7) 131 #define IMXUART_UFCR_DCEDTE (1 << 6) 132 #define IMXUART_UFCR_RXTL_MASK 0x0000003f 133 #define IMXUART_UFCR_RXTL_SHIFT 0 134 135 #define IMXUART_USR1_REG 0x0094 /* UART Status Register 1 */ 136 #define IMXUART_USR1_PARITYERR (1 << 15) 137 #define IMXUART_USR1_RTSS (1 << 14) 138 #define IMXUART_USR1_TRDY (1 << 13) 139 #define IMXUART_USR1_RTSD (1 << 12) 140 #define IMXUART_USR1_ESCF (1 << 11) 141 #define IMXUART_USR1_FRAMERR (1 << 10) 142 #define IMXUART_USR1_RRDY (1 << 9) 143 #define IMXUART_USR1_AGTIM (1 << 8) 144 #define IMXUART_USR1_DTRD (1 << 7) 145 #define IMXUART_USR1_RXDS (1 << 6) 146 #define IMXUART_USR1_AIRINT (1 << 5) 147 #define IMXUART_USR1_AWAKE (1 << 4) 148 /* 6040 5008 XXX */ 149 150 #define IMXUART_USR2_REG 0x0098 /* UART Status Register 2 */ 151 #define IMXUART_USR2_ADET (1 << 15) 152 #define IMXUART_USR2_TXFE (1 << 14) 153 #define IMXUART_USR2_DTRF (1 << 13) 154 #define IMXUART_USR2_IDLE (1 << 12) 155 #define IMXUART_USR2_ACST (1 << 11) 156 #define IMXUART_USR2_RIDELT (1 << 10) 157 #define IMXUART_USR2_RIIN (1 << 9) 158 #define IMXUART_USR2_IRINT (1 << 8) 159 #define IMXUART_USR2_WAKE (1 << 7) 160 #define IMXUART_USR2_DCDDELT (1 << 6) 161 #define IMXUART_USR2_DCDIN (1 << 5) 162 #define IMXUART_USR2_RTSF (1 << 4) 163 #define IMXUART_USR2_TXDC (1 << 3) 164 #define IMXUART_USR2_BRCD (1 << 2) 165 #define IMXUART_USR2_ORE (1 << 1) 166 #define IMXUART_USR2_RDR (1 << 0) 167 168 #define IMXUART_UESC_REG 0x009c /* UART Escape Character Register */ 169 #define IMXUART_UESC_ESC_CHAR_MASK 0x000000ff 170 171 #define IMXUART_UTIM_REG 0x00a0 /* UART Escape Timer Register */ 172 #define IMXUART_UTIM_TIM_MASK 0x00000fff 173 174 #define IMXUART_UBIR_REG 0x00a4 /* UART BRM Incremental Register */ 175 #define IMXUART_UBIR_INC_MASK 0x0000ffff 176 177 #define IMXUART_UBMR_REG 0x00a8 /* UART BRM Modulator Register */ 178 #define IMXUART_UBMR_MOD_MASK 0x0000ffff 179 180 #define IMXUART_UBRC_REG 0x00ac /* UART Baud Rate Count Register */ 181 #define IMXUART_UBRC_BCNT_MASK 0x0000ffff 182 183 #define IMXUART_ONEMS_REG 0x00b0 /* UART One Millisecond Register */ 184 #define IMXUART_ONEMS_ONEMS_MASK 0x00ffffff 185 186 #define IMXUART_UTS_REG 0x00b4 /* UART Test Register */ 187 #define IMXUART_UTS_FRCPERR (1 << 13) 188 #define IMXUART_UTS_LOOP (1 << 12) 189 #define IMXUART_UTS_DBGEN (1 << 11) 190 #define IMXUART_UTS_LOOPIR (1 << 10) 191 #define IMXUART_UTS_RXDBG (1 << 9) 192 #define IMXUART_UTS_TXEMPTY (1 << 6) 193 #define IMXUART_UTS_RXEMPTY (1 << 5) 194 #define IMXUART_UTS_TXFULL (1 << 4) 195 #define IMXUART_UTS_RXFULL (1 << 3) 196 #define IMXUART_UTS_SOFTRST (1 << 0) 197 198 #define REG(_r) IMXUART_ ## _r ## _REG 199 #define FLD(_r, _v) IMXUART_ ## _r ## _ ## _v 200 201 #define GETREG(bas, reg) \ 202 bus_space_read_4((bas)->bst, (bas)->bsh, (reg)) 203 #define SETREG(bas, reg, value) \ 204 bus_space_write_4((bas)->bst, (bas)->bsh, (reg), (value)) 205 206 #define CLR(_bas, _r, _b) \ 207 SETREG((_bas), (_r), GETREG((_bas), (_r)) & ~(_b)) 208 #define SET(_bas, _r, _b) \ 209 SETREG((_bas), (_r), GETREG((_bas), (_r)) | (_b)) 210 #define IS_SET(_bas, _r, _b) \ 211 ((GETREG((_bas), (_r)) & (_b)) ? 1 : 0) 212 213 #define ENA(_bas, _r, _b) SET((_bas), REG(_r), FLD(_r, _b)) 214 #define DIS(_bas, _r, _b) CLR((_bas), REG(_r), FLD(_r, _b)) 215 #define IS(_bas, _r, _b) IS_SET((_bas), REG(_r), FLD(_r, _b)) 216 217 #endif /* _UART_DEV_IMX5XX_H */ 218