xref: /freebsd/sys/dev/uart/uart_core.c (revision db33c6f3ae9d1231087710068ee4ea5398aacca7)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2003 Marcel Moolenaar
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/conf.h>
33 #include <sys/cons.h>
34 #include <sys/fcntl.h>
35 #include <sys/interrupt.h>
36 #include <sys/kdb.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/queue.h>
40 #include <sys/reboot.h>
41 #include <sys/sysctl.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
46 
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_bus.h>
49 #include <dev/uart/uart_cpu.h>
50 #include <dev/uart/uart_ppstypes.h>
51 
52 #include "uart_if.h"
53 
54 const char uart_driver_name[] = "uart";
55 
56 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs =
57     SLIST_HEAD_INITIALIZER(uart_sysdevs);
58 
59 static MALLOC_DEFINE(M_UART, "UART", "UART driver");
60 
61 #ifndef	UART_POLL_FREQ
62 #define	UART_POLL_FREQ		50
63 #endif
64 static int uart_poll_freq = UART_POLL_FREQ;
65 SYSCTL_INT(_debug, OID_AUTO, uart_poll_freq, CTLFLAG_RDTUN, &uart_poll_freq,
66     0, "UART poll frequency");
67 
68 static int uart_force_poll;
69 SYSCTL_INT(_debug, OID_AUTO, uart_force_poll, CTLFLAG_RDTUN, &uart_force_poll,
70     0, "Force UART polling");
71 
72 static inline int
73 uart_pps_mode_valid(int pps_mode)
74 {
75 	int opt;
76 
77 	switch(pps_mode & UART_PPS_SIGNAL_MASK) {
78 	case UART_PPS_DISABLED:
79 	case UART_PPS_CTS:
80 	case UART_PPS_DCD:
81 		break;
82 	default:
83 		return (false);
84 	}
85 
86 	opt = pps_mode & UART_PPS_OPTION_MASK;
87 	if ((opt & ~(UART_PPS_INVERT_PULSE | UART_PPS_NARROW_PULSE)) != 0)
88 		return (false);
89 
90 	return (true);
91 }
92 
93 static void
94 uart_pps_print_mode(struct uart_softc *sc)
95 {
96 
97 	device_printf(sc->sc_dev, "PPS capture mode: ");
98 	switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) {
99 	case UART_PPS_DISABLED:
100 		printf("disabled");
101 		break;
102 	case UART_PPS_CTS:
103 		printf("CTS");
104 		break;
105 	case UART_PPS_DCD:
106 		printf("DCD");
107 		break;
108 	default:
109 		printf("invalid");
110 		break;
111 	}
112 	if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
113 		printf("-Inverted");
114 	if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE)
115 		printf("-NarrowPulse");
116 	printf("\n");
117 }
118 
119 static int
120 uart_pps_mode_sysctl(SYSCTL_HANDLER_ARGS)
121 {
122 	struct uart_softc *sc;
123 	int err, tmp;
124 
125 	sc = arg1;
126 	tmp = sc->sc_pps_mode;
127 	err = sysctl_handle_int(oidp, &tmp, 0, req);
128 	if (err != 0 || req->newptr == NULL)
129 		return (err);
130 	if (!uart_pps_mode_valid(tmp))
131 		return (EINVAL);
132 	sc->sc_pps_mode = tmp;
133 	return(0);
134 }
135 
136 static void
137 uart_pps_process(struct uart_softc *sc, int ser_sig)
138 {
139 	sbintime_t now;
140 	int is_assert, pps_sig;
141 
142 	/* Which signal is configured as PPS?  Early out if none. */
143 	switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) {
144 	case UART_PPS_CTS:
145 		pps_sig = SER_CTS;
146 		break;
147 	case UART_PPS_DCD:
148 		pps_sig = SER_DCD;
149 		break;
150 	default:
151 		return;
152 	}
153 
154 	/* Early out if there is no change in the signal configured as PPS. */
155 	if ((ser_sig & SER_DELTA(pps_sig)) == 0)
156 		return;
157 
158 	/*
159 	 * In narrow-pulse mode we need to synthesize both capture and clear
160 	 * events from a single "delta occurred" indication from the uart
161 	 * hardware because the pulse width is too narrow to reliably detect
162 	 * both edges.  However, when the pulse width is close to our interrupt
163 	 * processing latency we might intermittantly catch both edges.  To
164 	 * guard against generating spurious events when that happens, we use a
165 	 * separate timer to ensure at least half a second elapses before we
166 	 * generate another event.
167 	 */
168 	pps_capture(&sc->sc_pps);
169 	if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
170 		now = getsbinuptime();
171 		if (now > sc->sc_pps_captime + 500 * SBT_1MS) {
172 			sc->sc_pps_captime = now;
173 			pps_event(&sc->sc_pps, PPS_CAPTUREASSERT);
174 			pps_event(&sc->sc_pps, PPS_CAPTURECLEAR);
175 		}
176 	} else  {
177 		is_assert = ser_sig & pps_sig;
178 		if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
179 			is_assert = !is_assert;
180 		pps_event(&sc->sc_pps, is_assert ? PPS_CAPTUREASSERT :
181 		    PPS_CAPTURECLEAR);
182 	}
183 }
184 
185 static void
186 uart_pps_init(struct uart_softc *sc)
187 {
188 	struct sysctl_ctx_list *ctx;
189 	struct sysctl_oid *tree;
190 
191 	ctx = device_get_sysctl_ctx(sc->sc_dev);
192 	tree = device_get_sysctl_tree(sc->sc_dev);
193 
194 	/*
195 	 * The historical default for pps capture mode is either DCD or CTS,
196 	 * depending on the UART_PPS_ON_CTS kernel option.  Start with that,
197 	 * then try to fetch the tunable that overrides the mode for all uart
198 	 * devices, then try to fetch the sysctl-tunable that overrides the mode
199 	 * for one specific device.
200 	 */
201 #ifdef UART_PPS_ON_CTS
202 	sc->sc_pps_mode = UART_PPS_CTS;
203 #else
204 	sc->sc_pps_mode = UART_PPS_DCD;
205 #endif
206 	TUNABLE_INT_FETCH("hw.uart.pps_mode", &sc->sc_pps_mode);
207 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "pps_mode",
208 	    CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, sc, 0,
209 	    uart_pps_mode_sysctl, "I", "pulse mode: 0/1/2=disabled/CTS/DCD; "
210 	    "add 0x10 to invert, 0x20 for narrow pulse");
211 
212 	if (!uart_pps_mode_valid(sc->sc_pps_mode)) {
213 		device_printf(sc->sc_dev,
214 		    "Invalid pps_mode 0x%02x configured; disabling PPS capture\n",
215 		    sc->sc_pps_mode);
216 		sc->sc_pps_mode = UART_PPS_DISABLED;
217 	} else if (bootverbose) {
218 		uart_pps_print_mode(sc);
219 	}
220 
221 	sc->sc_pps.ppscap = PPS_CAPTUREBOTH;
222 	sc->sc_pps.driver_mtx = uart_tty_getlock(sc);
223 	sc->sc_pps.driver_abi = PPS_ABI_VERSION;
224 	pps_init_abi(&sc->sc_pps);
225 }
226 
227 void
228 uart_add_sysdev(struct uart_devinfo *di)
229 {
230 	SLIST_INSERT_HEAD(&uart_sysdevs, di, next);
231 }
232 
233 const char *
234 uart_getname(struct uart_class *uc)
235 {
236 	return ((uc != NULL) ? uc->name : NULL);
237 }
238 
239 struct uart_ops *
240 uart_getops(struct uart_class *uc)
241 {
242 	return ((uc != NULL) ? uc->uc_ops : NULL);
243 }
244 
245 int
246 uart_getrange(struct uart_class *uc)
247 {
248 	return ((uc != NULL) ? uc->uc_range : 0);
249 }
250 
251 u_int
252 uart_getregshift(struct uart_class *uc)
253 {
254 	return ((uc != NULL) ? uc->uc_rshift : 0);
255 }
256 
257 u_int
258 uart_getregiowidth(struct uart_class *uc)
259 {
260 	return ((uc != NULL) ? uc->uc_riowidth : 0);
261 }
262 
263 /*
264  * Schedule a soft interrupt. We do this on the 0 to !0 transition
265  * of the TTY pending interrupt status.
266  */
267 void
268 uart_sched_softih(struct uart_softc *sc, uint32_t ipend)
269 {
270 	uint32_t new, old;
271 
272 	do {
273 		old = sc->sc_ttypend;
274 		new = old | ipend;
275 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
276 
277 	if ((old & SER_INT_MASK) == 0)
278 		swi_sched(sc->sc_softih, 0);
279 }
280 
281 /*
282  * A break condition has been detected. We treat the break condition as
283  * a special case that should not happen during normal operation. When
284  * the break condition is to be passed to higher levels in the form of
285  * a NUL character, we really want the break to be in the right place in
286  * the input stream. The overhead to achieve that is not in relation to
287  * the exceptional nature of the break condition, so we permit ourselves
288  * to be sloppy.
289  */
290 static __inline int
291 uart_intr_break(void *arg)
292 {
293 	struct uart_softc *sc = arg;
294 
295 #if defined(KDB)
296 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
297 		if (kdb_break())
298 			return (0);
299 	}
300 #endif
301 	if (sc->sc_opened)
302 		uart_sched_softih(sc, SER_INT_BREAK);
303 	return (0);
304 }
305 
306 /*
307  * Handle a receiver overrun situation. We lost at least 1 byte in the
308  * input stream and it's our job to contain the situation. We grab as
309  * much of the data we can, but otherwise flush the receiver FIFO to
310  * create some breathing room. The net effect is that we avoid the
311  * overrun condition to happen for the next X characters, where X is
312  * related to the FIFO size at the cost of losing data right away.
313  * So, instead of having multiple overrun interrupts in close proximity
314  * to each other and possibly pessimizing UART interrupt latency for
315  * other UARTs in a multiport configuration, we create a longer segment
316  * of missing characters by freeing up the FIFO.
317  * Each overrun condition is marked in the input buffer by a token. The
318  * token represents the loss of at least one, but possible more bytes in
319  * the input stream.
320  */
321 static __inline int
322 uart_intr_overrun(void *arg)
323 {
324 	struct uart_softc *sc = arg;
325 
326 	if (sc->sc_opened) {
327 		UART_RECEIVE(sc);
328 		if (uart_rx_put(sc, UART_STAT_OVERRUN))
329 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
330 		uart_sched_softih(sc, SER_INT_RXREADY);
331 	}
332 	sc->sc_rxoverruns++;
333 	UART_FLUSH(sc, UART_FLUSH_RECEIVER);
334 	return (0);
335 }
336 
337 /*
338  * Received data ready.
339  */
340 static __inline int
341 uart_intr_rxready(void *arg)
342 {
343 	struct uart_softc *sc = arg;
344 #if defined(KDB)
345 	int rxp;
346 
347 	rxp = sc->sc_rxput;
348 #endif
349 	UART_RECEIVE(sc);
350 #if defined(KDB)
351 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
352 		while (rxp != sc->sc_rxput) {
353 			kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk);
354 			if (rxp == sc->sc_rxbufsz)
355 				rxp = 0;
356 		}
357 	}
358 #endif
359 	if (sc->sc_opened)
360 		uart_sched_softih(sc, SER_INT_RXREADY);
361 	else
362 		sc->sc_rxput = sc->sc_rxget;	/* Ignore received data. */
363 	return (1);
364 }
365 
366 /*
367  * Line or modem status change (OOB signalling).
368  * We pass the signals to the software interrupt handler for further
369  * processing. Note that we merge the delta bits, but set the state
370  * bits. This is to avoid losing state transitions due to having more
371  * than 1 hardware interrupt between software interrupts.
372  */
373 static __inline int
374 uart_intr_sigchg(void *arg)
375 {
376 	struct uart_softc *sc = arg;
377 	int new, old, sig;
378 
379 	sig = UART_GETSIG(sc);
380 
381 	/*
382 	 * Time pulse counting support, invoked whenever the PPS parameters are
383 	 * currently set to capture either edge of the signal.
384 	 */
385 	if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
386 		uart_pps_process(sc, sig);
387 	}
388 
389 	/*
390 	 * Keep track of signal changes, even when the device is not
391 	 * opened. This allows us to inform upper layers about a
392 	 * possible loss of DCD and thus the existence of a (possibly)
393 	 * different connection when we have DCD back, during the time
394 	 * that the device was closed.
395 	 */
396 	do {
397 		old = sc->sc_ttypend;
398 		new = old & ~SER_MASK_STATE;
399 		new |= sig & SER_INT_SIGMASK;
400 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
401 
402 	if (sc->sc_opened)
403 		uart_sched_softih(sc, SER_INT_SIGCHG);
404 	return (1);
405 }
406 
407 /*
408  * The transmitter can accept more data.
409  */
410 static __inline int
411 uart_intr_txidle(void *arg)
412 {
413 	struct uart_softc *sc = arg;
414 
415 	if (sc->sc_txbusy) {
416 		sc->sc_txbusy = 0;
417 		uart_sched_softih(sc, SER_INT_TXIDLE);
418 	}
419 	return (0);
420 }
421 
422 static int
423 uart_intr(void *arg)
424 {
425 	struct uart_softc *sc = arg;
426 	int cnt, ipend, testintr;
427 
428 	if (sc->sc_leaving)
429 		return (FILTER_STRAY);
430 
431 	cnt = 0;
432 	testintr = sc->sc_testintr;
433 	while ((!testintr || cnt < 20) && (ipend = UART_IPEND(sc)) != 0) {
434 		cnt++;
435 		if (ipend & SER_INT_OVERRUN)
436 			uart_intr_overrun(sc);
437 		if (ipend & SER_INT_BREAK)
438 			uart_intr_break(sc);
439 		if (ipend & SER_INT_RXREADY)
440 			uart_intr_rxready(sc);
441 		if (ipend & SER_INT_SIGCHG)
442 			uart_intr_sigchg(sc);
443 		if (ipend & SER_INT_TXIDLE)
444 			uart_intr_txidle(sc);
445 	}
446 
447 	if (sc->sc_polled) {
448 		callout_reset(&sc->sc_timer, hz / uart_poll_freq,
449 		    (callout_func_t *)uart_intr, sc);
450 	}
451 
452 	return ((cnt == 0) ? FILTER_STRAY :
453 	    ((testintr && cnt == 20) ? FILTER_SCHEDULE_THREAD :
454 	    FILTER_HANDLED));
455 }
456 
457 serdev_intr_t *
458 uart_bus_ihand(device_t dev, int ipend)
459 {
460 
461 	switch (ipend) {
462 	case SER_INT_BREAK:
463 		return (uart_intr_break);
464 	case SER_INT_OVERRUN:
465 		return (uart_intr_overrun);
466 	case SER_INT_RXREADY:
467 		return (uart_intr_rxready);
468 	case SER_INT_SIGCHG:
469 		return (uart_intr_sigchg);
470 	case SER_INT_TXIDLE:
471 		return (uart_intr_txidle);
472 	}
473 	return (NULL);
474 }
475 
476 int
477 uart_bus_ipend(device_t dev)
478 {
479 	struct uart_softc *sc;
480 
481 	sc = device_get_softc(dev);
482 	return (UART_IPEND(sc));
483 }
484 
485 int
486 uart_bus_sysdev(device_t dev)
487 {
488 	struct uart_softc *sc;
489 
490 	sc = device_get_softc(dev);
491 	return ((sc->sc_sysdev != NULL) ? 1 : 0);
492 }
493 
494 int
495 uart_bus_probe(device_t dev, int regshft, int regiowidth, int rclk, int rid, int chan, int quirks)
496 {
497 	struct uart_softc *sc;
498 	struct uart_devinfo *sysdev;
499 	int error;
500 
501 	sc = device_get_softc(dev);
502 
503 	/*
504 	 * All uart_class references are weak. Check that the needed
505 	 * class has been compiled-in. Fail if not.
506 	 */
507 	if (sc->sc_class == NULL)
508 		return (ENXIO);
509 
510 	/*
511 	 * Initialize the instance. Note that the instance (=softc) does
512 	 * not necessarily match the hardware specific softc. We can't do
513 	 * anything about it now, because we may not attach to the device.
514 	 * Hardware drivers cannot use any of the class specific fields
515 	 * while probing.
516 	 */
517 	kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class);
518 	sc->sc_dev = dev;
519 	if (device_get_desc(dev) == NULL)
520 		device_set_desc(dev, uart_getname(sc->sc_class));
521 
522 	/*
523 	 * Allocate the register resource. We assume that all UARTs have
524 	 * a single register window in either I/O port space or memory
525 	 * mapped I/O space. Any UART that needs multiple windows will
526 	 * consequently not be supported by this driver as-is. We try I/O
527 	 * port space first because that's the common case.
528 	 */
529 	sc->sc_rrid = rid;
530 	sc->sc_rtype = SYS_RES_IOPORT;
531 	sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
532 	    RF_ACTIVE);
533 	if (sc->sc_rres == NULL) {
534 		sc->sc_rrid = rid;
535 		sc->sc_rtype = SYS_RES_MEMORY;
536 		sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype,
537 		    &sc->sc_rrid, RF_ACTIVE);
538 		if (sc->sc_rres == NULL)
539 			return (ENXIO);
540 	}
541 
542 	/*
543 	 * Fill in the bus access structure and compare this device with
544 	 * a possible console device and/or a debug port. We set the flags
545 	 * in the softc so that the hardware dependent probe can adjust
546 	 * accordingly. In general, you don't want to permanently disrupt
547 	 * console I/O.
548 	 */
549 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
550 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
551 	sc->sc_bas.chan = chan;
552 	sc->sc_bas.regshft = regshft;
553 	sc->sc_bas.regiowidth = regiowidth;
554 	sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk;
555 	sc->sc_bas.busy_detect = !!(quirks & UART_F_BUSY_DETECT);
556 
557 	SLIST_FOREACH(sysdev, &uart_sysdevs, next) {
558 		if (chan == sysdev->bas.chan &&
559 		    uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) {
560 			/* XXX check if ops matches class. */
561 			sc->sc_sysdev = sysdev;
562 			if (sysdev->bas.rclk != 0) {
563 				/* Let the boot sequence control */
564 				sc->sc_bas.rclk = sysdev->bas.rclk;
565 			} else {
566 				/* Boot didn't set it, use use class */
567 				sysdev->bas.rclk = sc->sc_bas.rclk;
568 			}
569                 }
570 	}
571 
572 	error = UART_PROBE(sc);
573 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
574 	return ((error) ? error : 0);
575 }
576 
577 int
578 uart_bus_attach(device_t dev)
579 {
580 	struct uart_softc *sc, *sc0;
581 	const char *sep;
582 	int error, filt;
583 
584 	/*
585 	 * The sc_class field defines the type of UART we're going to work
586 	 * with and thus the size of the softc. Replace the generic softc
587 	 * with one that matches the UART now that we're certain we handle
588 	 * the device.
589 	 */
590 	sc0 = device_get_softc(dev);
591 	if (sc0->sc_class->size > device_get_driver(dev)->size) {
592 		sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO);
593 		bcopy(sc0, sc, sizeof(*sc));
594 		device_set_softc(dev, sc);
595 	} else
596 		sc = sc0;
597 
598 	/*
599 	 * Now that we know the softc for this device, connect the back
600 	 * pointer from the sysdev for this device, if any
601 	 */
602 	if (sc->sc_sysdev != NULL)
603 		sc->sc_sysdev->sc = sc;
604 
605 	/*
606 	 * Protect ourselves against interrupts while we're not completely
607 	 * finished attaching and initializing. We don't expect interrupts
608 	 * until after UART_ATTACH(), though.
609 	 */
610 	sc->sc_leaving = 1;
611 
612 	mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN);
613 	if (sc->sc_hwmtx == NULL)
614 		sc->sc_hwmtx = &sc->sc_hwmtx_s;
615 
616 	/*
617 	 * Re-allocate. We expect that the softc contains the information
618 	 * collected by uart_bus_probe() intact.
619 	 */
620 	sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
621 	    RF_ACTIVE);
622 	if (sc->sc_rres == NULL) {
623 		mtx_destroy(&sc->sc_hwmtx_s);
624 		return (ENXIO);
625 	}
626 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
627 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
628 
629 	/*
630 	 * Ensure there is room for at least three full FIFOs of data in the
631 	 * receive buffer (handles the case of low-level drivers with huge
632 	 * FIFOs), and also ensure that there is no less than the historical
633 	 * size of 384 bytes (handles the typical small-FIFO case).
634 	 */
635 	sc->sc_rxbufsz = MAX(384, sc->sc_rxfifosz * 3);
636 	sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf),
637 	    M_UART, M_WAITOK);
638 	sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf),
639 	    M_UART, M_WAITOK);
640 
641 	error = UART_ATTACH(sc);
642 	if (error)
643 		goto fail;
644 
645 	if (sc->sc_hwiflow || sc->sc_hwoflow) {
646 		sep = "";
647 		device_print_prettyname(dev);
648 		if (sc->sc_hwiflow) {
649 			printf("%sRTS iflow", sep);
650 			sep = ", ";
651 		}
652 		if (sc->sc_hwoflow) {
653 			printf("%sCTS oflow", sep);
654 			sep = ", ";
655 		}
656 		printf("\n");
657 	}
658 
659 	if (sc->sc_sysdev != NULL) {
660 		if (sc->sc_sysdev->baudrate == 0) {
661 			if (UART_IOCTL(sc, UART_IOCTL_BAUD,
662 			    (intptr_t)&sc->sc_sysdev->baudrate) != 0)
663 				sc->sc_sysdev->baudrate = -1;
664 		}
665 		switch (sc->sc_sysdev->type) {
666 		case UART_DEV_CONSOLE:
667 			device_printf(dev, "console");
668 			break;
669 		case UART_DEV_DBGPORT:
670 			device_printf(dev, "debug port");
671 			break;
672 		case UART_DEV_KEYBOARD:
673 			device_printf(dev, "keyboard");
674 			break;
675 		default:
676 			device_printf(dev, "unknown system device");
677 			break;
678 		}
679 		printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate,
680 		    "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits,
681 		    sc->sc_sysdev->stopbits);
682 	}
683 
684 	sc->sc_leaving = 0;
685 	sc->sc_testintr = 1;
686 	filt = uart_intr(sc);
687 	sc->sc_testintr = 0;
688 
689 	/*
690 	 * Don't use interrupts if we couldn't clear any pending interrupt
691 	 * conditions. We may have broken H/W and polling is probably the
692 	 * safest thing to do.
693 	 */
694 	if (filt != FILTER_SCHEDULE_THREAD && !uart_force_poll) {
695 		sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
696 		    &sc->sc_irid, RF_ACTIVE | RF_SHAREABLE);
697 	}
698 	if (sc->sc_ires != NULL) {
699 		error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_TTY,
700 		    uart_intr, NULL, sc, &sc->sc_icookie);
701 		sc->sc_fastintr = (error == 0) ? 1 : 0;
702 
703 		if (!sc->sc_fastintr)
704 			error = bus_setup_intr(dev, sc->sc_ires,
705 			    INTR_TYPE_TTY | INTR_MPSAFE, NULL,
706 			    (driver_intr_t *)uart_intr, sc, &sc->sc_icookie);
707 
708 		if (error) {
709 			device_printf(dev, "could not activate interrupt\n");
710 			bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
711 			    sc->sc_ires);
712 			sc->sc_ires = NULL;
713 		}
714 	}
715 	if (sc->sc_ires == NULL) {
716 		/* No interrupt resource. Force polled mode. */
717 		sc->sc_polled = 1;
718 		callout_init(&sc->sc_timer, 1);
719 		callout_reset(&sc->sc_timer, hz / uart_poll_freq,
720 		    (callout_func_t *)uart_intr, sc);
721 	}
722 
723 	if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) {
724 		sep = "";
725 		device_print_prettyname(dev);
726 		if (sc->sc_fastintr) {
727 			printf("%sfast interrupt", sep);
728 			sep = ", ";
729 		}
730 		if (sc->sc_polled) {
731 			printf("%spolled mode (%dHz)", sep, uart_poll_freq);
732 			sep = ", ";
733 		}
734 		printf("\n");
735 	}
736 
737 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL) {
738 		if ((error = sc->sc_sysdev->attach(sc)) != 0)
739 			goto fail;
740 	} else {
741 		if ((error = uart_tty_attach(sc)) != 0)
742 			goto fail;
743 		uart_pps_init(sc);
744 	}
745 
746 	if (sc->sc_sysdev != NULL)
747 		sc->sc_sysdev->hwmtx = sc->sc_hwmtx;
748 
749 	if (sc->sc_rxfifosz > 1)
750 		SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
751 		    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
752 		    "rx_overruns", CTLFLAG_RD, &sc->sc_rxoverruns, 0,
753 		    "Receive overruns");
754 
755 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
756 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
757 	    "rclk", CTLFLAG_RD, &sc->sc_bas.rclk, 0,
758 	    "Baud clock for device");
759 
760 	return (0);
761 
762  fail:
763 	free(sc->sc_txbuf, M_UART);
764 	free(sc->sc_rxbuf, M_UART);
765 
766 	if (sc->sc_ires != NULL) {
767 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
768 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
769 		    sc->sc_ires);
770 	}
771 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
772 
773 	mtx_destroy(&sc->sc_hwmtx_s);
774 
775 	return (error);
776 }
777 
778 int
779 uart_bus_detach(device_t dev)
780 {
781 	struct uart_softc *sc;
782 
783 	sc = device_get_softc(dev);
784 
785 	sc->sc_leaving = 1;
786 
787 	if (sc->sc_sysdev != NULL)
788 		sc->sc_sysdev->hwmtx = NULL;
789 
790 	UART_DETACH(sc);
791 
792 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL)
793 		(*sc->sc_sysdev->detach)(sc);
794 	else
795 		uart_tty_detach(sc);
796 
797 	free(sc->sc_txbuf, M_UART);
798 	free(sc->sc_rxbuf, M_UART);
799 
800 	if (sc->sc_ires != NULL) {
801 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
802 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
803 		    sc->sc_ires);
804 	}
805 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
806 
807 	mtx_destroy(&sc->sc_hwmtx_s);
808 
809 	if (sc->sc_class->size > device_get_driver(dev)->size) {
810 		device_set_softc(dev, NULL);
811 		free(sc, M_UART);
812 	}
813 
814 	return (0);
815 }
816 
817 int
818 uart_bus_resume(device_t dev)
819 {
820 	struct uart_softc *sc;
821 
822 	sc = device_get_softc(dev);
823 	return (UART_ATTACH(sc));
824 }
825 
826 void
827 uart_grab(struct uart_devinfo *di)
828 {
829 
830 	if (di->sc)
831 		UART_GRAB(di->sc);
832 }
833 
834 void
835 uart_ungrab(struct uart_devinfo *di)
836 {
837 
838 	if (di->sc)
839 		UART_UNGRAB(di->sc);
840 }
841