xref: /freebsd/sys/dev/uart/uart_core.c (revision a10cee30c94cf5944826d2a495e9cdf339dfbcc8)
1 /*-
2  * Copyright (c) 2003 Marcel Moolenaar
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/cons.h>
35 #include <sys/fcntl.h>
36 #include <sys/interrupt.h>
37 #include <sys/kdb.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
41 #include <sys/reboot.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
46 
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_bus.h>
49 #include <dev/uart/uart_cpu.h>
50 
51 #include "uart_if.h"
52 
53 devclass_t uart_devclass;
54 char uart_driver_name[] = "uart";
55 
56 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs =
57     SLIST_HEAD_INITIALIZER(uart_sysdevs);
58 
59 static MALLOC_DEFINE(M_UART, "UART", "UART driver");
60 
61 #ifndef	UART_POLL_FREQ
62 #define	UART_POLL_FREQ		50
63 #endif
64 static int uart_poll_freq = UART_POLL_FREQ;
65 TUNABLE_INT("debug.uart_poll_freq", &uart_poll_freq);
66 
67 void
68 uart_add_sysdev(struct uart_devinfo *di)
69 {
70 	SLIST_INSERT_HEAD(&uart_sysdevs, di, next);
71 }
72 
73 const char *
74 uart_getname(struct uart_class *uc)
75 {
76 	return ((uc != NULL) ? uc->name : NULL);
77 }
78 
79 struct uart_ops *
80 uart_getops(struct uart_class *uc)
81 {
82 	return ((uc != NULL) ? uc->uc_ops : NULL);
83 }
84 
85 int
86 uart_getrange(struct uart_class *uc)
87 {
88 	return ((uc != NULL) ? uc->uc_range : 0);
89 }
90 
91 /*
92  * Schedule a soft interrupt. We do this on the 0 to !0 transition
93  * of the TTY pending interrupt status.
94  */
95 void
96 uart_sched_softih(struct uart_softc *sc, uint32_t ipend)
97 {
98 	uint32_t new, old;
99 
100 	do {
101 		old = sc->sc_ttypend;
102 		new = old | ipend;
103 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
104 
105 	if ((old & SER_INT_MASK) == 0)
106 		swi_sched(sc->sc_softih, 0);
107 }
108 
109 /*
110  * A break condition has been detected. We treat the break condition as
111  * a special case that should not happen during normal operation. When
112  * the break condition is to be passed to higher levels in the form of
113  * a NUL character, we really want the break to be in the right place in
114  * the input stream. The overhead to achieve that is not in relation to
115  * the exceptional nature of the break condition, so we permit ourselves
116  * to be sloppy.
117  */
118 static __inline int
119 uart_intr_break(void *arg)
120 {
121 	struct uart_softc *sc = arg;
122 
123 #if defined(KDB)
124 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
125 		if (kdb_break())
126 			return (0);
127 	}
128 #endif
129 	if (sc->sc_opened)
130 		uart_sched_softih(sc, SER_INT_BREAK);
131 	return (0);
132 }
133 
134 /*
135  * Handle a receiver overrun situation. We lost at least 1 byte in the
136  * input stream and it's our job to contain the situation. We grab as
137  * much of the data we can, but otherwise flush the receiver FIFO to
138  * create some breathing room. The net effect is that we avoid the
139  * overrun condition to happen for the next X characters, where X is
140  * related to the FIFO size at the cost of loosing data right away.
141  * So, instead of having multiple overrun interrupts in close proximity
142  * to each other and possibly pessimizing UART interrupt latency for
143  * other UARTs in a multiport configuration, we create a longer segment
144  * of missing characters by freeing up the FIFO.
145  * Each overrun condition is marked in the input buffer by a token. The
146  * token represents the loss of at least one, but possible more bytes in
147  * the input stream.
148  */
149 static __inline int
150 uart_intr_overrun(void *arg)
151 {
152 	struct uart_softc *sc = arg;
153 
154 	if (sc->sc_opened) {
155 		UART_RECEIVE(sc);
156 		if (uart_rx_put(sc, UART_STAT_OVERRUN))
157 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
158 		uart_sched_softih(sc, SER_INT_RXREADY);
159 	}
160 	UART_FLUSH(sc, UART_FLUSH_RECEIVER);
161 	return (0);
162 }
163 
164 /*
165  * Received data ready.
166  */
167 static __inline int
168 uart_intr_rxready(void *arg)
169 {
170 	struct uart_softc *sc = arg;
171 	int rxp;
172 
173 	rxp = sc->sc_rxput;
174 	UART_RECEIVE(sc);
175 #if defined(KDB)
176 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
177 		while (rxp != sc->sc_rxput) {
178 			kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk);
179 			if (rxp == sc->sc_rxbufsz)
180 				rxp = 0;
181 		}
182 	}
183 #endif
184 	if (sc->sc_opened)
185 		uart_sched_softih(sc, SER_INT_RXREADY);
186 	else
187 		sc->sc_rxput = sc->sc_rxget;	/* Ignore received data. */
188 	return (1);
189 }
190 
191 /*
192  * Line or modem status change (OOB signalling).
193  * We pass the signals to the software interrupt handler for further
194  * processing. Note that we merge the delta bits, but set the state
195  * bits. This is to avoid loosing state transitions due to having more
196  * than 1 hardware interrupt between software interrupts.
197  */
198 static __inline int
199 uart_intr_sigchg(void *arg)
200 {
201 	struct uart_softc *sc = arg;
202 	int new, old, sig;
203 
204 	sig = UART_GETSIG(sc);
205 
206 	if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
207 		if (sig & UART_SIG_DPPS) {
208 			pps_capture(&sc->sc_pps);
209 			pps_event(&sc->sc_pps, (sig & UART_SIG_PPS) ?
210 			    PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
211 		}
212 	}
213 
214 	/*
215 	 * Keep track of signal changes, even when the device is not
216 	 * opened. This allows us to inform upper layers about a
217 	 * possible loss of DCD and thus the existence of a (possibly)
218 	 * different connection when we have DCD back, during the time
219 	 * that the device was closed.
220 	 */
221 	do {
222 		old = sc->sc_ttypend;
223 		new = old & ~SER_MASK_STATE;
224 		new |= sig & SER_INT_SIGMASK;
225 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
226 
227 	if (sc->sc_opened)
228 		uart_sched_softih(sc, SER_INT_SIGCHG);
229 	return (1);
230 }
231 
232 /*
233  * The transmitter can accept more data.
234  */
235 static __inline int
236 uart_intr_txidle(void *arg)
237 {
238 	struct uart_softc *sc = arg;
239 
240 	if (sc->sc_txbusy) {
241 		sc->sc_txbusy = 0;
242 		uart_sched_softih(sc, SER_INT_TXIDLE);
243 	}
244 	return (0);
245 }
246 
247 static int
248 uart_intr(void *arg)
249 {
250 	struct uart_softc *sc = arg;
251 	int flag = 0, ipend;
252 
253 	while (!sc->sc_leaving && (ipend = UART_IPEND(sc)) != 0) {
254 		flag = 1;
255 		if (ipend & SER_INT_OVERRUN)
256 			uart_intr_overrun(sc);
257 		if (ipend & SER_INT_BREAK)
258 			uart_intr_break(sc);
259 		if (ipend & SER_INT_RXREADY)
260 			uart_intr_rxready(sc);
261 		if (ipend & SER_INT_SIGCHG)
262 			uart_intr_sigchg(sc);
263 		if (ipend & SER_INT_TXIDLE)
264 			uart_intr_txidle(sc);
265 	}
266 
267 	if (sc->sc_polled) {
268 		callout_reset(&sc->sc_timer, hz / uart_poll_freq,
269 		    (timeout_t *)uart_intr, sc);
270 	}
271 
272 	return((flag)?FILTER_HANDLED:FILTER_STRAY);
273 }
274 
275 serdev_intr_t *
276 uart_bus_ihand(device_t dev, int ipend)
277 {
278 
279 	switch (ipend) {
280 	case SER_INT_BREAK:
281 		return (uart_intr_break);
282 	case SER_INT_OVERRUN:
283 		return (uart_intr_overrun);
284 	case SER_INT_RXREADY:
285 		return (uart_intr_rxready);
286 	case SER_INT_SIGCHG:
287 		return (uart_intr_sigchg);
288 	case SER_INT_TXIDLE:
289 		return (uart_intr_txidle);
290 	}
291 	return (NULL);
292 }
293 
294 int
295 uart_bus_ipend(device_t dev)
296 {
297 	struct uart_softc *sc;
298 
299 	sc = device_get_softc(dev);
300 	return (UART_IPEND(sc));
301 }
302 
303 int
304 uart_bus_sysdev(device_t dev)
305 {
306 	struct uart_softc *sc;
307 
308 	sc = device_get_softc(dev);
309 	return ((sc->sc_sysdev != NULL) ? 1 : 0);
310 }
311 
312 int
313 uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan)
314 {
315 	struct uart_softc *sc;
316 	struct uart_devinfo *sysdev;
317 	int error;
318 
319 	sc = device_get_softc(dev);
320 
321 	/*
322 	 * All uart_class references are weak. Check that the needed
323 	 * class has been compiled-in. Fail if not.
324 	 */
325 	if (sc->sc_class == NULL)
326 		return (ENXIO);
327 
328 	/*
329 	 * Initialize the instance. Note that the instance (=softc) does
330 	 * not necessarily match the hardware specific softc. We can't do
331 	 * anything about it now, because we may not attach to the device.
332 	 * Hardware drivers cannot use any of the class specific fields
333 	 * while probing.
334 	 */
335 	kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class);
336 	sc->sc_dev = dev;
337 	if (device_get_desc(dev) == NULL)
338 		device_set_desc(dev, uart_getname(sc->sc_class));
339 
340 	/*
341 	 * Allocate the register resource. We assume that all UARTs have
342 	 * a single register window in either I/O port space or memory
343 	 * mapped I/O space. Any UART that needs multiple windows will
344 	 * consequently not be supported by this driver as-is. We try I/O
345 	 * port space first because that's the common case.
346 	 */
347 	sc->sc_rrid = rid;
348 	sc->sc_rtype = SYS_RES_IOPORT;
349 	sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid,
350 	    0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE);
351 	if (sc->sc_rres == NULL) {
352 		sc->sc_rrid = rid;
353 		sc->sc_rtype = SYS_RES_MEMORY;
354 		sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype,
355 		    &sc->sc_rrid, 0, ~0, uart_getrange(sc->sc_class),
356 		    RF_ACTIVE);
357 		if (sc->sc_rres == NULL)
358 			return (ENXIO);
359 	}
360 
361 	/*
362 	 * Fill in the bus access structure and compare this device with
363 	 * a possible console device and/or a debug port. We set the flags
364 	 * in the softc so that the hardware dependent probe can adjust
365 	 * accordingly. In general, you don't want to permanently disrupt
366 	 * console I/O.
367 	 */
368 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
369 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
370 	sc->sc_bas.chan = chan;
371 	sc->sc_bas.regshft = regshft;
372 	sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk;
373 
374 	SLIST_FOREACH(sysdev, &uart_sysdevs, next) {
375 		if (chan == sysdev->bas.chan &&
376 		    uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) {
377 			/* XXX check if ops matches class. */
378 			sc->sc_sysdev = sysdev;
379 			sysdev->bas.rclk = sc->sc_bas.rclk;
380 		}
381 	}
382 
383 	error = UART_PROBE(sc);
384 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
385 	return ((error) ? error : BUS_PROBE_DEFAULT);
386 }
387 
388 int
389 uart_bus_attach(device_t dev)
390 {
391 	struct uart_softc *sc, *sc0;
392 	const char *sep;
393 	int error;
394 
395 	/*
396 	 * The sc_class field defines the type of UART we're going to work
397 	 * with and thus the size of the softc. Replace the generic softc
398 	 * with one that matches the UART now that we're certain we handle
399 	 * the device.
400 	 */
401 	sc0 = device_get_softc(dev);
402 	if (sc0->sc_class->size > sizeof(*sc)) {
403 		sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO);
404 		bcopy(sc0, sc, sizeof(*sc));
405 		device_set_softc(dev, sc);
406 	} else
407 		sc = sc0;
408 
409 	/*
410 	 * Protect ourselves against interrupts while we're not completely
411 	 * finished attaching and initializing. We don't expect interrupts
412 	 * until after UART_ATTACH() though.
413 	 */
414 	sc->sc_leaving = 1;
415 
416 	mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN);
417 	if (sc->sc_hwmtx == NULL)
418 		sc->sc_hwmtx = &sc->sc_hwmtx_s;
419 
420 	/*
421 	 * Re-allocate. We expect that the softc contains the information
422 	 * collected by uart_bus_probe() intact.
423 	 */
424 	sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid,
425 	    0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE);
426 	if (sc->sc_rres == NULL) {
427 		mtx_destroy(&sc->sc_hwmtx_s);
428 		return (ENXIO);
429 	}
430 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
431 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
432 
433 	sc->sc_irid = 0;
434 	sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
435 	    RF_ACTIVE | RF_SHAREABLE);
436 	if (sc->sc_ires != NULL) {
437 		error = bus_setup_intr(dev,
438 		    sc->sc_ires, INTR_TYPE_TTY,
439 		    uart_intr, NULL, sc, &sc->sc_icookie);
440 		if (error)
441 			error = bus_setup_intr(dev,
442 			    sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE,
443 			    NULL, (driver_intr_t *)uart_intr, sc, &sc->sc_icookie);
444 		else
445 			sc->sc_fastintr = 1;
446 
447 		if (error) {
448 			device_printf(dev, "could not activate interrupt\n");
449 			bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
450 			    sc->sc_ires);
451 			sc->sc_ires = NULL;
452 		}
453 	}
454 	if (sc->sc_ires == NULL) {
455 		/* No interrupt resource. Force polled mode. */
456 		sc->sc_polled = 1;
457 		callout_init(&sc->sc_timer, 1);
458 	}
459 
460 	sc->sc_rxbufsz = 384;
461 	sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf),
462 	    M_UART, M_WAITOK);
463 	sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf),
464 	    M_UART, M_WAITOK);
465 
466 	error = UART_ATTACH(sc);
467 	if (error)
468 		goto fail;
469 
470 	if (sc->sc_hwiflow || sc->sc_hwoflow) {
471 		sep = "";
472 		device_print_prettyname(dev);
473 		if (sc->sc_hwiflow) {
474 			printf("%sRTS iflow", sep);
475 			sep = ", ";
476 		}
477 		if (sc->sc_hwoflow) {
478 			printf("%sCTS oflow", sep);
479 			sep = ", ";
480 		}
481 		printf("\n");
482 	}
483 
484 	if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) {
485 		sep = "";
486 		device_print_prettyname(dev);
487 		if (sc->sc_fastintr) {
488 			printf("%sfast interrupt", sep);
489 			sep = ", ";
490 		}
491 		if (sc->sc_polled) {
492 			printf("%spolled mode", sep);
493 			sep = ", ";
494 		}
495 		printf("\n");
496 	}
497 
498 	if (sc->sc_sysdev != NULL) {
499 		if (sc->sc_sysdev->baudrate == 0) {
500 			if (UART_IOCTL(sc, UART_IOCTL_BAUD,
501 			    (intptr_t)&sc->sc_sysdev->baudrate) != 0)
502 				sc->sc_sysdev->baudrate = -1;
503 		}
504 		switch (sc->sc_sysdev->type) {
505 		case UART_DEV_CONSOLE:
506 			device_printf(dev, "console");
507 			break;
508 		case UART_DEV_DBGPORT:
509 			device_printf(dev, "debug port");
510 			break;
511 		case UART_DEV_KEYBOARD:
512 			device_printf(dev, "keyboard");
513 			break;
514 		default:
515 			device_printf(dev, "unknown system device");
516 			break;
517 		}
518 		printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate,
519 		    "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits,
520 		    sc->sc_sysdev->stopbits);
521 	}
522 
523 	sc->sc_pps.ppscap = PPS_CAPTUREBOTH;
524 	pps_init(&sc->sc_pps);
525 
526 	error = (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL)
527 	    ? (*sc->sc_sysdev->attach)(sc) : uart_tty_attach(sc);
528 	if (error)
529 		goto fail;
530 
531 	if (sc->sc_sysdev != NULL)
532 		sc->sc_sysdev->hwmtx = sc->sc_hwmtx;
533 
534 	sc->sc_leaving = 0;
535 	uart_intr(sc);
536 	return (0);
537 
538  fail:
539 	free(sc->sc_txbuf, M_UART);
540 	free(sc->sc_rxbuf, M_UART);
541 
542 	if (sc->sc_ires != NULL) {
543 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
544 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
545 		    sc->sc_ires);
546 	}
547 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
548 
549 	mtx_destroy(&sc->sc_hwmtx_s);
550 
551 	return (error);
552 }
553 
554 int
555 uart_bus_detach(device_t dev)
556 {
557 	struct uart_softc *sc;
558 
559 	sc = device_get_softc(dev);
560 
561 	sc->sc_leaving = 1;
562 
563 	if (sc->sc_sysdev != NULL)
564 		sc->sc_sysdev->hwmtx = NULL;
565 
566 	UART_DETACH(sc);
567 
568 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL)
569 		(*sc->sc_sysdev->detach)(sc);
570 	else
571 		uart_tty_detach(sc);
572 
573 	free(sc->sc_txbuf, M_UART);
574 	free(sc->sc_rxbuf, M_UART);
575 
576 	if (sc->sc_ires != NULL) {
577 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
578 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
579 		    sc->sc_ires);
580 	}
581 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
582 
583 	mtx_destroy(&sc->sc_hwmtx_s);
584 
585 	if (sc->sc_class->size > sizeof(*sc)) {
586 		device_set_softc(dev, NULL);
587 		free(sc, M_UART);
588 	} else
589 		device_set_softc(dev, NULL);
590 
591 	return (0);
592 }
593