xref: /freebsd/sys/dev/uart/uart_core.c (revision 5dae51da3da0cc94d17bd67b308fad304ebec7e0)
1 /*-
2  * Copyright (c) 2003 Marcel Moolenaar
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/cons.h>
35 #include <sys/fcntl.h>
36 #include <sys/interrupt.h>
37 #include <sys/kdb.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
41 #include <sys/reboot.h>
42 #include <sys/sysctl.h>
43 #include <machine/bus.h>
44 #include <sys/rman.h>
45 #include <machine/resource.h>
46 #include <machine/stdarg.h>
47 
48 #include <dev/uart/uart.h>
49 #include <dev/uart/uart_bus.h>
50 #include <dev/uart/uart_cpu.h>
51 #include <dev/uart/uart_ppstypes.h>
52 
53 #include "uart_if.h"
54 
55 devclass_t uart_devclass;
56 const char uart_driver_name[] = "uart";
57 
58 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs =
59     SLIST_HEAD_INITIALIZER(uart_sysdevs);
60 
61 static MALLOC_DEFINE(M_UART, "UART", "UART driver");
62 
63 #ifndef	UART_POLL_FREQ
64 #define	UART_POLL_FREQ		50
65 #endif
66 static int uart_poll_freq = UART_POLL_FREQ;
67 SYSCTL_INT(_debug, OID_AUTO, uart_poll_freq, CTLFLAG_RDTUN, &uart_poll_freq,
68     0, "UART poll frequency");
69 
70 static int uart_force_poll;
71 SYSCTL_INT(_debug, OID_AUTO, uart_force_poll, CTLFLAG_RDTUN, &uart_force_poll,
72     0, "Force UART polling");
73 
74 static inline int
75 uart_pps_mode_valid(int pps_mode)
76 {
77 	int opt;
78 
79 	switch(pps_mode & UART_PPS_SIGNAL_MASK) {
80 	case UART_PPS_DISABLED:
81 	case UART_PPS_CTS:
82 	case UART_PPS_DCD:
83 		break;
84 	default:
85 		return (false);
86 	}
87 
88 	opt = pps_mode & UART_PPS_OPTION_MASK;
89 	if ((opt & ~(UART_PPS_INVERT_PULSE | UART_PPS_NARROW_PULSE)) != 0)
90 		return (false);
91 
92 	return (true);
93 }
94 
95 static void
96 uart_pps_print_mode(struct uart_softc *sc)
97 {
98 
99 	device_printf(sc->sc_dev, "PPS capture mode: ");
100 	switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) {
101 	case UART_PPS_DISABLED:
102 		printf("disabled");
103 		break;
104 	case UART_PPS_CTS:
105 		printf("CTS");
106 		break;
107 	case UART_PPS_DCD:
108 		printf("DCD");
109 		break;
110 	default:
111 		printf("invalid");
112 		break;
113 	}
114 	if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
115 		printf("-Inverted");
116 	if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE)
117 		printf("-NarrowPulse");
118 	printf("\n");
119 }
120 
121 static int
122 uart_pps_mode_sysctl(SYSCTL_HANDLER_ARGS)
123 {
124 	struct uart_softc *sc;
125 	int err, tmp;
126 
127 	sc = arg1;
128 	tmp = sc->sc_pps_mode;
129 	err = sysctl_handle_int(oidp, &tmp, 0, req);
130 	if (err != 0 || req->newptr == NULL)
131 		return (err);
132 	if (!uart_pps_mode_valid(tmp))
133 		return (EINVAL);
134 	sc->sc_pps_mode = tmp;
135 	return(0);
136 }
137 
138 static void
139 uart_pps_process(struct uart_softc *sc, int ser_sig)
140 {
141 	sbintime_t now;
142 	int is_assert, pps_sig;
143 
144 	/* Which signal is configured as PPS?  Early out if none. */
145 	switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) {
146 	case UART_PPS_CTS:
147 		pps_sig = SER_CTS;
148 		break;
149 	case UART_PPS_DCD:
150 		pps_sig = SER_DCD;
151 		break;
152 	default:
153 		return;
154 	}
155 
156 	/* Early out if there is no change in the signal configured as PPS. */
157 	if ((ser_sig & SER_DELTA(pps_sig)) == 0)
158 		return;
159 
160 	/*
161 	 * In narrow-pulse mode we need to synthesize both capture and clear
162 	 * events from a single "delta occurred" indication from the uart
163 	 * hardware because the pulse width is too narrow to reliably detect
164 	 * both edges.  However, when the pulse width is close to our interrupt
165 	 * processing latency we might intermittantly catch both edges.  To
166 	 * guard against generating spurious events when that happens, we use a
167 	 * separate timer to ensure at least half a second elapses before we
168 	 * generate another event.
169 	 */
170 	pps_capture(&sc->sc_pps);
171 	if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
172 		now = getsbinuptime();
173 		if (now > sc->sc_pps_captime + 500 * SBT_1MS) {
174 			sc->sc_pps_captime = now;
175 			pps_event(&sc->sc_pps, PPS_CAPTUREASSERT);
176 			pps_event(&sc->sc_pps, PPS_CAPTURECLEAR);
177 		}
178 	} else  {
179 		is_assert = ser_sig & pps_sig;
180 		if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE)
181 			is_assert = !is_assert;
182 		pps_event(&sc->sc_pps, is_assert ? PPS_CAPTUREASSERT :
183 		    PPS_CAPTURECLEAR);
184 	}
185 }
186 
187 static void
188 uart_pps_init(struct uart_softc *sc)
189 {
190 	struct sysctl_ctx_list *ctx;
191 	struct sysctl_oid *tree;
192 
193 	ctx = device_get_sysctl_ctx(sc->sc_dev);
194 	tree = device_get_sysctl_tree(sc->sc_dev);
195 
196 	/*
197 	 * The historical default for pps capture mode is either DCD or CTS,
198 	 * depending on the UART_PPS_ON_CTS kernel option.  Start with that,
199 	 * then try to fetch the tunable that overrides the mode for all uart
200 	 * devices, then try to fetch the sysctl-tunable that overrides the mode
201 	 * for one specific device.
202 	 */
203 #ifdef UART_PPS_ON_CTS
204 	sc->sc_pps_mode = UART_PPS_CTS;
205 #else
206 	sc->sc_pps_mode = UART_PPS_DCD;
207 #endif
208 	TUNABLE_INT_FETCH("hw.uart.pps_mode", &sc->sc_pps_mode);
209 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "pps_mode",
210 	    CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, uart_pps_mode_sysctl, "I",
211 	    "pulse mode: 0/1/2=disabled/CTS/DCD; "
212 	    "add 0x10 to invert, 0x20 for narrow pulse");
213 
214 	if (!uart_pps_mode_valid(sc->sc_pps_mode)) {
215 		device_printf(sc->sc_dev,
216 		    "Invalid pps_mode 0x%02x configured; disabling PPS capture\n",
217 		    sc->sc_pps_mode);
218 		sc->sc_pps_mode = UART_PPS_DISABLED;
219 	} else if (bootverbose) {
220 		uart_pps_print_mode(sc);
221 	}
222 
223 	sc->sc_pps.ppscap = PPS_CAPTUREBOTH;
224 	sc->sc_pps.driver_mtx = uart_tty_getlock(sc);
225 	sc->sc_pps.driver_abi = PPS_ABI_VERSION;
226 	pps_init_abi(&sc->sc_pps);
227 }
228 
229 void
230 uart_add_sysdev(struct uart_devinfo *di)
231 {
232 	SLIST_INSERT_HEAD(&uart_sysdevs, di, next);
233 }
234 
235 const char *
236 uart_getname(struct uart_class *uc)
237 {
238 	return ((uc != NULL) ? uc->name : NULL);
239 }
240 
241 struct uart_ops *
242 uart_getops(struct uart_class *uc)
243 {
244 	return ((uc != NULL) ? uc->uc_ops : NULL);
245 }
246 
247 int
248 uart_getrange(struct uart_class *uc)
249 {
250 	return ((uc != NULL) ? uc->uc_range : 0);
251 }
252 
253 u_int
254 uart_getregshift(struct uart_class *uc)
255 {
256 	return ((uc != NULL) ? uc->uc_rshift : 0);
257 }
258 
259 /*
260  * Schedule a soft interrupt. We do this on the 0 to !0 transition
261  * of the TTY pending interrupt status.
262  */
263 void
264 uart_sched_softih(struct uart_softc *sc, uint32_t ipend)
265 {
266 	uint32_t new, old;
267 
268 	do {
269 		old = sc->sc_ttypend;
270 		new = old | ipend;
271 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
272 
273 	if ((old & SER_INT_MASK) == 0)
274 		swi_sched(sc->sc_softih, 0);
275 }
276 
277 /*
278  * A break condition has been detected. We treat the break condition as
279  * a special case that should not happen during normal operation. When
280  * the break condition is to be passed to higher levels in the form of
281  * a NUL character, we really want the break to be in the right place in
282  * the input stream. The overhead to achieve that is not in relation to
283  * the exceptional nature of the break condition, so we permit ourselves
284  * to be sloppy.
285  */
286 static __inline int
287 uart_intr_break(void *arg)
288 {
289 	struct uart_softc *sc = arg;
290 
291 #if defined(KDB)
292 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
293 		if (kdb_break())
294 			return (0);
295 	}
296 #endif
297 	if (sc->sc_opened)
298 		uart_sched_softih(sc, SER_INT_BREAK);
299 	return (0);
300 }
301 
302 /*
303  * Handle a receiver overrun situation. We lost at least 1 byte in the
304  * input stream and it's our job to contain the situation. We grab as
305  * much of the data we can, but otherwise flush the receiver FIFO to
306  * create some breathing room. The net effect is that we avoid the
307  * overrun condition to happen for the next X characters, where X is
308  * related to the FIFO size at the cost of losing data right away.
309  * So, instead of having multiple overrun interrupts in close proximity
310  * to each other and possibly pessimizing UART interrupt latency for
311  * other UARTs in a multiport configuration, we create a longer segment
312  * of missing characters by freeing up the FIFO.
313  * Each overrun condition is marked in the input buffer by a token. The
314  * token represents the loss of at least one, but possible more bytes in
315  * the input stream.
316  */
317 static __inline int
318 uart_intr_overrun(void *arg)
319 {
320 	struct uart_softc *sc = arg;
321 
322 	if (sc->sc_opened) {
323 		UART_RECEIVE(sc);
324 		if (uart_rx_put(sc, UART_STAT_OVERRUN))
325 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
326 		uart_sched_softih(sc, SER_INT_RXREADY);
327 	}
328 	UART_FLUSH(sc, UART_FLUSH_RECEIVER);
329 	return (0);
330 }
331 
332 /*
333  * Received data ready.
334  */
335 static __inline int
336 uart_intr_rxready(void *arg)
337 {
338 	struct uart_softc *sc = arg;
339 	int rxp;
340 
341 	rxp = sc->sc_rxput;
342 	UART_RECEIVE(sc);
343 #if defined(KDB)
344 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
345 		while (rxp != sc->sc_rxput) {
346 			kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk);
347 			if (rxp == sc->sc_rxbufsz)
348 				rxp = 0;
349 		}
350 	}
351 #endif
352 	if (sc->sc_opened)
353 		uart_sched_softih(sc, SER_INT_RXREADY);
354 	else
355 		sc->sc_rxput = sc->sc_rxget;	/* Ignore received data. */
356 	return (1);
357 }
358 
359 /*
360  * Line or modem status change (OOB signalling).
361  * We pass the signals to the software interrupt handler for further
362  * processing. Note that we merge the delta bits, but set the state
363  * bits. This is to avoid losing state transitions due to having more
364  * than 1 hardware interrupt between software interrupts.
365  */
366 static __inline int
367 uart_intr_sigchg(void *arg)
368 {
369 	struct uart_softc *sc = arg;
370 	int new, old, sig;
371 
372 	sig = UART_GETSIG(sc);
373 
374 	/*
375 	 * Time pulse counting support, invoked whenever the PPS parameters are
376 	 * currently set to capture either edge of the signal.
377 	 */
378 	if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
379 		uart_pps_process(sc, sig);
380 	}
381 
382 	/*
383 	 * Keep track of signal changes, even when the device is not
384 	 * opened. This allows us to inform upper layers about a
385 	 * possible loss of DCD and thus the existence of a (possibly)
386 	 * different connection when we have DCD back, during the time
387 	 * that the device was closed.
388 	 */
389 	do {
390 		old = sc->sc_ttypend;
391 		new = old & ~SER_MASK_STATE;
392 		new |= sig & SER_INT_SIGMASK;
393 	} while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
394 
395 	if (sc->sc_opened)
396 		uart_sched_softih(sc, SER_INT_SIGCHG);
397 	return (1);
398 }
399 
400 /*
401  * The transmitter can accept more data.
402  */
403 static __inline int
404 uart_intr_txidle(void *arg)
405 {
406 	struct uart_softc *sc = arg;
407 
408 	if (sc->sc_txbusy) {
409 		sc->sc_txbusy = 0;
410 		uart_sched_softih(sc, SER_INT_TXIDLE);
411 	}
412 	return (0);
413 }
414 
415 static int
416 uart_intr(void *arg)
417 {
418 	struct uart_softc *sc = arg;
419 	int cnt, ipend, testintr;
420 
421 	if (sc->sc_leaving)
422 		return (FILTER_STRAY);
423 
424 	cnt = 0;
425 	testintr = sc->sc_testintr;
426 	while ((!testintr || cnt < 20) && (ipend = UART_IPEND(sc)) != 0) {
427 		cnt++;
428 		if (ipend & SER_INT_OVERRUN)
429 			uart_intr_overrun(sc);
430 		if (ipend & SER_INT_BREAK)
431 			uart_intr_break(sc);
432 		if (ipend & SER_INT_RXREADY)
433 			uart_intr_rxready(sc);
434 		if (ipend & SER_INT_SIGCHG)
435 			uart_intr_sigchg(sc);
436 		if (ipend & SER_INT_TXIDLE)
437 			uart_intr_txidle(sc);
438 	}
439 
440 	if (sc->sc_polled) {
441 		callout_reset(&sc->sc_timer, hz / uart_poll_freq,
442 		    (timeout_t *)uart_intr, sc);
443 	}
444 
445 	return ((cnt == 0) ? FILTER_STRAY :
446 	    ((testintr && cnt == 20) ? FILTER_SCHEDULE_THREAD :
447 	    FILTER_HANDLED));
448 }
449 
450 serdev_intr_t *
451 uart_bus_ihand(device_t dev, int ipend)
452 {
453 
454 	switch (ipend) {
455 	case SER_INT_BREAK:
456 		return (uart_intr_break);
457 	case SER_INT_OVERRUN:
458 		return (uart_intr_overrun);
459 	case SER_INT_RXREADY:
460 		return (uart_intr_rxready);
461 	case SER_INT_SIGCHG:
462 		return (uart_intr_sigchg);
463 	case SER_INT_TXIDLE:
464 		return (uart_intr_txidle);
465 	}
466 	return (NULL);
467 }
468 
469 int
470 uart_bus_ipend(device_t dev)
471 {
472 	struct uart_softc *sc;
473 
474 	sc = device_get_softc(dev);
475 	return (UART_IPEND(sc));
476 }
477 
478 int
479 uart_bus_sysdev(device_t dev)
480 {
481 	struct uart_softc *sc;
482 
483 	sc = device_get_softc(dev);
484 	return ((sc->sc_sysdev != NULL) ? 1 : 0);
485 }
486 
487 int
488 uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan)
489 {
490 	struct uart_softc *sc;
491 	struct uart_devinfo *sysdev;
492 	int error;
493 
494 	sc = device_get_softc(dev);
495 
496 	/*
497 	 * All uart_class references are weak. Check that the needed
498 	 * class has been compiled-in. Fail if not.
499 	 */
500 	if (sc->sc_class == NULL)
501 		return (ENXIO);
502 
503 	/*
504 	 * Initialize the instance. Note that the instance (=softc) does
505 	 * not necessarily match the hardware specific softc. We can't do
506 	 * anything about it now, because we may not attach to the device.
507 	 * Hardware drivers cannot use any of the class specific fields
508 	 * while probing.
509 	 */
510 	kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class);
511 	sc->sc_dev = dev;
512 	if (device_get_desc(dev) == NULL)
513 		device_set_desc(dev, uart_getname(sc->sc_class));
514 
515 	/*
516 	 * Allocate the register resource. We assume that all UARTs have
517 	 * a single register window in either I/O port space or memory
518 	 * mapped I/O space. Any UART that needs multiple windows will
519 	 * consequently not be supported by this driver as-is. We try I/O
520 	 * port space first because that's the common case.
521 	 */
522 	sc->sc_rrid = rid;
523 	sc->sc_rtype = SYS_RES_IOPORT;
524 	sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
525 	    RF_ACTIVE);
526 	if (sc->sc_rres == NULL) {
527 		sc->sc_rrid = rid;
528 		sc->sc_rtype = SYS_RES_MEMORY;
529 		sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype,
530 		    &sc->sc_rrid, RF_ACTIVE);
531 		if (sc->sc_rres == NULL)
532 			return (ENXIO);
533 	}
534 
535 	/*
536 	 * Fill in the bus access structure and compare this device with
537 	 * a possible console device and/or a debug port. We set the flags
538 	 * in the softc so that the hardware dependent probe can adjust
539 	 * accordingly. In general, you don't want to permanently disrupt
540 	 * console I/O.
541 	 */
542 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
543 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
544 	sc->sc_bas.chan = chan;
545 	sc->sc_bas.regshft = regshft;
546 	sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk;
547 
548 	SLIST_FOREACH(sysdev, &uart_sysdevs, next) {
549 		if (chan == sysdev->bas.chan &&
550 		    uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) {
551 			/* XXX check if ops matches class. */
552 			sc->sc_sysdev = sysdev;
553 			sysdev->bas.rclk = sc->sc_bas.rclk;
554 		}
555 	}
556 
557 	error = UART_PROBE(sc);
558 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
559 	return ((error) ? error : BUS_PROBE_DEFAULT);
560 }
561 
562 int
563 uart_bus_attach(device_t dev)
564 {
565 	struct uart_softc *sc, *sc0;
566 	const char *sep;
567 	int error, filt;
568 
569 	/*
570 	 * The sc_class field defines the type of UART we're going to work
571 	 * with and thus the size of the softc. Replace the generic softc
572 	 * with one that matches the UART now that we're certain we handle
573 	 * the device.
574 	 */
575 	sc0 = device_get_softc(dev);
576 	if (sc0->sc_class->size > sizeof(*sc)) {
577 		sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO);
578 		bcopy(sc0, sc, sizeof(*sc));
579 		device_set_softc(dev, sc);
580 	} else
581 		sc = sc0;
582 
583 	/*
584 	 * Now that we know the softc for this device, connect the back
585 	 * pointer from the sysdev for this device, if any
586 	 */
587 	if (sc->sc_sysdev != NULL)
588 		sc->sc_sysdev->sc = sc;
589 
590 	/*
591 	 * Protect ourselves against interrupts while we're not completely
592 	 * finished attaching and initializing. We don't expect interrupts
593 	 * until after UART_ATTACH(), though.
594 	 */
595 	sc->sc_leaving = 1;
596 
597 	mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN);
598 	if (sc->sc_hwmtx == NULL)
599 		sc->sc_hwmtx = &sc->sc_hwmtx_s;
600 
601 	/*
602 	 * Re-allocate. We expect that the softc contains the information
603 	 * collected by uart_bus_probe() intact.
604 	 */
605 	sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
606 	    RF_ACTIVE);
607 	if (sc->sc_rres == NULL) {
608 		mtx_destroy(&sc->sc_hwmtx_s);
609 		return (ENXIO);
610 	}
611 	sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
612 	sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
613 
614 	/*
615 	 * Ensure there is room for at least three full FIFOs of data in the
616 	 * receive buffer (handles the case of low-level drivers with huge
617 	 * FIFOs), and also ensure that there is no less than the historical
618 	 * size of 384 bytes (handles the typical small-FIFO case).
619 	 */
620 	sc->sc_rxbufsz = MAX(384, sc->sc_rxfifosz * 3);
621 	sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf),
622 	    M_UART, M_WAITOK);
623 	sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf),
624 	    M_UART, M_WAITOK);
625 
626 	error = UART_ATTACH(sc);
627 	if (error)
628 		goto fail;
629 
630 	if (sc->sc_hwiflow || sc->sc_hwoflow) {
631 		sep = "";
632 		device_print_prettyname(dev);
633 		if (sc->sc_hwiflow) {
634 			printf("%sRTS iflow", sep);
635 			sep = ", ";
636 		}
637 		if (sc->sc_hwoflow) {
638 			printf("%sCTS oflow", sep);
639 			sep = ", ";
640 		}
641 		printf("\n");
642 	}
643 
644 	if (sc->sc_sysdev != NULL) {
645 		if (sc->sc_sysdev->baudrate == 0) {
646 			if (UART_IOCTL(sc, UART_IOCTL_BAUD,
647 			    (intptr_t)&sc->sc_sysdev->baudrate) != 0)
648 				sc->sc_sysdev->baudrate = -1;
649 		}
650 		switch (sc->sc_sysdev->type) {
651 		case UART_DEV_CONSOLE:
652 			device_printf(dev, "console");
653 			break;
654 		case UART_DEV_DBGPORT:
655 			device_printf(dev, "debug port");
656 			break;
657 		case UART_DEV_KEYBOARD:
658 			device_printf(dev, "keyboard");
659 			break;
660 		default:
661 			device_printf(dev, "unknown system device");
662 			break;
663 		}
664 		printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate,
665 		    "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits,
666 		    sc->sc_sysdev->stopbits);
667 	}
668 
669 	sc->sc_leaving = 0;
670 	sc->sc_testintr = 1;
671 	filt = uart_intr(sc);
672 	sc->sc_testintr = 0;
673 
674 	/*
675 	 * Don't use interrupts if we couldn't clear any pending interrupt
676 	 * conditions. We may have broken H/W and polling is probably the
677 	 * safest thing to do.
678 	 */
679 	if (filt != FILTER_SCHEDULE_THREAD && !uart_force_poll) {
680 		sc->sc_irid = 0;
681 		sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
682 		    &sc->sc_irid, RF_ACTIVE | RF_SHAREABLE);
683 	}
684 	if (sc->sc_ires != NULL) {
685 		error = bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_TTY,
686 		    uart_intr, NULL, sc, &sc->sc_icookie);
687 		sc->sc_fastintr = (error == 0) ? 1 : 0;
688 
689 		if (!sc->sc_fastintr)
690 			error = bus_setup_intr(dev, sc->sc_ires,
691 			    INTR_TYPE_TTY | INTR_MPSAFE, NULL,
692 			    (driver_intr_t *)uart_intr, sc, &sc->sc_icookie);
693 
694 		if (error) {
695 			device_printf(dev, "could not activate interrupt\n");
696 			bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
697 			    sc->sc_ires);
698 			sc->sc_ires = NULL;
699 		}
700 	}
701 	if (sc->sc_ires == NULL) {
702 		/* No interrupt resource. Force polled mode. */
703 		sc->sc_polled = 1;
704 		callout_init(&sc->sc_timer, 1);
705 		callout_reset(&sc->sc_timer, hz / uart_poll_freq,
706 		    (timeout_t *)uart_intr, sc);
707 	}
708 
709 	if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) {
710 		sep = "";
711 		device_print_prettyname(dev);
712 		if (sc->sc_fastintr) {
713 			printf("%sfast interrupt", sep);
714 			sep = ", ";
715 		}
716 		if (sc->sc_polled) {
717 			printf("%spolled mode (%dHz)", sep, uart_poll_freq);
718 			sep = ", ";
719 		}
720 		printf("\n");
721 	}
722 
723 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL) {
724 		if ((error = sc->sc_sysdev->attach(sc)) != 0)
725 			goto fail;
726 	} else {
727 		if ((error = uart_tty_attach(sc)) != 0)
728 			goto fail;
729 		uart_pps_init(sc);
730 	}
731 
732 	if (sc->sc_sysdev != NULL)
733 		sc->sc_sysdev->hwmtx = sc->sc_hwmtx;
734 
735 	return (0);
736 
737  fail:
738 	free(sc->sc_txbuf, M_UART);
739 	free(sc->sc_rxbuf, M_UART);
740 
741 	if (sc->sc_ires != NULL) {
742 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
743 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
744 		    sc->sc_ires);
745 	}
746 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
747 
748 	mtx_destroy(&sc->sc_hwmtx_s);
749 
750 	return (error);
751 }
752 
753 int
754 uart_bus_detach(device_t dev)
755 {
756 	struct uart_softc *sc;
757 
758 	sc = device_get_softc(dev);
759 
760 	sc->sc_leaving = 1;
761 
762 	if (sc->sc_sysdev != NULL)
763 		sc->sc_sysdev->hwmtx = NULL;
764 
765 	UART_DETACH(sc);
766 
767 	if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL)
768 		(*sc->sc_sysdev->detach)(sc);
769 	else
770 		uart_tty_detach(sc);
771 
772 	free(sc->sc_txbuf, M_UART);
773 	free(sc->sc_rxbuf, M_UART);
774 
775 	if (sc->sc_ires != NULL) {
776 		bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
777 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
778 		    sc->sc_ires);
779 	}
780 	bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
781 
782 	mtx_destroy(&sc->sc_hwmtx_s);
783 
784 	if (sc->sc_class->size > sizeof(*sc)) {
785 		device_set_softc(dev, NULL);
786 		free(sc, M_UART);
787 	} else
788 		device_set_softc(dev, NULL);
789 
790 	return (0);
791 }
792 
793 int
794 uart_bus_resume(device_t dev)
795 {
796 	struct uart_softc *sc;
797 
798 	sc = device_get_softc(dev);
799 	return (UART_ATTACH(sc));
800 }
801 
802 void
803 uart_grab(struct uart_devinfo *di)
804 {
805 
806 	if (di->sc)
807 		UART_GRAB(di->sc);
808 }
809 
810 void
811 uart_ungrab(struct uart_devinfo *di)
812 {
813 
814 	if (di->sc)
815 		UART_UNGRAB(di->sc);
816 }
817