1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #ifndef KLD_MODULE 31 #include "opt_comconsole.h" 32 #endif 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/cons.h> 39 #include <sys/fcntl.h> 40 #include <sys/interrupt.h> 41 #include <sys/kdb.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/queue.h> 45 #include <sys/reboot.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include <sys/termios.h> 49 #include <sys/tty.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #include <dev/uart/uart.h> 54 #include <dev/uart/uart_bus.h> 55 #include <dev/uart/uart_cpu.h> 56 57 #include "uart_if.h" 58 59 devclass_t uart_devclass; 60 char uart_driver_name[] = "uart"; 61 62 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs = 63 SLIST_HEAD_INITIALIZER(uart_sysdevs); 64 65 MALLOC_DEFINE(M_UART, "UART", "UART driver"); 66 67 void 68 uart_add_sysdev(struct uart_devinfo *di) 69 { 70 SLIST_INSERT_HEAD(&uart_sysdevs, di, next); 71 } 72 73 /* 74 * Schedule a soft interrupt. We do this on the 0 to !0 transition 75 * of the TTY pending interrupt status. 76 */ 77 static void 78 uart_sched_softih(struct uart_softc *sc, uint32_t ipend) 79 { 80 uint32_t new, old; 81 82 do { 83 old = sc->sc_ttypend; 84 new = old | ipend; 85 } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new)); 86 87 if ((old & SER_INT_MASK) == 0) 88 swi_sched(sc->sc_softih, 0); 89 } 90 91 /* 92 * A break condition has been detected. We treat the break condition as 93 * a special case that should not happen during normal operation. When 94 * the break condition is to be passed to higher levels in the form of 95 * a NUL character, we really want the break to be in the right place in 96 * the input stream. The overhead to achieve that is not in relation to 97 * the exceptional nature of the break condition, so we permit ourselves 98 * to be sloppy. 99 */ 100 static __inline int 101 uart_intr_break(void *arg) 102 { 103 struct uart_softc *sc = arg; 104 105 #if defined(KDB) && defined(BREAK_TO_DEBUGGER) 106 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 107 kdb_enter("Line break on console"); 108 return (0); 109 } 110 #endif 111 if (sc->sc_opened) 112 uart_sched_softih(sc, SER_INT_BREAK); 113 return (0); 114 } 115 116 /* 117 * Handle a receiver overrun situation. We lost at least 1 byte in the 118 * input stream and it's our job to contain the situation. We grab as 119 * much of the data we can, but otherwise flush the receiver FIFO to 120 * create some breathing room. The net effect is that we avoid the 121 * overrun condition to happen for the next X characters, where X is 122 * related to the FIFO size at the cost of loosing data right away. 123 * So, instead of having multiple overrun interrupts in close proximity 124 * to each other and possibly pessimizing UART interrupt latency for 125 * other UARTs in a multiport configuration, we create a longer segment 126 * of missing characters by freeing up the FIFO. 127 * Each overrun condition is marked in the input buffer by a token. The 128 * token represents the loss of at least one, but possible more bytes in 129 * the input stream. 130 */ 131 static __inline int 132 uart_intr_overrun(void *arg) 133 { 134 struct uart_softc *sc = arg; 135 136 if (sc->sc_opened) { 137 UART_RECEIVE(sc); 138 if (uart_rx_put(sc, UART_STAT_OVERRUN)) 139 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 140 uart_sched_softih(sc, SER_INT_RXREADY); 141 } 142 UART_FLUSH(sc, UART_FLUSH_RECEIVER); 143 return (0); 144 } 145 146 /* 147 * Received data ready. 148 */ 149 static __inline int 150 uart_intr_rxready(void *arg) 151 { 152 struct uart_softc *sc = arg; 153 int rxp; 154 155 rxp = sc->sc_rxput; 156 UART_RECEIVE(sc); 157 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER) 158 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 159 while (rxp != sc->sc_rxput) { 160 if (kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk)) 161 kdb_enter("Break sequence on console"); 162 if (rxp == sc->sc_rxbufsz) 163 rxp = 0; 164 } 165 } 166 #endif 167 if (sc->sc_opened) 168 uart_sched_softih(sc, SER_INT_RXREADY); 169 else 170 sc->sc_rxput = sc->sc_rxget; /* Ignore received data. */ 171 return (1); 172 } 173 174 /* 175 * Line or modem status change (OOB signalling). 176 * We pass the signals to the software interrupt handler for further 177 * processing. Note that we merge the delta bits, but set the state 178 * bits. This is to avoid loosing state transitions due to having more 179 * than 1 hardware interrupt between software interrupts. 180 */ 181 static __inline int 182 uart_intr_sigchg(void *arg) 183 { 184 struct uart_softc *sc = arg; 185 int new, old, sig; 186 187 sig = UART_GETSIG(sc); 188 189 if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) { 190 if (sig & UART_SIG_DPPS) { 191 pps_capture(&sc->sc_pps); 192 pps_event(&sc->sc_pps, (sig & UART_SIG_PPS) ? 193 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 194 } 195 } 196 197 /* 198 * Keep track of signal changes, even when the device is not 199 * opened. This allows us to inform upper layers about a 200 * possible loss of DCD and thus the existence of a (possibly) 201 * different connection when we have DCD back, during the time 202 * that the device was closed. 203 */ 204 do { 205 old = sc->sc_ttypend; 206 new = old & ~SER_MASK_STATE; 207 new |= sig & SER_INT_SIGMASK; 208 } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new)); 209 210 if (sc->sc_opened) 211 uart_sched_softih(sc, SER_INT_SIGCHG); 212 return (1); 213 } 214 215 /* 216 * The transmitter can accept more data. 217 */ 218 static __inline int 219 uart_intr_txidle(void *arg) 220 { 221 struct uart_softc *sc = arg; 222 223 if (sc->sc_txbusy) { 224 sc->sc_txbusy = 0; 225 uart_sched_softih(sc, SER_INT_TXIDLE); 226 } 227 return (0); 228 } 229 230 static void 231 uart_intr(void *arg) 232 { 233 struct uart_softc *sc = arg; 234 int ipend; 235 236 while (!sc->sc_leaving && (ipend = UART_IPEND(sc)) != 0) { 237 if (ipend & SER_INT_OVERRUN) 238 uart_intr_overrun(sc); 239 if (ipend & SER_INT_BREAK) 240 uart_intr_break(sc); 241 if (ipend & SER_INT_RXREADY) 242 uart_intr_rxready(sc); 243 if (ipend & SER_INT_SIGCHG) 244 uart_intr_sigchg(sc); 245 if (ipend & SER_INT_TXIDLE) 246 uart_intr_txidle(sc); 247 } 248 } 249 250 serdev_intr_t * 251 uart_bus_ihand(device_t dev, int ipend) 252 { 253 254 switch (ipend) { 255 case SER_INT_BREAK: 256 return (uart_intr_break); 257 case SER_INT_OVERRUN: 258 return (uart_intr_overrun); 259 case SER_INT_RXREADY: 260 return (uart_intr_rxready); 261 case SER_INT_SIGCHG: 262 return (uart_intr_sigchg); 263 case SER_INT_TXIDLE: 264 return (uart_intr_txidle); 265 } 266 return (NULL); 267 } 268 269 int 270 uart_bus_sysdev(device_t dev) 271 { 272 struct uart_softc *sc; 273 274 sc = device_get_softc(dev); 275 return ((sc->sc_sysdev != NULL) ? 1 : 0); 276 } 277 278 int 279 uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan) 280 { 281 struct uart_softc *sc; 282 struct uart_devinfo *sysdev; 283 int error; 284 285 /* 286 * Initialize the instance. Note that the instance (=softc) does 287 * not necessarily match the hardware specific softc. We can't do 288 * anything about it now, because we may not attach to the device. 289 * Hardware drivers cannot use any of the class specific fields 290 * while probing. 291 */ 292 sc = device_get_softc(dev); 293 kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class); 294 sc->sc_dev = dev; 295 if (device_get_desc(dev) == NULL) 296 device_set_desc(dev, sc->sc_class->name); 297 298 /* 299 * Allocate the register resource. We assume that all UARTs have 300 * a single register window in either I/O port space or memory 301 * mapped I/O space. Any UART that needs multiple windows will 302 * consequently not be supported by this driver as-is. We try I/O 303 * port space first because that's the common case. 304 */ 305 sc->sc_rrid = rid; 306 sc->sc_rtype = SYS_RES_IOPORT; 307 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 308 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 309 if (sc->sc_rres == NULL) { 310 sc->sc_rrid = rid; 311 sc->sc_rtype = SYS_RES_MEMORY; 312 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, 313 &sc->sc_rrid, 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 314 if (sc->sc_rres == NULL) 315 return (ENXIO); 316 } 317 318 /* 319 * Fill in the bus access structure and compare this device with 320 * a possible console device and/or a debug port. We set the flags 321 * in the softc so that the hardware dependent probe can adjust 322 * accordingly. In general, you don't want to permanently disrupt 323 * console I/O. 324 */ 325 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); 326 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); 327 sc->sc_bas.chan = chan; 328 sc->sc_bas.regshft = regshft; 329 sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk; 330 331 SLIST_FOREACH(sysdev, &uart_sysdevs, next) { 332 if (chan == sysdev->bas.chan && 333 uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) { 334 /* XXX check if ops matches class. */ 335 sc->sc_sysdev = sysdev; 336 break; 337 } 338 } 339 340 error = UART_PROBE(sc); 341 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 342 return ((error) ? error : BUS_PROBE_DEFAULT); 343 } 344 345 int 346 uart_bus_attach(device_t dev) 347 { 348 struct uart_softc *sc, *sc0; 349 const char *sep; 350 int error; 351 352 /* 353 * The sc_class field defines the type of UART we're going to work 354 * with and thus the size of the softc. Replace the generic softc 355 * with one that matches the UART now that we're certain we handle 356 * the device. 357 */ 358 sc0 = device_get_softc(dev); 359 if (sc0->sc_class->size > sizeof(*sc)) { 360 sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO); 361 bcopy(sc0, sc, sizeof(*sc)); 362 device_set_softc(dev, sc); 363 } else 364 sc = sc0; 365 366 /* 367 * Protect ourselves against interrupts while we're not completely 368 * finished attaching and initializing. We don't expect interrupts 369 * until after UART_ATTACH() though. 370 */ 371 sc->sc_leaving = 1; 372 373 mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN); 374 if (sc->sc_hwmtx == NULL) 375 sc->sc_hwmtx = &sc->sc_hwmtx_s; 376 377 /* 378 * Re-allocate. We expect that the softc contains the information 379 * collected by uart_bus_probe() intact. 380 */ 381 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid, 382 0, ~0, sc->sc_class->uc_range, RF_ACTIVE); 383 if (sc->sc_rres == NULL) { 384 mtx_destroy(&sc->sc_hwmtx_s); 385 return (ENXIO); 386 } 387 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres); 388 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres); 389 390 sc->sc_irid = 0; 391 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid, 392 RF_ACTIVE | RF_SHAREABLE); 393 if (sc->sc_ires != NULL) { 394 error = bus_setup_intr(dev, 395 sc->sc_ires, INTR_TYPE_TTY | INTR_FAST, uart_intr, 396 sc, &sc->sc_icookie); 397 if (error) 398 error = bus_setup_intr(dev, 399 sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE, 400 uart_intr, sc, &sc->sc_icookie); 401 else 402 sc->sc_fastintr = 1; 403 404 if (error) { 405 device_printf(dev, "could not activate interrupt\n"); 406 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 407 sc->sc_ires); 408 sc->sc_ires = NULL; 409 } 410 } 411 if (sc->sc_ires == NULL) { 412 /* XXX no interrupt resource. Force polled mode. */ 413 sc->sc_polled = 1; 414 } 415 416 sc->sc_rxbufsz = IBUFSIZ; 417 sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf), 418 M_UART, M_WAITOK); 419 sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf), 420 M_UART, M_WAITOK); 421 422 error = UART_ATTACH(sc); 423 if (error) 424 goto fail; 425 426 if (sc->sc_hwiflow || sc->sc_hwoflow) { 427 sep = ""; 428 device_print_prettyname(dev); 429 if (sc->sc_hwiflow) { 430 printf("%sRTS iflow", sep); 431 sep = ", "; 432 } 433 if (sc->sc_hwoflow) { 434 printf("%sCTS oflow", sep); 435 sep = ", "; 436 } 437 printf("\n"); 438 } 439 440 if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) { 441 sep = ""; 442 device_print_prettyname(dev); 443 if (sc->sc_fastintr) { 444 printf("%sfast interrupt", sep); 445 sep = ", "; 446 } 447 if (sc->sc_polled) { 448 printf("%spolled mode", sep); 449 sep = ", "; 450 } 451 printf("\n"); 452 } 453 454 if (sc->sc_sysdev != NULL) { 455 if (sc->sc_sysdev->baudrate == 0) { 456 if (UART_IOCTL(sc, UART_IOCTL_BAUD, 457 (intptr_t)&sc->sc_sysdev->baudrate) != 0) 458 sc->sc_sysdev->baudrate = -1; 459 } 460 switch (sc->sc_sysdev->type) { 461 case UART_DEV_CONSOLE: 462 device_printf(dev, "console"); 463 break; 464 case UART_DEV_DBGPORT: 465 device_printf(dev, "debug port"); 466 break; 467 case UART_DEV_KEYBOARD: 468 device_printf(dev, "keyboard"); 469 break; 470 default: 471 device_printf(dev, "unknown system device"); 472 break; 473 } 474 printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate, 475 "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits, 476 sc->sc_sysdev->stopbits); 477 } 478 479 sc->sc_pps.ppscap = PPS_CAPTUREBOTH; 480 pps_init(&sc->sc_pps); 481 482 error = (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL) 483 ? (*sc->sc_sysdev->attach)(sc) : uart_tty_attach(sc); 484 if (error) 485 goto fail; 486 487 if (sc->sc_sysdev != NULL) 488 sc->sc_sysdev->hwmtx = sc->sc_hwmtx; 489 490 sc->sc_leaving = 0; 491 uart_intr(sc); 492 return (0); 493 494 fail: 495 free(sc->sc_txbuf, M_UART); 496 free(sc->sc_rxbuf, M_UART); 497 498 if (sc->sc_ires != NULL) { 499 bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); 500 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 501 sc->sc_ires); 502 } 503 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 504 505 mtx_destroy(&sc->sc_hwmtx_s); 506 507 return (error); 508 } 509 510 int 511 uart_bus_detach(device_t dev) 512 { 513 struct uart_softc *sc; 514 515 sc = device_get_softc(dev); 516 517 sc->sc_leaving = 1; 518 519 if (sc->sc_sysdev != NULL) 520 sc->sc_sysdev->hwmtx = NULL; 521 522 UART_DETACH(sc); 523 524 if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL) 525 (*sc->sc_sysdev->detach)(sc); 526 else 527 uart_tty_detach(sc); 528 529 free(sc->sc_txbuf, M_UART); 530 free(sc->sc_rxbuf, M_UART); 531 532 if (sc->sc_ires != NULL) { 533 bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie); 534 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, 535 sc->sc_ires); 536 } 537 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres); 538 539 mtx_destroy(&sc->sc_hwmtx_s); 540 541 if (sc->sc_class->size > sizeof(*sc)) { 542 device_set_softc(dev, NULL); 543 free(sc, M_UART); 544 } else 545 device_set_softc(dev, NULL); 546 547 return (0); 548 } 549