1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_UART_H_ 30 #define _DEV_UART_H_ 31 32 /* 33 * Bus access structure. This structure holds the minimum information needed 34 * to access the UART. The rclk field, although not important to actually 35 * access the UART, is important for baudrate programming, delay loops and 36 * other timing related computations. 37 */ 38 struct uart_bas { 39 bus_space_tag_t bst; 40 bus_space_handle_t bsh; 41 u_int chan; 42 u_int rclk; 43 u_int regshft; 44 u_int regiowidth; 45 }; 46 47 #define uart_regofs(bas, reg) ((reg) << (bas)->regshft) 48 #define uart_regiowidth(bas) ((bas)->regiowidth) 49 50 static inline uint32_t 51 uart_getreg(struct uart_bas *bas, int reg) 52 { 53 uint32_t ret; 54 55 switch (uart_regiowidth(bas)) { 56 case 4: 57 ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg)); 58 break; 59 case 2: 60 ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg)); 61 break; 62 default: 63 ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg)); 64 break; 65 } 66 67 return (ret); 68 } 69 70 static inline void 71 uart_setreg(struct uart_bas *bas, int reg, int value) 72 { 73 74 switch (uart_regiowidth(bas)) { 75 case 4: 76 bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 77 break; 78 case 2: 79 bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 80 break; 81 default: 82 bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 83 break; 84 } 85 } 86 87 /* 88 * XXX we don't know the length of the bus space address range in use by 89 * the UART. Since barriers don't use the length field currently, we put 90 * a zero there for now. 91 */ 92 #define uart_barrier(bas) \ 93 bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \ 94 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 95 96 /* 97 * UART device classes. 98 */ 99 struct uart_class; 100 101 extern struct uart_class uart_ns8250_class __attribute__((weak)); 102 extern struct uart_class uart_quicc_class __attribute__((weak)); 103 extern struct uart_class uart_s3c2410_class __attribute__((weak)); 104 extern struct uart_class uart_sab82532_class __attribute__((weak)); 105 extern struct uart_class uart_sbbc_class __attribute__((weak)); 106 extern struct uart_class uart_z8530_class __attribute__((weak)); 107 108 /* 109 * Device flags. 110 */ 111 #define UART_FLAGS_CONSOLE(f) ((f) & 0x10) 112 #define UART_FLAGS_DBGPORT(f) ((f) & 0x80) 113 #define UART_FLAGS_FCR_RX_LOW(f) ((f) & 0x100) 114 #define UART_FLAGS_FCR_RX_MEDL(f) ((f) & 0x200) 115 #define UART_FLAGS_FCR_RX_MEDH(f) ((f) & 0x400) 116 #define UART_FLAGS_FCR_RX_HIGH(f) ((f) & 0x800) 117 118 /* 119 * Data parity values (magical numbers related to ns8250). 120 */ 121 #define UART_PARITY_NONE 0 122 #define UART_PARITY_ODD 1 123 #define UART_PARITY_EVEN 3 124 #define UART_PARITY_MARK 5 125 #define UART_PARITY_SPACE 7 126 127 #endif /* _DEV_UART_H_ */ 128