1098ca2bdSWarner Losh /*- 2*718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3*718cf2ccSPedro F. Giffuni * 427d5dc18SMarcel Moolenaar * Copyright (c) 2003 Marcel Moolenaar 527d5dc18SMarcel Moolenaar * All rights reserved. 627d5dc18SMarcel Moolenaar * 727d5dc18SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 827d5dc18SMarcel Moolenaar * modification, are permitted provided that the following conditions 927d5dc18SMarcel Moolenaar * are met: 1027d5dc18SMarcel Moolenaar * 1127d5dc18SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1227d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1327d5dc18SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1427d5dc18SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1527d5dc18SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1627d5dc18SMarcel Moolenaar * 1727d5dc18SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1827d5dc18SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1927d5dc18SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2027d5dc18SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2127d5dc18SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2227d5dc18SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2327d5dc18SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2427d5dc18SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2527d5dc18SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2627d5dc18SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2727d5dc18SMarcel Moolenaar * 2827d5dc18SMarcel Moolenaar * $FreeBSD$ 2927d5dc18SMarcel Moolenaar */ 3027d5dc18SMarcel Moolenaar 3127d5dc18SMarcel Moolenaar #ifndef _DEV_UART_H_ 3227d5dc18SMarcel Moolenaar #define _DEV_UART_H_ 3327d5dc18SMarcel Moolenaar 3427d5dc18SMarcel Moolenaar /* 3527d5dc18SMarcel Moolenaar * Bus access structure. This structure holds the minimum information needed 3627d5dc18SMarcel Moolenaar * to access the UART. The rclk field, although not important to actually 3727d5dc18SMarcel Moolenaar * access the UART, is important for baudrate programming, delay loops and 3827d5dc18SMarcel Moolenaar * other timing related computations. 3927d5dc18SMarcel Moolenaar */ 4027d5dc18SMarcel Moolenaar struct uart_bas { 4127d5dc18SMarcel Moolenaar bus_space_tag_t bst; 4227d5dc18SMarcel Moolenaar bus_space_handle_t bsh; 43875f70dbSMarcel Moolenaar u_int chan; 4427d5dc18SMarcel Moolenaar u_int rclk; 45875f70dbSMarcel Moolenaar u_int regshft; 46c214a270SRuslan Bukin u_int regiowidth; 4727d5dc18SMarcel Moolenaar }; 4827d5dc18SMarcel Moolenaar 4927d5dc18SMarcel Moolenaar #define uart_regofs(bas, reg) ((reg) << (bas)->regshft) 50c214a270SRuslan Bukin #define uart_regiowidth(bas) ((bas)->regiowidth) 5127d5dc18SMarcel Moolenaar 52c214a270SRuslan Bukin static inline uint32_t 53c214a270SRuslan Bukin uart_getreg(struct uart_bas *bas, int reg) 54c214a270SRuslan Bukin { 55c214a270SRuslan Bukin uint32_t ret; 56c214a270SRuslan Bukin 57c214a270SRuslan Bukin switch (uart_regiowidth(bas)) { 58c214a270SRuslan Bukin case 4: 59c214a270SRuslan Bukin ret = bus_space_read_4(bas->bst, bas->bsh, uart_regofs(bas, reg)); 60c214a270SRuslan Bukin break; 61c214a270SRuslan Bukin case 2: 62c214a270SRuslan Bukin ret = bus_space_read_2(bas->bst, bas->bsh, uart_regofs(bas, reg)); 63c214a270SRuslan Bukin break; 64c214a270SRuslan Bukin default: 65c214a270SRuslan Bukin ret = bus_space_read_1(bas->bst, bas->bsh, uart_regofs(bas, reg)); 66c214a270SRuslan Bukin break; 67c214a270SRuslan Bukin } 68c214a270SRuslan Bukin 69c214a270SRuslan Bukin return (ret); 70c214a270SRuslan Bukin } 71c214a270SRuslan Bukin 72c214a270SRuslan Bukin static inline void 73c214a270SRuslan Bukin uart_setreg(struct uart_bas *bas, int reg, int value) 74c214a270SRuslan Bukin { 75c214a270SRuslan Bukin 76c214a270SRuslan Bukin switch (uart_regiowidth(bas)) { 77c214a270SRuslan Bukin case 4: 78c214a270SRuslan Bukin bus_space_write_4(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 79c214a270SRuslan Bukin break; 80c214a270SRuslan Bukin case 2: 81c214a270SRuslan Bukin bus_space_write_2(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 82c214a270SRuslan Bukin break; 83c214a270SRuslan Bukin default: 84c214a270SRuslan Bukin bus_space_write_1(bas->bst, bas->bsh, uart_regofs(bas, reg), value); 85c214a270SRuslan Bukin break; 86c214a270SRuslan Bukin } 87c214a270SRuslan Bukin } 8827d5dc18SMarcel Moolenaar 8927d5dc18SMarcel Moolenaar /* 9027d5dc18SMarcel Moolenaar * XXX we don't know the length of the bus space address range in use by 9127d5dc18SMarcel Moolenaar * the UART. Since barriers don't use the length field currently, we put 9227d5dc18SMarcel Moolenaar * a zero there for now. 9327d5dc18SMarcel Moolenaar */ 9427d5dc18SMarcel Moolenaar #define uart_barrier(bas) \ 9527d5dc18SMarcel Moolenaar bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \ 9627d5dc18SMarcel Moolenaar BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 9727d5dc18SMarcel Moolenaar 9827d5dc18SMarcel Moolenaar /* 99f8100ce2SMarcel Moolenaar * UART device classes. 100f8100ce2SMarcel Moolenaar */ 101f8100ce2SMarcel Moolenaar struct uart_class; 102f8100ce2SMarcel Moolenaar 103f8100ce2SMarcel Moolenaar extern struct uart_class uart_ns8250_class __attribute__((weak)); 1046b7ba544SRafal Jaworowski extern struct uart_class uart_quicc_class __attribute__((weak)); 1055d490515SAleksandr Rybalko extern struct uart_class uart_s3c2410_class __attribute__((weak)); 106f8100ce2SMarcel Moolenaar extern struct uart_class uart_sab82532_class __attribute__((weak)); 107d5dba21cSMarius Strobl extern struct uart_class uart_sbbc_class __attribute__((weak)); 108f8100ce2SMarcel Moolenaar extern struct uart_class uart_z8530_class __attribute__((weak)); 10964958185SIan Lepore 110f8100ce2SMarcel Moolenaar /* 11127d5dc18SMarcel Moolenaar * Device flags. 11227d5dc18SMarcel Moolenaar */ 11327d5dc18SMarcel Moolenaar #define UART_FLAGS_CONSOLE(f) ((f) & 0x10) 11427d5dc18SMarcel Moolenaar #define UART_FLAGS_DBGPORT(f) ((f) & 0x80) 115823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_LOW(f) ((f) & 0x100) 116823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_MEDL(f) ((f) & 0x200) 117823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_MEDH(f) ((f) & 0x400) 118823c77d7SSam Leffler #define UART_FLAGS_FCR_RX_HIGH(f) ((f) & 0x800) 11927d5dc18SMarcel Moolenaar 12027d5dc18SMarcel Moolenaar /* 12127d5dc18SMarcel Moolenaar * Data parity values (magical numbers related to ns8250). 12227d5dc18SMarcel Moolenaar */ 12327d5dc18SMarcel Moolenaar #define UART_PARITY_NONE 0 12427d5dc18SMarcel Moolenaar #define UART_PARITY_ODD 1 12527d5dc18SMarcel Moolenaar #define UART_PARITY_EVEN 3 12627d5dc18SMarcel Moolenaar #define UART_PARITY_MARK 5 12727d5dc18SMarcel Moolenaar #define UART_PARITY_SPACE 7 12827d5dc18SMarcel Moolenaar 12927d5dc18SMarcel Moolenaar #endif /* _DEV_UART_H_ */ 130