1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2010, LSI Corp. 5 * All rights reserved. 6 * Author : Manjunath Ranganathaiah 7 * Support: freebsdraid@lsi.com 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of the <ORGANIZATION> nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* bit's defination */ 38 39 #define TWS_BIT0 0x00000001 40 #define TWS_BIT1 0x00000002 41 #define TWS_BIT2 0x00000004 42 #define TWS_BIT3 0x00000008 43 #define TWS_BIT4 0x00000010 44 #define TWS_BIT5 0x00000020 45 #define TWS_BIT6 0x00000040 46 #define TWS_BIT7 0x00000080 47 #define TWS_BIT8 0x00000100 48 #define TWS_BIT9 0x00000200 49 #define TWS_BIT10 0x00000400 50 #define TWS_BIT11 0x00000800 51 #define TWS_BIT12 0x00001000 52 #define TWS_BIT13 0x00002000 53 #define TWS_BIT14 0x00004000 54 #define TWS_BIT15 0x00008000 55 #define TWS_BIT16 0x00010000 56 #define TWS_BIT17 0x00020000 57 #define TWS_BIT18 0x00040000 58 #define TWS_BIT19 0x00080000 59 #define TWS_BIT20 0x00100000 60 #define TWS_BIT21 0x00200000 61 #define TWS_BIT22 0x00400000 62 #define TWS_BIT23 0x00800000 63 #define TWS_BIT24 0x01000000 64 #define TWS_BIT25 0x02000000 65 #define TWS_BIT26 0x04000000 66 #define TWS_BIT27 0x08000000 67 #define TWS_BIT28 0x10000000 68 #define TWS_BIT29 0x20000000 69 #define TWS_BIT30 0x40000000 70 #define TWS_BIT31 0x80000000 71 72 #define TWS_SENSE_DATA_LENGTH 18 73 #define TWS_ERROR_SPECIFIC_DESC_LEN 98 74 75 /* response codes */ 76 #define TWS_SENSE_SCSI_CURRENT_ERROR 0x70 77 #define TWS_SENSE_SCSI_DEFERRED_ERROR 0x71 78 79 #define TWS_SRC_CTRL_ERROR 3 80 #define TWS_SRC_CTRL_EVENT 4 81 #define TWS_SRC_FREEBSD_DRIVER 5 82 #define TWS_SRC_FREEBSD_OS 8 83 84 enum tws_sense_severity { 85 error = 1, 86 warning , 87 info, 88 debug, 89 }; 90 91 /* 92 * Some errors of interest (in cmd_hdr->status_block.error) when a command 93 * is completed by the firmware with an error. 94 */ 95 #define TWS_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 96 #define TWS_ERROR_NOT_SUPPORTED 0x010D 97 #define TWS_ERROR_UNIT_OFFLINE 0x0128 98 #define TWS_ERROR_MORE_DATA 0x0231 99 100 /* AEN codes of interest. */ 101 #define TWS_AEN_QUEUE_EMPTY 0x00 102 #define TWS_AEN_SOFT_RESET 0x01 103 #define TWS_AEN_SYNC_TIME_WITH_HOST 0x31 104 105 /* AEN severity */ 106 #define TWS_SEVERITY_ERROR 0x1 107 #define TWS_SEVERITY_WARNING 0x2 108 #define TWS_SEVERITY_INFO 0x3 109 #define TWS_SEVERITY_DEBUG 0x4 110 111 #define TWS_64BIT_SG_ADDRESSES 0x00000001 112 #define TWS_BIT_EXTEND 0x00000002 113 114 #define TWS_BASE_FW_SRL 24 115 #define TWS_BASE_FW_BRANCH 0 116 #define TWS_BASE_FW_BUILD 1 117 #define TWS_CURRENT_FW_SRL 41 118 119 #define TWS_CURRENT_FW_BRANCH 8 120 #define TWS_CURRENT_FW_BUILD 4 121 #define TWS_CURRENT_ARCH_ID 0x000A 122 123 #define TWS_FIFO_EMPTY 0xFFFFFFFFFFFFFFFFull 124 #define TWS_FIFO_EMPTY32 0xFFFFFFFFull 125 126 /* Register offsets from base address. */ 127 #define TWS_CONTROL_REGISTER_OFFSET 0x0 128 #define TWS_STATUS_REGISTER_OFFSET 0x4 129 #define TWS_COMMAND_QUEUE_OFFSET 0x8 130 #define TWS_RESPONSE_QUEUE_OFFSET 0xC 131 #define TWS_COMMAND_QUEUE_OFFSET_LOW 0x20 132 #define TWS_COMMAND_QUEUE_OFFSET_HIGH 0x24 133 #define TWS_LARGE_RESPONSE_QUEUE_OFFSET 0x30 134 135 /* I2O offsets */ 136 #define TWS_I2O0_STATUS 0x0 137 138 #define TWS_I2O0_HIBDB 0x20 139 140 #define TWS_I2O0_HISTAT 0x30 141 #define TWS_I2O0_HIMASK 0x34 142 143 #define TWS_I2O0_HIBQP 0x40 144 #define TWS_I2O0_HOBQP 0x44 145 146 #define TWS_I2O0_CTL 0x74 147 148 #define TWS_I2O0_IOBDB 0x9C 149 #define TWS_I2O0_HOBDBC 0xA0 150 151 #define TWS_I2O0_SCRPD3 0xBC 152 153 #define TWS_I2O0_HIBQPL 0xC0 /* 64bit inb port low */ 154 #define TWS_I2O0_HIBQPH 0xC4 /* 64bit inb port high */ 155 #define TWS_I2O0_HOBQPL 0xC8 /* 64bit out port low */ 156 #define TWS_I2O0_HOBQPH 0xCC /* 64bit out port high */ 157 158 /* IOP related */ 159 #define TWS_I2O0_IOPOBQPL 0xD8 /* OBFL */ 160 #define TWS_I2O0_IOPOBQPH 0xDC /* OBFH */ 161 #define TWS_I2O0_SRC_ADDRH 0xF8 /* Msg ASA */ 162 163 #define TWS_MSG_ACC_MASK 0x20000000 164 #define TWS_32BIT_MASK 0xFFFFFFFF 165 166 /* revisit */ 167 #define TWS_FW_CMD_NOP 0x0 168 #define TWS_FW_CMD_INIT_CONNECTION 0x01 169 #define TWS_FW_CMD_EXECUTE_SCSI 0x10 170 171 #define TWS_FW_CMD_ATA_PASSTHROUGH 0x11 // This is really a PASSTHROUGH for both ATA and SCSI commands. 172 #define TWS_FW_CMD_GET_PARAM 0x12 173 #define TWS_FW_CMD_SET_PARAM 0x13 174 175 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \ 176 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 177 178 #define BUILD_RES__OPCODE(res, opcode) \ 179 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 180 181 #define GET_OPCODE(sgl_off__opcode) \ 182 (sgl_off__opcode & 0x1F) /* 3:5 */ 183 184 /* end revisit */ 185 186 /* Table #'s and id's of parameters of interest in firmware's param table. */ 187 #define TWS_PARAM_VERSION_TABLE 0x0402 188 #define TWS_PARAM_VERSION_FW 3 /* firmware version [16] */ 189 #define TWS_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 190 #define TWS_PARAM_CTLR_MODEL 8 /* Controller model [16] */ 191 192 #define TWS_PARAM_CONTROLLER_TABLE 0x0403 193 #define TWS_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */ 194 195 #define TWS_PARAM_TIME_TABLE 0x40A 196 #define TWS_PARAM_TIME_SCHED_TIME 0x3 197 198 #define TWS_PARAM_PHYS_TABLE 0x0001 199 #define TWS_PARAM_CONTROLLER_PHYS_COUNT 2 /* number of phys */ 200 201 #define TWS_9K_PARAM_DESCRIPTOR 0x8000 202 203 /* ----------- request ------------- */ 204 205 #pragma pack(1) 206 207 struct tws_cmd_init_connect { 208 u_int8_t res1__opcode; /* 3:5 */ 209 u_int8_t size; 210 u_int8_t request_id; 211 u_int8_t res2; 212 u_int8_t status; 213 u_int8_t flags; 214 u_int16_t message_credits; 215 u_int32_t features; 216 u_int16_t fw_srl; 217 u_int16_t fw_arch_id; 218 u_int16_t fw_branch; 219 u_int16_t fw_build; 220 u_int32_t result; 221 }; 222 223 /* Structure for downloading firmware onto the controller. */ 224 struct tws_cmd_download_firmware { 225 u_int8_t sgl_off__opcode;/* 3:5 */ 226 u_int8_t size; 227 u_int8_t request_id; 228 u_int8_t unit; 229 u_int8_t status; 230 u_int8_t flags; 231 u_int16_t param; 232 u_int8_t sgl[1]; 233 }; 234 235 /* Structure for hard resetting the controller. */ 236 struct tws_cmd_reset_firmware { 237 u_int8_t res1__opcode; /* 3:5 */ 238 u_int8_t size; 239 u_int8_t request_id; 240 u_int8_t unit; 241 u_int8_t status; 242 u_int8_t flags; 243 u_int8_t res2; 244 u_int8_t param; 245 }; 246 247 /* Structure for sending get/set param commands. */ 248 struct tws_cmd_param { 249 u_int8_t sgl_off__opcode;/* 3:5 */ 250 u_int8_t size; 251 u_int8_t request_id; 252 u_int8_t host_id__unit; /* 4:4 */ 253 u_int8_t status; 254 u_int8_t flags; 255 u_int16_t param_count; 256 u_int8_t sgl[1]; 257 }; 258 259 /* Generic command packet. */ 260 struct tws_cmd_generic { 261 u_int8_t sgl_off__opcode;/* 3:5 */ 262 u_int8_t size; 263 u_int8_t request_id; 264 u_int8_t host_id__unit; /* 4:4 */ 265 u_int8_t status; 266 u_int8_t flags; 267 u_int16_t count; /* block cnt, parameter cnt, message credits */ 268 }; 269 270 /* Command packet header. */ 271 struct tws_command_header { 272 u_int8_t sense_data[TWS_SENSE_DATA_LENGTH]; 273 struct { /* status block - additional sense data */ 274 u_int16_t srcnum; 275 u_int8_t reserved; 276 u_int8_t status; 277 u_int16_t error; 278 u_int8_t res__srcid; /* 4:4 */ 279 u_int8_t res__severity; /* 5:3 */ 280 } status_block; 281 u_int8_t err_specific_desc[TWS_ERROR_SPECIFIC_DESC_LEN]; 282 struct { /* sense buffer descriptor */ 283 u_int8_t size_header; 284 u_int16_t request_id; 285 u_int8_t size_sense; 286 } header_desc; 287 }; 288 289 /* Command - 1024 byte size including header (128+24+896)*/ 290 union tws_command_giga { 291 struct tws_cmd_init_connect init_connect; 292 struct tws_cmd_download_firmware download_fw; 293 struct tws_cmd_reset_firmware reset_fw; 294 struct tws_cmd_param param; 295 struct tws_cmd_generic generic; 296 u_int8_t padding[1024 - sizeof(struct tws_command_header)]; 297 }; 298 299 /* driver command pkt - 1024 byte size including header(128+24+744+128) */ 300 /* h/w & f/w supported command size excluding header 768 */ 301 struct tws_command_apache { 302 u_int8_t res__opcode; /* 3:5 */ 303 u_int8_t unit; 304 u_int16_t lun_l4__req_id; /* 4:12 */ 305 u_int8_t status; 306 u_int8_t sgl_offset; /* offset (in bytes) to sg_list, 307 from the end of sgl_entries */ 308 u_int16_t lun_h4__sgl_entries; 309 u_int8_t cdb[16]; 310 u_int8_t sg_list[744]; /* 768 - 24 */ 311 u_int8_t padding[128]; /* make it 1024 bytes */ 312 }; 313 314 struct tws_command_packet { 315 struct tws_command_header hdr; 316 union { 317 union tws_command_giga pkt_g; 318 struct tws_command_apache pkt_a; 319 } cmd; 320 }; 321 322 /* Structure describing payload for get/set param commands. */ 323 struct tws_getset_param { 324 u_int16_t table_id; 325 u_int8_t parameter_id; 326 u_int8_t reserved; 327 u_int16_t parameter_size_bytes; 328 u_int16_t parameter_actual_size_bytes; 329 u_int8_t data[1]; 330 }; 331 332 struct tws_outbound_response { 333 u_int32_t not_mfa :1; /* 1 if the structure is valid else MFA */ 334 u_int32_t reserved :7; /* reserved bits */ 335 u_int32_t status :8; /* should be 0 */ 336 u_int32_t request_id:16; /* request id */ 337 }; 338 339 /* Scatter/Gather list entry with 32 bit addresses. */ 340 struct tws_sg_desc32 { 341 u_int32_t address; 342 u_int32_t length :24; 343 u_int32_t flag :8; 344 }; 345 346 /* Scatter/Gather list entry with 64 bit addresses. */ 347 struct tws_sg_desc64 { 348 u_int64_t address; 349 u_int64_t length :32; 350 u_int64_t reserved :24; 351 u_int64_t flag :8; 352 }; 353 354 /* 355 * Packet that describes an AEN/error generated by the controller, 356 * shared with user 357 */ 358 struct tws_event_packet { 359 u_int32_t sequence_id; 360 u_int32_t time_stamp_sec; 361 u_int16_t aen_code; 362 u_int8_t severity; 363 u_int8_t retrieved; 364 u_int8_t repeat_count; 365 u_int8_t parameter_len; 366 u_int8_t parameter_data[TWS_ERROR_SPECIFIC_DESC_LEN]; 367 u_int32_t event_src; 368 u_int8_t severity_str[20]; 369 }; 370 371 #pragma pack() 372 373 struct tws_sense { 374 struct tws_command_header *hdr; 375 u_int64_t hdr_pkt_phy; 376 }; 377 378 struct tws_request { 379 struct tws_command_packet *cmd_pkt; /* command pkt */ 380 u_int64_t cmd_pkt_phy; /* cmd pkt physical address */ 381 void *data; /* ptr to data being passed to fw */ 382 u_int32_t length; /* length of data being passed to fw */ 383 384 u_int32_t state; /* request state */ 385 u_int32_t type; /* request type */ 386 u_int32_t flags; /* request flags */ 387 388 u_int32_t error_code; /* error during request processing */ 389 390 u_int32_t request_id; /* request id for tracking with fw */ 391 void (*cb)(struct tws_request *); /* callback func */ 392 bus_dmamap_t dma_map; /* dma map */ 393 union ccb *ccb_ptr; /* pointer to ccb */ 394 struct callout timeout; /* request timeout timer */ 395 struct tws_softc *sc; /* pointer back to ctlr softc */ 396 397 struct tws_request *next; /* pointer to next request */ 398 struct tws_request *prev; /* pointer to prev request */ 399 }; 400