1 /*- 2 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik 3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #define TSEC_REG_ID 0x000 /* Controller ID register #1. */ 30 #define TSEC_REG_ID2 0x004 /* Controller ID register #2. */ 31 32 /* TSEC General Control and Status Registers */ 33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */ 34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */ 35 #define TSEC_REG_EDIS 0x018 /* Error disabled register */ 36 #define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */ 37 #define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */ 38 #define TSEC_REG_PTV 0x028 /* Pause time value register */ 39 #define TSEC_REG_DMACTRL 0x02c /* DMA control register */ 40 #define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */ 41 42 /* TSEC FIFO Control and Status Registers */ 43 #define TSEC_REG_FIFO_PAUSE_CTRL 0x04c /* FIFO pause control register */ 44 #define TSEC_REG_FIFO_TX_THR 0x08c /* FIFO transmit threshold register */ 45 #define TSEC_REG_FIFO_TX_STARVE 0x098 /* FIFO transmit starve register */ 46 #define TSEC_REG_FIFO_TX_STARVE_SHUTOFF 0x09c /* FIFO transmit starve shutoff 47 * register */ 48 49 /* TSEC Transmit Control and Status Registers */ 50 #define TSEC_REG_TCTRL 0x100 /* Transmit control register */ 51 #define TSEC_REG_TSTAT 0x104 /* Transmit Status Register */ 52 #define TSEC_REG_TBDLEN 0x10c /* TxBD data length register */ 53 #define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing 54 * configuration register */ 55 #define TSEC_REG_CTBPTR 0x124 /* Current TxBD pointer register */ 56 #define TSEC_REG_TBPTR 0x184 /* TxBD pointer register */ 57 #define TSEC_REG_TBASE 0x204 /* TxBD base address register */ 58 #define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */ 59 #define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer 60 * register */ 61 62 /* TSEC Receive Control and Status Registers */ 63 #define TSEC_REG_RCTRL 0x300 /* Receive control register */ 64 #define TSEC_REG_RSTAT 0x304 /* Receive status register */ 65 #define TSEC_REG_RBDLEN 0x30c /* RxBD data length register */ 66 #define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing 67 * configuration register */ 68 #define TSEC_REG_CRBPTR 0x324 /* Current RxBD pointer register */ 69 #define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */ 70 #define TSEC_REG_RBPTR 0x384 /* RxBD pointer register */ 71 #define TSEC_REG_RBASE 0x404 /* RxBD base address register */ 72 73 /* TSEC MAC Registers */ 74 #define TSEC_REG_MACCFG1 0x500 /* MAC configuration 1 register */ 75 #define TSEC_REG_MACCFG2 0x504 /* MAC configuration 2 register */ 76 #define TSEC_REG_IPGIFG 0x508 /* Inter-packet gap/inter-frame gap 77 * register */ 78 #define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */ 79 #define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */ 80 #define TSEC_REG_MIIBASE 0x520 /* MII Management base, rest offsets */ 81 #define TSEC_REG_MIIMCFG 0x0 /* MII Management configuration register */ 82 #define TSEC_REG_MIIMCOM 0x4 /* MII Management command register */ 83 #define TSEC_REG_MIIMADD 0x8 /* MII Management address register */ 84 #define TSEC_REG_MIIMCON 0xc /* MII Management control register */ 85 #define TSEC_REG_MIIMSTAT 0x10 /* MII Management status register */ 86 #define TSEC_REG_MIIMIND 0x14 /* MII Management indicator register */ 87 #define TSEC_REG_IFSTAT 0x53c /* Interface status register */ 88 #define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */ 89 #define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */ 90 91 /* TSEC Transmit and Receive Counters */ 92 #define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte 93 * frame counter register */ 94 #define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte 95 * frame counter register */ 96 #define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte 97 * frame counter register */ 98 #define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte 99 * frame counter register */ 100 #define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte 101 * frame counter register */ 102 #define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte 103 * frame counter register */ 104 #define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte 105 * good VLAN frame counter register */ 106 107 /* TSEC Receive Counters */ 108 #define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */ 109 #define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */ 110 #define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */ 111 #define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter 112 * register */ 113 #define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter 114 * register */ 115 #define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter 116 * register */ 117 #define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter 118 * register */ 119 #define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter 120 * register */ 121 #define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter 122 * register */ 123 #define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter 124 * register */ 125 #define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */ 126 #define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter 127 * register */ 128 #define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter 129 * register */ 130 #define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter 131 * register */ 132 #define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */ 133 #define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */ 134 #define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */ 135 136 /* TSEC Transmit Counters */ 137 #define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */ 138 #define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */ 139 #define TSEC_REG_MON_TMCA 0x6e8 /* Transmit multicast packet counter 140 * register */ 141 #define TSEC_REG_MON_TBCA 0x6ec /* Transmit broadcast packet counter 142 * register */ 143 #define TSEC_REG_MON_TXPF 0x6f0 /* Transmit PAUSE control frame counter 144 * register */ 145 #define TSEC_REG_MON_TDFR 0x6f4 /* Transmit deferral packet counter 146 * register */ 147 #define TSEC_REG_MON_TEDF 0x6f8 /* Transmit excessive deferral packet 148 * counter register */ 149 #define TSEC_REG_MON_TSCL 0x6fc /* Transmit single collision packet counter 150 * register */ 151 #define TSEC_REG_MON_TMCL 0x700 /* Transmit multiple collision packet counter 152 * register */ 153 #define TSEC_REG_MON_TLCL 0x704 /* Transmit late collision packet counter 154 * register */ 155 #define TSEC_REG_MON_TXCL 0x708 /* Transmit excessive collision packet 156 * counter register */ 157 #define TSEC_REG_MON_TNCL 0x70c /* Transmit total collision counter 158 * register */ 159 #define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */ 160 #define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */ 161 #define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */ 162 #define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */ 163 #define TSEC_REG_MON_TOVR 0x724 /* Transmit oversize frame counter 164 * register */ 165 #define TSEC_REG_MON_TUND 0x728 /* Transmit undersize frame counter 166 * register */ 167 #define TSEC_REG_MON_TFRG 0x72c /* Transmit fragments frame counter 168 * register */ 169 170 /* TSEC General Registers */ 171 #define TSEC_REG_MON_CAR1 0x730 /* Carry register one register */ 172 #define TSEC_REG_MON_CAR2 0x734 /* Carry register two register */ 173 #define TSEC_REG_MON_CAM1 0x738 /* Carry register one mask register */ 174 #define TSEC_REG_MON_CAM2 0x73c /* Carry register two mask register */ 175 176 /* TSEC Hash Function Registers */ 177 #define TSEC_REG_IADDR0 0x800 /* Indivdual address register 0 */ 178 #define TSEC_REG_IADDR1 0x804 /* Indivdual address register 1 */ 179 #define TSEC_REG_IADDR2 0x808 /* Indivdual address register 2 */ 180 #define TSEC_REG_IADDR3 0x80c /* Indivdual address register 3 */ 181 #define TSEC_REG_IADDR4 0x810 /* Indivdual address register 4 */ 182 #define TSEC_REG_IADDR5 0x814 /* Indivdual address register 5 */ 183 #define TSEC_REG_IADDR6 0x818 /* Indivdual address register 6 */ 184 #define TSEC_REG_IADDR7 0x81c /* Indivdual address register 7 */ 185 #define TSEC_REG_GADDR0 0x880 /* Group address register 0 */ 186 #define TSEC_REG_GADDR1 0x884 /* Group address register 1 */ 187 #define TSEC_REG_GADDR2 0x888 /* Group address register 2 */ 188 #define TSEC_REG_GADDR3 0x88c /* Group address register 3 */ 189 #define TSEC_REG_GADDR4 0x890 /* Group address register 4 */ 190 #define TSEC_REG_GADDR5 0x894 /* Group address register 5 */ 191 #define TSEC_REG_GADDR6 0x898 /* Group address register 6 */ 192 #define TSEC_REG_GADDR7 0x89c /* Group address register 7 */ 193 #define TSEC_REG_IADDR(n) (TSEC_REG_IADDR0 + (n << 2)) 194 #define TSEC_REG_GADDR(n) (TSEC_REG_GADDR0 + (n << 2)) 195 196 /* TSEC attribute registers */ 197 #define TSEC_REG_ATTR 0xbf8 /* Attributes Register */ 198 #define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */ 199 200 /* Size of TSEC registers area */ 201 #define TSEC_IO_SIZE 0x1000 202 203 /* reg bits */ 204 #define TSEC_FIFO_PAUSE_CTRL_EN 0x0002 205 206 #define TSEC_DMACTRL_TDSEN 0x00000080 /* Tx Data snoop enable */ 207 #define TSEC_DMACTRL_TBDSEN 0x00000040 /* TxBD snoop enable */ 208 #define TSEC_DMACTRL_GRS 0x00000010 /* Graceful receive stop */ 209 #define TSEC_DMACTRL_GTS 0x00000008 /* Graceful transmit stop */ 210 #define DMACTRL_WWR 0x00000002 /* Write with response */ 211 #define DMACTRL_WOP 0x00000001 /* Wait or poll */ 212 213 #define TSEC_RCTRL_VLEX 0x00002000 /* Enable automatic VLAN tag 214 * extraction and deletion 215 * from Ethernet frames */ 216 #define TSEC_RCTRL_IPCSEN 0x00000200 /* IP Checksum verification enable */ 217 #define TSEC_RCTRL_TUCSEN 0x00000100 /* TCP or UDP Checksum verification enable */ 218 #define TSEC_RCTRL_PRSDEP 0x000000C0 /* Parser control */ 219 #define TSEC_RCRTL_PRSFM 0x00000020 /* FIFO-mode parsing */ 220 #define TSEC_RCTRL_BC_REJ 0x00000010 /* Broadcast frame reject */ 221 #define TSEC_RCTRL_PROM 0x00000008 /* Promiscuous mode */ 222 #define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */ 223 224 #define TSEC_RCTRL_PRSDEP_PARSER_OFF 0x00000000 /* Parser Disabled */ 225 #define TSEC_RCTRL_PRSDEP_PARSE_L2 0x00000040 /* Parse L2 */ 226 #define TSEC_RCTRL_PRSDEP_PARSE_L23 0x00000080 /* Parse L2 and L3 */ 227 #define TSEC_RCTRL_PRSDEP_PARSE_L234 0x000000C0 /* Parse L2, L3 and L4 */ 228 229 #define TSEC_TCTRL_IPCSEN 0x00004000 /* IP header checksum generation enable */ 230 #define TSEC_TCTRL_TUCSEN 0x00002000 /* TCP/UDP header checksum generation enable */ 231 232 #define TSEC_TSTAT_THLT 0x80000000 /* Transmit halt */ 233 #define TSEC_RSTAT_QHLT 0x00800000 /* RxBD queue is halted */ 234 235 #define TSEC_IEVENT_BABR 0x80000000 /* Babbling receive error */ 236 #define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */ 237 #define TSEC_IEVENT_BSY 0x20000000 /* Busy condition interrupt */ 238 #define TSEC_IEVENT_EBERR 0x10000000 /* Ethernet bus error */ 239 #define TSEC_IEVENT_MSRO 0x04000000 /* MSTAT Register Overflow */ 240 #define TSEC_IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ 241 #define TSEC_IEVENT_BABT 0x01000000 /* Babbling transmit error */ 242 #define TSEC_IEVENT_TXC 0x00800000 /* Transmit control interrupt */ 243 #define TSEC_IEVENT_TXE 0x00400000 /* Transmit error */ 244 #define TSEC_IEVENT_TXB 0x00200000 /* Transmit buffer */ 245 #define TSEC_IEVENT_TXF 0x00100000 /* Transmit frame interrupt */ 246 #define TSEC_IEVENT_LC 0x00040000 /* Late collision */ 247 #define TSEC_IEVENT_CRL 0x00020000 /* Collision retry limit/excessive 248 * defer abort */ 249 #define TSEC_IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ 250 #define TSEC_IEVENT_RXB 0x00008000 /* Receive buffer */ 251 #define TSEC_IEVENT_MMRD 0x00000400 /* MII management read completion */ 252 #define TSEC_IEVENT_MMWR 0x00000200 /* MII management write completion */ 253 #define TSEC_IEVENT_GRSC 0x00000100 /* Graceful receive stop complete */ 254 #define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */ 255 256 #define TSEC_IMASK_BREN 0x80000000 /* Babbling receiver interrupt */ 257 #define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */ 258 #define TSEC_IMASK_BSYEN 0x20000000 /* Busy interrupt */ 259 #define TSEC_IMASK_EBERREN 0x10000000 /* Ethernet controller bus error */ 260 #define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */ 261 #define TSEC_IMASK_GTSCEN 0x02000000 /* Graceful transmit stop complete interrupt */ 262 #define TSEC_IMASK_BTEN 0x01000000 /* Babbling transmitter interrupt */ 263 #define TSEC_IMASK_TXCEN 0x00800000 /* Transmit control interrupt */ 264 #define TSEC_IMASK_TXEEN 0x00400000 /* Transmit error interrupt */ 265 #define TSEC_IMASK_TXBEN 0x00200000 /* Transmit buffer interrupt */ 266 #define TSEC_IMASK_TXFEN 0x00100000 /* Transmit frame interrupt */ 267 #define TSEC_IMASK_LCEN 0x00040000 /* Late collision */ 268 #define TSEC_IMASK_CRLEN 0x00020000 /* Collision retry limit/excessive defer */ 269 #define TSEC_IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun */ 270 #define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */ 271 #define TSEC_IMASK_MMRD 0x00000400 /* MII management read completion */ 272 #define TSEC_IMASK_MMWR 0x00000200 /* MII management write completion */ 273 #define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */ 274 #define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */ 275 276 #define TSEC_ATTR_ELCWT 0x00004000 /* Write extracted data to L2 cache */ 277 #define TSEC_ATTR_BDLWT 0x00000800 /* Write buffer descriptor to L2 cache */ 278 #define TSEC_ATTR_RDSEN 0x00000080 /* Rx data snoop enable */ 279 #define TSEC_ATTR_RBDSEN 0x00000040 /* RxBD snoop enable */ 280 281 #define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Soft reset */ 282 #define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset receive MAC control block */ 283 #define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset transmit MAC control block */ 284 #define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset receive function block */ 285 #define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset transmit function block */ 286 #define TSEC_MACCFG1_LOOPBACK 0x00000100 /* Loopback */ 287 #define TSEC_MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ 288 #define TSEC_MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ 289 #define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* Receive enable synchronized 290 * to the receive stream (Read-only) */ 291 #define TSEC_MACCFG1_RX_EN 0x00000004 /* Receive enable */ 292 #define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* Transmit enable synchronized 293 * to the transmit stream (Read-only) */ 294 #define TSEC_MACCFG1_TX_EN 0x00000001 /* Transmit enable */ 295 296 #define TSEC_MACCFG2_PRECNT 0x00007000 /* Preamble Length (0x7) */ 297 #define TSEC_MACCFG2_IF 0x00000300 /* Determines the type of interface 298 * to which the MAC is connected */ 299 #define TSEC_MACCFG2_MII 0x00000100 /* Nibble mode (MII) */ 300 #define TSEC_MACCFG2_GMII 0x00000200 /* Byte mode (GMII/TBI) */ 301 #define TSEC_MACCFG2_HUGEFRAME 0x00000020 /* Huge frame enable */ 302 #define TSEC_MACCFG2_LENGTHCHECK 0x00000010 /* Length check */ 303 #define TSEC_MACCFG2_PADCRC 0x00000004 /* Pad and append CRC */ 304 #define TSEC_MACCFG2_CRCEN 0x00000002 /* CRC enable */ 305 #define TSEC_MACCFG2_FULLDUPLEX 0x00000001 /* Full duplex configure */ 306 307 #define TSEC_ECNTRL_STEN 0x00001000 /* Statistics enabled */ 308 #define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII I/F mode */ 309 #define TSEC_ECNTRL_TBIM 0x00000020 /* Ten-bit I/F mode */ 310 #define TSEC_ECNTRL_R100M 0x00000008 /* RGMII/RMII 100 mode */ 311 #define TSEC_ECNTRL_RMM 0x00000004 /* Reduced-pin mode */ 312 #define TSEC_ECNTRL_SGMIIM 0x00000002 /* Serial GMII mode */ 313 314 #define TSEC_MIIMCFG_RESETMGMT 0x80000000 /* Reset management */ 315 #define TSEC_MIIMCFG_NOPRE 0x00000010 /* Preamble suppress */ 316 #define TSEC_MIIMCFG_CLKDIV28 0x00000007 /* source clock divided by 28 */ 317 #define TSEC_MIIMCFG_CLKDIV20 0x00000006 /* source clock divided by 20 */ 318 #define TSEC_MIIMCFG_CLKDIV14 0x00000005 /* source clock divided by 14 */ 319 #define TSEC_MIIMCFG_CLKDIV10 0x00000004 /* source clock divided by 10 */ 320 #define TSEC_MIIMCFG_CLKDIV8 0x00000003 /* source clock divided by 8 */ 321 #define TSEC_MIIMCFG_CLKDIV6 0x00000002 /* source clock divided by 6 */ 322 #define TSEC_MIIMCFG_CLKDIV4 0x00000001 /* source clock divided by 4 */ 323 324 #define TSEC_MIIMIND_NOTVALID 0x00000004 /* Not valid */ 325 #define TSEC_MIIMIND_SCAN 0x00000002 /* Scan in progress */ 326 #define TSEC_MIIMIND_BUSY 0x00000001 /* Busy */ 327 328 #define TSEC_MIIMCOM_SCANCYCLE 0x00000002 /* Scan cycle */ 329 #define TSEC_MIIMCOM_READCYCLE 0x00000001 /* Read cycle */ 330 331 /* Transmit Data Buffer Descriptor (TxBD) Field Descriptions */ 332 #define TSEC_TXBD_R 0x8000 /* Ready */ 333 #define TSEC_TXBD_PADCRC 0x4000 /* PAD/CRC */ 334 #define TSEC_TXBD_W 0x2000 /* Wrap */ 335 #define TSEC_TXBD_I 0x1000 /* Interrupt */ 336 #define TSEC_TXBD_L 0x0800 /* Last in frame */ 337 #define TSEC_TXBD_TC 0x0400 /* Tx CRC */ 338 #define TSEC_TXBD_DEF 0x0200 /* Defer indication */ 339 #define TSEC_TXBD_TO1 0x0100 /* Transmit software ownership */ 340 #define TSEC_TXBD_HFE 0x0080 /* Huge frame enable (written by user) */ 341 #define TSEC_TXBD_LC 0x0080 /* Late collision (written by TSEC) */ 342 #define TSEC_TXBD_RL 0x0040 /* Retransmission Limit */ 343 #define TSEC_TXBD_TOE 0x0002 /* TCP/IP Offload Enable */ 344 #define TSEC_TXBD_UN 0x0002 /* Underrun */ 345 #define TSEC_TXBD_TXTRUNC 0x0001 /* TX truncation */ 346 347 /* Receive Data Buffer Descriptor (RxBD) Field Descriptions */ 348 #define TSEC_RXBD_E 0x8000 /* Empty */ 349 #define TSEC_RXBD_RO1 0x4000 /* Receive software ownership bit */ 350 #define TSEC_RXBD_W 0x2000 /* Wrap */ 351 #define TSEC_RXBD_I 0x1000 /* Interrupt */ 352 #define TSEC_RXBD_L 0x0800 /* Last in frame */ 353 #define TSEC_RXBD_F 0x0400 /* First in frame */ 354 #define TSEC_RXBD_M 0x0100 /* Miss - The frame was received because 355 * of promiscuous mode. */ 356 #define TSEC_RXBD_B 0x0080 /* Broadcast */ 357 #define TSEC_RXBD_MC 0x0040 /* Multicast */ 358 #define TSEC_RXBD_LG 0x0020 /* Large - Rx frame length violation */ 359 #define TSEC_RXBD_NO 0x0010 /* Rx non-octet aligned frame */ 360 #define TSEC_RXBD_SH 0x0008 /* Short frame */ 361 #define TSEC_RXBD_CR 0x0004 /* Rx CRC error */ 362 #define TSEC_RXBD_OV 0x0002 /* Overrun */ 363 #define TSEC_RXBD_TR 0x0001 /* Truncation */ 364 #define TSEC_RXBD_ZEROONINIT (TSEC_RXBD_TR | TSEC_RXBD_OV | TSEC_RXBD_CR | \ 365 TSEC_RXBD_SH | TSEC_RXBD_NO | TSEC_RXBD_LG | TSEC_RXBD_MC | \ 366 TSEC_RXBD_B | TSEC_RXBD_M) 367 368 #define TSEC_TXBUFFER_ALIGNMENT 64 369 #define TSEC_RXBUFFER_ALIGNMENT 64 370 371 /* Transmit Path Off-Load Frame Control Block flags */ 372 #define TSEC_TX_FCB_VLAN 0x8000 /* VLAN control word valid */ 373 #define TSEC_TX_FCB_L3_IS_IP 0x4000 /* Layer 3 header is an IP header */ 374 #define TSEC_TX_FCB_L3_IS_IP6 0x2000 /* IP header is IP version 6 */ 375 #define TSEC_TX_FCB_L4_IS_TCP_UDP 0x1000 /* Layer 4 header is a TCP or UDP header */ 376 #define TSEC_TX_FCB_L4_IS_UDP 0x0800 /* UDP protocol at layer 4 */ 377 #define TSEC_TX_FCB_CSUM_IP 0x0400 /* Checksum IP header enable */ 378 #define TSEC_TX_FCB_CSUM_TCP_UDP 0x0200 /* Checksum TCP or UDP header enable */ 379 #define TSEC_TX_FCB_FLAG_NO_PH_CSUM 0x0100 /* Disable pseudo-header checksum */ 380 #define TSEC_TX_FCB_FLAG_PTP 0x0001 /* This is a PTP packet */ 381 382 /* Receive Path Off-Load Frame Control Block flags */ 383 #define TSEC_RX_FCB_VLAN 0x8000 /* VLAN tag recognized */ 384 #define TSEC_RX_FCB_IP_FOUND 0x4000 /* IP header found at layer 3 */ 385 #define TSEC_RX_FCB_IP6_FOUND 0x2000 /* IP version 6 header found at layer 3 */ 386 #define TSEC_RX_FCB_TCP_UDP_FOUND 0x1000 /* TCP or UDP header found at layer 4 */ 387 #define TSEC_RX_FCB_IP_CSUM 0x0800 /* IPv4 header checksum checked */ 388 #define TSEC_RX_FCB_TCP_UDP_CSUM 0x0400 /* TCP or UDP header checksum checked */ 389 #define TSEC_RX_FCB_IP_CSUM_ERROR 0x0200 /* IPv4 header checksum verification error */ 390 #define TSEC_RX_FCB_TCP_UDP_CSUM_ERROR 0x0100 /* TCP or UDP header checksum verification error */ 391 #define TSEC_RX_FCB_PARSE_ERROR 0x000C /* Parse error */ 392