1 /*- 2 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _IF_TSEC_H 29 #define _IF_TSEC_H 30 31 #include <dev/ofw/openfirm.h> 32 33 #define TSEC_RX_NUM_DESC 256 34 #define TSEC_TX_NUM_DESC 256 35 36 /* Interrupt Coalescing types */ 37 #define TSEC_IC_RX 0 38 #define TSEC_IC_TX 1 39 40 /* eTSEC ID */ 41 #define TSEC_ETSEC_ID 0x0124 42 43 /* Frame sizes */ 44 #define TSEC_MIN_FRAME_SIZE 64 45 #define TSEC_MAX_FRAME_SIZE 9600 46 47 struct tsec_softc { 48 /* XXX MII bus requires that struct ifnet is first!!! */ 49 struct ifnet *tsec_ifp; 50 51 struct mtx transmit_lock; /* transmitter lock */ 52 struct mtx receive_lock; /* receiver lock */ 53 54 phandle_t node; 55 device_t dev; 56 device_t tsec_miibus; 57 struct mii_data *tsec_mii; /* MII media control */ 58 int tsec_link; 59 60 bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ 61 bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ 62 struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ 63 uint32_t tsec_tx_raddr; /* real address of TX descriptors */ 64 65 bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ 66 bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ 67 struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ 68 uint32_t tsec_rx_raddr; /* real address of RX descriptors */ 69 70 bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ 71 bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ 72 73 struct rx_data_type { 74 bus_dmamap_t map; /* mbuf map */ 75 struct mbuf *mbuf; 76 uint32_t paddr; /* DMA address of buffer */ 77 } rx_data[TSEC_RX_NUM_DESC]; 78 79 uint32_t tx_cur_desc_cnt; 80 uint32_t tx_dirty_desc_cnt; 81 uint32_t rx_cur_desc_cnt; 82 83 struct resource *sc_rres; /* register resource */ 84 int sc_rrid; /* register rid */ 85 struct { 86 bus_space_tag_t bst; 87 bus_space_handle_t bsh; 88 } sc_bas; 89 90 struct resource *sc_transmit_ires; 91 void *sc_transmit_ihand; 92 int sc_transmit_irid; 93 struct resource *sc_receive_ires; 94 void *sc_receive_ihand; 95 int sc_receive_irid; 96 struct resource *sc_error_ires; 97 void *sc_error_ihand; 98 int sc_error_irid; 99 100 int tsec_if_flags; 101 int is_etsec; 102 103 /* Watchdog and MII tick related */ 104 struct callout tsec_callout; 105 int tsec_watchdog; 106 107 /* TX maps */ 108 bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; 109 110 /* unused TX maps data */ 111 uint32_t tx_map_unused_get_cnt; 112 uint32_t tx_map_unused_put_cnt; 113 bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; 114 115 /* used TX maps data */ 116 uint32_t tx_map_used_get_cnt; 117 uint32_t tx_map_used_put_cnt; 118 bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; 119 120 /* mbufs in TX queue */ 121 uint32_t tx_mbuf_used_get_cnt; 122 uint32_t tx_mbuf_used_put_cnt; 123 struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; 124 125 /* interrupt coalescing */ 126 struct mtx ic_lock; 127 uint32_t rx_ic_time; /* RW, valid values 0..65535 */ 128 uint32_t rx_ic_count; /* RW, valid values 0..255 */ 129 uint32_t tx_ic_time; 130 uint32_t tx_ic_count; 131 132 /* currently received frame */ 133 struct mbuf *frame; 134 135 int phyaddr; 136 bus_space_tag_t phy_bst; 137 bus_space_handle_t phy_bsh; 138 int phy_regoff; 139 }; 140 141 /* interface to get/put generic objects */ 142 #define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) 143 144 #define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) 145 146 #define TSEC_GET_GENERIC(hand, tab, count, wrap) \ 147 ((hand)->tab[TSEC_INC((hand)->count, wrap)]) 148 149 #define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ 150 ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) 151 152 #define TSEC_BACK_GENERIC(sc, count, wrap) do { \ 153 if ((sc)->count > 0) \ 154 (sc)->count--; \ 155 else \ 156 (sc)->count = (wrap) - 1; \ 157 } while (0) 158 159 /* TX maps interface */ 160 #define TSEC_TX_MAP_CNT_INIT(sc) do { \ 161 TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ 162 TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ 163 TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ 164 TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ 165 } while (0) 166 167 /* interface to get/put unused TX maps */ 168 #define TSEC_ALLOC_TX_MAP(sc) \ 169 TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ 170 TSEC_TX_NUM_DESC) 171 172 #define TSEC_FREE_TX_MAP(sc, val) \ 173 TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ 174 TSEC_TX_NUM_DESC, val) 175 176 /* interface to get/put used TX maps */ 177 #define TSEC_GET_TX_MAP(sc) \ 178 TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ 179 TSEC_TX_NUM_DESC) 180 181 #define TSEC_PUT_TX_MAP(sc, val) \ 182 TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ 183 TSEC_TX_NUM_DESC, val) 184 185 /* interface to get/put TX mbufs in send queue */ 186 #define TSEC_TX_MBUF_CNT_INIT(sc) do { \ 187 TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ 188 TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ 189 } while (0) 190 191 #define TSEC_GET_TX_MBUF(sc) \ 192 TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ 193 TSEC_TX_NUM_DESC) 194 195 #define TSEC_PUT_TX_MBUF(sc, val) \ 196 TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ 197 TSEC_TX_NUM_DESC, val) 198 199 #define TSEC_EMPTYQ_TX_MBUF(sc) \ 200 ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) 201 202 /* interface for manage tx tsec_desc */ 203 #define TSEC_TX_DESC_CNT_INIT(sc) do { \ 204 TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ 205 TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ 206 } while (0) 207 208 #define TSEC_GET_CUR_TX_DESC(sc) \ 209 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ 210 TSEC_TX_NUM_DESC) 211 212 #define TSEC_GET_DIRTY_TX_DESC(sc) \ 213 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ 214 TSEC_TX_NUM_DESC) 215 216 #define TSEC_BACK_DIRTY_TX_DESC(sc) \ 217 TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) 218 219 #define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ 220 ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) 221 222 #define TSEC_FREE_TX_DESC(sc) \ 223 (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ 224 ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ 225 : \ 226 (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ 227 + (sc)->tx_dirty_desc_cnt - 1)) 228 229 /* interface for manage rx tsec_desc */ 230 #define TSEC_RX_DESC_CNT_INIT(sc) do { \ 231 TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ 232 } while (0) 233 234 #define TSEC_GET_CUR_RX_DESC(sc) \ 235 &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ 236 TSEC_RX_NUM_DESC) 237 238 #define TSEC_BACK_CUR_RX_DESC(sc) \ 239 TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) 240 241 #define TSEC_GET_CUR_RX_DESC_CNT(sc) \ 242 ((sc)->rx_cur_desc_cnt) 243 244 /* init all counters (for init only!) */ 245 #define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ 246 TSEC_TX_MAP_CNT_INIT(sc); \ 247 TSEC_TX_MBUF_CNT_INIT(sc); \ 248 TSEC_TX_DESC_CNT_INIT(sc); \ 249 TSEC_RX_DESC_CNT_INIT(sc); \ 250 } while (0) 251 252 /* read/write bus functions */ 253 #define TSEC_READ(sc, reg) \ 254 bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 255 #define TSEC_WRITE(sc, reg, val) \ 256 bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 257 258 extern struct mtx tsec_phy_mtx; 259 #define TSEC_PHY_LOCK(sc) mtx_lock(&tsec_phy_mtx) 260 #define TSEC_PHY_UNLOCK(sc) mtx_unlock(&tsec_phy_mtx) 261 #define TSEC_PHY_READ(sc, reg) \ 262 bus_space_read_4((sc)->phy_bst, (sc)->phy_bsh, \ 263 (reg) + (sc)->phy_regoff) 264 #define TSEC_PHY_WRITE(sc, reg, val) \ 265 bus_space_write_4((sc)->phy_bst, (sc)->phy_bsh, \ 266 (reg) + (sc)->phy_regoff, (val)) 267 268 /* Lock for transmitter */ 269 #define TSEC_TRANSMIT_LOCK(sc) do { \ 270 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 271 mtx_lock(&(sc)->transmit_lock); \ 272 } while (0) 273 274 #define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 275 #define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 276 277 /* Lock for receiver */ 278 #define TSEC_RECEIVE_LOCK(sc) do { \ 279 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 280 mtx_lock(&(sc)->receive_lock); \ 281 } while (0) 282 283 #define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 284 #define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 285 286 /* Lock for interrupts coalescing */ 287 #define TSEC_IC_LOCK(sc) do { \ 288 mtx_assert(&(sc)->ic_lock, MA_NOTOWNED); \ 289 mtx_lock(&(sc)->ic_lock); \ 290 } while (0) 291 292 #define TSEC_IC_UNLOCK(sc) mtx_unlock(&(sc)->ic_lock) 293 #define TSEC_IC_LOCK_ASSERT(sc) mtx_assert(&(sc)->ic_lock, MA_OWNED) 294 295 /* Global tsec lock (with all locks) */ 296 #define TSEC_GLOBAL_LOCK(sc) do { \ 297 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 298 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 299 panic("tsec deadlock possibility detection!"); \ 300 } \ 301 mtx_lock(&(sc)->transmit_lock); \ 302 mtx_lock(&(sc)->receive_lock); \ 303 } while (0) 304 305 #define TSEC_GLOBAL_UNLOCK(sc) do { \ 306 TSEC_RECEIVE_UNLOCK(sc); \ 307 TSEC_TRANSMIT_UNLOCK(sc); \ 308 } while (0) 309 310 #define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ 311 TSEC_TRANSMIT_LOCK_ASSERT(sc); \ 312 TSEC_RECEIVE_LOCK_ASSERT(sc); \ 313 } while (0) 314 315 /* From global to {transmit,receive} */ 316 #define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ 317 mtx_unlock(&(sc)->receive_lock);\ 318 } while (0) 319 320 #define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ 321 mtx_unlock(&(sc)->transmit_lock);\ 322 } while (0) 323 324 struct tsec_desc { 325 volatile uint16_t flags; /* descriptor flags */ 326 volatile uint16_t length; /* buffer length */ 327 volatile uint32_t bufptr; /* buffer pointer */ 328 }; 329 330 #define TSEC_READ_RETRY 10000 331 #define TSEC_READ_DELAY 100 332 333 /* Structures and defines for TCP/IP Off-load */ 334 struct tsec_tx_fcb { 335 volatile uint16_t flags; 336 volatile uint8_t l4_offset; 337 volatile uint8_t l3_offset; 338 volatile uint16_t ph_chsum; 339 volatile uint16_t vlan; 340 }; 341 342 struct tsec_rx_fcb { 343 volatile uint16_t flags; 344 volatile uint8_t rq_index; 345 volatile uint8_t protocol; 346 volatile uint16_t unused; 347 volatile uint16_t vlan; 348 }; 349 350 #define TSEC_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 351 352 #define TSEC_TX_FCB_IP4 TSEC_TX_FCB_L3_IS_IP 353 #define TSEC_TX_FCB_IP6 (TSEC_TX_FCB_L3_IS_IP | TSEC_TX_FCB_L3_IS_IP6) 354 355 #define TSEC_TX_FCB_TCP TSEC_TX_FCB_L4_IS_TCP_UDP 356 #define TSEC_TX_FCB_UDP (TSEC_TX_FCB_L4_IS_TCP_UDP | TSEC_TX_FCB_L4_IS_UDP) 357 358 #define TSEC_RX_FCB_IP_CSUM_CHECKED(flags) \ 359 ((flags & (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP6_FOUND | \ 360 TSEC_RX_FCB_IP_CSUM | TSEC_RX_FCB_PARSE_ERROR)) \ 361 == (TSEC_RX_FCB_IP_FOUND | TSEC_RX_FCB_IP_CSUM)) 362 363 #define TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) \ 364 ((flags & (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM \ 365 | TSEC_RX_FCB_PARSE_ERROR)) \ 366 == (TSEC_RX_FCB_TCP_UDP_FOUND | TSEC_RX_FCB_TCP_UDP_CSUM)) 367 368 /* Prototypes */ 369 extern devclass_t tsec_devclass; 370 371 int tsec_attach(struct tsec_softc *sc); 372 int tsec_detach(struct tsec_softc *sc); 373 374 void tsec_error_intr(void *arg); 375 void tsec_receive_intr(void *arg); 376 void tsec_transmit_intr(void *arg); 377 378 int tsec_miibus_readreg(device_t dev, int phy, int reg); 379 int tsec_miibus_writereg(device_t dev, int phy, int reg, int value); 380 void tsec_miibus_statchg(device_t dev); 381 int tsec_resume(device_t dev); /* XXX */ 382 int tsec_shutdown(device_t dev); 383 int tsec_suspend(device_t dev); /* XXX */ 384 385 void tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr); 386 387 #endif /* _IF_TSEC_H */ 388