1 /*- 2 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _IF_TSEC_H 29 #define _IF_TSEC_H 30 31 #define TSEC_RX_NUM_DESC 256 32 #define TSEC_TX_NUM_DESC 256 33 34 struct tsec_softc { 35 /* XXX MII bus requires that struct ifnet is first!!! */ 36 struct ifnet *tsec_ifp; 37 38 struct mtx transmit_lock; /* transmitter lock */ 39 struct mtx receive_lock; /* receiver lock */ 40 41 device_t dev; 42 device_t tsec_miibus; 43 struct mii_data *tsec_mii; /* MII media control */ 44 int tsec_link; 45 46 bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ 47 bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ 48 struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ 49 uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ 50 51 bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ 52 bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ 53 struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ 54 uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ 55 56 bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ 57 bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ 58 59 struct rx_data_type { 60 bus_dmamap_t map; /* mbuf map */ 61 struct mbuf *mbuf; 62 uint32_t paddr; /* DMA addres of buffer */ 63 } rx_data[TSEC_RX_NUM_DESC]; 64 65 uint32_t tx_cur_desc_cnt; 66 uint32_t tx_dirty_desc_cnt; 67 uint32_t rx_cur_desc_cnt; 68 69 struct resource *sc_rres; /* register resource */ 70 int sc_rrid; /* register rid */ 71 struct { 72 bus_space_tag_t bst; 73 bus_space_handle_t bsh; 74 } sc_bas; 75 76 struct resource *sc_transmit_ires; 77 void *sc_transmit_ihand; 78 int sc_transmit_irid; 79 struct resource *sc_receive_ires; 80 void *sc_receive_ihand; 81 int sc_receive_irid; 82 struct resource *sc_error_ires; 83 void *sc_error_ihand; 84 int sc_error_irid; 85 86 int tsec_if_flags; 87 88 /* Watchdog and MII tick related */ 89 struct callout tsec_callout; 90 int tsec_watchdog; 91 92 /* TX maps */ 93 bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; 94 95 /* unused TX maps data */ 96 uint32_t tx_map_unused_get_cnt; 97 uint32_t tx_map_unused_put_cnt; 98 bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; 99 100 /* used TX maps data */ 101 uint32_t tx_map_used_get_cnt; 102 uint32_t tx_map_used_put_cnt; 103 bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; 104 105 /* mbufs in TX queue */ 106 uint32_t tx_mbuf_used_get_cnt; 107 uint32_t tx_mbuf_used_put_cnt; 108 struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; 109 }; 110 111 /* interface to get/put generic objects */ 112 #define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) 113 114 #define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) 115 116 #define TSEC_GET_GENERIC(hand, tab, count, wrap) \ 117 ((hand)->tab[TSEC_INC((hand)->count, wrap)]) 118 119 #define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ 120 ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) 121 122 #define TSEC_BACK_GENERIC(sc, count, wrap) do { \ 123 if ((sc)->count > 0) \ 124 (sc)->count--; \ 125 else \ 126 (sc)->count = (wrap) - 1; \ 127 } while (0) 128 129 /* TX maps interface */ 130 #define TSEC_TX_MAP_CNT_INIT(sc) do { \ 131 TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ 132 TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ 133 TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ 134 TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ 135 } while (0) 136 137 /* interface to get/put unused TX maps */ 138 #define TSEC_ALLOC_TX_MAP(sc) \ 139 TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ 140 TSEC_TX_NUM_DESC) 141 142 #define TSEC_FREE_TX_MAP(sc, val) \ 143 TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ 144 TSEC_TX_NUM_DESC, val) 145 146 /* interface to get/put used TX maps */ 147 #define TSEC_GET_TX_MAP(sc) \ 148 TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ 149 TSEC_TX_NUM_DESC) 150 151 #define TSEC_PUT_TX_MAP(sc, val) \ 152 TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ 153 TSEC_TX_NUM_DESC, val) 154 155 /* interface to get/put TX mbufs in send queue */ 156 #define TSEC_TX_MBUF_CNT_INIT(sc) do { \ 157 TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ 158 TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ 159 } while (0) 160 161 #define TSEC_GET_TX_MBUF(sc) \ 162 TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ 163 TSEC_TX_NUM_DESC) 164 165 #define TSEC_PUT_TX_MBUF(sc, val) \ 166 TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ 167 TSEC_TX_NUM_DESC, val) 168 169 #define TSEC_EMPTYQ_TX_MBUF(sc) \ 170 ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) 171 172 /* interface for manage tx tsec_desc */ 173 #define TSEC_TX_DESC_CNT_INIT(sc) do { \ 174 TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ 175 TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ 176 } while (0) 177 178 #define TSEC_GET_CUR_TX_DESC(sc) \ 179 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ 180 TSEC_TX_NUM_DESC) 181 182 #define TSEC_GET_DIRTY_TX_DESC(sc) \ 183 &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ 184 TSEC_TX_NUM_DESC) 185 186 #define TSEC_BACK_DIRTY_TX_DESC(sc) \ 187 TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) 188 189 #define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ 190 ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) 191 192 #define TSEC_FREE_TX_DESC(sc) \ 193 (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ 194 ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ 195 : \ 196 (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ 197 + (sc)->tx_dirty_desc_cnt - 1)) 198 199 /* interface for manage rx tsec_desc */ 200 #define TSEC_RX_DESC_CNT_INIT(sc) do { \ 201 TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ 202 } while (0) 203 204 #define TSEC_GET_CUR_RX_DESC(sc) \ 205 &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ 206 TSEC_RX_NUM_DESC) 207 208 #define TSEC_BACK_CUR_RX_DESC(sc) \ 209 TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) 210 211 #define TSEC_GET_CUR_RX_DESC_CNT(sc) \ 212 ((sc)->rx_cur_desc_cnt) 213 214 /* init all counters (for init only!) */ 215 #define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ 216 TSEC_TX_MAP_CNT_INIT(sc); \ 217 TSEC_TX_MBUF_CNT_INIT(sc); \ 218 TSEC_TX_DESC_CNT_INIT(sc); \ 219 TSEC_RX_DESC_CNT_INIT(sc); \ 220 } while (0) 221 222 /* read/write bus functions */ 223 #define TSEC_READ(sc, reg) \ 224 bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 225 #define TSEC_WRITE(sc, reg, val) \ 226 bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 227 228 /* Lock for transmitter */ 229 #define TSEC_TRANSMIT_LOCK(sc) do { \ 230 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 231 mtx_lock(&(sc)->transmit_lock); \ 232 } while (0) 233 234 #define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 235 #define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 236 237 /* Lock for receiver */ 238 #define TSEC_RECEIVE_LOCK(sc) do { \ 239 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 240 mtx_lock(&(sc)->receive_lock); \ 241 } while (0) 242 243 #define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 244 #define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 245 246 /* Global tsec lock (with all locks) */ 247 #define TSEC_GLOBAL_LOCK(sc) do { \ 248 if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 249 (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 250 panic("tsec deadlock possibility detection!"); \ 251 } \ 252 mtx_lock(&(sc)->transmit_lock); \ 253 mtx_lock(&(sc)->receive_lock); \ 254 } while (0) 255 256 #define TSEC_GLOBAL_UNLOCK(sc) do { \ 257 TSEC_RECEIVE_UNLOCK(sc); \ 258 TSEC_TRANSMIT_UNLOCK(sc); \ 259 } while (0) 260 261 #define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ 262 TSEC_TRANSMIT_LOCK_ASSERT(sc); \ 263 TSEC_RECEIVE_LOCK_ASSERT(sc); \ 264 } while (0) 265 266 /* From global to {transmit,receive} */ 267 #define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ 268 mtx_unlock(&(sc)->receive_lock);\ 269 } while (0) 270 271 #define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ 272 mtx_unlock(&(sc)->transmit_lock);\ 273 } while (0) 274 275 struct tsec_desc { 276 volatile uint16_t flags; /* descriptor flags */ 277 volatile uint16_t length; /* buffer length */ 278 volatile uint32_t bufptr; /* buffer pointer */ 279 }; 280 281 #define TSEC_READ_RETRY 10000 282 #define TSEC_READ_DELAY 100 283 284 /* Prototypes */ 285 extern devclass_t tsec_devclass; 286 287 int tsec_attach(struct tsec_softc *sc); 288 int tsec_detach(struct tsec_softc *sc); 289 290 void tsec_error_intr(void *arg); 291 void tsec_receive_intr(void *arg); 292 void tsec_transmit_intr(void *arg); 293 294 int tsec_miibus_readreg(device_t dev, int phy, int reg); 295 void tsec_miibus_writereg(device_t dev, int phy, int reg, int value); 296 void tsec_miibus_statchg(device_t dev); 297 int tsec_resume(device_t dev); /* XXX */ 298 void tsec_shutdown(device_t dev); 299 int tsec_suspend(device_t dev); /* XXX */ 300 301 void tsec_get_hwaddr(struct tsec_softc *sc, uint8_t *addr); 302 303 #endif 304