1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 31 */ 32 #include <sys/cdefs.h> 33 #ifdef HAVE_KERNEL_OPTION_HEADERS 34 #include "opt_device_polling.h" 35 #endif 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 48 #include <net/bpf.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in_systm.h> 59 #include <netinet/in.h> 60 #include <netinet/ip.h> 61 62 #include <machine/bus.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/tsec/if_tsec.h> 68 #include <dev/tsec/if_tsecreg.h> 69 70 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 71 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 72 const char *dname); 73 static void tsec_dma_ctl(struct tsec_softc *sc, int state); 74 static void tsec_encap(if_t ifp, struct tsec_softc *sc, 75 struct mbuf *m0, uint16_t fcb_flags, int *start_tx); 76 static void tsec_free_dma(struct tsec_softc *sc); 77 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 78 static int tsec_ifmedia_upd(if_t ifp); 79 static void tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr); 80 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 81 struct mbuf **mbufp, uint32_t *paddr); 82 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 83 int nseg, int error); 84 static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 85 static void tsec_init(void *xsc); 86 static void tsec_init_locked(struct tsec_softc *sc); 87 static int tsec_ioctl(if_t ifp, u_long command, caddr_t data); 88 static void tsec_reset_mac(struct tsec_softc *sc); 89 static void tsec_setfilter(struct tsec_softc *sc); 90 static void tsec_set_mac_address(struct tsec_softc *sc); 91 static void tsec_start(if_t ifp); 92 static void tsec_start_locked(if_t ifp); 93 static void tsec_stop(struct tsec_softc *sc); 94 static void tsec_tick(void *arg); 95 static void tsec_watchdog(struct tsec_softc *sc); 96 static void tsec_add_sysctls(struct tsec_softc *sc); 97 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 98 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 99 static void tsec_set_rxic(struct tsec_softc *sc); 100 static void tsec_set_txic(struct tsec_softc *sc); 101 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 102 static void tsec_transmit_intr_locked(struct tsec_softc *sc); 103 static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 104 static void tsec_offload_setup(struct tsec_softc *sc); 105 static void tsec_offload_process_frame(struct tsec_softc *sc, 106 struct mbuf *m); 107 static void tsec_setup_multicast(struct tsec_softc *sc); 108 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 109 110 DRIVER_MODULE(miibus, tsec, miibus_driver, 0, 0); 111 MODULE_DEPEND(tsec, ether, 1, 1, 1); 112 MODULE_DEPEND(tsec, miibus, 1, 1, 1); 113 114 struct mtx tsec_phy_mtx; 115 116 int 117 tsec_attach(struct tsec_softc *sc) 118 { 119 uint8_t hwaddr[ETHER_ADDR_LEN]; 120 if_t ifp; 121 int error = 0; 122 int i; 123 124 /* Initialize global (because potentially shared) MII lock */ 125 if (!mtx_initialized(&tsec_phy_mtx)) 126 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF); 127 128 /* Reset all TSEC counters */ 129 TSEC_TX_RX_COUNTERS_INIT(sc); 130 131 /* Stop DMA engine if enabled by firmware */ 132 tsec_dma_ctl(sc, 0); 133 134 /* Reset MAC */ 135 tsec_reset_mac(sc); 136 137 /* Disable interrupts for now */ 138 tsec_intrs_ctl(sc, 0); 139 140 /* Configure defaults for interrupts coalescing */ 141 sc->rx_ic_time = 768; 142 sc->rx_ic_count = 16; 143 sc->tx_ic_time = 768; 144 sc->tx_ic_count = 16; 145 tsec_set_rxic(sc); 146 tsec_set_txic(sc); 147 tsec_add_sysctls(sc); 148 149 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 150 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 151 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 152 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 153 154 if (error) { 155 tsec_detach(sc); 156 return (ENXIO); 157 } 158 159 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 160 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 161 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 162 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 163 if (error) { 164 tsec_detach(sc); 165 return (ENXIO); 166 } 167 168 /* Allocate a busdma tag for TX mbufs. */ 169 error = bus_dma_tag_create(NULL, /* parent */ 170 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 171 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 172 BUS_SPACE_MAXADDR, /* highaddr */ 173 NULL, NULL, /* filtfunc, filtfuncarg */ 174 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 175 TSEC_TX_MAX_DMA_SEGS, /* nsegments */ 176 MCLBYTES, 0, /* maxsegsz, flags */ 177 NULL, NULL, /* lockfunc, lockfuncarg */ 178 &sc->tsec_tx_mtag); /* dmat */ 179 if (error) { 180 device_printf(sc->dev, "failed to allocate busdma tag " 181 "(tx mbufs)\n"); 182 tsec_detach(sc); 183 return (ENXIO); 184 } 185 186 /* Allocate a busdma tag for RX mbufs. */ 187 error = bus_dma_tag_create(NULL, /* parent */ 188 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 189 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 190 BUS_SPACE_MAXADDR, /* highaddr */ 191 NULL, NULL, /* filtfunc, filtfuncarg */ 192 MCLBYTES, /* maxsize */ 193 1, /* nsegments */ 194 MCLBYTES, 0, /* maxsegsz, flags */ 195 NULL, NULL, /* lockfunc, lockfuncarg */ 196 &sc->tsec_rx_mtag); /* dmat */ 197 if (error) { 198 device_printf(sc->dev, "failed to allocate busdma tag " 199 "(rx mbufs)\n"); 200 tsec_detach(sc); 201 return (ENXIO); 202 } 203 204 /* Create TX busdma maps */ 205 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 206 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, 207 &sc->tx_bufmap[i].map); 208 if (error) { 209 device_printf(sc->dev, "failed to init TX ring\n"); 210 tsec_detach(sc); 211 return (ENXIO); 212 } 213 sc->tx_bufmap[i].map_initialized = 1; 214 } 215 216 /* Create RX busdma maps and zero mbuf handlers */ 217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 219 &sc->rx_data[i].map); 220 if (error) { 221 device_printf(sc->dev, "failed to init RX ring\n"); 222 tsec_detach(sc); 223 return (ENXIO); 224 } 225 sc->rx_data[i].mbuf = NULL; 226 } 227 228 /* Create mbufs for RX buffers */ 229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 232 if (error) { 233 device_printf(sc->dev, "can't load rx DMA map %d, " 234 "error = %d\n", i, error); 235 tsec_detach(sc); 236 return (error); 237 } 238 } 239 240 /* Create network interface for upper layers */ 241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 242 if (ifp == NULL) { 243 device_printf(sc->dev, "if_alloc() failed\n"); 244 tsec_detach(sc); 245 return (ENOMEM); 246 } 247 248 if_setsoftc(ifp, sc); 249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 250 if_setflags(ifp, IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST); 251 if_setinitfn(ifp, tsec_init); 252 if_setstartfn(ifp, tsec_start); 253 if_setioctlfn(ifp, tsec_ioctl); 254 255 if_setsendqlen(ifp, TSEC_TX_NUM_DESC - 1); 256 if_setsendqready(ifp); 257 258 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 259 if (sc->is_etsec) 260 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 261 262 if_setcapenable(ifp, if_getcapabilities(ifp)); 263 264 #ifdef DEVICE_POLLING 265 /* Advertise that polling is supported */ 266 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 267 #endif 268 269 /* Attach PHY(s) */ 270 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 271 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 272 0); 273 if (error) { 274 device_printf(sc->dev, "attaching PHYs failed\n"); 275 if_free(ifp); 276 sc->tsec_ifp = NULL; 277 tsec_detach(sc); 278 return (error); 279 } 280 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 281 282 /* Set MAC address */ 283 tsec_get_hwaddr(sc, hwaddr); 284 ether_ifattach(ifp, hwaddr); 285 286 return (0); 287 } 288 289 int 290 tsec_detach(struct tsec_softc *sc) 291 { 292 293 if (sc->tsec_ifp != NULL) { 294 #ifdef DEVICE_POLLING 295 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) 296 ether_poll_deregister(sc->tsec_ifp); 297 #endif 298 299 /* Stop TSEC controller and free TX queue */ 300 if (sc->sc_rres) 301 tsec_shutdown(sc->dev); 302 303 /* Detach network interface */ 304 ether_ifdetach(sc->tsec_ifp); 305 if_free(sc->tsec_ifp); 306 sc->tsec_ifp = NULL; 307 } 308 309 /* Free DMA resources */ 310 tsec_free_dma(sc); 311 312 return (0); 313 } 314 315 int 316 tsec_shutdown(device_t dev) 317 { 318 struct tsec_softc *sc; 319 320 sc = device_get_softc(dev); 321 322 TSEC_GLOBAL_LOCK(sc); 323 tsec_stop(sc); 324 TSEC_GLOBAL_UNLOCK(sc); 325 return (0); 326 } 327 328 int 329 tsec_suspend(device_t dev) 330 { 331 332 /* TODO not implemented! */ 333 return (0); 334 } 335 336 int 337 tsec_resume(device_t dev) 338 { 339 340 /* TODO not implemented! */ 341 return (0); 342 } 343 344 static void 345 tsec_init(void *xsc) 346 { 347 struct tsec_softc *sc = xsc; 348 349 TSEC_GLOBAL_LOCK(sc); 350 tsec_init_locked(sc); 351 TSEC_GLOBAL_UNLOCK(sc); 352 } 353 354 static int 355 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags) 356 { 357 int timeout; 358 359 /* 360 * The status indicators are not set immediately after a command. 361 * Discard the first value. 362 */ 363 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND); 364 365 timeout = TSEC_READ_RETRY; 366 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout) 367 DELAY(TSEC_READ_DELAY); 368 369 return (timeout == 0); 370 } 371 372 static void 373 tsec_init_locked(struct tsec_softc *sc) 374 { 375 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 376 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 377 if_t ifp = sc->tsec_ifp; 378 uint32_t val, i; 379 int timeout; 380 381 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 382 return; 383 384 TSEC_GLOBAL_LOCK_ASSERT(sc); 385 tsec_stop(sc); 386 387 /* 388 * These steps are according to the MPC8555E PowerQUICCIII RM: 389 * 14.7 Initialization/Application Information 390 */ 391 392 /* Step 1: soft reset MAC */ 393 tsec_reset_mac(sc); 394 395 /* Step 2: Initialize MACCFG2 */ 396 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 397 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 398 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 399 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 400 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 401 ); 402 403 /* Step 3: Initialize ECNTRL 404 * While the documentation states that R100M is ignored if RPM is 405 * not set, it does seem to be needed to get the orange boxes to 406 * work (which have a Marvell 88E1111 PHY). Go figure. 407 */ 408 409 /* 410 * XXX kludge - use circumstancial evidence to program ECNTRL 411 * correctly. Ideally we need some board information to guide 412 * us here. 413 */ 414 i = TSEC_READ(sc, TSEC_REG_ID2); 415 val = (i & 0xffff) 416 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 417 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 418 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 419 420 /* Step 4: Initialize MAC station address */ 421 tsec_set_mac_address(sc); 422 423 /* 424 * Step 5: Assign a Physical address to the TBI so as to not conflict 425 * with the external PHY physical address 426 */ 427 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 428 429 TSEC_PHY_LOCK(sc); 430 431 /* Step 6: Reset the management interface */ 432 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 433 434 /* Step 7: Setup the MII Mgmt clock speed */ 435 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 436 437 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 438 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 439 440 TSEC_PHY_UNLOCK(sc); 441 if (timeout) { 442 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 443 return; 444 } 445 446 /* Step 9: Setup the MII Mgmt */ 447 mii_mediachg(sc->tsec_mii); 448 449 /* Step 10: Clear IEVENT register */ 450 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 451 452 /* Step 11: Enable interrupts */ 453 #ifdef DEVICE_POLLING 454 /* 455 * ...only if polling is not turned on. Disable interrupts explicitly 456 * if polling is enabled. 457 */ 458 if (if_getcapenable(ifp) & IFCAP_POLLING ) 459 tsec_intrs_ctl(sc, 0); 460 else 461 #endif /* DEVICE_POLLING */ 462 tsec_intrs_ctl(sc, 1); 463 464 /* Step 12: Initialize IADDRn */ 465 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 466 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 467 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 468 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 469 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 470 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 471 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 472 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 473 474 /* Step 13: Initialize GADDRn */ 475 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 476 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 477 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 478 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 479 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 480 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 481 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 482 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 483 484 /* Step 14: Initialize RCTRL */ 485 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 486 487 /* Step 15: Initialize DMACTRL */ 488 tsec_dma_ctl(sc, 1); 489 490 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 491 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 492 493 /* 494 * Step 17: Initialize transmit/receive descriptor rings. 495 * Initialize TBASE and RBASE. 496 */ 497 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 498 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 499 500 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 501 tx_desc[i].bufptr = 0; 502 tx_desc[i].length = 0; 503 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 504 TSEC_TXBD_W : 0); 505 } 506 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 508 509 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 510 rx_desc[i].bufptr = sc->rx_data[i].paddr; 511 rx_desc[i].length = 0; 512 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 513 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 514 } 515 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 517 518 /* Step 18: Initialize the maximum receive buffer length */ 519 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 520 521 /* Step 19: Configure ethernet frame sizes */ 522 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 523 tsec_set_mtu(sc, if_getmtu(ifp)); 524 525 /* Step 20: Enable Rx and RxBD sdata snooping */ 526 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 527 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 528 529 /* Step 21: Reset collision counters in hardware */ 530 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 531 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 532 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 533 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 534 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 535 536 /* Step 22: Mask all CAM interrupts */ 537 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 538 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 539 540 /* Step 23: Enable Rx and Tx */ 541 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 542 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 543 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 544 545 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 546 TSEC_TX_RX_COUNTERS_INIT(sc); 547 548 /* Step 25: Setup TCP/IP Off-Load engine */ 549 if (sc->is_etsec) 550 tsec_offload_setup(sc); 551 552 /* Step 26: Setup multicast filters */ 553 tsec_setup_multicast(sc); 554 555 /* Step 27: Activate network interface */ 556 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 557 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 558 sc->tsec_if_flags = if_getflags(ifp); 559 sc->tsec_watchdog = 0; 560 561 /* Schedule watchdog timeout */ 562 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 563 } 564 565 static void 566 tsec_set_mac_address(struct tsec_softc *sc) 567 { 568 uint32_t macbuf[2] = { 0, 0 }; 569 char *macbufp, *curmac; 570 int i; 571 572 TSEC_GLOBAL_LOCK_ASSERT(sc); 573 574 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 575 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN, 576 sizeof(macbuf))); 577 578 macbufp = (char *)macbuf; 579 curmac = (char *)if_getlladdr(sc->tsec_ifp); 580 581 /* Correct order of MAC address bytes */ 582 for (i = 1; i <= ETHER_ADDR_LEN; i++) 583 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 584 585 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 586 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 587 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 588 } 589 590 /* 591 * DMA control function, if argument state is: 592 * 0 - DMA engine will be disabled 593 * 1 - DMA engine will be enabled 594 */ 595 static void 596 tsec_dma_ctl(struct tsec_softc *sc, int state) 597 { 598 device_t dev; 599 uint32_t dma_flags, timeout; 600 601 dev = sc->dev; 602 603 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 604 605 switch (state) { 606 case 0: 607 /* Temporarily clear stop graceful stop bits. */ 608 tsec_dma_ctl(sc, 1000); 609 610 /* Set it again */ 611 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 612 break; 613 case 1000: 614 case 1: 615 /* Set write with response (WWR), wait (WOP) and snoop bits */ 616 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 617 DMACTRL_WWR | DMACTRL_WOP); 618 619 /* Clear graceful stop bits */ 620 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 621 break; 622 default: 623 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 624 state); 625 } 626 627 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 628 629 switch (state) { 630 case 0: 631 /* Wait for DMA stop */ 632 timeout = TSEC_READ_RETRY; 633 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 634 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 635 DELAY(TSEC_READ_DELAY); 636 637 if (timeout == 0) 638 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 639 break; 640 case 1: 641 /* Restart transmission function */ 642 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 643 } 644 } 645 646 /* 647 * Interrupts control function, if argument state is: 648 * 0 - all TSEC interrupts will be masked 649 * 1 - all TSEC interrupts will be unmasked 650 */ 651 static void 652 tsec_intrs_ctl(struct tsec_softc *sc, int state) 653 { 654 device_t dev; 655 656 dev = sc->dev; 657 658 switch (state) { 659 case 0: 660 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 661 break; 662 case 1: 663 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 664 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 665 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 666 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 667 break; 668 default: 669 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 670 state); 671 } 672 } 673 674 static void 675 tsec_reset_mac(struct tsec_softc *sc) 676 { 677 uint32_t maccfg1_flags; 678 679 /* Set soft reset bit */ 680 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 681 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 682 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 683 684 /* Clear soft reset bit */ 685 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 686 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 687 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 688 } 689 690 static void 691 tsec_watchdog(struct tsec_softc *sc) 692 { 693 if_t ifp; 694 695 TSEC_GLOBAL_LOCK_ASSERT(sc); 696 697 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 698 return; 699 700 ifp = sc->tsec_ifp; 701 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 702 if_printf(ifp, "watchdog timeout\n"); 703 704 tsec_stop(sc); 705 tsec_init_locked(sc); 706 } 707 708 static void 709 tsec_start(if_t ifp) 710 { 711 struct tsec_softc *sc = if_getsoftc(ifp); 712 713 TSEC_TRANSMIT_LOCK(sc); 714 tsec_start_locked(ifp); 715 TSEC_TRANSMIT_UNLOCK(sc); 716 } 717 718 static void 719 tsec_start_locked(if_t ifp) 720 { 721 struct tsec_softc *sc; 722 struct mbuf *m0; 723 struct tsec_tx_fcb *tx_fcb; 724 int csum_flags; 725 int start_tx; 726 uint16_t fcb_flags; 727 728 sc = if_getsoftc(ifp); 729 start_tx = 0; 730 731 TSEC_TRANSMIT_LOCK_ASSERT(sc); 732 733 if (sc->tsec_link == 0) 734 return; 735 736 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 737 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 738 739 for (;;) { 740 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) { 741 /* No free descriptors */ 742 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 743 break; 744 } 745 746 /* Get packet from the queue */ 747 m0 = if_dequeue(ifp); 748 if (m0 == NULL) 749 break; 750 751 /* Insert TCP/IP Off-load frame control block */ 752 fcb_flags = 0; 753 csum_flags = m0->m_pkthdr.csum_flags; 754 if (csum_flags) { 755 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 756 if (m0 == NULL) 757 break; 758 759 if (csum_flags & CSUM_IP) 760 fcb_flags |= TSEC_TX_FCB_IP4 | 761 TSEC_TX_FCB_CSUM_IP; 762 763 if (csum_flags & CSUM_TCP) 764 fcb_flags |= TSEC_TX_FCB_TCP | 765 TSEC_TX_FCB_CSUM_TCP_UDP; 766 767 if (csum_flags & CSUM_UDP) 768 fcb_flags |= TSEC_TX_FCB_UDP | 769 TSEC_TX_FCB_CSUM_TCP_UDP; 770 771 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 772 tx_fcb->flags = fcb_flags; 773 tx_fcb->l3_offset = ETHER_HDR_LEN; 774 tx_fcb->l4_offset = sizeof(struct ip); 775 } 776 777 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx); 778 } 779 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 780 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 781 782 if (start_tx) { 783 /* Enable transmitter and watchdog timer */ 784 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 785 sc->tsec_watchdog = 5; 786 } 787 } 788 789 static void 790 tsec_encap(if_t ifp, struct tsec_softc *sc, struct mbuf *m0, 791 uint16_t fcb_flags, int *start_tx) 792 { 793 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS]; 794 int error, i, nsegs; 795 struct tsec_bufmap *tx_bufmap; 796 uint32_t tx_idx; 797 uint16_t flags; 798 799 TSEC_TRANSMIT_LOCK_ASSERT(sc); 800 801 tx_idx = sc->tx_idx_head; 802 tx_bufmap = &sc->tx_bufmap[tx_idx]; 803 804 /* Create mapping in DMA memory */ 805 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0, 806 segs, &nsegs, BUS_DMA_NOWAIT); 807 if (error == EFBIG) { 808 /* Too many segments! Defrag and try again. */ 809 struct mbuf *m = m_defrag(m0, M_NOWAIT); 810 811 if (m == NULL) { 812 m_freem(m0); 813 return; 814 } 815 m0 = m; 816 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 817 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 818 } 819 if (error != 0) { 820 /* Give up. */ 821 m_freem(m0); 822 return; 823 } 824 825 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 826 BUS_DMASYNC_PREWRITE); 827 tx_bufmap->mbuf = m0; 828 829 /* 830 * Fill in the TX descriptors back to front so that READY bit in first 831 * descriptor is set last. 832 */ 833 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1); 834 sc->tx_idx_head = tx_idx; 835 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC; 836 for (i = nsegs - 1; i >= 0; i--) { 837 struct tsec_desc *tx_desc; 838 839 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1); 840 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 841 tx_desc->length = segs[i].ds_len; 842 tx_desc->bufptr = segs[i].ds_addr; 843 844 if (i == 0) { 845 wmb(); 846 847 if (fcb_flags != 0) 848 flags |= TSEC_TXBD_TOE; 849 } 850 851 /* 852 * Set flags: 853 * - wrap 854 * - checksum 855 * - ready to send 856 * - transmit the CRC sequence after the last data byte 857 * - interrupt after the last buffer 858 */ 859 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ? 860 TSEC_TXBD_W : 0) | flags; 861 862 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I); 863 } 864 865 BPF_MTAP(ifp, m0); 866 *start_tx = 1; 867 } 868 869 static void 870 tsec_setfilter(struct tsec_softc *sc) 871 { 872 if_t ifp; 873 uint32_t flags; 874 875 ifp = sc->tsec_ifp; 876 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 877 878 /* Promiscuous mode */ 879 if (if_getflags(ifp) & IFF_PROMISC) 880 flags |= TSEC_RCTRL_PROM; 881 else 882 flags &= ~TSEC_RCTRL_PROM; 883 884 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 885 } 886 887 #ifdef DEVICE_POLLING 888 static poll_handler_t tsec_poll; 889 890 static int 891 tsec_poll(if_t ifp, enum poll_cmd cmd, int count) 892 { 893 uint32_t ie; 894 struct tsec_softc *sc = if_getsoftc(ifp); 895 int rx_npkts; 896 897 rx_npkts = 0; 898 899 TSEC_GLOBAL_LOCK(sc); 900 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 901 TSEC_GLOBAL_UNLOCK(sc); 902 return (rx_npkts); 903 } 904 905 if (cmd == POLL_AND_CHECK_STATUS) { 906 tsec_error_intr_locked(sc, count); 907 908 /* Clear all events reported */ 909 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 910 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 911 } 912 913 tsec_transmit_intr_locked(sc); 914 915 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 916 917 rx_npkts = tsec_receive_intr_locked(sc, count); 918 919 TSEC_RECEIVE_UNLOCK(sc); 920 921 return (rx_npkts); 922 } 923 #endif /* DEVICE_POLLING */ 924 925 static int 926 tsec_ioctl(if_t ifp, u_long command, caddr_t data) 927 { 928 struct tsec_softc *sc = if_getsoftc(ifp); 929 struct ifreq *ifr = (struct ifreq *)data; 930 int mask, error = 0; 931 932 switch (command) { 933 case SIOCSIFMTU: 934 TSEC_GLOBAL_LOCK(sc); 935 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 936 if_setmtu(ifp, ifr->ifr_mtu); 937 else 938 error = EINVAL; 939 TSEC_GLOBAL_UNLOCK(sc); 940 break; 941 case SIOCSIFFLAGS: 942 TSEC_GLOBAL_LOCK(sc); 943 if (if_getflags(ifp) & IFF_UP) { 944 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 945 if ((sc->tsec_if_flags ^ if_getflags(ifp)) & 946 IFF_PROMISC) 947 tsec_setfilter(sc); 948 949 if ((sc->tsec_if_flags ^ if_getflags(ifp)) & 950 IFF_ALLMULTI) 951 tsec_setup_multicast(sc); 952 } else 953 tsec_init_locked(sc); 954 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 955 tsec_stop(sc); 956 957 sc->tsec_if_flags = if_getflags(ifp); 958 TSEC_GLOBAL_UNLOCK(sc); 959 break; 960 case SIOCADDMULTI: 961 case SIOCDELMULTI: 962 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 963 TSEC_GLOBAL_LOCK(sc); 964 tsec_setup_multicast(sc); 965 TSEC_GLOBAL_UNLOCK(sc); 966 } 967 case SIOCGIFMEDIA: 968 case SIOCSIFMEDIA: 969 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 970 command); 971 break; 972 case SIOCSIFCAP: 973 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 974 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 975 TSEC_GLOBAL_LOCK(sc); 976 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 977 if_setcapenablebit(ifp, IFCAP_HWCSUM & ifr->ifr_reqcap, 0); 978 tsec_offload_setup(sc); 979 TSEC_GLOBAL_UNLOCK(sc); 980 } 981 #ifdef DEVICE_POLLING 982 if (mask & IFCAP_POLLING) { 983 if (ifr->ifr_reqcap & IFCAP_POLLING) { 984 error = ether_poll_register(tsec_poll, ifp); 985 if (error) 986 return (error); 987 988 TSEC_GLOBAL_LOCK(sc); 989 /* Disable interrupts */ 990 tsec_intrs_ctl(sc, 0); 991 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 992 TSEC_GLOBAL_UNLOCK(sc); 993 } else { 994 error = ether_poll_deregister(ifp); 995 TSEC_GLOBAL_LOCK(sc); 996 /* Enable interrupts */ 997 tsec_intrs_ctl(sc, 1); 998 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 999 TSEC_GLOBAL_UNLOCK(sc); 1000 } 1001 } 1002 #endif 1003 break; 1004 1005 default: 1006 error = ether_ioctl(ifp, command, data); 1007 } 1008 1009 /* Flush buffers if not empty */ 1010 if (if_getflags(ifp) & IFF_UP) 1011 tsec_start(ifp); 1012 return (error); 1013 } 1014 1015 static int 1016 tsec_ifmedia_upd(if_t ifp) 1017 { 1018 struct tsec_softc *sc = if_getsoftc(ifp); 1019 struct mii_data *mii; 1020 1021 TSEC_TRANSMIT_LOCK(sc); 1022 1023 mii = sc->tsec_mii; 1024 mii_mediachg(mii); 1025 1026 TSEC_TRANSMIT_UNLOCK(sc); 1027 return (0); 1028 } 1029 1030 static void 1031 tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1032 { 1033 struct tsec_softc *sc = if_getsoftc(ifp); 1034 struct mii_data *mii; 1035 1036 TSEC_TRANSMIT_LOCK(sc); 1037 1038 mii = sc->tsec_mii; 1039 mii_pollstat(mii); 1040 1041 ifmr->ifm_active = mii->mii_media_active; 1042 ifmr->ifm_status = mii->mii_media_status; 1043 1044 TSEC_TRANSMIT_UNLOCK(sc); 1045 } 1046 1047 static int 1048 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1049 uint32_t *paddr) 1050 { 1051 struct mbuf *new_mbuf; 1052 bus_dma_segment_t seg[1]; 1053 int error, nsegs; 1054 1055 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1056 1057 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1058 if (new_mbuf == NULL) 1059 return (ENOBUFS); 1060 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1061 1062 if (*mbufp) { 1063 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1064 bus_dmamap_unload(tag, map); 1065 } 1066 1067 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1068 BUS_DMA_NOWAIT); 1069 KASSERT(nsegs == 1, ("Too many segments returned!")); 1070 if (nsegs != 1 || error) 1071 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1072 1073 #if 0 1074 if (error) { 1075 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1076 error); 1077 m_freem(new_mbuf); 1078 return (ENOBUFS); 1079 } 1080 #endif 1081 1082 #if 0 1083 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1084 ("Wrong alignment of RX buffer!")); 1085 #endif 1086 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1087 1088 (*mbufp) = new_mbuf; 1089 (*paddr) = seg->ds_addr; 1090 return (0); 1091 } 1092 1093 static void 1094 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1095 { 1096 u_int32_t *paddr; 1097 1098 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1099 paddr = arg; 1100 *paddr = segs->ds_addr; 1101 } 1102 1103 static int 1104 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1105 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1106 { 1107 int error; 1108 1109 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1110 error = bus_dma_tag_create(NULL, /* parent */ 1111 PAGE_SIZE, 0, /* alignment, boundary */ 1112 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1113 BUS_SPACE_MAXADDR, /* highaddr */ 1114 NULL, NULL, /* filtfunc, filtfuncarg */ 1115 dsize, 1, /* maxsize, nsegments */ 1116 dsize, 0, /* maxsegsz, flags */ 1117 NULL, NULL, /* lockfunc, lockfuncarg */ 1118 dtag); /* dmat */ 1119 1120 if (error) { 1121 device_printf(dev, "failed to allocate busdma %s tag\n", 1122 dname); 1123 (*vaddr) = NULL; 1124 return (ENXIO); 1125 } 1126 1127 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1128 dmap); 1129 if (error) { 1130 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1131 dname); 1132 bus_dma_tag_destroy(*dtag); 1133 (*vaddr) = NULL; 1134 return (ENXIO); 1135 } 1136 1137 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1138 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1139 if (error) { 1140 device_printf(dev, "cannot get address of the %s " 1141 "descriptors\n", dname); 1142 bus_dmamem_free(*dtag, *vaddr, *dmap); 1143 bus_dma_tag_destroy(*dtag); 1144 (*vaddr) = NULL; 1145 return (ENXIO); 1146 } 1147 1148 return (0); 1149 } 1150 1151 static void 1152 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1153 { 1154 1155 if (vaddr == NULL) 1156 return; 1157 1158 /* Unmap descriptors from DMA memory */ 1159 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1160 BUS_DMASYNC_POSTWRITE); 1161 bus_dmamap_unload(dtag, dmap); 1162 1163 /* Free descriptors memory */ 1164 bus_dmamem_free(dtag, vaddr, dmap); 1165 1166 /* Destroy descriptors tag */ 1167 bus_dma_tag_destroy(dtag); 1168 } 1169 1170 static void 1171 tsec_free_dma(struct tsec_softc *sc) 1172 { 1173 int i; 1174 1175 /* Free TX maps */ 1176 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1177 if (sc->tx_bufmap[i].map_initialized) 1178 bus_dmamap_destroy(sc->tsec_tx_mtag, 1179 sc->tx_bufmap[i].map); 1180 /* Destroy tag for TX mbufs */ 1181 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1182 1183 /* Free RX mbufs and maps */ 1184 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1185 if (sc->rx_data[i].mbuf) { 1186 /* Unload buffer from DMA */ 1187 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1188 BUS_DMASYNC_POSTREAD); 1189 bus_dmamap_unload(sc->tsec_rx_mtag, 1190 sc->rx_data[i].map); 1191 1192 /* Free buffer */ 1193 m_freem(sc->rx_data[i].mbuf); 1194 } 1195 /* Destroy map for this buffer */ 1196 if (sc->rx_data[i].map != NULL) 1197 bus_dmamap_destroy(sc->tsec_rx_mtag, 1198 sc->rx_data[i].map); 1199 } 1200 /* Destroy tag for RX mbufs */ 1201 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1202 1203 /* Unload TX/RX descriptors */ 1204 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1205 sc->tsec_tx_vaddr); 1206 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1207 sc->tsec_rx_vaddr); 1208 } 1209 1210 static void 1211 tsec_stop(struct tsec_softc *sc) 1212 { 1213 if_t ifp; 1214 uint32_t tmpval; 1215 1216 TSEC_GLOBAL_LOCK_ASSERT(sc); 1217 1218 ifp = sc->tsec_ifp; 1219 1220 /* Disable interface and watchdog timer */ 1221 callout_stop(&sc->tsec_callout); 1222 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1223 sc->tsec_watchdog = 0; 1224 1225 /* Disable all interrupts and stop DMA */ 1226 tsec_intrs_ctl(sc, 0); 1227 tsec_dma_ctl(sc, 0); 1228 1229 /* Remove pending data from TX queue */ 1230 while (sc->tx_idx_tail != sc->tx_idx_head) { 1231 bus_dmamap_sync(sc->tsec_tx_mtag, 1232 sc->tx_bufmap[sc->tx_idx_tail].map, 1233 BUS_DMASYNC_POSTWRITE); 1234 bus_dmamap_unload(sc->tsec_tx_mtag, 1235 sc->tx_bufmap[sc->tx_idx_tail].map); 1236 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf); 1237 sc->tx_idx_tail = (sc->tx_idx_tail + 1) 1238 & (TSEC_TX_NUM_DESC - 1); 1239 } 1240 1241 /* Disable RX and TX */ 1242 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1243 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1244 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1245 DELAY(10); 1246 } 1247 1248 static void 1249 tsec_tick(void *arg) 1250 { 1251 struct tsec_softc *sc = arg; 1252 if_t ifp; 1253 int link; 1254 1255 TSEC_GLOBAL_LOCK(sc); 1256 1257 tsec_watchdog(sc); 1258 1259 ifp = sc->tsec_ifp; 1260 link = sc->tsec_link; 1261 1262 mii_tick(sc->tsec_mii); 1263 1264 if (link == 0 && sc->tsec_link == 1 && 1265 (!if_sendq_empty(ifp))) 1266 tsec_start_locked(ifp); 1267 1268 /* Schedule another timeout one second from now. */ 1269 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1270 1271 TSEC_GLOBAL_UNLOCK(sc); 1272 } 1273 1274 /* 1275 * This is the core RX routine. It replenishes mbufs in the descriptor and 1276 * sends data which have been dma'ed into host memory to upper layer. 1277 * 1278 * Loops at most count times if count is > 0, or until done if count < 0. 1279 */ 1280 static int 1281 tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1282 { 1283 struct tsec_desc *rx_desc; 1284 if_t ifp; 1285 struct rx_data_type *rx_data; 1286 struct mbuf *m; 1287 uint32_t i; 1288 int c, rx_npkts; 1289 uint16_t flags; 1290 1291 TSEC_RECEIVE_LOCK_ASSERT(sc); 1292 1293 ifp = sc->tsec_ifp; 1294 rx_data = sc->rx_data; 1295 rx_npkts = 0; 1296 1297 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1298 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1299 1300 for (c = 0; ; c++) { 1301 if (count >= 0 && count-- == 0) 1302 break; 1303 1304 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1305 flags = rx_desc->flags; 1306 1307 /* Check if there is anything to receive */ 1308 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1309 /* 1310 * Avoid generating another interrupt 1311 */ 1312 if (flags & TSEC_RXBD_E) 1313 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1314 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1315 /* 1316 * We didn't consume current descriptor and have to 1317 * return it to the queue 1318 */ 1319 TSEC_BACK_CUR_RX_DESC(sc); 1320 break; 1321 } 1322 1323 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1324 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1325 rx_desc->length = 0; 1326 rx_desc->flags = (rx_desc->flags & 1327 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1328 1329 if (sc->frame != NULL) { 1330 m_free(sc->frame); 1331 sc->frame = NULL; 1332 } 1333 1334 continue; 1335 } 1336 1337 /* Ok... process frame */ 1338 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1339 m = rx_data[i].mbuf; 1340 m->m_len = rx_desc->length; 1341 1342 if (sc->frame != NULL) { 1343 if ((flags & TSEC_RXBD_L) != 0) 1344 m->m_len -= m_length(sc->frame, NULL); 1345 1346 m->m_flags &= ~M_PKTHDR; 1347 m_cat(sc->frame, m); 1348 } else { 1349 sc->frame = m; 1350 } 1351 1352 m = NULL; 1353 1354 if ((flags & TSEC_RXBD_L) != 0) { 1355 m = sc->frame; 1356 sc->frame = NULL; 1357 } 1358 1359 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1360 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1361 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1362 /* 1363 * We ran out of mbufs; didn't consume current 1364 * descriptor and have to return it to the queue. 1365 */ 1366 TSEC_BACK_CUR_RX_DESC(sc); 1367 break; 1368 } 1369 1370 /* Attach new buffer to descriptor and clear flags */ 1371 rx_desc->bufptr = rx_data[i].paddr; 1372 rx_desc->length = 0; 1373 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1374 TSEC_RXBD_E | TSEC_RXBD_I; 1375 1376 if (m != NULL) { 1377 m->m_pkthdr.rcvif = ifp; 1378 1379 m_fixhdr(m); 1380 m_adj(m, -ETHER_CRC_LEN); 1381 1382 if (sc->is_etsec) 1383 tsec_offload_process_frame(sc, m); 1384 1385 TSEC_RECEIVE_UNLOCK(sc); 1386 if_input(ifp, m); 1387 TSEC_RECEIVE_LOCK(sc); 1388 rx_npkts++; 1389 } 1390 } 1391 1392 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1394 1395 /* 1396 * Make sure TSEC receiver is not halted. 1397 * 1398 * Various conditions can stop the TSEC receiver, but not all are 1399 * signaled and handled by error interrupt, so make sure the receiver 1400 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1401 * halted, and is harmless if already running. 1402 */ 1403 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1404 return (rx_npkts); 1405 } 1406 1407 void 1408 tsec_receive_intr(void *arg) 1409 { 1410 struct tsec_softc *sc = arg; 1411 1412 TSEC_RECEIVE_LOCK(sc); 1413 1414 #ifdef DEVICE_POLLING 1415 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) { 1416 TSEC_RECEIVE_UNLOCK(sc); 1417 return; 1418 } 1419 #endif 1420 1421 /* Confirm the interrupt was received by driver */ 1422 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1423 tsec_receive_intr_locked(sc, -1); 1424 1425 TSEC_RECEIVE_UNLOCK(sc); 1426 } 1427 1428 static void 1429 tsec_transmit_intr_locked(struct tsec_softc *sc) 1430 { 1431 if_t ifp; 1432 uint32_t tx_idx; 1433 1434 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1435 1436 ifp = sc->tsec_ifp; 1437 1438 /* Update collision statistics */ 1439 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL)); 1440 1441 /* Reset collision counters in hardware */ 1442 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1443 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1444 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1445 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1446 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1447 1448 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1449 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1450 1451 tx_idx = sc->tx_idx_tail; 1452 while (tx_idx != sc->tx_idx_head) { 1453 struct tsec_desc *tx_desc; 1454 struct tsec_bufmap *tx_bufmap; 1455 1456 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 1457 if (tx_desc->flags & TSEC_TXBD_R) { 1458 break; 1459 } 1460 1461 tx_bufmap = &sc->tx_bufmap[tx_idx]; 1462 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1); 1463 if (tx_bufmap->mbuf == NULL) 1464 continue; 1465 1466 /* 1467 * This is the last buf in this packet, so unmap and free it. 1468 */ 1469 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 1470 BUS_DMASYNC_POSTWRITE); 1471 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map); 1472 m_freem(tx_bufmap->mbuf); 1473 tx_bufmap->mbuf = NULL; 1474 1475 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1476 } 1477 sc->tx_idx_tail = tx_idx; 1478 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1479 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1480 1481 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1482 tsec_start_locked(ifp); 1483 1484 if (sc->tx_idx_tail == sc->tx_idx_head) 1485 sc->tsec_watchdog = 0; 1486 } 1487 1488 void 1489 tsec_transmit_intr(void *arg) 1490 { 1491 struct tsec_softc *sc = arg; 1492 1493 TSEC_TRANSMIT_LOCK(sc); 1494 1495 #ifdef DEVICE_POLLING 1496 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) { 1497 TSEC_TRANSMIT_UNLOCK(sc); 1498 return; 1499 } 1500 #endif 1501 /* Confirm the interrupt was received by driver */ 1502 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1503 tsec_transmit_intr_locked(sc); 1504 1505 TSEC_TRANSMIT_UNLOCK(sc); 1506 } 1507 1508 static void 1509 tsec_error_intr_locked(struct tsec_softc *sc, int count) 1510 { 1511 if_t ifp; 1512 uint32_t eflags; 1513 1514 TSEC_GLOBAL_LOCK_ASSERT(sc); 1515 1516 ifp = sc->tsec_ifp; 1517 1518 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1519 1520 /* Clear events bits in hardware */ 1521 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1522 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1523 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1524 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1525 1526 /* Check transmitter errors */ 1527 if (eflags & TSEC_IEVENT_TXE) { 1528 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1529 1530 if (eflags & TSEC_IEVENT_LC) 1531 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1532 1533 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1534 } 1535 1536 /* Check for discarded frame due to a lack of buffers */ 1537 if (eflags & TSEC_IEVENT_BSY) { 1538 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1539 } 1540 1541 if (if_getflags(ifp) & IFF_DEBUG) 1542 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1543 eflags); 1544 1545 if (eflags & TSEC_IEVENT_EBERR) { 1546 if_printf(ifp, "System bus error occurred during" 1547 "DMA transaction (flags: 0x%x)\n", eflags); 1548 tsec_init_locked(sc); 1549 } 1550 1551 if (eflags & TSEC_IEVENT_BABT) 1552 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1553 1554 if (eflags & TSEC_IEVENT_BABR) 1555 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1556 } 1557 1558 void 1559 tsec_error_intr(void *arg) 1560 { 1561 struct tsec_softc *sc = arg; 1562 1563 TSEC_GLOBAL_LOCK(sc); 1564 tsec_error_intr_locked(sc, -1); 1565 TSEC_GLOBAL_UNLOCK(sc); 1566 } 1567 1568 int 1569 tsec_miibus_readreg(device_t dev, int phy, int reg) 1570 { 1571 struct tsec_softc *sc; 1572 int timeout; 1573 int rv; 1574 1575 sc = device_get_softc(dev); 1576 1577 TSEC_PHY_LOCK(); 1578 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1579 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1581 1582 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY); 1583 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT); 1584 TSEC_PHY_UNLOCK(); 1585 1586 if (timeout) 1587 device_printf(dev, "Timeout while reading from PHY!\n"); 1588 1589 return (rv); 1590 } 1591 1592 int 1593 tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1594 { 1595 struct tsec_softc *sc; 1596 int timeout; 1597 1598 sc = device_get_softc(dev); 1599 1600 TSEC_PHY_LOCK(); 1601 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1602 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value); 1603 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 1604 TSEC_PHY_UNLOCK(); 1605 1606 if (timeout) 1607 device_printf(dev, "Timeout while writing to PHY!\n"); 1608 1609 return (0); 1610 } 1611 1612 void 1613 tsec_miibus_statchg(device_t dev) 1614 { 1615 struct tsec_softc *sc; 1616 struct mii_data *mii; 1617 uint32_t ecntrl, id, tmp; 1618 int link; 1619 1620 sc = device_get_softc(dev); 1621 mii = sc->tsec_mii; 1622 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1623 1624 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1625 1626 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1627 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1628 else 1629 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1630 1631 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1632 case IFM_1000_T: 1633 case IFM_1000_SX: 1634 tmp |= TSEC_MACCFG2_GMII; 1635 sc->tsec_link = link; 1636 break; 1637 case IFM_100_TX: 1638 case IFM_10_T: 1639 tmp |= TSEC_MACCFG2_MII; 1640 sc->tsec_link = link; 1641 break; 1642 case IFM_NONE: 1643 if (link) 1644 device_printf(dev, "No speed selected but link " 1645 "active!\n"); 1646 sc->tsec_link = 0; 1647 return; 1648 default: 1649 sc->tsec_link = 0; 1650 device_printf(dev, "Unknown speed (%d), link %s!\n", 1651 IFM_SUBTYPE(mii->mii_media_active), 1652 ((link) ? "up" : "down")); 1653 return; 1654 } 1655 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1656 1657 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1658 id = TSEC_READ(sc, TSEC_REG_ID2); 1659 if (id & 0xffff) { 1660 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1661 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1662 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1663 } 1664 } 1665 1666 static void 1667 tsec_add_sysctls(struct tsec_softc *sc) 1668 { 1669 struct sysctl_ctx_list *ctx; 1670 struct sysctl_oid_list *children; 1671 struct sysctl_oid *tree; 1672 1673 ctx = device_get_sysctl_ctx(sc->dev); 1674 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1675 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1676 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing"); 1677 children = SYSCTL_CHILDREN(tree); 1678 1679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1680 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1681 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)"); 1682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1683 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1684 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)"); 1685 1686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1687 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1688 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)"); 1689 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1690 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1691 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)"); 1692 } 1693 1694 /* 1695 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1696 * interrupt is raised either upon: 1697 * 1698 * - threshold-defined period of time elapsed, or 1699 * - threshold-defined number of frames is received/transmitted, 1700 * whichever occurs first. 1701 * 1702 * The following sysctls regulate IC behaviour (for TX/RX separately): 1703 * 1704 * dev.tsec.<unit>.int_coal.rx_time 1705 * dev.tsec.<unit>.int_coal.rx_count 1706 * dev.tsec.<unit>.int_coal.tx_time 1707 * dev.tsec.<unit>.int_coal.tx_count 1708 * 1709 * Values: 1710 * 1711 * - 0 for either time or count disables IC on the given TX/RX path 1712 * 1713 * - count: 1-255 (expresses frame count number; note that value of 1 is 1714 * effectively IC off) 1715 * 1716 * - time: 1-65535 (value corresponds to a real time period and is 1717 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1718 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1719 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1720 * TSEC reference manual. 1721 */ 1722 static int 1723 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1724 { 1725 int error; 1726 uint32_t time; 1727 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1728 1729 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1730 1731 error = sysctl_handle_int(oidp, &time, 0, req); 1732 if (error != 0) 1733 return (error); 1734 1735 if (time > 65535) 1736 return (EINVAL); 1737 1738 TSEC_IC_LOCK(sc); 1739 if (arg2 == TSEC_IC_RX) { 1740 sc->rx_ic_time = time; 1741 tsec_set_rxic(sc); 1742 } else { 1743 sc->tx_ic_time = time; 1744 tsec_set_txic(sc); 1745 } 1746 TSEC_IC_UNLOCK(sc); 1747 1748 return (0); 1749 } 1750 1751 static int 1752 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1753 { 1754 int error; 1755 uint32_t count; 1756 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1757 1758 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1759 1760 error = sysctl_handle_int(oidp, &count, 0, req); 1761 if (error != 0) 1762 return (error); 1763 1764 if (count > 255) 1765 return (EINVAL); 1766 1767 TSEC_IC_LOCK(sc); 1768 if (arg2 == TSEC_IC_RX) { 1769 sc->rx_ic_count = count; 1770 tsec_set_rxic(sc); 1771 } else { 1772 sc->tx_ic_count = count; 1773 tsec_set_txic(sc); 1774 } 1775 TSEC_IC_UNLOCK(sc); 1776 1777 return (0); 1778 } 1779 1780 static void 1781 tsec_set_rxic(struct tsec_softc *sc) 1782 { 1783 uint32_t rxic_val; 1784 1785 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1786 /* Disable RX IC */ 1787 rxic_val = 0; 1788 else { 1789 rxic_val = 0x80000000; 1790 rxic_val |= (sc->rx_ic_count << 21); 1791 rxic_val |= sc->rx_ic_time; 1792 } 1793 1794 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1795 } 1796 1797 static void 1798 tsec_set_txic(struct tsec_softc *sc) 1799 { 1800 uint32_t txic_val; 1801 1802 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1803 /* Disable TX IC */ 1804 txic_val = 0; 1805 else { 1806 txic_val = 0x80000000; 1807 txic_val |= (sc->tx_ic_count << 21); 1808 txic_val |= sc->tx_ic_time; 1809 } 1810 1811 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1812 } 1813 1814 static void 1815 tsec_offload_setup(struct tsec_softc *sc) 1816 { 1817 if_t ifp = sc->tsec_ifp; 1818 uint32_t reg; 1819 1820 TSEC_GLOBAL_LOCK_ASSERT(sc); 1821 1822 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1823 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1824 1825 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 1826 if_sethwassist(ifp, TSEC_CHECKSUM_FEATURES); 1827 else 1828 if_sethwassist(ifp, 0); 1829 1830 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1831 1832 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1833 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1834 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1835 1836 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 1837 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1838 TSEC_RCTRL_PRSDEP_PARSE_L234; 1839 1840 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1841 } 1842 1843 static void 1844 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1845 { 1846 struct tsec_rx_fcb rx_fcb; 1847 int csum_flags = 0; 1848 int protocol, flags; 1849 1850 TSEC_RECEIVE_LOCK_ASSERT(sc); 1851 1852 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1853 flags = rx_fcb.flags; 1854 protocol = rx_fcb.protocol; 1855 1856 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1857 csum_flags |= CSUM_IP_CHECKED; 1858 1859 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1860 csum_flags |= CSUM_IP_VALID; 1861 } 1862 1863 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1864 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1865 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1866 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1867 m->m_pkthdr.csum_data = 0xFFFF; 1868 } 1869 1870 m->m_pkthdr.csum_flags = csum_flags; 1871 1872 if (flags & TSEC_RX_FCB_VLAN) { 1873 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1874 m->m_flags |= M_VLANTAG; 1875 } 1876 1877 m_adj(m, sizeof(struct tsec_rx_fcb)); 1878 } 1879 1880 static u_int 1881 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1882 { 1883 uint32_t h, *hashtable = arg; 1884 1885 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF; 1886 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1887 1888 return (1); 1889 } 1890 1891 static void 1892 tsec_setup_multicast(struct tsec_softc *sc) 1893 { 1894 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1895 if_t ifp = sc->tsec_ifp; 1896 int i; 1897 1898 TSEC_GLOBAL_LOCK_ASSERT(sc); 1899 1900 if (if_getflags(ifp) & IFF_ALLMULTI) { 1901 for (i = 0; i < 8; i++) 1902 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1903 1904 return; 1905 } 1906 1907 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable); 1908 1909 for (i = 0; i < 8; i++) 1910 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1911 } 1912 1913 static int 1914 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1915 { 1916 1917 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1918 1919 TSEC_GLOBAL_LOCK_ASSERT(sc); 1920 1921 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1922 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1923 return (mtu); 1924 } 1925 1926 return (0); 1927 } 1928