1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #ifdef HAVE_KERNEL_OPTION_HEADERS 36 #include "opt_device_polling.h" 37 #endif 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/mbuf.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 50 #include <net/bpf.h> 51 #include <net/ethernet.h> 52 #include <net/if.h> 53 #include <net/if_var.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in_systm.h> 61 #include <netinet/in.h> 62 #include <netinet/ip.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/tsec/if_tsec.h> 70 #include <dev/tsec/if_tsecreg.h> 71 72 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 73 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 74 const char *dname); 75 static void tsec_dma_ctl(struct tsec_softc *sc, int state); 76 static void tsec_encap(if_t ifp, struct tsec_softc *sc, 77 struct mbuf *m0, uint16_t fcb_flags, int *start_tx); 78 static void tsec_free_dma(struct tsec_softc *sc); 79 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 80 static int tsec_ifmedia_upd(if_t ifp); 81 static void tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr); 82 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 83 struct mbuf **mbufp, uint32_t *paddr); 84 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 85 int nseg, int error); 86 static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 87 static void tsec_init(void *xsc); 88 static void tsec_init_locked(struct tsec_softc *sc); 89 static int tsec_ioctl(if_t ifp, u_long command, caddr_t data); 90 static void tsec_reset_mac(struct tsec_softc *sc); 91 static void tsec_setfilter(struct tsec_softc *sc); 92 static void tsec_set_mac_address(struct tsec_softc *sc); 93 static void tsec_start(if_t ifp); 94 static void tsec_start_locked(if_t ifp); 95 static void tsec_stop(struct tsec_softc *sc); 96 static void tsec_tick(void *arg); 97 static void tsec_watchdog(struct tsec_softc *sc); 98 static void tsec_add_sysctls(struct tsec_softc *sc); 99 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 100 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 101 static void tsec_set_rxic(struct tsec_softc *sc); 102 static void tsec_set_txic(struct tsec_softc *sc); 103 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 104 static void tsec_transmit_intr_locked(struct tsec_softc *sc); 105 static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 106 static void tsec_offload_setup(struct tsec_softc *sc); 107 static void tsec_offload_process_frame(struct tsec_softc *sc, 108 struct mbuf *m); 109 static void tsec_setup_multicast(struct tsec_softc *sc); 110 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 111 112 DRIVER_MODULE(miibus, tsec, miibus_driver, 0, 0); 113 MODULE_DEPEND(tsec, ether, 1, 1, 1); 114 MODULE_DEPEND(tsec, miibus, 1, 1, 1); 115 116 struct mtx tsec_phy_mtx; 117 118 int 119 tsec_attach(struct tsec_softc *sc) 120 { 121 uint8_t hwaddr[ETHER_ADDR_LEN]; 122 if_t ifp; 123 int error = 0; 124 int i; 125 126 /* Initialize global (because potentially shared) MII lock */ 127 if (!mtx_initialized(&tsec_phy_mtx)) 128 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF); 129 130 /* Reset all TSEC counters */ 131 TSEC_TX_RX_COUNTERS_INIT(sc); 132 133 /* Stop DMA engine if enabled by firmware */ 134 tsec_dma_ctl(sc, 0); 135 136 /* Reset MAC */ 137 tsec_reset_mac(sc); 138 139 /* Disable interrupts for now */ 140 tsec_intrs_ctl(sc, 0); 141 142 /* Configure defaults for interrupts coalescing */ 143 sc->rx_ic_time = 768; 144 sc->rx_ic_count = 16; 145 sc->tx_ic_time = 768; 146 sc->tx_ic_count = 16; 147 tsec_set_rxic(sc); 148 tsec_set_txic(sc); 149 tsec_add_sysctls(sc); 150 151 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 152 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 153 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 154 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 155 156 if (error) { 157 tsec_detach(sc); 158 return (ENXIO); 159 } 160 161 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 162 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 163 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 164 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 165 if (error) { 166 tsec_detach(sc); 167 return (ENXIO); 168 } 169 170 /* Allocate a busdma tag for TX mbufs. */ 171 error = bus_dma_tag_create(NULL, /* parent */ 172 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 173 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 174 BUS_SPACE_MAXADDR, /* highaddr */ 175 NULL, NULL, /* filtfunc, filtfuncarg */ 176 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 177 TSEC_TX_MAX_DMA_SEGS, /* nsegments */ 178 MCLBYTES, 0, /* maxsegsz, flags */ 179 NULL, NULL, /* lockfunc, lockfuncarg */ 180 &sc->tsec_tx_mtag); /* dmat */ 181 if (error) { 182 device_printf(sc->dev, "failed to allocate busdma tag " 183 "(tx mbufs)\n"); 184 tsec_detach(sc); 185 return (ENXIO); 186 } 187 188 /* Allocate a busdma tag for RX mbufs. */ 189 error = bus_dma_tag_create(NULL, /* parent */ 190 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 191 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 192 BUS_SPACE_MAXADDR, /* highaddr */ 193 NULL, NULL, /* filtfunc, filtfuncarg */ 194 MCLBYTES, /* maxsize */ 195 1, /* nsegments */ 196 MCLBYTES, 0, /* maxsegsz, flags */ 197 NULL, NULL, /* lockfunc, lockfuncarg */ 198 &sc->tsec_rx_mtag); /* dmat */ 199 if (error) { 200 device_printf(sc->dev, "failed to allocate busdma tag " 201 "(rx mbufs)\n"); 202 tsec_detach(sc); 203 return (ENXIO); 204 } 205 206 /* Create TX busdma maps */ 207 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, 209 &sc->tx_bufmap[i].map); 210 if (error) { 211 device_printf(sc->dev, "failed to init TX ring\n"); 212 tsec_detach(sc); 213 return (ENXIO); 214 } 215 sc->tx_bufmap[i].map_initialized = 1; 216 } 217 218 /* Create RX busdma maps and zero mbuf handlers */ 219 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 220 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 221 &sc->rx_data[i].map); 222 if (error) { 223 device_printf(sc->dev, "failed to init RX ring\n"); 224 tsec_detach(sc); 225 return (ENXIO); 226 } 227 sc->rx_data[i].mbuf = NULL; 228 } 229 230 /* Create mbufs for RX buffers */ 231 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 232 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 233 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 234 if (error) { 235 device_printf(sc->dev, "can't load rx DMA map %d, " 236 "error = %d\n", i, error); 237 tsec_detach(sc); 238 return (error); 239 } 240 } 241 242 /* Create network interface for upper layers */ 243 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 244 if (ifp == NULL) { 245 device_printf(sc->dev, "if_alloc() failed\n"); 246 tsec_detach(sc); 247 return (ENOMEM); 248 } 249 250 if_setsoftc(ifp, sc); 251 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 252 if_setflags(ifp, IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST); 253 if_setinitfn(ifp, tsec_init); 254 if_setstartfn(ifp, tsec_start); 255 if_setioctlfn(ifp, tsec_ioctl); 256 257 if_setsendqlen(ifp, TSEC_TX_NUM_DESC - 1); 258 if_setsendqready(ifp); 259 260 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 261 if (sc->is_etsec) 262 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 263 264 if_setcapenable(ifp, if_getcapabilities(ifp)); 265 266 #ifdef DEVICE_POLLING 267 /* Advertise that polling is supported */ 268 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 269 #endif 270 271 /* Attach PHY(s) */ 272 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 273 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 274 0); 275 if (error) { 276 device_printf(sc->dev, "attaching PHYs failed\n"); 277 if_free(ifp); 278 sc->tsec_ifp = NULL; 279 tsec_detach(sc); 280 return (error); 281 } 282 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 283 284 /* Set MAC address */ 285 tsec_get_hwaddr(sc, hwaddr); 286 ether_ifattach(ifp, hwaddr); 287 288 return (0); 289 } 290 291 int 292 tsec_detach(struct tsec_softc *sc) 293 { 294 295 if (sc->tsec_ifp != NULL) { 296 #ifdef DEVICE_POLLING 297 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) 298 ether_poll_deregister(sc->tsec_ifp); 299 #endif 300 301 /* Stop TSEC controller and free TX queue */ 302 if (sc->sc_rres) 303 tsec_shutdown(sc->dev); 304 305 /* Detach network interface */ 306 ether_ifdetach(sc->tsec_ifp); 307 if_free(sc->tsec_ifp); 308 sc->tsec_ifp = NULL; 309 } 310 311 /* Free DMA resources */ 312 tsec_free_dma(sc); 313 314 return (0); 315 } 316 317 int 318 tsec_shutdown(device_t dev) 319 { 320 struct tsec_softc *sc; 321 322 sc = device_get_softc(dev); 323 324 TSEC_GLOBAL_LOCK(sc); 325 tsec_stop(sc); 326 TSEC_GLOBAL_UNLOCK(sc); 327 return (0); 328 } 329 330 int 331 tsec_suspend(device_t dev) 332 { 333 334 /* TODO not implemented! */ 335 return (0); 336 } 337 338 int 339 tsec_resume(device_t dev) 340 { 341 342 /* TODO not implemented! */ 343 return (0); 344 } 345 346 static void 347 tsec_init(void *xsc) 348 { 349 struct tsec_softc *sc = xsc; 350 351 TSEC_GLOBAL_LOCK(sc); 352 tsec_init_locked(sc); 353 TSEC_GLOBAL_UNLOCK(sc); 354 } 355 356 static int 357 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags) 358 { 359 int timeout; 360 361 /* 362 * The status indicators are not set immediately after a command. 363 * Discard the first value. 364 */ 365 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND); 366 367 timeout = TSEC_READ_RETRY; 368 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout) 369 DELAY(TSEC_READ_DELAY); 370 371 return (timeout == 0); 372 } 373 374 static void 375 tsec_init_locked(struct tsec_softc *sc) 376 { 377 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 378 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 379 if_t ifp = sc->tsec_ifp; 380 uint32_t val, i; 381 int timeout; 382 383 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 384 return; 385 386 TSEC_GLOBAL_LOCK_ASSERT(sc); 387 tsec_stop(sc); 388 389 /* 390 * These steps are according to the MPC8555E PowerQUICCIII RM: 391 * 14.7 Initialization/Application Information 392 */ 393 394 /* Step 1: soft reset MAC */ 395 tsec_reset_mac(sc); 396 397 /* Step 2: Initialize MACCFG2 */ 398 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 399 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 400 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 401 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 402 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 403 ); 404 405 /* Step 3: Initialize ECNTRL 406 * While the documentation states that R100M is ignored if RPM is 407 * not set, it does seem to be needed to get the orange boxes to 408 * work (which have a Marvell 88E1111 PHY). Go figure. 409 */ 410 411 /* 412 * XXX kludge - use circumstancial evidence to program ECNTRL 413 * correctly. Ideally we need some board information to guide 414 * us here. 415 */ 416 i = TSEC_READ(sc, TSEC_REG_ID2); 417 val = (i & 0xffff) 418 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 419 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 420 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 421 422 /* Step 4: Initialize MAC station address */ 423 tsec_set_mac_address(sc); 424 425 /* 426 * Step 5: Assign a Physical address to the TBI so as to not conflict 427 * with the external PHY physical address 428 */ 429 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 430 431 TSEC_PHY_LOCK(sc); 432 433 /* Step 6: Reset the management interface */ 434 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 435 436 /* Step 7: Setup the MII Mgmt clock speed */ 437 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 438 439 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 440 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 441 442 TSEC_PHY_UNLOCK(sc); 443 if (timeout) { 444 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 445 return; 446 } 447 448 /* Step 9: Setup the MII Mgmt */ 449 mii_mediachg(sc->tsec_mii); 450 451 /* Step 10: Clear IEVENT register */ 452 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 453 454 /* Step 11: Enable interrupts */ 455 #ifdef DEVICE_POLLING 456 /* 457 * ...only if polling is not turned on. Disable interrupts explicitly 458 * if polling is enabled. 459 */ 460 if (if_getcapenable(ifp) & IFCAP_POLLING ) 461 tsec_intrs_ctl(sc, 0); 462 else 463 #endif /* DEVICE_POLLING */ 464 tsec_intrs_ctl(sc, 1); 465 466 /* Step 12: Initialize IADDRn */ 467 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 468 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 469 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 470 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 471 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 472 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 473 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 474 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 475 476 /* Step 13: Initialize GADDRn */ 477 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 478 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 479 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 480 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 481 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 482 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 483 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 484 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 485 486 /* Step 14: Initialize RCTRL */ 487 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 488 489 /* Step 15: Initialize DMACTRL */ 490 tsec_dma_ctl(sc, 1); 491 492 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 493 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 494 495 /* 496 * Step 17: Initialize transmit/receive descriptor rings. 497 * Initialize TBASE and RBASE. 498 */ 499 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 500 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 501 502 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 503 tx_desc[i].bufptr = 0; 504 tx_desc[i].length = 0; 505 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 506 TSEC_TXBD_W : 0); 507 } 508 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 510 511 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 512 rx_desc[i].bufptr = sc->rx_data[i].paddr; 513 rx_desc[i].length = 0; 514 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 515 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 516 } 517 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 519 520 /* Step 18: Initialize the maximum receive buffer length */ 521 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 522 523 /* Step 19: Configure ethernet frame sizes */ 524 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 525 tsec_set_mtu(sc, if_getmtu(ifp)); 526 527 /* Step 20: Enable Rx and RxBD sdata snooping */ 528 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 529 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 530 531 /* Step 21: Reset collision counters in hardware */ 532 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 533 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 534 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 535 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 536 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 537 538 /* Step 22: Mask all CAM interrupts */ 539 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 540 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 541 542 /* Step 23: Enable Rx and Tx */ 543 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 544 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 545 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 546 547 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 548 TSEC_TX_RX_COUNTERS_INIT(sc); 549 550 /* Step 25: Setup TCP/IP Off-Load engine */ 551 if (sc->is_etsec) 552 tsec_offload_setup(sc); 553 554 /* Step 26: Setup multicast filters */ 555 tsec_setup_multicast(sc); 556 557 /* Step 27: Activate network interface */ 558 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 559 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 560 sc->tsec_if_flags = if_getflags(ifp); 561 sc->tsec_watchdog = 0; 562 563 /* Schedule watchdog timeout */ 564 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 565 } 566 567 static void 568 tsec_set_mac_address(struct tsec_softc *sc) 569 { 570 uint32_t macbuf[2] = { 0, 0 }; 571 char *macbufp, *curmac; 572 int i; 573 574 TSEC_GLOBAL_LOCK_ASSERT(sc); 575 576 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 577 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN, 578 sizeof(macbuf))); 579 580 macbufp = (char *)macbuf; 581 curmac = (char *)if_getlladdr(sc->tsec_ifp); 582 583 /* Correct order of MAC address bytes */ 584 for (i = 1; i <= ETHER_ADDR_LEN; i++) 585 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 586 587 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 588 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 589 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 590 } 591 592 /* 593 * DMA control function, if argument state is: 594 * 0 - DMA engine will be disabled 595 * 1 - DMA engine will be enabled 596 */ 597 static void 598 tsec_dma_ctl(struct tsec_softc *sc, int state) 599 { 600 device_t dev; 601 uint32_t dma_flags, timeout; 602 603 dev = sc->dev; 604 605 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 606 607 switch (state) { 608 case 0: 609 /* Temporarily clear stop graceful stop bits. */ 610 tsec_dma_ctl(sc, 1000); 611 612 /* Set it again */ 613 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 614 break; 615 case 1000: 616 case 1: 617 /* Set write with response (WWR), wait (WOP) and snoop bits */ 618 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 619 DMACTRL_WWR | DMACTRL_WOP); 620 621 /* Clear graceful stop bits */ 622 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 623 break; 624 default: 625 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 626 state); 627 } 628 629 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 630 631 switch (state) { 632 case 0: 633 /* Wait for DMA stop */ 634 timeout = TSEC_READ_RETRY; 635 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 636 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 637 DELAY(TSEC_READ_DELAY); 638 639 if (timeout == 0) 640 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 641 break; 642 case 1: 643 /* Restart transmission function */ 644 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 645 } 646 } 647 648 /* 649 * Interrupts control function, if argument state is: 650 * 0 - all TSEC interrupts will be masked 651 * 1 - all TSEC interrupts will be unmasked 652 */ 653 static void 654 tsec_intrs_ctl(struct tsec_softc *sc, int state) 655 { 656 device_t dev; 657 658 dev = sc->dev; 659 660 switch (state) { 661 case 0: 662 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 663 break; 664 case 1: 665 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 666 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 667 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 668 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 669 break; 670 default: 671 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 672 state); 673 } 674 } 675 676 static void 677 tsec_reset_mac(struct tsec_softc *sc) 678 { 679 uint32_t maccfg1_flags; 680 681 /* Set soft reset bit */ 682 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 683 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 684 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 685 686 /* Clear soft reset bit */ 687 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 688 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 689 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 690 } 691 692 static void 693 tsec_watchdog(struct tsec_softc *sc) 694 { 695 if_t ifp; 696 697 TSEC_GLOBAL_LOCK_ASSERT(sc); 698 699 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 700 return; 701 702 ifp = sc->tsec_ifp; 703 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 704 if_printf(ifp, "watchdog timeout\n"); 705 706 tsec_stop(sc); 707 tsec_init_locked(sc); 708 } 709 710 static void 711 tsec_start(if_t ifp) 712 { 713 struct tsec_softc *sc = if_getsoftc(ifp); 714 715 TSEC_TRANSMIT_LOCK(sc); 716 tsec_start_locked(ifp); 717 TSEC_TRANSMIT_UNLOCK(sc); 718 } 719 720 static void 721 tsec_start_locked(if_t ifp) 722 { 723 struct tsec_softc *sc; 724 struct mbuf *m0; 725 struct tsec_tx_fcb *tx_fcb; 726 int csum_flags; 727 int start_tx; 728 uint16_t fcb_flags; 729 730 sc = if_getsoftc(ifp); 731 start_tx = 0; 732 733 TSEC_TRANSMIT_LOCK_ASSERT(sc); 734 735 if (sc->tsec_link == 0) 736 return; 737 738 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 739 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 740 741 for (;;) { 742 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) { 743 /* No free descriptors */ 744 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 745 break; 746 } 747 748 /* Get packet from the queue */ 749 m0 = if_dequeue(ifp); 750 if (m0 == NULL) 751 break; 752 753 /* Insert TCP/IP Off-load frame control block */ 754 fcb_flags = 0; 755 csum_flags = m0->m_pkthdr.csum_flags; 756 if (csum_flags) { 757 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 758 if (m0 == NULL) 759 break; 760 761 if (csum_flags & CSUM_IP) 762 fcb_flags |= TSEC_TX_FCB_IP4 | 763 TSEC_TX_FCB_CSUM_IP; 764 765 if (csum_flags & CSUM_TCP) 766 fcb_flags |= TSEC_TX_FCB_TCP | 767 TSEC_TX_FCB_CSUM_TCP_UDP; 768 769 if (csum_flags & CSUM_UDP) 770 fcb_flags |= TSEC_TX_FCB_UDP | 771 TSEC_TX_FCB_CSUM_TCP_UDP; 772 773 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 774 tx_fcb->flags = fcb_flags; 775 tx_fcb->l3_offset = ETHER_HDR_LEN; 776 tx_fcb->l4_offset = sizeof(struct ip); 777 } 778 779 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx); 780 } 781 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 783 784 if (start_tx) { 785 /* Enable transmitter and watchdog timer */ 786 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 787 sc->tsec_watchdog = 5; 788 } 789 } 790 791 static void 792 tsec_encap(if_t ifp, struct tsec_softc *sc, struct mbuf *m0, 793 uint16_t fcb_flags, int *start_tx) 794 { 795 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS]; 796 int error, i, nsegs; 797 struct tsec_bufmap *tx_bufmap; 798 uint32_t tx_idx; 799 uint16_t flags; 800 801 TSEC_TRANSMIT_LOCK_ASSERT(sc); 802 803 tx_idx = sc->tx_idx_head; 804 tx_bufmap = &sc->tx_bufmap[tx_idx]; 805 806 /* Create mapping in DMA memory */ 807 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0, 808 segs, &nsegs, BUS_DMA_NOWAIT); 809 if (error == EFBIG) { 810 /* Too many segments! Defrag and try again. */ 811 struct mbuf *m = m_defrag(m0, M_NOWAIT); 812 813 if (m == NULL) { 814 m_freem(m0); 815 return; 816 } 817 m0 = m; 818 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 819 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 820 } 821 if (error != 0) { 822 /* Give up. */ 823 m_freem(m0); 824 return; 825 } 826 827 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 828 BUS_DMASYNC_PREWRITE); 829 tx_bufmap->mbuf = m0; 830 831 /* 832 * Fill in the TX descriptors back to front so that READY bit in first 833 * descriptor is set last. 834 */ 835 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1); 836 sc->tx_idx_head = tx_idx; 837 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC; 838 for (i = nsegs - 1; i >= 0; i--) { 839 struct tsec_desc *tx_desc; 840 841 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1); 842 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 843 tx_desc->length = segs[i].ds_len; 844 tx_desc->bufptr = segs[i].ds_addr; 845 846 if (i == 0) { 847 wmb(); 848 849 if (fcb_flags != 0) 850 flags |= TSEC_TXBD_TOE; 851 } 852 853 /* 854 * Set flags: 855 * - wrap 856 * - checksum 857 * - ready to send 858 * - transmit the CRC sequence after the last data byte 859 * - interrupt after the last buffer 860 */ 861 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ? 862 TSEC_TXBD_W : 0) | flags; 863 864 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I); 865 } 866 867 BPF_MTAP(ifp, m0); 868 *start_tx = 1; 869 } 870 871 static void 872 tsec_setfilter(struct tsec_softc *sc) 873 { 874 if_t ifp; 875 uint32_t flags; 876 877 ifp = sc->tsec_ifp; 878 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 879 880 /* Promiscuous mode */ 881 if (if_getflags(ifp) & IFF_PROMISC) 882 flags |= TSEC_RCTRL_PROM; 883 else 884 flags &= ~TSEC_RCTRL_PROM; 885 886 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 887 } 888 889 #ifdef DEVICE_POLLING 890 static poll_handler_t tsec_poll; 891 892 static int 893 tsec_poll(if_t ifp, enum poll_cmd cmd, int count) 894 { 895 uint32_t ie; 896 struct tsec_softc *sc = if_getsoftc(ifp); 897 int rx_npkts; 898 899 rx_npkts = 0; 900 901 TSEC_GLOBAL_LOCK(sc); 902 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 903 TSEC_GLOBAL_UNLOCK(sc); 904 return (rx_npkts); 905 } 906 907 if (cmd == POLL_AND_CHECK_STATUS) { 908 tsec_error_intr_locked(sc, count); 909 910 /* Clear all events reported */ 911 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 912 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 913 } 914 915 tsec_transmit_intr_locked(sc); 916 917 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 918 919 rx_npkts = tsec_receive_intr_locked(sc, count); 920 921 TSEC_RECEIVE_UNLOCK(sc); 922 923 return (rx_npkts); 924 } 925 #endif /* DEVICE_POLLING */ 926 927 static int 928 tsec_ioctl(if_t ifp, u_long command, caddr_t data) 929 { 930 struct tsec_softc *sc = if_getsoftc(ifp); 931 struct ifreq *ifr = (struct ifreq *)data; 932 int mask, error = 0; 933 934 switch (command) { 935 case SIOCSIFMTU: 936 TSEC_GLOBAL_LOCK(sc); 937 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 938 if_setmtu(ifp, ifr->ifr_mtu); 939 else 940 error = EINVAL; 941 TSEC_GLOBAL_UNLOCK(sc); 942 break; 943 case SIOCSIFFLAGS: 944 TSEC_GLOBAL_LOCK(sc); 945 if (if_getflags(ifp) & IFF_UP) { 946 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 947 if ((sc->tsec_if_flags ^ if_getflags(ifp)) & 948 IFF_PROMISC) 949 tsec_setfilter(sc); 950 951 if ((sc->tsec_if_flags ^ if_getflags(ifp)) & 952 IFF_ALLMULTI) 953 tsec_setup_multicast(sc); 954 } else 955 tsec_init_locked(sc); 956 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 957 tsec_stop(sc); 958 959 sc->tsec_if_flags = if_getflags(ifp); 960 TSEC_GLOBAL_UNLOCK(sc); 961 break; 962 case SIOCADDMULTI: 963 case SIOCDELMULTI: 964 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 965 TSEC_GLOBAL_LOCK(sc); 966 tsec_setup_multicast(sc); 967 TSEC_GLOBAL_UNLOCK(sc); 968 } 969 case SIOCGIFMEDIA: 970 case SIOCSIFMEDIA: 971 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 972 command); 973 break; 974 case SIOCSIFCAP: 975 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 976 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 977 TSEC_GLOBAL_LOCK(sc); 978 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 979 if_setcapenablebit(ifp, IFCAP_HWCSUM & ifr->ifr_reqcap, 0); 980 tsec_offload_setup(sc); 981 TSEC_GLOBAL_UNLOCK(sc); 982 } 983 #ifdef DEVICE_POLLING 984 if (mask & IFCAP_POLLING) { 985 if (ifr->ifr_reqcap & IFCAP_POLLING) { 986 error = ether_poll_register(tsec_poll, ifp); 987 if (error) 988 return (error); 989 990 TSEC_GLOBAL_LOCK(sc); 991 /* Disable interrupts */ 992 tsec_intrs_ctl(sc, 0); 993 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 994 TSEC_GLOBAL_UNLOCK(sc); 995 } else { 996 error = ether_poll_deregister(ifp); 997 TSEC_GLOBAL_LOCK(sc); 998 /* Enable interrupts */ 999 tsec_intrs_ctl(sc, 1); 1000 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1001 TSEC_GLOBAL_UNLOCK(sc); 1002 } 1003 } 1004 #endif 1005 break; 1006 1007 default: 1008 error = ether_ioctl(ifp, command, data); 1009 } 1010 1011 /* Flush buffers if not empty */ 1012 if (if_getflags(ifp) & IFF_UP) 1013 tsec_start(ifp); 1014 return (error); 1015 } 1016 1017 static int 1018 tsec_ifmedia_upd(if_t ifp) 1019 { 1020 struct tsec_softc *sc = if_getsoftc(ifp); 1021 struct mii_data *mii; 1022 1023 TSEC_TRANSMIT_LOCK(sc); 1024 1025 mii = sc->tsec_mii; 1026 mii_mediachg(mii); 1027 1028 TSEC_TRANSMIT_UNLOCK(sc); 1029 return (0); 1030 } 1031 1032 static void 1033 tsec_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1034 { 1035 struct tsec_softc *sc = if_getsoftc(ifp); 1036 struct mii_data *mii; 1037 1038 TSEC_TRANSMIT_LOCK(sc); 1039 1040 mii = sc->tsec_mii; 1041 mii_pollstat(mii); 1042 1043 ifmr->ifm_active = mii->mii_media_active; 1044 ifmr->ifm_status = mii->mii_media_status; 1045 1046 TSEC_TRANSMIT_UNLOCK(sc); 1047 } 1048 1049 static int 1050 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1051 uint32_t *paddr) 1052 { 1053 struct mbuf *new_mbuf; 1054 bus_dma_segment_t seg[1]; 1055 int error, nsegs; 1056 1057 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1058 1059 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1060 if (new_mbuf == NULL) 1061 return (ENOBUFS); 1062 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1063 1064 if (*mbufp) { 1065 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1066 bus_dmamap_unload(tag, map); 1067 } 1068 1069 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1070 BUS_DMA_NOWAIT); 1071 KASSERT(nsegs == 1, ("Too many segments returned!")); 1072 if (nsegs != 1 || error) 1073 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1074 1075 #if 0 1076 if (error) { 1077 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1078 error); 1079 m_freem(new_mbuf); 1080 return (ENOBUFS); 1081 } 1082 #endif 1083 1084 #if 0 1085 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1086 ("Wrong alignment of RX buffer!")); 1087 #endif 1088 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1089 1090 (*mbufp) = new_mbuf; 1091 (*paddr) = seg->ds_addr; 1092 return (0); 1093 } 1094 1095 static void 1096 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1097 { 1098 u_int32_t *paddr; 1099 1100 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1101 paddr = arg; 1102 *paddr = segs->ds_addr; 1103 } 1104 1105 static int 1106 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1107 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1108 { 1109 int error; 1110 1111 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1112 error = bus_dma_tag_create(NULL, /* parent */ 1113 PAGE_SIZE, 0, /* alignment, boundary */ 1114 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1115 BUS_SPACE_MAXADDR, /* highaddr */ 1116 NULL, NULL, /* filtfunc, filtfuncarg */ 1117 dsize, 1, /* maxsize, nsegments */ 1118 dsize, 0, /* maxsegsz, flags */ 1119 NULL, NULL, /* lockfunc, lockfuncarg */ 1120 dtag); /* dmat */ 1121 1122 if (error) { 1123 device_printf(dev, "failed to allocate busdma %s tag\n", 1124 dname); 1125 (*vaddr) = NULL; 1126 return (ENXIO); 1127 } 1128 1129 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1130 dmap); 1131 if (error) { 1132 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1133 dname); 1134 bus_dma_tag_destroy(*dtag); 1135 (*vaddr) = NULL; 1136 return (ENXIO); 1137 } 1138 1139 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1140 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1141 if (error) { 1142 device_printf(dev, "cannot get address of the %s " 1143 "descriptors\n", dname); 1144 bus_dmamem_free(*dtag, *vaddr, *dmap); 1145 bus_dma_tag_destroy(*dtag); 1146 (*vaddr) = NULL; 1147 return (ENXIO); 1148 } 1149 1150 return (0); 1151 } 1152 1153 static void 1154 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1155 { 1156 1157 if (vaddr == NULL) 1158 return; 1159 1160 /* Unmap descriptors from DMA memory */ 1161 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1162 BUS_DMASYNC_POSTWRITE); 1163 bus_dmamap_unload(dtag, dmap); 1164 1165 /* Free descriptors memory */ 1166 bus_dmamem_free(dtag, vaddr, dmap); 1167 1168 /* Destroy descriptors tag */ 1169 bus_dma_tag_destroy(dtag); 1170 } 1171 1172 static void 1173 tsec_free_dma(struct tsec_softc *sc) 1174 { 1175 int i; 1176 1177 /* Free TX maps */ 1178 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1179 if (sc->tx_bufmap[i].map_initialized) 1180 bus_dmamap_destroy(sc->tsec_tx_mtag, 1181 sc->tx_bufmap[i].map); 1182 /* Destroy tag for TX mbufs */ 1183 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1184 1185 /* Free RX mbufs and maps */ 1186 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1187 if (sc->rx_data[i].mbuf) { 1188 /* Unload buffer from DMA */ 1189 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1190 BUS_DMASYNC_POSTREAD); 1191 bus_dmamap_unload(sc->tsec_rx_mtag, 1192 sc->rx_data[i].map); 1193 1194 /* Free buffer */ 1195 m_freem(sc->rx_data[i].mbuf); 1196 } 1197 /* Destroy map for this buffer */ 1198 if (sc->rx_data[i].map != NULL) 1199 bus_dmamap_destroy(sc->tsec_rx_mtag, 1200 sc->rx_data[i].map); 1201 } 1202 /* Destroy tag for RX mbufs */ 1203 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1204 1205 /* Unload TX/RX descriptors */ 1206 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1207 sc->tsec_tx_vaddr); 1208 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1209 sc->tsec_rx_vaddr); 1210 } 1211 1212 static void 1213 tsec_stop(struct tsec_softc *sc) 1214 { 1215 if_t ifp; 1216 uint32_t tmpval; 1217 1218 TSEC_GLOBAL_LOCK_ASSERT(sc); 1219 1220 ifp = sc->tsec_ifp; 1221 1222 /* Disable interface and watchdog timer */ 1223 callout_stop(&sc->tsec_callout); 1224 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1225 sc->tsec_watchdog = 0; 1226 1227 /* Disable all interrupts and stop DMA */ 1228 tsec_intrs_ctl(sc, 0); 1229 tsec_dma_ctl(sc, 0); 1230 1231 /* Remove pending data from TX queue */ 1232 while (sc->tx_idx_tail != sc->tx_idx_head) { 1233 bus_dmamap_sync(sc->tsec_tx_mtag, 1234 sc->tx_bufmap[sc->tx_idx_tail].map, 1235 BUS_DMASYNC_POSTWRITE); 1236 bus_dmamap_unload(sc->tsec_tx_mtag, 1237 sc->tx_bufmap[sc->tx_idx_tail].map); 1238 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf); 1239 sc->tx_idx_tail = (sc->tx_idx_tail + 1) 1240 & (TSEC_TX_NUM_DESC - 1); 1241 } 1242 1243 /* Disable RX and TX */ 1244 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1245 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1246 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1247 DELAY(10); 1248 } 1249 1250 static void 1251 tsec_tick(void *arg) 1252 { 1253 struct tsec_softc *sc = arg; 1254 if_t ifp; 1255 int link; 1256 1257 TSEC_GLOBAL_LOCK(sc); 1258 1259 tsec_watchdog(sc); 1260 1261 ifp = sc->tsec_ifp; 1262 link = sc->tsec_link; 1263 1264 mii_tick(sc->tsec_mii); 1265 1266 if (link == 0 && sc->tsec_link == 1 && 1267 (!if_sendq_empty(ifp))) 1268 tsec_start_locked(ifp); 1269 1270 /* Schedule another timeout one second from now. */ 1271 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1272 1273 TSEC_GLOBAL_UNLOCK(sc); 1274 } 1275 1276 /* 1277 * This is the core RX routine. It replenishes mbufs in the descriptor and 1278 * sends data which have been dma'ed into host memory to upper layer. 1279 * 1280 * Loops at most count times if count is > 0, or until done if count < 0. 1281 */ 1282 static int 1283 tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1284 { 1285 struct tsec_desc *rx_desc; 1286 if_t ifp; 1287 struct rx_data_type *rx_data; 1288 struct mbuf *m; 1289 uint32_t i; 1290 int c, rx_npkts; 1291 uint16_t flags; 1292 1293 TSEC_RECEIVE_LOCK_ASSERT(sc); 1294 1295 ifp = sc->tsec_ifp; 1296 rx_data = sc->rx_data; 1297 rx_npkts = 0; 1298 1299 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1301 1302 for (c = 0; ; c++) { 1303 if (count >= 0 && count-- == 0) 1304 break; 1305 1306 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1307 flags = rx_desc->flags; 1308 1309 /* Check if there is anything to receive */ 1310 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1311 /* 1312 * Avoid generating another interrupt 1313 */ 1314 if (flags & TSEC_RXBD_E) 1315 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1316 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1317 /* 1318 * We didn't consume current descriptor and have to 1319 * return it to the queue 1320 */ 1321 TSEC_BACK_CUR_RX_DESC(sc); 1322 break; 1323 } 1324 1325 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1326 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1327 rx_desc->length = 0; 1328 rx_desc->flags = (rx_desc->flags & 1329 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1330 1331 if (sc->frame != NULL) { 1332 m_free(sc->frame); 1333 sc->frame = NULL; 1334 } 1335 1336 continue; 1337 } 1338 1339 /* Ok... process frame */ 1340 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1341 m = rx_data[i].mbuf; 1342 m->m_len = rx_desc->length; 1343 1344 if (sc->frame != NULL) { 1345 if ((flags & TSEC_RXBD_L) != 0) 1346 m->m_len -= m_length(sc->frame, NULL); 1347 1348 m->m_flags &= ~M_PKTHDR; 1349 m_cat(sc->frame, m); 1350 } else { 1351 sc->frame = m; 1352 } 1353 1354 m = NULL; 1355 1356 if ((flags & TSEC_RXBD_L) != 0) { 1357 m = sc->frame; 1358 sc->frame = NULL; 1359 } 1360 1361 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1362 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1363 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1364 /* 1365 * We ran out of mbufs; didn't consume current 1366 * descriptor and have to return it to the queue. 1367 */ 1368 TSEC_BACK_CUR_RX_DESC(sc); 1369 break; 1370 } 1371 1372 /* Attach new buffer to descriptor and clear flags */ 1373 rx_desc->bufptr = rx_data[i].paddr; 1374 rx_desc->length = 0; 1375 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1376 TSEC_RXBD_E | TSEC_RXBD_I; 1377 1378 if (m != NULL) { 1379 m->m_pkthdr.rcvif = ifp; 1380 1381 m_fixhdr(m); 1382 m_adj(m, -ETHER_CRC_LEN); 1383 1384 if (sc->is_etsec) 1385 tsec_offload_process_frame(sc, m); 1386 1387 TSEC_RECEIVE_UNLOCK(sc); 1388 if_input(ifp, m); 1389 TSEC_RECEIVE_LOCK(sc); 1390 rx_npkts++; 1391 } 1392 } 1393 1394 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 1397 /* 1398 * Make sure TSEC receiver is not halted. 1399 * 1400 * Various conditions can stop the TSEC receiver, but not all are 1401 * signaled and handled by error interrupt, so make sure the receiver 1402 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1403 * halted, and is harmless if already running. 1404 */ 1405 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1406 return (rx_npkts); 1407 } 1408 1409 void 1410 tsec_receive_intr(void *arg) 1411 { 1412 struct tsec_softc *sc = arg; 1413 1414 TSEC_RECEIVE_LOCK(sc); 1415 1416 #ifdef DEVICE_POLLING 1417 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) { 1418 TSEC_RECEIVE_UNLOCK(sc); 1419 return; 1420 } 1421 #endif 1422 1423 /* Confirm the interrupt was received by driver */ 1424 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1425 tsec_receive_intr_locked(sc, -1); 1426 1427 TSEC_RECEIVE_UNLOCK(sc); 1428 } 1429 1430 static void 1431 tsec_transmit_intr_locked(struct tsec_softc *sc) 1432 { 1433 if_t ifp; 1434 uint32_t tx_idx; 1435 1436 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1437 1438 ifp = sc->tsec_ifp; 1439 1440 /* Update collision statistics */ 1441 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL)); 1442 1443 /* Reset collision counters in hardware */ 1444 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1445 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1446 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1447 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1448 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1449 1450 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1451 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1452 1453 tx_idx = sc->tx_idx_tail; 1454 while (tx_idx != sc->tx_idx_head) { 1455 struct tsec_desc *tx_desc; 1456 struct tsec_bufmap *tx_bufmap; 1457 1458 tx_desc = &sc->tsec_tx_vaddr[tx_idx]; 1459 if (tx_desc->flags & TSEC_TXBD_R) { 1460 break; 1461 } 1462 1463 tx_bufmap = &sc->tx_bufmap[tx_idx]; 1464 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1); 1465 if (tx_bufmap->mbuf == NULL) 1466 continue; 1467 1468 /* 1469 * This is the last buf in this packet, so unmap and free it. 1470 */ 1471 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map, 1472 BUS_DMASYNC_POSTWRITE); 1473 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map); 1474 m_freem(tx_bufmap->mbuf); 1475 tx_bufmap->mbuf = NULL; 1476 1477 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1478 } 1479 sc->tx_idx_tail = tx_idx; 1480 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1481 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1482 1483 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1484 tsec_start_locked(ifp); 1485 1486 if (sc->tx_idx_tail == sc->tx_idx_head) 1487 sc->tsec_watchdog = 0; 1488 } 1489 1490 void 1491 tsec_transmit_intr(void *arg) 1492 { 1493 struct tsec_softc *sc = arg; 1494 1495 TSEC_TRANSMIT_LOCK(sc); 1496 1497 #ifdef DEVICE_POLLING 1498 if (if_getcapenable(sc->tsec_ifp) & IFCAP_POLLING) { 1499 TSEC_TRANSMIT_UNLOCK(sc); 1500 return; 1501 } 1502 #endif 1503 /* Confirm the interrupt was received by driver */ 1504 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1505 tsec_transmit_intr_locked(sc); 1506 1507 TSEC_TRANSMIT_UNLOCK(sc); 1508 } 1509 1510 static void 1511 tsec_error_intr_locked(struct tsec_softc *sc, int count) 1512 { 1513 if_t ifp; 1514 uint32_t eflags; 1515 1516 TSEC_GLOBAL_LOCK_ASSERT(sc); 1517 1518 ifp = sc->tsec_ifp; 1519 1520 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1521 1522 /* Clear events bits in hardware */ 1523 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1524 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1525 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1526 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1527 1528 /* Check transmitter errors */ 1529 if (eflags & TSEC_IEVENT_TXE) { 1530 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1531 1532 if (eflags & TSEC_IEVENT_LC) 1533 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1534 1535 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1536 } 1537 1538 /* Check for discarded frame due to a lack of buffers */ 1539 if (eflags & TSEC_IEVENT_BSY) { 1540 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1541 } 1542 1543 if (if_getflags(ifp) & IFF_DEBUG) 1544 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1545 eflags); 1546 1547 if (eflags & TSEC_IEVENT_EBERR) { 1548 if_printf(ifp, "System bus error occurred during" 1549 "DMA transaction (flags: 0x%x)\n", eflags); 1550 tsec_init_locked(sc); 1551 } 1552 1553 if (eflags & TSEC_IEVENT_BABT) 1554 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1555 1556 if (eflags & TSEC_IEVENT_BABR) 1557 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1558 } 1559 1560 void 1561 tsec_error_intr(void *arg) 1562 { 1563 struct tsec_softc *sc = arg; 1564 1565 TSEC_GLOBAL_LOCK(sc); 1566 tsec_error_intr_locked(sc, -1); 1567 TSEC_GLOBAL_UNLOCK(sc); 1568 } 1569 1570 int 1571 tsec_miibus_readreg(device_t dev, int phy, int reg) 1572 { 1573 struct tsec_softc *sc; 1574 int timeout; 1575 int rv; 1576 1577 sc = device_get_softc(dev); 1578 1579 TSEC_PHY_LOCK(); 1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1581 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1582 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1583 1584 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY); 1585 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT); 1586 TSEC_PHY_UNLOCK(); 1587 1588 if (timeout) 1589 device_printf(dev, "Timeout while reading from PHY!\n"); 1590 1591 return (rv); 1592 } 1593 1594 int 1595 tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1596 { 1597 struct tsec_softc *sc; 1598 int timeout; 1599 1600 sc = device_get_softc(dev); 1601 1602 TSEC_PHY_LOCK(); 1603 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1604 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value); 1605 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY); 1606 TSEC_PHY_UNLOCK(); 1607 1608 if (timeout) 1609 device_printf(dev, "Timeout while writing to PHY!\n"); 1610 1611 return (0); 1612 } 1613 1614 void 1615 tsec_miibus_statchg(device_t dev) 1616 { 1617 struct tsec_softc *sc; 1618 struct mii_data *mii; 1619 uint32_t ecntrl, id, tmp; 1620 int link; 1621 1622 sc = device_get_softc(dev); 1623 mii = sc->tsec_mii; 1624 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1625 1626 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1627 1628 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1629 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1630 else 1631 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1632 1633 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1634 case IFM_1000_T: 1635 case IFM_1000_SX: 1636 tmp |= TSEC_MACCFG2_GMII; 1637 sc->tsec_link = link; 1638 break; 1639 case IFM_100_TX: 1640 case IFM_10_T: 1641 tmp |= TSEC_MACCFG2_MII; 1642 sc->tsec_link = link; 1643 break; 1644 case IFM_NONE: 1645 if (link) 1646 device_printf(dev, "No speed selected but link " 1647 "active!\n"); 1648 sc->tsec_link = 0; 1649 return; 1650 default: 1651 sc->tsec_link = 0; 1652 device_printf(dev, "Unknown speed (%d), link %s!\n", 1653 IFM_SUBTYPE(mii->mii_media_active), 1654 ((link) ? "up" : "down")); 1655 return; 1656 } 1657 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1658 1659 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1660 id = TSEC_READ(sc, TSEC_REG_ID2); 1661 if (id & 0xffff) { 1662 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1663 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1664 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1665 } 1666 } 1667 1668 static void 1669 tsec_add_sysctls(struct tsec_softc *sc) 1670 { 1671 struct sysctl_ctx_list *ctx; 1672 struct sysctl_oid_list *children; 1673 struct sysctl_oid *tree; 1674 1675 ctx = device_get_sysctl_ctx(sc->dev); 1676 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1677 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1678 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing"); 1679 children = SYSCTL_CHILDREN(tree); 1680 1681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1682 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1683 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)"); 1684 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1685 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX, 1686 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)"); 1687 1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1689 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1690 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)"); 1691 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1692 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX, 1693 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)"); 1694 } 1695 1696 /* 1697 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1698 * interrupt is raised either upon: 1699 * 1700 * - threshold-defined period of time elapsed, or 1701 * - threshold-defined number of frames is received/transmitted, 1702 * whichever occurs first. 1703 * 1704 * The following sysctls regulate IC behaviour (for TX/RX separately): 1705 * 1706 * dev.tsec.<unit>.int_coal.rx_time 1707 * dev.tsec.<unit>.int_coal.rx_count 1708 * dev.tsec.<unit>.int_coal.tx_time 1709 * dev.tsec.<unit>.int_coal.tx_count 1710 * 1711 * Values: 1712 * 1713 * - 0 for either time or count disables IC on the given TX/RX path 1714 * 1715 * - count: 1-255 (expresses frame count number; note that value of 1 is 1716 * effectively IC off) 1717 * 1718 * - time: 1-65535 (value corresponds to a real time period and is 1719 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1720 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1721 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1722 * TSEC reference manual. 1723 */ 1724 static int 1725 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1726 { 1727 int error; 1728 uint32_t time; 1729 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1730 1731 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1732 1733 error = sysctl_handle_int(oidp, &time, 0, req); 1734 if (error != 0) 1735 return (error); 1736 1737 if (time > 65535) 1738 return (EINVAL); 1739 1740 TSEC_IC_LOCK(sc); 1741 if (arg2 == TSEC_IC_RX) { 1742 sc->rx_ic_time = time; 1743 tsec_set_rxic(sc); 1744 } else { 1745 sc->tx_ic_time = time; 1746 tsec_set_txic(sc); 1747 } 1748 TSEC_IC_UNLOCK(sc); 1749 1750 return (0); 1751 } 1752 1753 static int 1754 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1755 { 1756 int error; 1757 uint32_t count; 1758 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1759 1760 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1761 1762 error = sysctl_handle_int(oidp, &count, 0, req); 1763 if (error != 0) 1764 return (error); 1765 1766 if (count > 255) 1767 return (EINVAL); 1768 1769 TSEC_IC_LOCK(sc); 1770 if (arg2 == TSEC_IC_RX) { 1771 sc->rx_ic_count = count; 1772 tsec_set_rxic(sc); 1773 } else { 1774 sc->tx_ic_count = count; 1775 tsec_set_txic(sc); 1776 } 1777 TSEC_IC_UNLOCK(sc); 1778 1779 return (0); 1780 } 1781 1782 static void 1783 tsec_set_rxic(struct tsec_softc *sc) 1784 { 1785 uint32_t rxic_val; 1786 1787 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1788 /* Disable RX IC */ 1789 rxic_val = 0; 1790 else { 1791 rxic_val = 0x80000000; 1792 rxic_val |= (sc->rx_ic_count << 21); 1793 rxic_val |= sc->rx_ic_time; 1794 } 1795 1796 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1797 } 1798 1799 static void 1800 tsec_set_txic(struct tsec_softc *sc) 1801 { 1802 uint32_t txic_val; 1803 1804 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1805 /* Disable TX IC */ 1806 txic_val = 0; 1807 else { 1808 txic_val = 0x80000000; 1809 txic_val |= (sc->tx_ic_count << 21); 1810 txic_val |= sc->tx_ic_time; 1811 } 1812 1813 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1814 } 1815 1816 static void 1817 tsec_offload_setup(struct tsec_softc *sc) 1818 { 1819 if_t ifp = sc->tsec_ifp; 1820 uint32_t reg; 1821 1822 TSEC_GLOBAL_LOCK_ASSERT(sc); 1823 1824 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1825 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1826 1827 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 1828 if_sethwassist(ifp, TSEC_CHECKSUM_FEATURES); 1829 else 1830 if_sethwassist(ifp, 0); 1831 1832 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1833 1834 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1835 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1836 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1837 1838 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 1839 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1840 TSEC_RCTRL_PRSDEP_PARSE_L234; 1841 1842 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1843 } 1844 1845 static void 1846 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1847 { 1848 struct tsec_rx_fcb rx_fcb; 1849 int csum_flags = 0; 1850 int protocol, flags; 1851 1852 TSEC_RECEIVE_LOCK_ASSERT(sc); 1853 1854 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1855 flags = rx_fcb.flags; 1856 protocol = rx_fcb.protocol; 1857 1858 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1859 csum_flags |= CSUM_IP_CHECKED; 1860 1861 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1862 csum_flags |= CSUM_IP_VALID; 1863 } 1864 1865 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1866 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1867 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1868 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1869 m->m_pkthdr.csum_data = 0xFFFF; 1870 } 1871 1872 m->m_pkthdr.csum_flags = csum_flags; 1873 1874 if (flags & TSEC_RX_FCB_VLAN) { 1875 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1876 m->m_flags |= M_VLANTAG; 1877 } 1878 1879 m_adj(m, sizeof(struct tsec_rx_fcb)); 1880 } 1881 1882 static u_int 1883 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1884 { 1885 uint32_t h, *hashtable = arg; 1886 1887 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF; 1888 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1889 1890 return (1); 1891 } 1892 1893 static void 1894 tsec_setup_multicast(struct tsec_softc *sc) 1895 { 1896 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1897 if_t ifp = sc->tsec_ifp; 1898 int i; 1899 1900 TSEC_GLOBAL_LOCK_ASSERT(sc); 1901 1902 if (if_getflags(ifp) & IFF_ALLMULTI) { 1903 for (i = 0; i < 8; i++) 1904 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1905 1906 return; 1907 } 1908 1909 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable); 1910 1911 for (i = 0; i < 8; i++) 1912 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1913 } 1914 1915 static int 1916 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1917 { 1918 1919 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1920 1921 TSEC_GLOBAL_LOCK_ASSERT(sc); 1922 1923 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1924 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1925 return (mtu); 1926 } 1927 1928 return (0); 1929 } 1930