1 /*- 2 * Copyright (c) 2018 Stormshield. 3 * Copyright (c) 2018 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "tpm20.h" 32 33 /* 34 * CRB register space as defined in 35 * TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22 36 */ 37 #define TPM_LOC_STATE 0x0 38 #define TPM_LOC_CTRL 0x8 39 #define TPM_LOC_STS 0xC 40 #define TPM_CRB_INTF_ID 0x30 41 #define TPM_CRB_CTRL_EXT 0x38 42 #define TPM_CRB_CTRL_REQ 0x40 43 #define TPM_CRB_CTRL_STS 0x44 44 #define TPM_CRB_CTRL_CANCEL 0x48 45 #define TPM_CRB_CTRL_START 0x4C 46 #define TPM_CRB_INT_ENABLE 0x50 47 #define TPM_CRB_INT_STS 0x54 48 #define TPM_CRB_CTRL_CMD_SIZE 0x58 49 #define TPM_CRB_CTRL_CMD_LADDR 0x5C 50 #define TPM_CRB_CTRL_CMD_HADDR 0x60 51 #define TPM_CRB_CTRL_RSP_SIZE 0x64 52 #define TPM_CRB_CTRL_RSP_ADDR 0x68 53 #define TPM_CRB_CTRL_RSP_HADDR 0x6c 54 #define TPM_CRB_DATA_BUFFER 0x80 55 56 #define TPM_LOC_STATE_ESTB BIT(0) 57 #define TPM_LOC_STATE_ASSIGNED BIT(1) 58 #define TPM_LOC_STATE_ACTIVE_MASK 0x9C 59 #define TPM_LOC_STATE_VALID BIT(7) 60 61 #define TPM_CRB_INTF_ID_TYPE_CRB 0x1 62 #define TPM_CRB_INTF_ID_TYPE 0x7 63 64 #define TPM_LOC_CTRL_REQUEST BIT(0) 65 #define TPM_LOC_CTRL_RELINQUISH BIT(1) 66 67 #define TPM_CRB_CTRL_REQ_GO_READY BIT(0) 68 #define TPM_CRB_CTRL_REQ_GO_IDLE BIT(1) 69 70 #define TPM_CRB_CTRL_STS_ERR_BIT BIT(0) 71 #define TPM_CRB_CTRL_STS_IDLE_BIT BIT(1) 72 73 #define TPM_CRB_CTRL_CANCEL_CMD BIT(0) 74 75 #define TPM_CRB_CTRL_START_CMD BIT(0) 76 77 #define TPM_CRB_INT_ENABLE_BIT BIT(31) 78 79 struct tpmcrb_sc { 80 struct tpm_sc base; 81 bus_size_t cmd_off; 82 bus_size_t rsp_off; 83 size_t cmd_buf_size; 84 size_t rsp_buf_size; 85 }; 86 87 88 int tpmcrb_transmit(struct tpm_sc *sc, size_t size); 89 90 static int tpmcrb_acpi_probe(device_t dev); 91 static int tpmcrb_attach(device_t dev); 92 static int tpmcrb_detach(device_t dev); 93 94 static ACPI_STATUS tpmcrb_fix_buff_offsets(ACPI_RESOURCE *res, void *arg); 95 96 static bool tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off, 97 uint32_t mask, uint32_t val, int32_t timeout); 98 static bool tpmcrb_request_locality(struct tpm_sc *sc, int locality); 99 static void tpmcrb_relinquish_locality(struct tpm_sc *sc); 100 static bool tpmcrb_cancel_cmd(struct tpm_sc *sc); 101 102 char *tpmcrb_ids[] = {"MSFT0101", NULL}; 103 104 static int 105 tpmcrb_acpi_probe(device_t dev) 106 { 107 int err; 108 ACPI_TABLE_TPM23 *tbl; 109 ACPI_STATUS status; 110 err = ACPI_ID_PROBE(device_get_parent(dev), dev, tpmcrb_ids, NULL); 111 if (err > 0) 112 return (err); 113 /*Find TPM2 Header*/ 114 status = AcpiGetTable(ACPI_SIG_TPM2, 1, (ACPI_TABLE_HEADER **) &tbl); 115 if(ACPI_FAILURE(status) || 116 tbl->StartMethod != TPM2_START_METHOD_CRB) 117 err = ENXIO; 118 119 device_set_desc(dev, "Trusted Platform Module 2.0, CRB mode"); 120 return (err); 121 } 122 123 static ACPI_STATUS 124 tpmcrb_fix_buff_offsets(ACPI_RESOURCE *res, void *arg) 125 { 126 struct tpmcrb_sc *crb_sc; 127 size_t length; 128 uint32_t base_addr; 129 130 crb_sc = (struct tpmcrb_sc *)arg; 131 132 if (res->Type != ACPI_RESOURCE_TYPE_FIXED_MEMORY32) 133 return (AE_OK); 134 135 base_addr = res->Data.FixedMemory32.Address; 136 length = res->Data.FixedMemory32.AddressLength; 137 138 if (crb_sc->cmd_off > base_addr && crb_sc->cmd_off < base_addr + length) 139 crb_sc->cmd_off -= base_addr; 140 if (crb_sc->rsp_off > base_addr && crb_sc->rsp_off < base_addr + length) 141 crb_sc->rsp_off -= base_addr; 142 143 return (AE_OK); 144 } 145 146 static int 147 tpmcrb_attach(device_t dev) 148 { 149 struct tpmcrb_sc *crb_sc; 150 struct tpm_sc *sc; 151 ACPI_HANDLE handle; 152 ACPI_STATUS status; 153 int result; 154 155 crb_sc = device_get_softc(dev); 156 sc = &crb_sc->base; 157 handle = acpi_get_handle(dev); 158 159 sc->dev = dev; 160 161 sc->mem_rid = 0; 162 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 163 RF_ACTIVE); 164 if (sc->mem_res == NULL) 165 return (ENXIO); 166 167 if(!tpmcrb_request_locality(sc, 0)) { 168 tpmcrb_detach(dev); 169 return (ENXIO); 170 } 171 172 /* 173 * Disable all interrupts for now, since I don't have a device that 174 * works in CRB mode and supports them. 175 */ 176 AND4(sc, TPM_CRB_INT_ENABLE, ~TPM_CRB_INT_ENABLE_BIT); 177 sc->interrupts = false; 178 179 /* 180 * Read addresses of Tx/Rx buffers and their sizes. Note that they 181 * can be implemented by a single buffer. Also for some reason CMD 182 * addr is stored in two 4 byte neighboring registers, whereas RSP is 183 * stored in a single 8 byte one. 184 */ 185 #ifdef __amd64__ 186 crb_sc->rsp_off = RD8(sc, TPM_CRB_CTRL_RSP_ADDR); 187 #else 188 crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR); 189 crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32); 190 #endif 191 crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR); 192 crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32); 193 crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE); 194 crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE); 195 196 tpmcrb_relinquish_locality(sc); 197 198 /* Emulator returns address in acpi space instead of an offset */ 199 status = AcpiWalkResources(handle, "_CRS", tpmcrb_fix_buff_offsets, 200 (void *)crb_sc); 201 if (ACPI_FAILURE(status)) { 202 tpmcrb_detach(dev); 203 return (ENXIO); 204 } 205 206 if (crb_sc->rsp_off == crb_sc->cmd_off) { 207 /* 208 * If Tx/Rx buffers are implemented as one they have to be of 209 * same size 210 */ 211 if (crb_sc->cmd_buf_size != crb_sc->rsp_buf_size) { 212 device_printf(sc->dev, 213 "Overlapping Tx/Rx buffers have different sizes\n"); 214 tpmcrb_detach(dev); 215 return (ENXIO); 216 } 217 } 218 219 sc->transmit = tpmcrb_transmit; 220 221 result = tpm20_init(sc); 222 if (result != 0) 223 tpmcrb_detach(dev); 224 225 return (result); 226 } 227 228 static int 229 tpmcrb_detach(device_t dev) 230 { 231 struct tpm_sc *sc; 232 233 sc = device_get_softc(dev); 234 235 if (sc->mem_res != NULL) 236 bus_release_resource(dev, SYS_RES_MEMORY, 237 sc->mem_rid, sc->mem_res); 238 239 tpm20_release(sc); 240 return (0); 241 } 242 243 static bool 244 tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off, uint32_t mask, uint32_t val, 245 int32_t timeout) 246 { 247 248 /* Check for condition */ 249 if ((RD4(sc, off) & mask) == val) 250 return (true); 251 252 while (timeout > 0) { 253 if ((RD4(sc, off) & mask) == val) 254 return (true); 255 256 pause("TPM in polling mode", 1); 257 timeout -= tick; 258 } 259 return (false); 260 } 261 262 static bool 263 tpmcrb_request_locality(struct tpm_sc *sc, int locality) 264 { 265 uint32_t mask; 266 267 /* Currently we only support Locality 0 */ 268 if (locality != 0) 269 return (false); 270 271 mask = TPM_LOC_STATE_VALID | TPM_LOC_STATE_ASSIGNED; 272 273 OR4(sc, TPM_LOC_CTRL, TPM_LOC_CTRL_REQUEST); 274 if (!tpm_wait_for_u32(sc, TPM_LOC_STATE, mask, mask, TPM_TIMEOUT_C)) 275 return (false); 276 277 return (true); 278 } 279 280 static void 281 tpmcrb_relinquish_locality(struct tpm_sc *sc) 282 { 283 284 OR4(sc, TPM_LOC_CTRL, TPM_LOC_CTRL_RELINQUISH); 285 } 286 287 static bool 288 tpmcrb_cancel_cmd(struct tpm_sc *sc) 289 { 290 uint32_t mask = ~0; 291 292 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD); 293 if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_START, 294 mask, ~mask, TPM_TIMEOUT_B)) { 295 device_printf(sc->dev, 296 "Device failed to cancel command\n"); 297 return (false); 298 } 299 300 WR4(sc, TPM_CRB_CTRL_CANCEL, !TPM_CRB_CTRL_CANCEL_CMD); 301 return (true); 302 } 303 304 int 305 tpmcrb_transmit(struct tpm_sc *sc, size_t length) 306 { 307 struct tpmcrb_sc *crb_sc; 308 uint32_t mask, curr_cmd; 309 int timeout, bytes_available; 310 311 crb_sc = (struct tpmcrb_sc *)sc; 312 313 sx_assert(&sc->dev_lock, SA_XLOCKED); 314 315 if (length > crb_sc->cmd_buf_size) { 316 device_printf(sc->dev, 317 "Requested transfer is bigger than buffer size\n"); 318 return (E2BIG); 319 } 320 321 if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) { 322 device_printf(sc->dev, 323 "Device has Error bit set\n"); 324 return (EIO); 325 } 326 if (!tpmcrb_request_locality(sc, 0)) { 327 device_printf(sc->dev, 328 "Failed to obtain locality\n"); 329 return (EIO); 330 } 331 /* Clear cancellation bit */ 332 WR4(sc, TPM_CRB_CTRL_CANCEL, !TPM_CRB_CTRL_CANCEL_CMD); 333 334 /* Switch device to idle state if necessary */ 335 if (!(RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_IDLE_BIT)) { 336 OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_IDLE); 337 338 mask = TPM_CRB_CTRL_STS_IDLE_BIT; 339 if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS, 340 mask, mask, TPM_TIMEOUT_C)) { 341 device_printf(sc->dev, 342 "Failed to transition to idle state\n"); 343 return (EIO); 344 } 345 } 346 /* Switch to ready state */ 347 OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_READY); 348 349 mask = TPM_CRB_CTRL_REQ_GO_READY; 350 if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_STS, 351 mask, !mask, TPM_TIMEOUT_C)) { 352 device_printf(sc->dev, 353 "Failed to transition to ready state\n"); 354 return (EIO); 355 } 356 357 /* 358 * Calculate timeout for current command. 359 * Command code is passed in bytes 6-10. 360 */ 361 curr_cmd = be32toh(*(uint32_t *) (&sc->buf[6])); 362 timeout = tpm20_get_timeout(curr_cmd); 363 364 /* Send command and tell device to process it. */ 365 bus_write_region_stream_1(sc->mem_res, crb_sc->cmd_off, 366 sc->buf, length); 367 bus_barrier(sc->mem_res, crb_sc->cmd_off, 368 length, BUS_SPACE_BARRIER_WRITE); 369 370 WR4(sc, TPM_CRB_CTRL_START, TPM_CRB_CTRL_START_CMD); 371 bus_barrier(sc->mem_res, TPM_CRB_CTRL_START, 372 4, BUS_SPACE_BARRIER_WRITE); 373 374 mask = ~0; 375 if (!tpm_wait_for_u32(sc, TPM_CRB_CTRL_START, mask, ~mask, timeout)) { 376 device_printf(sc->dev, 377 "Timeout while waiting for device to process cmd\n"); 378 if (!tpmcrb_cancel_cmd(sc)) 379 return (EIO); 380 } 381 382 /* Read response header. Length is passed in bytes 2 - 6. */ 383 bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off, 384 sc->buf, TPM_HEADER_SIZE); 385 bytes_available = be32toh(*(uint32_t *) (&sc->buf[2])); 386 387 if (bytes_available > TPM_BUFSIZE || bytes_available < TPM_HEADER_SIZE) { 388 device_printf(sc->dev, 389 "Incorrect response size: %d\n", 390 bytes_available); 391 return (EIO); 392 } 393 394 bus_read_region_stream_1(sc->mem_res, crb_sc->rsp_off + TPM_HEADER_SIZE, 395 &sc->buf[TPM_HEADER_SIZE], bytes_available - TPM_HEADER_SIZE); 396 397 OR4(sc, TPM_CRB_CTRL_REQ, TPM_CRB_CTRL_REQ_GO_IDLE); 398 399 tpmcrb_relinquish_locality(sc); 400 sc->pending_data_length = bytes_available; 401 402 return (0); 403 } 404 405 /* ACPI Driver */ 406 static device_method_t tpmcrb_methods[] = { 407 DEVMETHOD(device_probe, tpmcrb_acpi_probe), 408 DEVMETHOD(device_attach, tpmcrb_attach), 409 DEVMETHOD(device_detach, tpmcrb_detach), 410 DEVMETHOD(device_shutdown, tpm20_shutdown), 411 DEVMETHOD(device_suspend, tpm20_suspend), 412 {0, 0} 413 }; 414 static driver_t tpmcrb_driver = { 415 "tpmcrb", tpmcrb_methods, sizeof(struct tpmcrb_sc), 416 }; 417 418 devclass_t tpmcrb_devclass; 419 DRIVER_MODULE(tpmcrb, acpi, tpmcrb_driver, tpmcrb_devclass, 0, 0); 420