1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. 41 * The first group of registers are actually copies of the PCI 42 * configuration space registers. 43 */ 44 45 #define TI_PCI_ID 0x000 /* PCI device/vendor ID */ 46 #define TI_PCI_CMDSTAT 0x004 47 #define TI_PCI_CLASSCODE 0x008 48 #define TI_PCI_BIST 0x00C 49 #define TI_PCI_LOMEM 0x010 /* Shared memory base address */ 50 #define TI_PCI_SUBSYS 0x02C 51 #define TI_PCI_ROMBASE 0x030 52 #define TI_PCI_INT 0x03C 53 54 #ifndef PCIM_CMD_MWIEN 55 #define PCIM_CMD_MWIEN 0x0010 56 #endif 57 58 /* 59 * Alteon AceNIC PCI vendor/device ID. 60 */ 61 #define ALT_VENDORID 0x12AE 62 #define ALT_DEVICEID_ACENIC 0x0001 63 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 64 65 /* 66 * 3Com 3c985 PCI vendor/device ID. 67 */ 68 #define TC_VENDORID 0x10B7 69 #define TC_DEVICEID_3C985 0x0001 70 71 /* 72 * Netgear GA620 PCI vendor/device ID. 73 */ 74 #define NG_VENDORID 0x1385 75 #define NG_DEVICEID_GA620 0x620A 76 #define NG_DEVICEID_GA620T 0x630A 77 78 /* 79 * SGI device/vendor ID. 80 */ 81 #define SGI_VENDORID 0x10A9 82 #define SGI_DEVICEID_TIGON 0x0009 83 84 /* 85 * DEC vendor ID, Farallon device ID. Apparently, Farallon used 86 * the DEC vendor ID in their cards by mistake. 87 */ 88 #define DEC_VENDORID 0x1011 89 #define DEC_DEVICEID_FARALLON_PN9000SX 0x001a 90 91 /* 92 * Tigon configuration and control registers. 93 */ 94 #define TI_MISC_HOST_CTL 0x040 95 #define TI_MISC_LOCAL_CTL 0x044 96 #define TI_SEM_AB 0x048 /* Tigon 2 only */ 97 #define TI_MISC_CONF 0x050 /* Tigon 2 only */ 98 #define TI_TIMER_BITS 0x054 99 #define TI_TIMERREF 0x058 100 #define TI_PCI_STATE 0x05C 101 #define TI_MAIN_EVENT_A 0x060 102 #define TI_MAILBOX_EVENT_A 0x064 103 #define TI_WINBASE 0x068 104 #define TI_WINDATA 0x06C 105 #define TI_MAIN_EVENT_B 0x070 /* Tigon 2 only */ 106 #define TI_MAILBOX_EVENT_B 0x074 /* Tigon 2 only */ 107 #define TI_TIMERREF_B 0x078 /* Tigon 2 only */ 108 #define TI_SERIAL 0x07C 109 110 /* 111 * Misc host control bits. 112 */ 113 #define TI_MHC_INTSTATE 0x00000001 114 #define TI_MHC_CLEARINT 0x00000002 115 #define TI_MHC_RESET 0x00000008 116 #define TI_MHC_BYTE_SWAP_ENB 0x00000010 117 #define TI_MHC_WORD_SWAP_ENB 0x00000020 118 #define TI_MHC_MASK_INTS 0x00000040 119 #define TI_MHC_CHIP_REV_MASK 0xF0000000 120 121 #define TI_MHC_BIGENDIAN_INIT \ 122 (TI_MHC_BYTE_SWAP_ENB|TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 123 124 #define TI_MHC_LITTLEENDIAN_INIT \ 125 (TI_MHC_WORD_SWAP_ENB|TI_MHC_CLEARINT) 126 127 /* 128 * Tigon chip rev values. Rev 4 is the Tigon 1. Rev 6 is the Tigon 2. 129 * Rev 5 is also the Tigon 2, but is a broken version which was never 130 * used in any actual hardware, so we ignore it. 131 */ 132 #define TI_REV_TIGON_I 0x40000000 133 #define TI_REV_TIGON_II 0x60000000 134 135 /* 136 * Firmware revision that we want. 137 */ 138 #define TI_FIRMWARE_MAJOR 0xc 139 #define TI_FIRMWARE_MINOR 0x4 140 #define TI_FIRMWARE_FIX 0xd 141 142 /* 143 * Miscelaneous Local Control register. 144 */ 145 #define TI_MLC_EE_WRITE_ENB 0x00000010 146 #define TI_MLC_SRAM_BANK_256K 0x00000200 147 #define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 148 #define TI_MLC_LOCALADDR_21 0x00004000 149 #define TI_MLC_LOCALADDR_22 0x00008000 150 #define TI_MLC_SBUS_WRITEERR 0x00080000 151 #define TI_MLC_EE_CLK 0x00100000 152 #define TI_MLC_EE_TXEN 0x00200000 153 #define TI_MLC_EE_DOUT 0x00400000 154 #define TI_MLC_EE_DIN 0x00800000 155 156 /* 157 * Offset of MAC address inside EEPROM. 158 */ 159 #define TI_EE_MAC_OFFSET 0x8c 160 161 #define TI_DMA_ASSIST 0x11C 162 #define TI_CPU_STATE 0x140 163 #define TI_CPU_PROGRAM_COUNTER 0x144 164 #define TI_SRAM_ADDR 0x154 165 #define TI_SRAM_DATA 0x158 166 #define TI_GEN_0 0x180 167 #define TI_GEN_X 0x1FC 168 #define TI_MAC_TX_STATE 0x200 169 #define TI_MAC_RX_STATE 0x220 170 #define TI_CPU_CTL_B 0x240 /* Tigon 2 only */ 171 #define TI_CPU_PROGRAM_COUNTER_B 0x244 /* Tigon 2 only */ 172 #define TI_SRAM_ADDR_B 0x254 /* Tigon 2 only */ 173 #define TI_SRAM_DATA_B 0x258 /* Tigon 2 only */ 174 #define TI_GEN_B_0 0x280 /* Tigon 2 only */ 175 #define TI_GEN_B_X 0x2FC /* Tigon 2 only */ 176 177 /* 178 * Misc config register. 179 */ 180 #define TI_MCR_SRAM_SYNCHRONOUS 0x00100000 /* Tigon 2 only */ 181 182 /* 183 * PCI state register. 184 */ 185 #define TI_PCISTATE_FORCE_RESET 0x00000001 186 #define TI_PCISTATE_PROVIDE_LEN 0x00000002 187 #define TI_PCISTATE_READ_MAXDMA 0x0000001C 188 #define TI_PCISTATE_WRITE_MAXDMA 0x000000E0 189 #define TI_PCISTATE_MINDMA 0x0000FF00 190 #define TI_PCISTATE_FIFO_RETRY_ENB 0x00010000 191 #define TI_PCISTATE_USE_MEM_RD_MULT 0x00020000 192 #define TI_PCISTATE_NO_SWAP_READ_DMA 0x00040000 193 #define TI_PCISTATE_NO_SWAP_WRITE_DMA 0x00080000 194 #define TI_PCISTATE_66MHZ_BUS 0x00080000 /* Tigon 2 only */ 195 #define TI_PCISTATE_32BIT_BUS 0x00100000 /* Tigon 2 only */ 196 #define TI_PCISTATE_ENB_BYTE_ENABLES 0x00800000 /* Tigon 2 only */ 197 #define TI_PCISTATE_READ_CMD 0x0F000000 198 #define TI_PCISTATE_WRITE_CMD 0xF0000000 199 200 #define TI_PCI_READMAX_4 0x04 201 #define TI_PCI_READMAX_16 0x08 202 #define TI_PCI_READMAX_32 0x0C 203 #define TI_PCI_READMAX_64 0x10 204 #define TI_PCI_READMAX_128 0x14 205 #define TI_PCI_READMAX_256 0x18 206 #define TI_PCI_READMAX_1024 0x1C 207 208 #define TI_PCI_WRITEMAX_4 0x20 209 #define TI_PCI_WRITEMAX_16 0x40 210 #define TI_PCI_WRITEMAX_32 0x60 211 #define TI_PCI_WRITEMAX_64 0x80 212 #define TI_PCI_WRITEMAX_128 0xA0 213 #define TI_PCI_WRITEMAX_256 0xC0 214 #define TI_PCI_WRITEMAX_1024 0xE0 215 216 #define TI_PCI_READ_CMD 0x06000000 217 #define TI_PCI_WRITE_CMD 0x70000000 218 219 /* 220 * DMA state register. 221 */ 222 #define TI_DMASTATE_ENABLE 0x00000001 223 #define TI_DMASTATE_PAUSE 0x00000002 224 225 /* 226 * CPU state register. 227 */ 228 #define TI_CPUSTATE_RESET 0x00000001 229 #define TI_CPUSTATE_STEP 0x00000002 230 #define TI_CPUSTATE_ROMFAIL 0x00000010 231 #define TI_CPUSTATE_HALT 0x00010000 232 /* 233 * MAC TX state register 234 */ 235 #define TI_TXSTATE_RESET 0x00000001 236 #define TI_TXSTATE_ENB 0x00000002 237 #define TI_TXSTATE_STOP 0x00000004 238 239 /* 240 * MAC RX state register 241 */ 242 #define TI_RXSTATE_RESET 0x00000001 243 #define TI_RXSTATE_ENB 0x00000002 244 #define TI_RXSTATE_STOP 0x00000004 245 246 /* 247 * Tigon 2 mailbox registers. The mailbox area consists of 256 bytes 248 * split into 64 bit registers. Only the lower 32 bits of each mailbox 249 * are used. 250 */ 251 #define TI_MB_HOSTINTR_HI 0x500 252 #define TI_MB_HOSTINTR_LO 0x504 253 #define TI_MB_HOSTINTR TI_MB_HOSTINTR_LO 254 #define TI_MB_CMDPROD_IDX_HI 0x508 255 #define TI_MB_CMDPROD_IDX_LO 0x50C 256 #define TI_MB_CMDPROD_IDX TI_MB_CMDPROD_IDX_LO 257 #define TI_MB_SENDPROD_IDX_HI 0x510 258 #define TI_MB_SENDPROD_IDX_LO 0x514 259 #define TI_MB_SENDPROD_IDX TI_MB_SENDPROD_IDX_LO 260 #define TI_MB_STDRXPROD_IDX_HI 0x518 /* Tigon 2 only */ 261 #define TI_MB_STDRXPROD_IDX_LO 0x51C /* Tigon 2 only */ 262 #define TI_MB_STDRXPROD_IDX TI_MB_STDRXPROD_IDX_LO 263 #define TI_MB_JUMBORXPROD_IDX_HI 0x520 /* Tigon 2 only */ 264 #define TI_MB_JUMBORXPROD_IDX_LO 0x524 /* Tigon 2 only */ 265 #define TI_MB_JUMBORXPROD_IDX TI_MB_JUMBORXPROD_IDX_LO 266 #define TI_MB_MINIRXPROD_IDX_HI 0x528 /* Tigon 2 only */ 267 #define TI_MB_MINIRXPROD_IDX_LO 0x52C /* Tigon 2 only */ 268 #define TI_MB_MINIRXPROD_IDX TI_MB_MINIRXPROD_IDX_LO 269 #define TI_MB_RSVD 0x530 270 271 /* 272 * Tigon 2 general communication registers. These are 64 and 32 bit 273 * registers which are only valid after the firmware has been 274 * loaded and started. They actually exist in NIC memory but are 275 * mapped into the host memory via the shared memory region. 276 * 277 * The NIC internally maps these registers starting at address 0, 278 * so to determine the NIC address of any of these registers, we 279 * subtract 0x600 (the address of the first register). 280 */ 281 282 #define TI_GCR_BASE 0x600 283 #define TI_GCR_MACADDR 0x600 284 #define TI_GCR_PAR0 0x600 285 #define TI_GCR_PAR1 0x604 286 #define TI_GCR_GENINFO_HI 0x608 287 #define TI_GCR_GENINFO_LO 0x60C 288 #define TI_GCR_MCASTADDR 0x610 /* obsolete */ 289 #define TI_GCR_MAR0 0x610 /* obsolete */ 290 #define TI_GCR_MAR1 0x614 /* obsolete */ 291 #define TI_GCR_OPMODE 0x618 292 #define TI_GCR_DMA_READCFG 0x61C 293 #define TI_GCR_DMA_WRITECFG 0x620 294 #define TI_GCR_TX_BUFFER_RATIO 0x624 295 #define TI_GCR_EVENTCONS_IDX 0x628 296 #define TI_GCR_CMDCONS_IDX 0x62C 297 #define TI_GCR_TUNEPARMS 0x630 298 #define TI_GCR_RX_COAL_TICKS 0x630 299 #define TI_GCR_TX_COAL_TICKS 0x634 300 #define TI_GCR_STAT_TICKS 0x638 301 #define TI_GCR_TX_MAX_COAL_BD 0x63C 302 #define TI_GCR_RX_MAX_COAL_BD 0x640 303 #define TI_GCR_NIC_TRACING 0x644 304 #define TI_GCR_GLINK 0x648 305 #define TI_GCR_LINK 0x64C 306 #define TI_GCR_NICTRACE_PTR 0x650 307 #define TI_GCR_NICTRACE_START 0x654 308 #define TI_GCR_NICTRACE_LEN 0x658 309 #define TI_GCR_IFINDEX 0x65C 310 #define TI_GCR_IFMTU 0x660 311 #define TI_GCR_MASK_INTRS 0x664 312 #define TI_GCR_GLINK_STAT 0x668 313 #define TI_GCR_LINK_STAT 0x66C 314 #define TI_GCR_RXRETURNCONS_IDX 0x680 315 #define TI_GCR_CMDRING 0x700 316 317 #define TI_GCR_NIC_ADDR(x) (x - TI_GCR_BASE); 318 319 /* 320 * Local memory window. The local memory window is a 2K shared 321 * memory region which can be used to access the NIC's internal 322 * SRAM. The window can be mapped to a given 2K region using 323 * the TI_WINDOW_BASE register. 324 */ 325 #define TI_WINDOW 0x800 326 #define TI_WINLEN 0x800 327 328 #define TI_TICKS_PER_SEC 1000000 329 330 /* 331 * Operation mode register. 332 */ 333 #define TI_OPMODE_BYTESWAP_BD 0x00000002 334 #define TI_OPMODE_WORDSWAP_BD 0x00000004 335 #define TI_OPMODE_WARN_ENB 0x00000008 /* not yet implimented */ 336 #define TI_OPMODE_BYTESWAP_DATA 0x00000010 337 #define TI_OPMODE_1_DMA_ACTIVE 0x00000040 338 #define TI_OPMODE_SBUS 0x00000100 339 #define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 340 #define TI_OPMODE_INCLUDE_CRC 0x00000400 341 #define TI_OPMODE_RX_BADFRAMES 0x00000800 342 #define TI_OPMODE_NO_EVENT_INTRS 0x00001000 343 #define TI_OPMODE_NO_TX_INTRS 0x00002000 344 #define TI_OPMODE_NO_RX_INTRS 0x00004000 345 #define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ 346 347 /* 348 * DMA configuration thresholds. 349 */ 350 #define TI_DMA_STATE_THRESH_16W 0x00000100 351 #define TI_DMA_STATE_THRESH_8W 0x00000080 352 #define TI_DMA_STATE_THRESH_4W 0x00000040 353 #define TI_DMA_STATE_THRESH_2W 0x00000020 354 #define TI_DMA_STATE_THRESH_1W 0x00000010 355 356 #define TI_DMA_STATE_FORCE_32_BIT 0x00000008 357 358 /* 359 * Gigabit link status bits. 360 */ 361 #define TI_GLNK_SENSE_NO_BEG 0x00002000 362 #define TI_GLNK_LOOPBACK 0x00004000 363 #define TI_GLNK_PREF 0x00008000 364 #define TI_GLNK_1000MB 0x00040000 365 #define TI_GLNK_FULL_DUPLEX 0x00080000 366 #define TI_GLNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 367 #define TI_GLNK_RX_FLOWCTL_Y 0x00800000 368 #define TI_GLNK_AUTONEGENB 0x20000000 369 #define TI_GLNK_ENB 0x40000000 370 371 /* 372 * Link status bits. 373 */ 374 #define TI_LNK_LOOPBACK 0x00004000 375 #define TI_LNK_PREF 0x00008000 376 #define TI_LNK_10MB 0x00010000 377 #define TI_LNK_100MB 0x00020000 378 #define TI_LNK_1000MB 0x00040000 379 #define TI_LNK_FULL_DUPLEX 0x00080000 380 #define TI_LNK_HALF_DUPLEX 0x00100000 381 #define TI_LNK_TX_FLOWCTL_Y 0x00200000 /* Tigon 2 only */ 382 #define TI_LNK_RX_FLOWCTL_Y 0x00800000 383 #define TI_LNK_AUTONEGENB 0x20000000 384 #define TI_LNK_ENB 0x40000000 385 386 /* 387 * Ring size constants. 388 */ 389 #define TI_EVENT_RING_CNT 256 390 #define TI_CMD_RING_CNT 64 391 #define TI_STD_RX_RING_CNT 512 392 #define TI_JUMBO_RX_RING_CNT 256 393 #define TI_MINI_RX_RING_CNT 1024 394 #define TI_RETURN_RING_CNT 2048 395 396 /* 397 * Possible TX ring sizes. 398 */ 399 #define TI_TX_RING_CNT_128 128 400 #define TI_TX_RING_BASE_128 0x3800 401 402 #define TI_TX_RING_CNT_256 256 403 #define TI_TX_RING_BASE_256 0x3000 404 405 #define TI_TX_RING_CNT_512 512 406 #define TI_TX_RING_BASE_512 0x2000 407 408 #define TI_TX_RING_CNT TI_TX_RING_CNT_512 409 #define TI_TX_RING_BASE TI_TX_RING_BASE_512 410 411 /* 412 * The Tigon can have up to 8MB of external SRAM, however the Tigon 1 413 * is limited to 2MB total, and in general I think most adapters have 414 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 415 * be safe we use the largest possible value (zeroing memory that 416 * isn't there doesn't hurt anything). 417 */ 418 #define TI_MEM_MAX 0x7FFFFF 419 420 /* 421 * Even on the alpha, pci addresses are 32-bit quantities 422 */ 423 424 #ifdef __64_bit_pci_addressing__ 425 typedef struct { 426 u_int64_t ti_addr; 427 } ti_hostaddr; 428 #define TI_HOSTADDR(x) x.ti_addr 429 #else 430 typedef struct { 431 u_int32_t ti_addr_hi; 432 u_int32_t ti_addr_lo; 433 } ti_hostaddr; 434 #define TI_HOSTADDR(x) x.ti_addr_lo 435 #endif 436 437 /* 438 * Ring control block structure. The rules for the max_len field 439 * are as follows: 440 * 441 * For the send ring, max_len indicates the number of entries in the 442 * ring (128, 256 or 512). 443 * 444 * For the standard receive ring, max_len indicates the threshold 445 * used to decide when a frame should be put in the jumbo receive ring 446 * instead of the standard one. 447 * 448 * For the mini ring, max_len indicates the size of the buffers in the 449 * ring. This is the value used to decide when a frame is small enough 450 * to be placed in the mini ring. 451 * 452 * For the return receive ring, max_len indicates the number of entries 453 * in the ring. It can be one of 2048, 1024 or 0 (which is the same as 454 * 2048 for backwards compatibility). The value 1024 can only be used 455 * if the mini ring is disabled. 456 */ 457 struct ti_rcb { 458 ti_hostaddr ti_hostaddr; 459 #if BYTE_ORDER == BIG_ENDIAN 460 u_int16_t ti_max_len; 461 u_int16_t ti_flags; 462 #else 463 u_int16_t ti_flags; 464 u_int16_t ti_max_len; 465 #endif 466 u_int32_t ti_unused; 467 }; 468 469 #define TI_RCB_FLAG_TCP_UDP_CKSUM 0x00000001 470 #define TI_RCB_FLAG_IP_CKSUM 0x00000002 471 #define TI_RCB_FLAG_NO_PHDR_CKSUM 0x00000008 472 #define TI_RCB_FLAG_VLAN_ASSIST 0x00000010 473 #define TI_RCB_FLAG_COAL_UPD_ONLY 0x00000020 474 #define TI_RCB_FLAG_HOST_RING 0x00000040 475 #define TI_RCB_FLAG_IEEE_SNAP_CKSUM 0x00000080 476 #define TI_RCB_FLAG_USE_EXT_RX_BD 0x00000100 477 #define TI_RCB_FLAG_RING_DISABLED 0x00000200 478 479 struct ti_producer { 480 u_int32_t ti_idx; 481 u_int32_t ti_unused; 482 }; 483 484 /* 485 * Tigon statistics counters. 486 */ 487 struct ti_stats { 488 /* 489 * MAC stats, taken from RFC 1643, ethernet-like MIB 490 */ 491 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 492 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 493 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 494 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 495 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 496 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 497 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 498 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 499 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 500 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 501 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 502 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 503 /* 504 * interface stats, taken from RFC 1213, MIB-II, interfaces group 505 */ 506 volatile u_int32_t ifIndex; /* 12 */ 507 volatile u_int32_t ifType; /* 13 */ 508 volatile u_int32_t ifMtu; /* 14 */ 509 volatile u_int32_t ifSpeed; /* 15 */ 510 volatile u_int32_t ifAdminStatus; /* 16 */ 511 #define IF_ADMIN_STATUS_UP 1 512 #define IF_ADMIN_STATUS_DOWN 2 513 #define IF_ADMIN_STATUS_TESTING 3 514 volatile u_int32_t ifOperStatus; /* 17 */ 515 #define IF_OPER_STATUS_UP 1 516 #define IF_OPER_STATUS_DOWN 2 517 #define IF_OPER_STATUS_TESTING 3 518 #define IF_OPER_STATUS_UNKNOWN 4 519 #define IF_OPER_STATUS_DORMANT 5 520 volatile u_int32_t ifLastChange; /* 18 */ 521 volatile u_int32_t ifInDiscards; /* 19 */ 522 volatile u_int32_t ifInErrors; /* 20 */ 523 volatile u_int32_t ifInUnknownProtos; /* 21 */ 524 volatile u_int32_t ifOutDiscards; /* 22 */ 525 volatile u_int32_t ifOutErrors; /* 23 */ 526 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 527 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 528 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 529 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 530 /* 531 * more interface stats, taken from RFC 1573, MIB-IIupdate, 532 * interfaces group 533 */ 534 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 535 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 536 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 537 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 538 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 539 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 540 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 541 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 542 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 543 volatile u_int32_t ifHighSpeed; /* 53 */ 544 volatile u_int32_t ifPromiscuousMode; /* 54 */ 545 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 546 /* 547 * Host Commands 548 */ 549 volatile u_int32_t nicCmdsHostState; /* 56 */ 550 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 551 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 552 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 553 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 554 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 555 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 556 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 557 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 558 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 559 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 560 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 561 volatile u_int32_t nicCmdsClearStats; /* 68 */ 562 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 563 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 564 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 565 volatile u_int32_t nicCmdsUnknown; /* 72 */ 566 /* 567 * NIC Events 568 */ 569 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 570 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 571 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 572 volatile u_int32_t nicEventsError; /* 76 */ 573 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 574 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 575 /* 576 * Ring manipulation 577 */ 578 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 579 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 580 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 581 /* 582 * Interrupts 583 */ 584 volatile u_int32_t nicInterrupts; /* 82 */ 585 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 586 /* 587 * BD Coalessing Thresholds 588 */ 589 volatile u_int32_t nicEventThresholdHit; /* 84 */ 590 volatile u_int32_t nicSendThresholdHit; /* 85 */ 591 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 592 /* 593 * DMA Attentions 594 */ 595 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 596 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 597 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 598 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 599 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 600 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 601 /* 602 * NIC Resources 603 */ 604 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 605 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 606 volatile u_int32_t nicEventRingFull; /* 95 */ 607 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 608 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 609 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 610 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 611 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 612 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 613 volatile u_int32_t nicSendBDs; /* current count 102 */ 614 volatile u_int32_t nicRecvBDs; /* current count 103 */ 615 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 616 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 617 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 618 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 619 volatile u_int32_t nicJumboSpillOver; /* 108 */ 620 volatile u_int32_t nicSbusHangCleared; /* 109 */ 621 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 622 /* 623 * Stats from MAC rx completion 624 */ 625 volatile u_int32_t nicMacRxLateColls; /* 111 */ 626 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 627 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 628 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 629 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 630 /* 631 * Stats from the mac_stats area 632 */ 633 volatile u_int32_t nicMacRxDropUla; /* 116 */ 634 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 635 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 636 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 637 volatile u_int32_t nicMacRxColls; /* 120 */ 638 /* 639 * MAC RX Attentions 640 */ 641 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 642 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 643 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 644 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 645 volatile u_int32_t nicMacReset; /* 125 */ 646 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 647 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 648 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 649 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 650 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 651 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 652 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 653 /* 654 * Stats from the mac_stats area 655 */ 656 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 657 /* 658 * MAC TX Attentions 659 */ 660 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 661 /* 662 * NIC Profile 663 */ 664 volatile u_int32_t nicProfile[32]; /* 135 */ 665 /* 666 * Pat to 1024 bytes. 667 */ 668 u_int32_t pad[75]; 669 }; 670 /* 671 * Tigon general information block. This resides in host memory 672 * and contains the status counters, ring control blocks and 673 * producer pointers. 674 */ 675 676 struct ti_gib { 677 struct ti_stats ti_stats; 678 struct ti_rcb ti_ev_rcb; 679 struct ti_rcb ti_cmd_rcb; 680 struct ti_rcb ti_tx_rcb; 681 struct ti_rcb ti_std_rx_rcb; 682 struct ti_rcb ti_jumbo_rx_rcb; 683 struct ti_rcb ti_mini_rx_rcb; 684 struct ti_rcb ti_return_rcb; 685 ti_hostaddr ti_ev_prodidx_ptr; 686 ti_hostaddr ti_return_prodidx_ptr; 687 ti_hostaddr ti_tx_considx_ptr; 688 ti_hostaddr ti_refresh_stats_ptr; 689 }; 690 691 /* 692 * Buffer descriptor structures. There are basically three types 693 * of structures: normal receive descriptors, extended receive 694 * descriptors and transmit descriptors. The extended receive 695 * descriptors are optionally used only for the jumbo receive ring. 696 */ 697 698 struct ti_rx_desc { 699 ti_hostaddr ti_addr; 700 #if BYTE_ORDER == BIG_ENDIAN 701 u_int16_t ti_idx; 702 u_int16_t ti_len; 703 #else 704 u_int16_t ti_len; 705 u_int16_t ti_idx; 706 #endif 707 #if BYTE_ORDER == BIG_ENDIAN 708 u_int16_t ti_type; 709 u_int16_t ti_flags; 710 #else 711 u_int16_t ti_flags; 712 u_int16_t ti_type; 713 #endif 714 #if BYTE_ORDER == BIG_ENDIAN 715 u_int16_t ti_ip_cksum; 716 u_int16_t ti_tcp_udp_cksum; 717 #else 718 u_int16_t ti_tcp_udp_cksum; 719 u_int16_t ti_ip_cksum; 720 #endif 721 #if BYTE_ORDER == BIG_ENDIAN 722 u_int16_t ti_error_flags; 723 u_int16_t ti_vlan_tag; 724 #else 725 u_int16_t ti_vlan_tag; 726 u_int16_t ti_error_flags; 727 #endif 728 u_int32_t ti_rsvd; 729 u_int32_t ti_opaque; 730 }; 731 732 struct ti_rx_desc_ext { 733 ti_hostaddr ti_addr1; 734 ti_hostaddr ti_addr2; 735 ti_hostaddr ti_addr3; 736 #if BYTE_ORDER == BIG_ENDIAN 737 u_int16_t ti_len1; 738 u_int16_t ti_len2; 739 #else 740 u_int16_t ti_len2; 741 u_int16_t ti_len1; 742 #endif 743 #if BYTE_ORDER == BIG_ENDIAN 744 u_int16_t ti_len3; 745 u_int16_t ti_rsvd0; 746 #else 747 u_int16_t ti_rsvd0; 748 u_int16_t ti_len3; 749 #endif 750 ti_hostaddr ti_addr0; 751 #if BYTE_ORDER == BIG_ENDIAN 752 u_int16_t ti_idx; 753 u_int16_t ti_len0; 754 #else 755 u_int16_t ti_len0; 756 u_int16_t ti_idx; 757 #endif 758 #if BYTE_ORDER == BIG_ENDIAN 759 u_int16_t ti_type; 760 u_int16_t ti_flags; 761 #else 762 u_int16_t ti_flags; 763 u_int16_t ti_type; 764 #endif 765 #if BYTE_ORDER == BIG_ENDIAN 766 u_int16_t ti_ip_cksum; 767 u_int16_t ti_tcp_udp_cksum; 768 #else 769 u_int16_t ti_tcp_udp_cksum; 770 u_int16_t ti_ip_cksum; 771 #endif 772 #if BYTE_ORDER == BIG_ENDIAN 773 u_int16_t ti_error_flags; 774 u_int16_t ti_vlan_tag; 775 #else 776 u_int16_t ti_vlan_tag; 777 u_int16_t ti_error_flags; 778 #endif 779 u_int32_t ti_rsvd1; 780 u_int32_t ti_opaque; 781 }; 782 783 /* 784 * Transmit descriptors are, mercifully, very small. 785 */ 786 struct ti_tx_desc { 787 ti_hostaddr ti_addr; 788 #if BYTE_ORDER == BIG_ENDIAN 789 u_int16_t ti_len; 790 u_int16_t ti_flags; 791 #else 792 u_int16_t ti_flags; 793 u_int16_t ti_len; 794 #endif 795 #if BYTE_ORDER == BIG_ENDIAN 796 u_int16_t ti_rsvd; 797 u_int16_t ti_vlan_tag; 798 #else 799 u_int16_t ti_vlan_tag; 800 u_int16_t ti_rsvd; 801 #endif 802 }; 803 804 /* 805 * NOTE! On the Alpha, we have an alignment constraint. 806 * The first thing in the packet is a 14-byte Ethernet header. 807 * This means that the packet is misaligned. To compensate, 808 * we actually offset the data 2 bytes into the cluster. This 809 * alignes the packet after the Ethernet header at a 32-bit 810 * boundary. 811 */ 812 813 #define ETHER_ALIGN 2 814 815 #define TI_FRAMELEN 1518 816 #define TI_JUMBO_FRAMELEN 9018 817 #define TI_JUMBO_MTU (TI_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 818 #define TI_PAGE_SIZE PAGE_SIZE 819 #define TI_MIN_FRAMELEN 60 820 821 /* 822 * Buffer descriptor error flags. 823 */ 824 #define TI_BDERR_CRC 0x0001 825 #define TI_BDERR_COLLDETECT 0x0002 826 #define TI_BDERR_LINKLOST 0x0004 827 #define TI_BDERR_DECODE 0x0008 828 #define TI_BDERR_ODD_NIBBLES 0x0010 829 #define TI_BDERR_MAC_ABRT 0x0020 830 #define TI_BDERR_RUNT 0x0040 831 #define TI_BDERR_TRUNC 0x0080 832 #define TI_BDERR_GIANT 0x0100 833 834 /* 835 * Buffer descriptor flags. 836 */ 837 #define TI_BDFLAG_TCP_UDP_CKSUM 0x0001 838 #define TI_BDFLAG_IP_CKSUM 0x0002 839 #define TI_BDFLAG_END 0x0004 840 #define TI_BDFLAG_MORE 0x0008 841 #define TI_BDFLAG_JUMBO_RING 0x0010 842 #define TI_BDFLAG_UCAST_PKT 0x0020 843 #define TI_BDFLAG_MCAST_PKT 0x0040 844 #define TI_BDFLAG_BCAST_PKT 0x0060 845 #define TI_BDFLAG_IP_FRAG 0x0080 846 #define TI_BDFLAG_IP_FRAG_END 0x0100 847 #define TI_BDFLAG_VLAN_TAG 0x0200 848 #define TI_BDFLAG_ERROR 0x0400 849 #define TI_BDFLAG_COAL_NOW 0x0800 850 #define TI_BDFLAG_MINI_RING 0x1000 851 852 /* 853 * Descriptor type flags. I think these only have meaning for 854 * the Tigon 1. I had to extract them from the sample driver source 855 * since they aren't in the manual. 856 */ 857 #define TI_BDTYPE_TYPE_NULL 0x0000 858 #define TI_BDTYPE_SEND_BD 0x0001 859 #define TI_BDTYPE_RECV_BD 0x0002 860 #define TI_BDTYPE_RECV_JUMBO_BD 0x0003 861 #define TI_BDTYPE_RECV_BD_LAST 0x0004 862 #define TI_BDTYPE_SEND_DATA 0x0005 863 #define TI_BDTYPE_SEND_DATA_LAST 0x0006 864 #define TI_BDTYPE_RECV_DATA 0x0007 865 #define TI_BDTYPE_RECV_DATA_LAST 0x000b 866 #define TI_BDTYPE_EVENT_RUPT 0x000c 867 #define TI_BDTYPE_EVENT_NO_RUPT 0x000d 868 #define TI_BDTYPE_ODD_START 0x000e 869 #define TI_BDTYPE_UPDATE_STATS 0x000f 870 #define TI_BDTYPE_SEND_DUMMY_DMA 0x0010 871 #define TI_BDTYPE_EVENT_PROD 0x0011 872 #define TI_BDTYPE_TX_CONS 0x0012 873 #define TI_BDTYPE_RX_PROD 0x0013 874 #define TI_BDTYPE_REFRESH_STATS 0x0014 875 #define TI_BDTYPE_SEND_DATA_LAST_VLAN 0x0015 876 #define TI_BDTYPE_SEND_DATA_COAL 0x0016 877 #define TI_BDTYPE_SEND_DATA_LAST_COAL 0x0017 878 #define TI_BDTYPE_SEND_DATA_LAST_VLAN_COAL 0x0018 879 #define TI_BDTYPE_TX_CONS_NO_INTR 0x0019 880 881 /* 882 * Tigon command structure. 883 */ 884 struct ti_cmd_desc { 885 #if BYTE_ORDER == BIG_ENDIAN 886 u_int32_t ti_cmd:8; 887 u_int32_t ti_code:12; 888 u_int32_t ti_idx:12; 889 #else 890 u_int32_t ti_idx:12; 891 u_int32_t ti_code:12; 892 u_int32_t ti_cmd:8; 893 #endif 894 }; 895 896 #define TI_CMD_HOST_STATE 0x01 897 #define TI_CMD_CODE_STACK_UP 0x01 898 #define TI_CMD_CODE_STACK_DOWN 0x02 899 900 /* 901 * This command enables software address filtering. It's a workaround 902 * for a bug in the Tigon 1 and not implemented for the Tigon 2. 903 */ 904 #define TI_CMD_FDR_FILTERING 0x02 905 #define TI_CMD_CODE_FILT_ENB 0x01 906 #define TI_CMD_CODE_FILT_DIS 0x02 907 908 #define TI_CMD_SET_RX_PROD_IDX 0x03 /* obsolete */ 909 #define TI_CMD_UPDATE_GENCOM 0x04 910 #define TI_CMD_RESET_JUMBO_RING 0x05 911 #define TI_CMD_SET_PARTIAL_RX_CNT 0x06 912 #define TI_CMD_ADD_MCAST_ADDR 0x08 /* obsolete */ 913 #define TI_CMD_DEL_MCAST_ADDR 0x09 /* obsolete */ 914 915 #define TI_CMD_SET_PROMISC_MODE 0x0A 916 #define TI_CMD_CODE_PROMISC_ENB 0x01 917 #define TI_CMD_CODE_PROMISC_DIS 0x02 918 919 #define TI_CMD_LINK_NEGOTIATION 0x0B 920 #define TI_CMD_CODE_NEGOTIATE_BOTH 0x00 921 #define TI_CMD_CODE_NEGOTIATE_GIGABIT 0x01 922 #define TI_CMD_CODE_NEGOTIATE_10_100 0x02 923 924 #define TI_CMD_SET_MAC_ADDR 0x0C 925 #define TI_CMD_CLR_PROFILE 0x0D 926 927 #define TI_CMD_SET_ALLMULTI 0x0E 928 #define TI_CMD_CODE_ALLMULTI_ENB 0x01 929 #define TI_CMD_CODE_ALLMULTI_DIS 0x02 930 931 #define TI_CMD_CLR_STATS 0x0F 932 #define TI_CMD_SET_RX_JUMBO_PROD_IDX 0x10 /* obsolete */ 933 #define TI_CMD_RFRSH_STATS 0x11 934 935 #define TI_CMD_EXT_ADD_MCAST 0x12 936 #define TI_CMD_EXT_DEL_MCAST 0x13 937 938 /* 939 * Utility macros to make issuing commands a little simpler. Assumes 940 * that 'sc' and 'cmd' are in local scope. 941 */ 942 #define TI_DO_CMD(x, y, z) \ 943 cmd.ti_cmd = x; \ 944 cmd.ti_code = y; \ 945 cmd.ti_idx = z; \ 946 ti_cmd(sc, &cmd); 947 948 #define TI_DO_CMD_EXT(x, y, z, v, w) \ 949 cmd.ti_cmd = x; \ 950 cmd.ti_code = y; \ 951 cmd.ti_idx = z; \ 952 ti_cmd_ext(sc, &cmd, v, w); 953 954 /* 955 * Other utility macros. 956 */ 957 #define TI_INC(x, y) (x) = (x + 1) % y 958 959 #define TI_UPDATE_JUMBOPROD(x, y) \ 960 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 961 TI_DO_CMD(TI_CMD_SET_RX_JUMBO_PROD_IDX, 0, y); \ 962 } else { \ 963 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 964 } 965 966 #define TI_UPDATE_MINIPROD(x, y) \ 967 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y); 968 969 #define TI_UPDATE_STDPROD(x, y) \ 970 if (x->ti_hwrev == TI_HWREV_TIGON) { \ 971 TI_DO_CMD(TI_CMD_SET_RX_PROD_IDX, 0, y); \ 972 } else { \ 973 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 974 } 975 976 977 /* 978 * Tigon event structure. 979 */ 980 struct ti_event_desc { 981 #if BYTE_ORDER == BIG_ENDIAN 982 u_int32_t ti_event:8; 983 u_int32_t ti_code:12; 984 u_int32_t ti_idx:12; 985 #else 986 u_int32_t ti_idx:12; 987 u_int32_t ti_code:12; 988 u_int32_t ti_event:8; 989 #endif 990 u_int32_t ti_rsvd; 991 }; 992 993 /* 994 * Tigon events. 995 */ 996 #define TI_EV_FIRMWARE_UP 0x01 997 #define TI_EV_STATS_UPDATED 0x04 998 999 #define TI_EV_LINKSTAT_CHANGED 0x06 1000 #define TI_EV_CODE_GIG_LINK_UP 0x01 1001 #define TI_EV_CODE_LINK_DOWN 0x02 1002 #define TI_EV_CODE_LINK_UP 0x03 1003 1004 #define TI_EV_ERROR 0x07 1005 #define TI_EV_CODE_ERR_INVAL_CMD 0x01 1006 #define TI_EV_CODE_ERR_UNIMP_CMD 0x02 1007 #define TI_EV_CODE_ERR_BADCFG 0x03 1008 1009 #define TI_EV_MCAST_UPDATED 0x08 1010 #define TI_EV_CODE_MCAST_ADD 0x01 1011 #define TI_EV_CODE_MCAST_DEL 0x02 1012 1013 #define TI_EV_RESET_JUMBO_RING 0x09 1014 /* 1015 * Register access macros. The Tigon always uses memory mapped register 1016 * accesses and all registers must be accessed with 32 bit operations. 1017 */ 1018 1019 #define CSR_WRITE_4(sc, reg, val) \ 1020 bus_space_write_4(sc->ti_btag, sc->ti_bhandle, reg, val) 1021 1022 #define CSR_READ_4(sc, reg) \ 1023 bus_space_read_4(sc->ti_btag, sc->ti_bhandle, reg) 1024 1025 #define TI_SETBIT(sc, reg, x) \ 1026 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 1027 #define TI_CLRBIT(sc, reg, x) \ 1028 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 1029 1030 /* 1031 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 1032 * values are tuneable. They control the actual amount of buffers 1033 * allocated for the standard, mini and jumbo receive rings. 1034 */ 1035 1036 #define TI_SSLOTS 256 1037 #define TI_MSLOTS 256 1038 #define TI_JSLOTS 384 1039 1040 #define TI_JRAWLEN (TI_JUMBO_FRAMELEN + ETHER_ALIGN) 1041 #define TI_JLEN (TI_JRAWLEN + (sizeof(u_int64_t) - \ 1042 (TI_JRAWLEN % sizeof(u_int64_t)))) 1043 #define TI_JPAGESZ PAGE_SIZE 1044 #define TI_RESID (TI_JPAGESZ - (TI_JLEN * TI_JSLOTS) % TI_JPAGESZ) 1045 #define TI_JMEM ((TI_JLEN * TI_JSLOTS) + TI_RESID) 1046 1047 /* 1048 * Ring structures. Most of these reside in host memory and we tell 1049 * the NIC where they are via the ring control blocks. The exceptions 1050 * are the tx and command rings, which live in NIC memory and which 1051 * we access via the shared memory window. 1052 */ 1053 struct ti_ring_data { 1054 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; 1055 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 1056 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1057 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1058 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1059 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1060 /* 1061 * Make sure producer structures are aligned on 32-byte cache 1062 * line boundaries. 1063 */ 1064 struct ti_producer ti_ev_prodidx_r; 1065 u_int32_t ti_pad0[6]; 1066 struct ti_producer ti_return_prodidx_r; 1067 u_int32_t ti_pad1[6]; 1068 struct ti_producer ti_tx_considx_r; 1069 u_int32_t ti_pad2[6]; 1070 struct ti_tx_desc *ti_tx_ring_nic;/* pointer to shared mem */ 1071 struct ti_cmd_desc *ti_cmd_ring; /* pointer to shared mem */ 1072 struct ti_gib ti_info; 1073 }; 1074 1075 /* 1076 * Mbuf pointers. We need these to keep track of the virtual addresses 1077 * of our mbuf chains since we can only convert from physical to virtual, 1078 * not the other way around. 1079 */ 1080 struct ti_chain_data { 1081 struct mbuf *ti_tx_chain[TI_TX_RING_CNT]; 1082 struct mbuf *ti_rx_std_chain[TI_STD_RX_RING_CNT]; 1083 struct mbuf *ti_rx_jumbo_chain[TI_JUMBO_RX_RING_CNT]; 1084 struct mbuf *ti_rx_mini_chain[TI_MINI_RX_RING_CNT]; 1085 /* Stick the jumbo mem management stuff here too. */ 1086 caddr_t ti_jslots[TI_JSLOTS]; 1087 void *ti_jumbo_buf; 1088 }; 1089 1090 struct ti_type { 1091 u_int16_t ti_vid; 1092 u_int16_t ti_did; 1093 char *ti_name; 1094 }; 1095 1096 #define TI_HWREV_TIGON 0x01 1097 #define TI_HWREV_TIGON_II 0x02 1098 #define TI_TIMEOUT 1000 1099 #define TI_TXCONS_UNSET 0xFFFF /* impossible value */ 1100 1101 struct ti_mc_entry { 1102 struct ether_addr mc_addr; 1103 SLIST_ENTRY(ti_mc_entry) mc_entries; 1104 }; 1105 1106 struct ti_jpool_entry { 1107 int slot; 1108 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1109 }; 1110 1111 struct ti_softc { 1112 struct arpcom arpcom; /* interface info */ 1113 bus_space_handle_t ti_bhandle; 1114 vm_offset_t ti_vhandle; 1115 bus_space_tag_t ti_btag; 1116 void *ti_intrhand; 1117 struct resource *ti_irq; 1118 struct resource *ti_res; 1119 struct ifmedia ifmedia; /* media info */ 1120 u_int8_t ti_unit; /* interface number */ 1121 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1122 u_int8_t ti_copper; /* 1000baseTX card */ 1123 u_int8_t ti_linkstat; /* Link state */ 1124 struct ti_ring_data *ti_rdata; /* rings */ 1125 struct ti_chain_data ti_cdata; /* mbufs */ 1126 #define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1127 #define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1128 #define ti_tx_considx ti_rdata->ti_tx_considx_r 1129 u_int16_t ti_tx_saved_considx; 1130 u_int16_t ti_rx_saved_considx; 1131 u_int16_t ti_ev_saved_considx; 1132 u_int16_t ti_cmd_saved_prodidx; 1133 u_int16_t ti_std; /* current std ring head */ 1134 u_int16_t ti_mini; /* current mini ring head */ 1135 u_int16_t ti_jumbo; /* current jumo ring head */ 1136 SLIST_HEAD(__ti_mchead, ti_mc_entry) ti_mc_listhead; 1137 SLIST_HEAD(__ti_jfreehead, ti_jpool_entry) ti_jfree_listhead; 1138 SLIST_HEAD(__ti_jinusehead, ti_jpool_entry) ti_jinuse_listhead; 1139 u_int32_t ti_stat_ticks; 1140 u_int32_t ti_rx_coal_ticks; 1141 u_int32_t ti_tx_coal_ticks; 1142 u_int32_t ti_rx_max_coal_bds; 1143 u_int32_t ti_tx_max_coal_bds; 1144 u_int32_t ti_tx_buf_ratio; 1145 int ti_if_flags; 1146 int ti_txcnt; 1147 struct mtx ti_mtx; 1148 }; 1149 1150 #define TI_LOCK(_sc) mtx_enter(&(_sc)->ti_mtx, MTX_DEF) 1151 #define TI_UNLOCK(_sc) mtx_exit(&(_sc)->ti_mtx, MTX_DEF) 1152 1153 /* 1154 * Microchip Technology 24Cxx EEPROM control bytes 1155 */ 1156 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 1157 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 1158 1159 /* 1160 * Note that EEPROM_START leaves transmission enabled. 1161 */ 1162 #define EEPROM_START \ 1163 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock pin high */\ 1164 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Set DATA bit to 1 */ \ 1165 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit to write bit */\ 1166 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA bit to 0 again */\ 1167 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1168 1169 /* 1170 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 1171 * that no further data can be written to the EEPROM I/O pin. 1172 */ 1173 #define EEPROM_STOP \ 1174 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit */ \ 1175 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Pull DATA to 0 */ \ 1176 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock high */ \ 1177 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Enable xmit */ \ 1178 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); /* Toggle DATA to 1 */ \ 1179 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); /* Disable xmit. */ \ 1180 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); /* Pull clock low again */ 1181 1182 1183 #ifdef __alpha__ 1184 #undef vtophys 1185 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1186 #endif 1187