1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/queue.h> 91 92 #include <net/if.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 #include <pci/pcireg.h> 118 #include <pci/pcivar.h> 119 120 #include <pci/if_tireg.h> 121 #include <pci/ti_fw.h> 122 #include <pci/ti_fw2.h> 123 124 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 125 126 #if !defined(lint) 127 static const char rcsid[] = 128 "$FreeBSD$"; 129 #endif 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 135 static struct ti_type ti_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 137 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 139 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 140 { TC_VENDORID, TC_DEVICEID_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { NG_VENDORID, NG_DEVICEID_GA620, 143 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 144 { NG_VENDORID, NG_DEVICEID_GA620T, 145 "Netgear GA620 1000baseT Gigabit Ethernet" }, 146 { SGI_VENDORID, SGI_DEVICEID_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 149 "Farallon PN9000SX Gigabit Ethernet" }, 150 { 0, 0, NULL } 151 }; 152 153 static int ti_probe __P((device_t)); 154 static int ti_attach __P((device_t)); 155 static int ti_detach __P((device_t)); 156 static void ti_txeof __P((struct ti_softc *)); 157 static void ti_rxeof __P((struct ti_softc *)); 158 159 static void ti_stats_update __P((struct ti_softc *)); 160 static int ti_encap __P((struct ti_softc *, struct mbuf *, 161 u_int32_t *)); 162 163 static void ti_intr __P((void *)); 164 static void ti_start __P((struct ifnet *)); 165 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 166 static void ti_init __P((void *)); 167 static void ti_init2 __P((struct ti_softc *)); 168 static void ti_stop __P((struct ti_softc *)); 169 static void ti_watchdog __P((struct ifnet *)); 170 static void ti_shutdown __P((device_t)); 171 static int ti_ifmedia_upd __P((struct ifnet *)); 172 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 175 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 176 int, u_int8_t *)); 177 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 178 179 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 180 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 181 static void ti_setmulti __P((struct ti_softc *)); 182 183 static void ti_mem __P((struct ti_softc *, u_int32_t, 184 u_int32_t, caddr_t)); 185 static void ti_loadfw __P((struct ti_softc *)); 186 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 187 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 188 caddr_t, int)); 189 static void ti_handle_events __P((struct ti_softc *)); 190 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 191 static void *ti_jalloc __P((struct ti_softc *)); 192 static void ti_jfree __P((caddr_t, void *)); 193 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 194 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 195 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 196 static int ti_init_rx_ring_std __P((struct ti_softc *)); 197 static void ti_free_rx_ring_std __P((struct ti_softc *)); 198 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 199 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 200 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 201 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 202 static void ti_free_tx_ring __P((struct ti_softc *)); 203 static int ti_init_tx_ring __P((struct ti_softc *)); 204 205 static int ti_64bitslot_war __P((struct ti_softc *)); 206 static int ti_chipinit __P((struct ti_softc *)); 207 static int ti_gibinit __P((struct ti_softc *)); 208 209 static device_method_t ti_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ti_probe), 212 DEVMETHOD(device_attach, ti_attach), 213 DEVMETHOD(device_detach, ti_detach), 214 DEVMETHOD(device_shutdown, ti_shutdown), 215 { 0, 0 } 216 }; 217 218 static driver_t ti_driver = { 219 "ti", 220 ti_methods, 221 sizeof(struct ti_softc) 222 }; 223 224 static devclass_t ti_devclass; 225 226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228 /* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231 static u_int32_t ti_eeprom_putbyte(sc, byte) 232 struct ti_softc *sc; 233 int byte; 234 { 235 register int i, ack = 0; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) { 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } else { 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 } 251 DELAY(1); 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 DELAY(1); 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 } 256 257 /* 258 * Turn off TX mode. 259 */ 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 261 262 /* 263 * Check for ack. 264 */ 265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 269 return(ack); 270 } 271 272 /* 273 * Read a byte of data stored in the EEPROM at address 'addr.' 274 * We have to send two address bytes since the EEPROM can hold 275 * more than 256 bytes of data. 276 */ 277 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 278 struct ti_softc *sc; 279 int addr; 280 u_int8_t *dest; 281 { 282 register int i; 283 u_int8_t byte = 0; 284 285 EEPROM_START; 286 287 /* 288 * Send write control code to EEPROM. 289 */ 290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 291 printf("ti%d: failed to send write command, status: %x\n", 292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 /* 297 * Send first byte of address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 300 printf("ti%d: failed to send address, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 /* 305 * Send second byte address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 313 EEPROM_STOP; 314 EEPROM_START; 315 /* 316 * Send read control code to EEPROM. 317 */ 318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 319 printf("ti%d: failed to send read command, status: %x\n", 320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 321 return(1); 322 } 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 328 for (i = 0x80; i; i >>= 1) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 332 byte |= i; 333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 334 DELAY(1); 335 } 336 337 EEPROM_STOP; 338 339 /* 340 * No ACK generated for read, so just return byte. 341 */ 342 343 *dest = byte; 344 345 return(0); 346 } 347 348 /* 349 * Read a sequence of bytes from the EEPROM. 350 */ 351 static int ti_read_eeprom(sc, dest, off, cnt) 352 struct ti_softc *sc; 353 caddr_t dest; 354 int off; 355 int cnt; 356 { 357 int err = 0, i; 358 u_int8_t byte = 0; 359 360 for (i = 0; i < cnt; i++) { 361 err = ti_eeprom_getbyte(sc, off + i, &byte); 362 if (err) 363 break; 364 *(dest + i) = byte; 365 } 366 367 return(err ? 1 : 0); 368 } 369 370 /* 371 * NIC memory access function. Can be used to either clear a section 372 * of NIC local memory or (if buf is non-NULL) copy data into it. 373 */ 374 static void ti_mem(sc, addr, len, buf) 375 struct ti_softc *sc; 376 u_int32_t addr, len; 377 caddr_t buf; 378 { 379 int segptr, segsize, cnt; 380 caddr_t ti_winbase, ptr; 381 382 segptr = addr; 383 cnt = len; 384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 385 ptr = buf; 386 387 while(cnt) { 388 if (cnt < TI_WINLEN) 389 segsize = cnt; 390 else 391 segsize = TI_WINLEN - (segptr % TI_WINLEN); 392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 393 if (buf == NULL) 394 bzero((char *)ti_winbase + (segptr & 395 (TI_WINLEN - 1)), segsize); 396 else { 397 bcopy((char *)ptr, (char *)ti_winbase + 398 (segptr & (TI_WINLEN - 1)), segsize); 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406 } 407 408 /* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413 static void ti_loadfw(sc) 414 struct ti_softc *sc; 415 { 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("ti%d: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("ti%d: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("ti%d: can't load firmware: unknown hardware rev\n", 461 sc->ti_unit); 462 break; 463 } 464 465 return; 466 } 467 468 /* 469 * Send the NIC a command via the command ring. 470 */ 471 static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474 { 475 u_int32_t index; 476 477 if (sc->ti_rdata->ti_cmd_ring == NULL) 478 return; 479 480 index = sc->ti_cmd_saved_prodidx; 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 482 TI_INC(index, TI_CMD_RING_CNT); 483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 484 sc->ti_cmd_saved_prodidx = index; 485 486 return; 487 } 488 489 /* 490 * Send the NIC an extended command. The 'len' parameter specifies the 491 * number of command slots to include after the initial command. 492 */ 493 static void ti_cmd_ext(sc, cmd, arg, len) 494 struct ti_softc *sc; 495 struct ti_cmd_desc *cmd; 496 caddr_t arg; 497 int len; 498 { 499 u_int32_t index; 500 register int i; 501 502 if (sc->ti_rdata->ti_cmd_ring == NULL) 503 return; 504 505 index = sc->ti_cmd_saved_prodidx; 506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 507 TI_INC(index, TI_CMD_RING_CNT); 508 for (i = 0; i < len; i++) { 509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 510 *(u_int32_t *)(&arg[i * 4])); 511 TI_INC(index, TI_CMD_RING_CNT); 512 } 513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 514 sc->ti_cmd_saved_prodidx = index; 515 516 return; 517 } 518 519 /* 520 * Handle events that have triggered interrupts. 521 */ 522 static void ti_handle_events(sc) 523 struct ti_softc *sc; 524 { 525 struct ti_event_desc *e; 526 527 if (sc->ti_rdata->ti_event_ring == NULL) 528 return; 529 530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 532 switch(e->ti_event) { 533 case TI_EV_LINKSTAT_CHANGED: 534 sc->ti_linkstat = e->ti_code; 535 if (e->ti_code == TI_EV_CODE_LINK_UP) 536 printf("ti%d: 10/100 link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 538 printf("ti%d: gigabit link up\n", sc->ti_unit); 539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 540 printf("ti%d: link down\n", sc->ti_unit); 541 break; 542 case TI_EV_ERROR: 543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 544 printf("ti%d: invalid command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 546 printf("ti%d: unknown command\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 548 printf("ti%d: bad config data\n", sc->ti_unit); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("ti%d: unknown event: %d\n", 562 sc->ti_unit, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571 } 572 573 /* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596 static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598 { 599 caddr_t ptr; 600 register int i; 601 struct ti_jpool_entry *entry; 602 603 /* Grab a big chunk o' storage. */ 604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 609 return(ENOBUFS); 610 } 611 612 SLIST_INIT(&sc->ti_jfree_listhead); 613 SLIST_INIT(&sc->ti_jinuse_listhead); 614 615 /* 616 * Now divide it up into 9K pieces and save the addresses 617 * in an array. 618 */ 619 ptr = sc->ti_cdata.ti_jumbo_buf; 620 for (i = 0; i < TI_JSLOTS; i++) { 621 sc->ti_cdata.ti_jslots[i] = ptr; 622 ptr += TI_JLEN; 623 entry = malloc(sizeof(struct ti_jpool_entry), 624 M_DEVBUF, M_NOWAIT); 625 if (entry == NULL) { 626 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 627 M_DEVBUF); 628 sc->ti_cdata.ti_jumbo_buf = NULL; 629 printf("ti%d: no memory for jumbo " 630 "buffer queue!\n", sc->ti_unit); 631 return(ENOBUFS); 632 } 633 entry->slot = i; 634 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 635 } 636 637 return(0); 638 } 639 640 /* 641 * Allocate a jumbo buffer. 642 */ 643 static void *ti_jalloc(sc) 644 struct ti_softc *sc; 645 { 646 struct ti_jpool_entry *entry; 647 648 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 649 650 if (entry == NULL) { 651 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 652 return(NULL); 653 } 654 655 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 656 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 657 return(sc->ti_cdata.ti_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 static void ti_jfree(buf, args) 664 caddr_t buf; 665 void *args; 666 { 667 struct ti_softc *sc; 668 int i; 669 struct ti_jpool_entry *entry; 670 671 /* Extract the softc struct pointer. */ 672 sc = (struct ti_softc *)args; 673 674 if (sc == NULL) 675 panic("ti_jfree: didn't get softc pointer!"); 676 677 /* calculate the slot this buffer belongs to */ 678 i = ((vm_offset_t)buf 679 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 680 681 if ((i < 0) || (i >= TI_JSLOTS)) 682 panic("ti_jfree: asked to free buffer that we don't manage!"); 683 684 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 685 if (entry == NULL) 686 panic("ti_jfree: buffer not in use!"); 687 entry->slot = i; 688 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 689 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 690 691 return; 692 } 693 694 695 /* 696 * Intialize a standard receive ring descriptor. 697 */ 698 static int ti_newbuf_std(sc, i, m) 699 struct ti_softc *sc; 700 int i; 701 struct mbuf *m; 702 { 703 struct mbuf *m_new = NULL; 704 struct ti_rx_desc *r; 705 706 if (m == NULL) { 707 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 708 if (m_new == NULL) { 709 printf("ti%d: mbuf allocation failed " 710 "-- packet dropped!\n", sc->ti_unit); 711 return(ENOBUFS); 712 } 713 714 MCLGET(m_new, M_DONTWAIT); 715 if (!(m_new->m_flags & M_EXT)) { 716 printf("ti%d: cluster allocation failed " 717 "-- packet dropped!\n", sc->ti_unit); 718 m_freem(m_new); 719 return(ENOBUFS); 720 } 721 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 722 } else { 723 m_new = m; 724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 725 m_new->m_data = m_new->m_ext.ext_buf; 726 } 727 728 m_adj(m_new, ETHER_ALIGN); 729 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 730 r = &sc->ti_rdata->ti_rx_std_ring[i]; 731 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 732 r->ti_type = TI_BDTYPE_RECV_BD; 733 r->ti_flags = 0; 734 if (sc->arpcom.ac_if.if_hwassist) 735 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 736 r->ti_len = m_new->m_len; 737 r->ti_idx = i; 738 739 return(0); 740 } 741 742 /* 743 * Intialize a mini receive ring descriptor. This only applies to 744 * the Tigon 2. 745 */ 746 static int ti_newbuf_mini(sc, i, m) 747 struct ti_softc *sc; 748 int i; 749 struct mbuf *m; 750 { 751 struct mbuf *m_new = NULL; 752 struct ti_rx_desc *r; 753 754 if (m == NULL) { 755 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 756 if (m_new == NULL) { 757 printf("ti%d: mbuf allocation failed " 758 "-- packet dropped!\n", sc->ti_unit); 759 return(ENOBUFS); 760 } 761 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 762 } else { 763 m_new = m; 764 m_new->m_data = m_new->m_pktdat; 765 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 766 } 767 768 m_adj(m_new, ETHER_ALIGN); 769 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 770 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 771 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 772 r->ti_type = TI_BDTYPE_RECV_BD; 773 r->ti_flags = TI_BDFLAG_MINI_RING; 774 if (sc->arpcom.ac_if.if_hwassist) 775 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 776 r->ti_len = m_new->m_len; 777 r->ti_idx = i; 778 779 return(0); 780 } 781 782 /* 783 * Initialize a jumbo receive ring descriptor. This allocates 784 * a jumbo buffer from the pool managed internally by the driver. 785 */ 786 static int ti_newbuf_jumbo(sc, i, m) 787 struct ti_softc *sc; 788 int i; 789 struct mbuf *m; 790 { 791 struct mbuf *m_new = NULL; 792 struct ti_rx_desc *r; 793 794 if (m == NULL) { 795 caddr_t *buf = NULL; 796 797 /* Allocate the mbuf. */ 798 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 799 if (m_new == NULL) { 800 printf("ti%d: mbuf allocation failed " 801 "-- packet dropped!\n", sc->ti_unit); 802 return(ENOBUFS); 803 } 804 805 /* Allocate the jumbo buffer */ 806 buf = ti_jalloc(sc); 807 if (buf == NULL) { 808 m_freem(m_new); 809 printf("ti%d: jumbo allocation failed " 810 "-- packet dropped!\n", sc->ti_unit); 811 return(ENOBUFS); 812 } 813 814 /* Attach the buffer to the mbuf. */ 815 m_new->m_data = (void *) buf; 816 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 817 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 818 (struct ti_softc *)sc, 0, EXT_NET_DRV); 819 } else { 820 m_new = m; 821 m_new->m_data = m_new->m_ext.ext_buf; 822 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 823 } 824 825 m_adj(m_new, ETHER_ALIGN); 826 /* Set up the descriptor. */ 827 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 828 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 829 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 830 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 831 r->ti_flags = TI_BDFLAG_JUMBO_RING; 832 if (sc->arpcom.ac_if.if_hwassist) 833 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 834 r->ti_len = m_new->m_len; 835 r->ti_idx = i; 836 837 return(0); 838 } 839 840 /* 841 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 842 * that's 1MB or memory, which is a lot. For now, we fill only the first 843 * 256 ring entries and hope that our CPU is fast enough to keep up with 844 * the NIC. 845 */ 846 static int ti_init_rx_ring_std(sc) 847 struct ti_softc *sc; 848 { 849 register int i; 850 struct ti_cmd_desc cmd; 851 852 for (i = 0; i < TI_SSLOTS; i++) { 853 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 854 return(ENOBUFS); 855 }; 856 857 TI_UPDATE_STDPROD(sc, i - 1); 858 sc->ti_std = i - 1; 859 860 return(0); 861 } 862 863 static void ti_free_rx_ring_std(sc) 864 struct ti_softc *sc; 865 { 866 register int i; 867 868 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 869 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 870 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 871 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 872 } 873 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 874 sizeof(struct ti_rx_desc)); 875 } 876 877 return; 878 } 879 880 static int ti_init_rx_ring_jumbo(sc) 881 struct ti_softc *sc; 882 { 883 register int i; 884 struct ti_cmd_desc cmd; 885 886 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 887 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 888 return(ENOBUFS); 889 }; 890 891 TI_UPDATE_JUMBOPROD(sc, i - 1); 892 sc->ti_jumbo = i - 1; 893 894 return(0); 895 } 896 897 static void ti_free_rx_ring_jumbo(sc) 898 struct ti_softc *sc; 899 { 900 register int i; 901 902 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 903 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 904 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 905 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 906 } 907 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 908 sizeof(struct ti_rx_desc)); 909 } 910 911 return; 912 } 913 914 static int ti_init_rx_ring_mini(sc) 915 struct ti_softc *sc; 916 { 917 register int i; 918 919 for (i = 0; i < TI_MSLOTS; i++) { 920 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 921 return(ENOBUFS); 922 }; 923 924 TI_UPDATE_MINIPROD(sc, i - 1); 925 sc->ti_mini = i - 1; 926 927 return(0); 928 } 929 930 static void ti_free_rx_ring_mini(sc) 931 struct ti_softc *sc; 932 { 933 register int i; 934 935 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 936 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 937 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 938 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 939 } 940 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 941 sizeof(struct ti_rx_desc)); 942 } 943 944 return; 945 } 946 947 static void ti_free_tx_ring(sc) 948 struct ti_softc *sc; 949 { 950 register int i; 951 952 if (sc->ti_rdata->ti_tx_ring == NULL) 953 return; 954 955 for (i = 0; i < TI_TX_RING_CNT; i++) { 956 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 957 m_freem(sc->ti_cdata.ti_tx_chain[i]); 958 sc->ti_cdata.ti_tx_chain[i] = NULL; 959 } 960 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 961 sizeof(struct ti_tx_desc)); 962 } 963 964 return; 965 } 966 967 static int ti_init_tx_ring(sc) 968 struct ti_softc *sc; 969 { 970 sc->ti_txcnt = 0; 971 sc->ti_tx_saved_considx = 0; 972 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 973 return(0); 974 } 975 976 /* 977 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 978 * but we have to support the old way too so that Tigon 1 cards will 979 * work. 980 */ 981 void ti_add_mcast(sc, addr) 982 struct ti_softc *sc; 983 struct ether_addr *addr; 984 { 985 struct ti_cmd_desc cmd; 986 u_int16_t *m; 987 u_int32_t ext[2] = {0, 0}; 988 989 m = (u_int16_t *)&addr->octet[0]; 990 991 switch(sc->ti_hwrev) { 992 case TI_HWREV_TIGON: 993 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 994 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 995 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 996 break; 997 case TI_HWREV_TIGON_II: 998 ext[0] = htons(m[0]); 999 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1000 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1001 break; 1002 default: 1003 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1004 break; 1005 } 1006 1007 return; 1008 } 1009 1010 void ti_del_mcast(sc, addr) 1011 struct ti_softc *sc; 1012 struct ether_addr *addr; 1013 { 1014 struct ti_cmd_desc cmd; 1015 u_int16_t *m; 1016 u_int32_t ext[2] = {0, 0}; 1017 1018 m = (u_int16_t *)&addr->octet[0]; 1019 1020 switch(sc->ti_hwrev) { 1021 case TI_HWREV_TIGON: 1022 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1023 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1024 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1025 break; 1026 case TI_HWREV_TIGON_II: 1027 ext[0] = htons(m[0]); 1028 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1029 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1030 break; 1031 default: 1032 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1033 break; 1034 } 1035 1036 return; 1037 } 1038 1039 /* 1040 * Configure the Tigon's multicast address filter. 1041 * 1042 * The actual multicast table management is a bit of a pain, thanks to 1043 * slight brain damage on the part of both Alteon and us. With our 1044 * multicast code, we are only alerted when the multicast address table 1045 * changes and at that point we only have the current list of addresses: 1046 * we only know the current state, not the previous state, so we don't 1047 * actually know what addresses were removed or added. The firmware has 1048 * state, but we can't get our grubby mits on it, and there is no 'delete 1049 * all multicast addresses' command. Hence, we have to maintain our own 1050 * state so we know what addresses have been programmed into the NIC at 1051 * any given time. 1052 */ 1053 static void ti_setmulti(sc) 1054 struct ti_softc *sc; 1055 { 1056 struct ifnet *ifp; 1057 struct ifmultiaddr *ifma; 1058 struct ti_cmd_desc cmd; 1059 struct ti_mc_entry *mc; 1060 u_int32_t intrs; 1061 1062 ifp = &sc->arpcom.ac_if; 1063 1064 if (ifp->if_flags & IFF_ALLMULTI) { 1065 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1066 return; 1067 } else { 1068 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1069 } 1070 1071 /* Disable interrupts. */ 1072 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1073 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1074 1075 /* First, zot all the existing filters. */ 1076 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1077 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1078 ti_del_mcast(sc, &mc->mc_addr); 1079 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1080 free(mc, M_DEVBUF); 1081 } 1082 1083 /* Now program new ones. */ 1084 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1085 if (ifma->ifma_addr->sa_family != AF_LINK) 1086 continue; 1087 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1088 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1089 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1090 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1091 ti_add_mcast(sc, &mc->mc_addr); 1092 } 1093 1094 /* Re-enable interrupts. */ 1095 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1096 1097 return; 1098 } 1099 1100 /* 1101 * Check to see if the BIOS has configured us for a 64 bit slot when 1102 * we aren't actually in one. If we detect this condition, we can work 1103 * around it on the Tigon 2 by setting a bit in the PCI state register, 1104 * but for the Tigon 1 we must give up and abort the interface attach. 1105 */ 1106 static int ti_64bitslot_war(sc) 1107 struct ti_softc *sc; 1108 { 1109 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1110 CSR_WRITE_4(sc, 0x600, 0); 1111 CSR_WRITE_4(sc, 0x604, 0); 1112 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1113 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1114 if (sc->ti_hwrev == TI_HWREV_TIGON) 1115 return(EINVAL); 1116 else { 1117 TI_SETBIT(sc, TI_PCI_STATE, 1118 TI_PCISTATE_32BIT_BUS); 1119 return(0); 1120 } 1121 } 1122 } 1123 1124 return(0); 1125 } 1126 1127 /* 1128 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1129 * self-test results. 1130 */ 1131 static int ti_chipinit(sc) 1132 struct ti_softc *sc; 1133 { 1134 u_int32_t cacheline; 1135 u_int32_t pci_writemax = 0; 1136 1137 /* Initialize link to down state. */ 1138 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1139 1140 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1141 1142 /* Set endianness before we access any non-PCI registers. */ 1143 #if BYTE_ORDER == BIG_ENDIAN 1144 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1145 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1146 #else 1147 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1148 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1149 #endif 1150 1151 /* Check the ROM failed bit to see if self-tests passed. */ 1152 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1153 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1154 return(ENODEV); 1155 } 1156 1157 /* Halt the CPU. */ 1158 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1159 1160 /* Figure out the hardware revision. */ 1161 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1162 case TI_REV_TIGON_I: 1163 sc->ti_hwrev = TI_HWREV_TIGON; 1164 break; 1165 case TI_REV_TIGON_II: 1166 sc->ti_hwrev = TI_HWREV_TIGON_II; 1167 break; 1168 default: 1169 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1170 return(ENODEV); 1171 } 1172 1173 /* Do special setup for Tigon 2. */ 1174 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1175 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1176 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1177 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1178 } 1179 1180 /* Set up the PCI state register. */ 1181 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1182 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1183 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1184 } 1185 1186 /* Clear the read/write max DMA parameters. */ 1187 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1188 TI_PCISTATE_READ_MAXDMA)); 1189 1190 /* Get cache line size. */ 1191 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1192 1193 /* 1194 * If the system has set enabled the PCI memory write 1195 * and invalidate command in the command register, set 1196 * the write max parameter accordingly. This is necessary 1197 * to use MWI with the Tigon 2. 1198 */ 1199 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1200 switch(cacheline) { 1201 case 1: 1202 case 4: 1203 case 8: 1204 case 16: 1205 case 32: 1206 case 64: 1207 break; 1208 default: 1209 /* Disable PCI memory write and invalidate. */ 1210 if (bootverbose) 1211 printf("ti%d: cache line size %d not " 1212 "supported; disabling PCI MWI\n", 1213 sc->ti_unit, cacheline); 1214 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1215 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1216 break; 1217 } 1218 } 1219 1220 #ifdef __brokenalpha__ 1221 /* 1222 * From the Alteon sample driver: 1223 * Must insure that we do not cross an 8K (bytes) boundary 1224 * for DMA reads. Our highest limit is 1K bytes. This is a 1225 * restriction on some ALPHA platforms with early revision 1226 * 21174 PCI chipsets, such as the AlphaPC 164lx 1227 */ 1228 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1229 #else 1230 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1231 #endif 1232 1233 /* This sets the min dma param all the way up (0xff). */ 1234 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1235 1236 /* Configure DMA variables. */ 1237 #if BYTE_ORDER == BIG_ENDIAN 1238 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1239 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1240 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1241 TI_OPMODE_DONT_FRAG_JUMBO); 1242 #else 1243 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1244 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1245 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1246 #endif 1247 1248 /* 1249 * Only allow 1 DMA channel to be active at a time. 1250 * I don't think this is a good idea, but without it 1251 * the firmware racks up lots of nicDmaReadRingFull 1252 * errors. This is not compatible with hardware checksums. 1253 */ 1254 if (sc->arpcom.ac_if.if_hwassist == 0) 1255 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1256 1257 /* Recommended settings from Tigon manual. */ 1258 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1259 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1260 1261 if (ti_64bitslot_war(sc)) { 1262 printf("ti%d: bios thinks we're in a 64 bit slot, " 1263 "but we aren't", sc->ti_unit); 1264 return(EINVAL); 1265 } 1266 1267 return(0); 1268 } 1269 1270 /* 1271 * Initialize the general information block and firmware, and 1272 * start the CPU(s) running. 1273 */ 1274 static int ti_gibinit(sc) 1275 struct ti_softc *sc; 1276 { 1277 struct ti_rcb *rcb; 1278 int i; 1279 struct ifnet *ifp; 1280 1281 ifp = &sc->arpcom.ac_if; 1282 1283 /* Disable interrupts for now. */ 1284 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1285 1286 /* Tell the chip where to find the general information block. */ 1287 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1288 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1289 1290 /* Load the firmware into SRAM. */ 1291 ti_loadfw(sc); 1292 1293 /* Set up the contents of the general info and ring control blocks. */ 1294 1295 /* Set up the event ring and producer pointer. */ 1296 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1297 1298 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1299 rcb->ti_flags = 0; 1300 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1301 vtophys(&sc->ti_ev_prodidx); 1302 sc->ti_ev_prodidx.ti_idx = 0; 1303 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1304 sc->ti_ev_saved_considx = 0; 1305 1306 /* Set up the command ring and producer mailbox. */ 1307 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1308 1309 sc->ti_rdata->ti_cmd_ring = 1310 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1311 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1312 rcb->ti_flags = 0; 1313 rcb->ti_max_len = 0; 1314 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1315 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1316 } 1317 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1318 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1319 sc->ti_cmd_saved_prodidx = 0; 1320 1321 /* 1322 * Assign the address of the stats refresh buffer. 1323 * We re-use the current stats buffer for this to 1324 * conserve memory. 1325 */ 1326 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1327 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1328 1329 /* Set up the standard receive ring. */ 1330 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1331 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1332 rcb->ti_max_len = TI_FRAMELEN; 1333 rcb->ti_flags = 0; 1334 if (sc->arpcom.ac_if.if_hwassist) 1335 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1336 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1337 #if NVLAN > 0 1338 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1339 #endif 1340 1341 /* Set up the jumbo receive ring. */ 1342 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1343 TI_HOSTADDR(rcb->ti_hostaddr) = 1344 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1345 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1346 rcb->ti_flags = 0; 1347 if (sc->arpcom.ac_if.if_hwassist) 1348 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1349 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1350 #if NVLAN > 0 1351 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1352 #endif 1353 1354 /* 1355 * Set up the mini ring. Only activated on the 1356 * Tigon 2 but the slot in the config block is 1357 * still there on the Tigon 1. 1358 */ 1359 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1360 TI_HOSTADDR(rcb->ti_hostaddr) = 1361 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1362 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1363 if (sc->ti_hwrev == TI_HWREV_TIGON) 1364 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1365 else 1366 rcb->ti_flags = 0; 1367 if (sc->arpcom.ac_if.if_hwassist) 1368 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1369 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1370 #if NVLAN > 0 1371 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1372 #endif 1373 1374 /* 1375 * Set up the receive return ring. 1376 */ 1377 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1378 TI_HOSTADDR(rcb->ti_hostaddr) = 1379 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1380 rcb->ti_flags = 0; 1381 rcb->ti_max_len = TI_RETURN_RING_CNT; 1382 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1383 vtophys(&sc->ti_return_prodidx); 1384 1385 /* 1386 * Set up the tx ring. Note: for the Tigon 2, we have the option 1387 * of putting the transmit ring in the host's address space and 1388 * letting the chip DMA it instead of leaving the ring in the NIC's 1389 * memory and accessing it through the shared memory region. We 1390 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1391 * so we have to revert to the shared memory scheme if we detect 1392 * a Tigon 1 chip. 1393 */ 1394 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1395 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1396 sc->ti_rdata->ti_tx_ring_nic = 1397 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1398 } 1399 bzero((char *)sc->ti_rdata->ti_tx_ring, 1400 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1401 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1402 if (sc->ti_hwrev == TI_HWREV_TIGON) 1403 rcb->ti_flags = 0; 1404 else 1405 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1406 #if NVLAN > 0 1407 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1408 #endif 1409 if (sc->arpcom.ac_if.if_hwassist) 1410 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1411 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1412 rcb->ti_max_len = TI_TX_RING_CNT; 1413 if (sc->ti_hwrev == TI_HWREV_TIGON) 1414 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1415 else 1416 TI_HOSTADDR(rcb->ti_hostaddr) = 1417 vtophys(&sc->ti_rdata->ti_tx_ring); 1418 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1419 vtophys(&sc->ti_tx_considx); 1420 1421 /* Set up tuneables */ 1422 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1423 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1424 (sc->ti_rx_coal_ticks / 10)); 1425 else 1426 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1427 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1428 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1429 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1430 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1431 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1432 1433 /* Turn interrupts on. */ 1434 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1435 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1436 1437 /* Start CPU. */ 1438 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1439 1440 return(0); 1441 } 1442 1443 /* 1444 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1445 * against our list and return its name if we find a match. 1446 */ 1447 static int ti_probe(dev) 1448 device_t dev; 1449 { 1450 struct ti_type *t; 1451 1452 t = ti_devs; 1453 1454 while(t->ti_name != NULL) { 1455 if ((pci_get_vendor(dev) == t->ti_vid) && 1456 (pci_get_device(dev) == t->ti_did)) { 1457 device_set_desc(dev, t->ti_name); 1458 return(0); 1459 } 1460 t++; 1461 } 1462 1463 return(ENXIO); 1464 } 1465 1466 static int ti_attach(dev) 1467 device_t dev; 1468 { 1469 u_int32_t command; 1470 struct ifnet *ifp; 1471 struct ti_softc *sc; 1472 int unit, error = 0, rid; 1473 1474 sc = device_get_softc(dev); 1475 unit = device_get_unit(dev); 1476 bzero(sc, sizeof(struct ti_softc)); 1477 1478 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1479 TI_LOCK(sc); 1480 1481 /* 1482 * Map control/status registers. 1483 */ 1484 command = pci_read_config(dev, PCIR_COMMAND, 4); 1485 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1486 pci_write_config(dev, PCIR_COMMAND, command, 4); 1487 command = pci_read_config(dev, PCIR_COMMAND, 4); 1488 1489 if (!(command & PCIM_CMD_MEMEN)) { 1490 printf("ti%d: failed to enable memory mapping!\n", unit); 1491 error = ENXIO; 1492 goto fail; 1493 } 1494 1495 rid = TI_PCI_LOMEM; 1496 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1497 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1498 1499 if (sc->ti_res == NULL) { 1500 printf ("ti%d: couldn't map memory\n", unit); 1501 error = ENXIO; 1502 goto fail; 1503 } 1504 1505 sc->ti_btag = rman_get_bustag(sc->ti_res); 1506 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1507 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1508 1509 /* Allocate interrupt */ 1510 rid = 0; 1511 1512 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1513 RF_SHAREABLE | RF_ACTIVE); 1514 1515 if (sc->ti_irq == NULL) { 1516 printf("ti%d: couldn't map interrupt\n", unit); 1517 error = ENXIO; 1518 goto fail; 1519 } 1520 1521 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1522 ti_intr, sc, &sc->ti_intrhand); 1523 1524 if (error) { 1525 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1526 bus_release_resource(dev, SYS_RES_MEMORY, 1527 TI_PCI_LOMEM, sc->ti_res); 1528 printf("ti%d: couldn't set up irq\n", unit); 1529 goto fail; 1530 } 1531 1532 sc->ti_unit = unit; 1533 1534 if (ti_chipinit(sc)) { 1535 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1536 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1537 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1538 bus_release_resource(dev, SYS_RES_MEMORY, 1539 TI_PCI_LOMEM, sc->ti_res); 1540 error = ENXIO; 1541 goto fail; 1542 } 1543 1544 /* Zero out the NIC's on-board SRAM. */ 1545 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1546 1547 /* Init again -- zeroing memory may have clobbered some registers. */ 1548 if (ti_chipinit(sc)) { 1549 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1550 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1551 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1552 bus_release_resource(dev, SYS_RES_MEMORY, 1553 TI_PCI_LOMEM, sc->ti_res); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 /* 1559 * Get station address from the EEPROM. Note: the manual states 1560 * that the MAC address is at offset 0x8c, however the data is 1561 * stored as two longwords (since that's how it's loaded into 1562 * the NIC). This means the MAC address is actually preceeded 1563 * by two zero bytes. We need to skip over those. 1564 */ 1565 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1566 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1567 printf("ti%d: failed to read station address\n", unit); 1568 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1569 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1570 bus_release_resource(dev, SYS_RES_MEMORY, 1571 TI_PCI_LOMEM, sc->ti_res); 1572 error = ENXIO; 1573 goto fail; 1574 } 1575 1576 /* 1577 * A Tigon chip was detected. Inform the world. 1578 */ 1579 printf("ti%d: Ethernet address: %6D\n", unit, 1580 sc->arpcom.ac_enaddr, ":"); 1581 1582 /* Allocate the general information block and ring buffers. */ 1583 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1584 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1585 1586 if (sc->ti_rdata == NULL) { 1587 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1589 bus_release_resource(dev, SYS_RES_MEMORY, 1590 TI_PCI_LOMEM, sc->ti_res); 1591 error = ENXIO; 1592 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1593 goto fail; 1594 } 1595 1596 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1597 1598 /* Try to allocate memory for jumbo buffers. */ 1599 if (ti_alloc_jumbo_mem(sc)) { 1600 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1601 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1602 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1603 bus_release_resource(dev, SYS_RES_MEMORY, 1604 TI_PCI_LOMEM, sc->ti_res); 1605 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1606 M_DEVBUF); 1607 error = ENXIO; 1608 goto fail; 1609 } 1610 1611 /* 1612 * We really need a better way to tell a 1000baseTX card 1613 * from a 1000baseSX one, since in theory there could be 1614 * OEMed 1000baseTX cards from lame vendors who aren't 1615 * clever enough to change the PCI ID. For the moment 1616 * though, the AceNIC is the only copper card available. 1617 */ 1618 if (pci_get_vendor(dev) == ALT_VENDORID && 1619 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1620 sc->ti_copper = 1; 1621 /* Ok, it's not the only copper card available. */ 1622 if (pci_get_vendor(dev) == NG_VENDORID && 1623 pci_get_device(dev) == NG_DEVICEID_GA620T) 1624 sc->ti_copper = 1; 1625 1626 /* Set default tuneable values. */ 1627 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1628 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1629 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1630 sc->ti_rx_max_coal_bds = 64; 1631 sc->ti_tx_max_coal_bds = 128; 1632 sc->ti_tx_buf_ratio = 21; 1633 1634 /* Set up ifnet structure */ 1635 ifp = &sc->arpcom.ac_if; 1636 ifp->if_softc = sc; 1637 ifp->if_unit = sc->ti_unit; 1638 ifp->if_name = "ti"; 1639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1640 ifp->if_ioctl = ti_ioctl; 1641 ifp->if_output = ether_output; 1642 ifp->if_start = ti_start; 1643 ifp->if_watchdog = ti_watchdog; 1644 ifp->if_init = ti_init; 1645 ifp->if_mtu = ETHERMTU; 1646 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1647 1648 /* Set up ifmedia support. */ 1649 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1650 if (sc->ti_copper) { 1651 /* 1652 * Copper cards allow manual 10/100 mode selection, 1653 * but not manual 1000baseTX mode selection. Why? 1654 * Becuase currently there's no way to specify the 1655 * master/slave setting through the firmware interface, 1656 * so Alteon decided to just bag it and handle it 1657 * via autonegotiation. 1658 */ 1659 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1660 ifmedia_add(&sc->ifmedia, 1661 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1662 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1663 ifmedia_add(&sc->ifmedia, 1664 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1665 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1666 ifmedia_add(&sc->ifmedia, 1667 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1668 } else { 1669 /* Fiber cards don't support 10/100 modes. */ 1670 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1671 ifmedia_add(&sc->ifmedia, 1672 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1673 } 1674 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1675 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1676 1677 /* 1678 * Call MI attach routine. 1679 */ 1680 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1681 TI_UNLOCK(sc); 1682 return(0); 1683 1684 fail: 1685 TI_UNLOCK(sc); 1686 mtx_destroy(&sc->ti_mtx); 1687 return(error); 1688 } 1689 1690 static int ti_detach(dev) 1691 device_t dev; 1692 { 1693 struct ti_softc *sc; 1694 struct ifnet *ifp; 1695 1696 1697 sc = device_get_softc(dev); 1698 TI_LOCK(sc); 1699 ifp = &sc->arpcom.ac_if; 1700 1701 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1702 ti_stop(sc); 1703 1704 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1705 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1706 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1707 1708 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1709 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1710 ifmedia_removeall(&sc->ifmedia); 1711 1712 TI_UNLOCK(sc); 1713 mtx_destroy(&sc->ti_mtx); 1714 1715 return(0); 1716 } 1717 1718 /* 1719 * Frame reception handling. This is called if there's a frame 1720 * on the receive return list. 1721 * 1722 * Note: we have to be able to handle three possibilities here: 1723 * 1) the frame is from the mini receive ring (can only happen) 1724 * on Tigon 2 boards) 1725 * 2) the frame is from the jumbo recieve ring 1726 * 3) the frame is from the standard receive ring 1727 */ 1728 1729 static void ti_rxeof(sc) 1730 struct ti_softc *sc; 1731 { 1732 struct ifnet *ifp; 1733 struct ti_cmd_desc cmd; 1734 1735 ifp = &sc->arpcom.ac_if; 1736 1737 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1738 struct ti_rx_desc *cur_rx; 1739 u_int32_t rxidx; 1740 struct ether_header *eh; 1741 struct mbuf *m = NULL; 1742 #if NVLAN > 0 1743 u_int16_t vlan_tag = 0; 1744 int have_tag = 0; 1745 #endif 1746 1747 cur_rx = 1748 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1749 rxidx = cur_rx->ti_idx; 1750 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1751 1752 #if NVLAN > 0 1753 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1754 have_tag = 1; 1755 vlan_tag = cur_rx->ti_vlan_tag; 1756 } 1757 #endif 1758 1759 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1760 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1761 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1762 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1763 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1764 ifp->if_ierrors++; 1765 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1766 continue; 1767 } 1768 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1769 ifp->if_ierrors++; 1770 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1771 continue; 1772 } 1773 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1774 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1775 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1776 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1777 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1778 ifp->if_ierrors++; 1779 ti_newbuf_mini(sc, sc->ti_mini, m); 1780 continue; 1781 } 1782 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1783 ifp->if_ierrors++; 1784 ti_newbuf_mini(sc, sc->ti_mini, m); 1785 continue; 1786 } 1787 } else { 1788 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1789 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1790 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1791 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1792 ifp->if_ierrors++; 1793 ti_newbuf_std(sc, sc->ti_std, m); 1794 continue; 1795 } 1796 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1797 ifp->if_ierrors++; 1798 ti_newbuf_std(sc, sc->ti_std, m); 1799 continue; 1800 } 1801 } 1802 1803 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1804 ifp->if_ipackets++; 1805 eh = mtod(m, struct ether_header *); 1806 m->m_pkthdr.rcvif = ifp; 1807 1808 /* Remove header from mbuf and pass it on. */ 1809 m_adj(m, sizeof(struct ether_header)); 1810 1811 if (ifp->if_hwassist) { 1812 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1813 CSUM_DATA_VALID; 1814 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1815 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1816 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1817 } 1818 1819 #if NVLAN > 0 1820 /* 1821 * If we received a packet with a vlan tag, pass it 1822 * to vlan_input() instead of ether_input(). 1823 */ 1824 if (have_tag) { 1825 vlan_input_tag(eh, m, vlan_tag); 1826 have_tag = vlan_tag = 0; 1827 continue; 1828 } 1829 #endif 1830 ether_input(ifp, eh, m); 1831 } 1832 1833 /* Only necessary on the Tigon 1. */ 1834 if (sc->ti_hwrev == TI_HWREV_TIGON) 1835 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1836 sc->ti_rx_saved_considx); 1837 1838 TI_UPDATE_STDPROD(sc, sc->ti_std); 1839 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1840 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1841 1842 return; 1843 } 1844 1845 static void ti_txeof(sc) 1846 struct ti_softc *sc; 1847 { 1848 struct ti_tx_desc *cur_tx = NULL; 1849 struct ifnet *ifp; 1850 1851 ifp = &sc->arpcom.ac_if; 1852 1853 /* 1854 * Go through our tx ring and free mbufs for those 1855 * frames that have been sent. 1856 */ 1857 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1858 u_int32_t idx = 0; 1859 1860 idx = sc->ti_tx_saved_considx; 1861 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1862 if (idx > 383) 1863 CSR_WRITE_4(sc, TI_WINBASE, 1864 TI_TX_RING_BASE + 6144); 1865 else if (idx > 255) 1866 CSR_WRITE_4(sc, TI_WINBASE, 1867 TI_TX_RING_BASE + 4096); 1868 else if (idx > 127) 1869 CSR_WRITE_4(sc, TI_WINBASE, 1870 TI_TX_RING_BASE + 2048); 1871 else 1872 CSR_WRITE_4(sc, TI_WINBASE, 1873 TI_TX_RING_BASE); 1874 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1875 } else 1876 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1877 if (cur_tx->ti_flags & TI_BDFLAG_END) 1878 ifp->if_opackets++; 1879 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1880 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1881 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1882 } 1883 sc->ti_txcnt--; 1884 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1885 ifp->if_timer = 0; 1886 } 1887 1888 if (cur_tx != NULL) 1889 ifp->if_flags &= ~IFF_OACTIVE; 1890 1891 return; 1892 } 1893 1894 static void ti_intr(xsc) 1895 void *xsc; 1896 { 1897 struct ti_softc *sc; 1898 struct ifnet *ifp; 1899 1900 sc = xsc; 1901 TI_LOCK(sc); 1902 ifp = &sc->arpcom.ac_if; 1903 1904 #ifdef notdef 1905 /* Avoid this for now -- checking this register is expensive. */ 1906 /* Make sure this is really our interrupt. */ 1907 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 1908 TI_UNLOCK(sc); 1909 return; 1910 } 1911 #endif 1912 1913 /* Ack interrupt and stop others from occuring. */ 1914 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1915 1916 if (ifp->if_flags & IFF_RUNNING) { 1917 /* Check RX return ring producer/consumer */ 1918 ti_rxeof(sc); 1919 1920 /* Check TX ring producer/consumer */ 1921 ti_txeof(sc); 1922 } 1923 1924 ti_handle_events(sc); 1925 1926 /* Re-enable interrupts. */ 1927 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1928 1929 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1930 ti_start(ifp); 1931 1932 TI_UNLOCK(sc); 1933 1934 return; 1935 } 1936 1937 static void ti_stats_update(sc) 1938 struct ti_softc *sc; 1939 { 1940 struct ifnet *ifp; 1941 1942 ifp = &sc->arpcom.ac_if; 1943 1944 ifp->if_collisions += 1945 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 1946 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 1947 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 1948 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 1949 ifp->if_collisions; 1950 1951 return; 1952 } 1953 1954 /* 1955 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 1956 * pointers to descriptors. 1957 */ 1958 static int ti_encap(sc, m_head, txidx) 1959 struct ti_softc *sc; 1960 struct mbuf *m_head; 1961 u_int32_t *txidx; 1962 { 1963 struct ti_tx_desc *f = NULL; 1964 struct mbuf *m; 1965 u_int32_t frag, cur, cnt = 0; 1966 u_int16_t csum_flags = 0; 1967 #if NVLAN > 0 1968 struct ifvlan *ifv = NULL; 1969 1970 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1971 m_head->m_pkthdr.rcvif != NULL && 1972 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1973 ifv = m_head->m_pkthdr.rcvif->if_softc; 1974 #endif 1975 1976 m = m_head; 1977 cur = frag = *txidx; 1978 1979 if (m_head->m_pkthdr.csum_flags) { 1980 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1981 csum_flags |= TI_BDFLAG_IP_CKSUM; 1982 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 1983 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 1984 if (m_head->m_flags & M_LASTFRAG) 1985 csum_flags |= TI_BDFLAG_IP_FRAG_END; 1986 else if (m_head->m_flags & M_FRAG) 1987 csum_flags |= TI_BDFLAG_IP_FRAG; 1988 } 1989 /* 1990 * Start packing the mbufs in this chain into 1991 * the fragment pointers. Stop when we run out 1992 * of fragments or hit the end of the mbuf chain. 1993 */ 1994 for (m = m_head; m != NULL; m = m->m_next) { 1995 if (m->m_len != 0) { 1996 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1997 if (frag > 383) 1998 CSR_WRITE_4(sc, TI_WINBASE, 1999 TI_TX_RING_BASE + 6144); 2000 else if (frag > 255) 2001 CSR_WRITE_4(sc, TI_WINBASE, 2002 TI_TX_RING_BASE + 4096); 2003 else if (frag > 127) 2004 CSR_WRITE_4(sc, TI_WINBASE, 2005 TI_TX_RING_BASE + 2048); 2006 else 2007 CSR_WRITE_4(sc, TI_WINBASE, 2008 TI_TX_RING_BASE); 2009 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2010 } else 2011 f = &sc->ti_rdata->ti_tx_ring[frag]; 2012 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2013 break; 2014 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2015 f->ti_len = m->m_len; 2016 f->ti_flags = csum_flags; 2017 #if NVLAN > 0 2018 if (ifv != NULL) { 2019 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2020 f->ti_vlan_tag = ifv->ifv_tag; 2021 } else { 2022 f->ti_vlan_tag = 0; 2023 } 2024 #endif 2025 /* 2026 * Sanity check: avoid coming within 16 descriptors 2027 * of the end of the ring. 2028 */ 2029 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2030 return(ENOBUFS); 2031 cur = frag; 2032 TI_INC(frag, TI_TX_RING_CNT); 2033 cnt++; 2034 } 2035 } 2036 2037 if (m != NULL) 2038 return(ENOBUFS); 2039 2040 if (frag == sc->ti_tx_saved_considx) 2041 return(ENOBUFS); 2042 2043 if (sc->ti_hwrev == TI_HWREV_TIGON) 2044 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2045 TI_BDFLAG_END; 2046 else 2047 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2048 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2049 sc->ti_txcnt += cnt; 2050 2051 *txidx = frag; 2052 2053 return(0); 2054 } 2055 2056 /* 2057 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2058 * to the mbuf data regions directly in the transmit descriptors. 2059 */ 2060 static void ti_start(ifp) 2061 struct ifnet *ifp; 2062 { 2063 struct ti_softc *sc; 2064 struct mbuf *m_head = NULL; 2065 u_int32_t prodidx = 0; 2066 2067 sc = ifp->if_softc; 2068 TI_LOCK(sc); 2069 2070 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2071 2072 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2073 IF_DEQUEUE(&ifp->if_snd, m_head); 2074 if (m_head == NULL) 2075 break; 2076 2077 /* 2078 * XXX 2079 * safety overkill. If this is a fragmented packet chain 2080 * with delayed TCP/UDP checksums, then only encapsulate 2081 * it if we have enough descriptors to handle the entire 2082 * chain at once. 2083 * (paranoia -- may not actually be needed) 2084 */ 2085 if (m_head->m_flags & M_FIRSTFRAG && 2086 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2087 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2088 m_head->m_pkthdr.csum_data + 16) { 2089 IF_PREPEND(&ifp->if_snd, m_head); 2090 ifp->if_flags |= IFF_OACTIVE; 2091 break; 2092 } 2093 } 2094 2095 /* 2096 * Pack the data into the transmit ring. If we 2097 * don't have room, set the OACTIVE flag and wait 2098 * for the NIC to drain the ring. 2099 */ 2100 if (ti_encap(sc, m_head, &prodidx)) { 2101 IF_PREPEND(&ifp->if_snd, m_head); 2102 ifp->if_flags |= IFF_OACTIVE; 2103 break; 2104 } 2105 2106 /* 2107 * If there's a BPF listener, bounce a copy of this frame 2108 * to him. 2109 */ 2110 if (ifp->if_bpf) 2111 bpf_mtap(ifp, m_head); 2112 } 2113 2114 /* Transmit */ 2115 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2116 2117 /* 2118 * Set a timeout in case the chip goes out to lunch. 2119 */ 2120 ifp->if_timer = 5; 2121 TI_UNLOCK(sc); 2122 2123 return; 2124 } 2125 2126 static void ti_init(xsc) 2127 void *xsc; 2128 { 2129 struct ti_softc *sc = xsc; 2130 2131 /* Cancel pending I/O and flush buffers. */ 2132 ti_stop(sc); 2133 2134 TI_LOCK(sc); 2135 /* Init the gen info block, ring control blocks and firmware. */ 2136 if (ti_gibinit(sc)) { 2137 printf("ti%d: initialization failure\n", sc->ti_unit); 2138 TI_UNLOCK(sc); 2139 return; 2140 } 2141 2142 TI_UNLOCK(sc); 2143 2144 return; 2145 } 2146 2147 static void ti_init2(sc) 2148 struct ti_softc *sc; 2149 { 2150 struct ti_cmd_desc cmd; 2151 struct ifnet *ifp; 2152 u_int16_t *m; 2153 struct ifmedia *ifm; 2154 int tmp; 2155 2156 ifp = &sc->arpcom.ac_if; 2157 2158 /* Specify MTU and interface index. */ 2159 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2160 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2161 ETHER_HDR_LEN + ETHER_CRC_LEN); 2162 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2163 2164 /* Load our MAC address. */ 2165 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2166 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2167 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2168 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2169 2170 /* Enable or disable promiscuous mode as needed. */ 2171 if (ifp->if_flags & IFF_PROMISC) { 2172 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2173 } else { 2174 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2175 } 2176 2177 /* Program multicast filter. */ 2178 ti_setmulti(sc); 2179 2180 /* 2181 * If this is a Tigon 1, we should tell the 2182 * firmware to use software packet filtering. 2183 */ 2184 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2185 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2186 } 2187 2188 /* Init RX ring. */ 2189 ti_init_rx_ring_std(sc); 2190 2191 /* Init jumbo RX ring. */ 2192 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2193 ti_init_rx_ring_jumbo(sc); 2194 2195 /* 2196 * If this is a Tigon 2, we can also configure the 2197 * mini ring. 2198 */ 2199 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2200 ti_init_rx_ring_mini(sc); 2201 2202 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2203 sc->ti_rx_saved_considx = 0; 2204 2205 /* Init TX ring. */ 2206 ti_init_tx_ring(sc); 2207 2208 /* Tell firmware we're alive. */ 2209 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2210 2211 /* Enable host interrupts. */ 2212 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2213 2214 ifp->if_flags |= IFF_RUNNING; 2215 ifp->if_flags &= ~IFF_OACTIVE; 2216 2217 /* 2218 * Make sure to set media properly. We have to do this 2219 * here since we have to issue commands in order to set 2220 * the link negotiation and we can't issue commands until 2221 * the firmware is running. 2222 */ 2223 ifm = &sc->ifmedia; 2224 tmp = ifm->ifm_media; 2225 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2226 ti_ifmedia_upd(ifp); 2227 ifm->ifm_media = tmp; 2228 2229 return; 2230 } 2231 2232 /* 2233 * Set media options. 2234 */ 2235 static int ti_ifmedia_upd(ifp) 2236 struct ifnet *ifp; 2237 { 2238 struct ti_softc *sc; 2239 struct ifmedia *ifm; 2240 struct ti_cmd_desc cmd; 2241 2242 sc = ifp->if_softc; 2243 ifm = &sc->ifmedia; 2244 2245 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2246 return(EINVAL); 2247 2248 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2249 case IFM_AUTO: 2250 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2251 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2252 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2253 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2254 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2255 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2256 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2257 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2258 break; 2259 case IFM_1000_SX: 2260 case IFM_1000_TX: 2261 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2262 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2263 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2264 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2265 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2266 } 2267 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2268 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2269 break; 2270 case IFM_100_FX: 2271 case IFM_10_FL: 2272 case IFM_100_TX: 2273 case IFM_10_T: 2274 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2275 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2276 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2277 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2278 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2279 } else { 2280 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2281 } 2282 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2283 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2284 } else { 2285 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2286 } 2287 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2288 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2289 break; 2290 } 2291 2292 return(0); 2293 } 2294 2295 /* 2296 * Report current media status. 2297 */ 2298 static void ti_ifmedia_sts(ifp, ifmr) 2299 struct ifnet *ifp; 2300 struct ifmediareq *ifmr; 2301 { 2302 struct ti_softc *sc; 2303 u_int32_t media = 0; 2304 2305 sc = ifp->if_softc; 2306 2307 ifmr->ifm_status = IFM_AVALID; 2308 ifmr->ifm_active = IFM_ETHER; 2309 2310 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2311 return; 2312 2313 ifmr->ifm_status |= IFM_ACTIVE; 2314 2315 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2316 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2317 if (sc->ti_copper) 2318 ifmr->ifm_active |= IFM_1000_TX; 2319 else 2320 ifmr->ifm_active |= IFM_1000_SX; 2321 if (media & TI_GLNK_FULL_DUPLEX) 2322 ifmr->ifm_active |= IFM_FDX; 2323 else 2324 ifmr->ifm_active |= IFM_HDX; 2325 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2326 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2327 if (sc->ti_copper) { 2328 if (media & TI_LNK_100MB) 2329 ifmr->ifm_active |= IFM_100_TX; 2330 if (media & TI_LNK_10MB) 2331 ifmr->ifm_active |= IFM_10_T; 2332 } else { 2333 if (media & TI_LNK_100MB) 2334 ifmr->ifm_active |= IFM_100_FX; 2335 if (media & TI_LNK_10MB) 2336 ifmr->ifm_active |= IFM_10_FL; 2337 } 2338 if (media & TI_LNK_FULL_DUPLEX) 2339 ifmr->ifm_active |= IFM_FDX; 2340 if (media & TI_LNK_HALF_DUPLEX) 2341 ifmr->ifm_active |= IFM_HDX; 2342 } 2343 2344 return; 2345 } 2346 2347 static int ti_ioctl(ifp, command, data) 2348 struct ifnet *ifp; 2349 u_long command; 2350 caddr_t data; 2351 { 2352 struct ti_softc *sc = ifp->if_softc; 2353 struct ifreq *ifr = (struct ifreq *) data; 2354 int error = 0; 2355 struct ti_cmd_desc cmd; 2356 2357 TI_LOCK(sc); 2358 2359 switch(command) { 2360 case SIOCSIFADDR: 2361 case SIOCGIFADDR: 2362 error = ether_ioctl(ifp, command, data); 2363 break; 2364 case SIOCSIFMTU: 2365 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2366 error = EINVAL; 2367 else { 2368 ifp->if_mtu = ifr->ifr_mtu; 2369 ti_init(sc); 2370 } 2371 break; 2372 case SIOCSIFFLAGS: 2373 if (ifp->if_flags & IFF_UP) { 2374 /* 2375 * If only the state of the PROMISC flag changed, 2376 * then just use the 'set promisc mode' command 2377 * instead of reinitializing the entire NIC. Doing 2378 * a full re-init means reloading the firmware and 2379 * waiting for it to start up, which may take a 2380 * second or two. 2381 */ 2382 if (ifp->if_flags & IFF_RUNNING && 2383 ifp->if_flags & IFF_PROMISC && 2384 !(sc->ti_if_flags & IFF_PROMISC)) { 2385 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2386 TI_CMD_CODE_PROMISC_ENB, 0); 2387 } else if (ifp->if_flags & IFF_RUNNING && 2388 !(ifp->if_flags & IFF_PROMISC) && 2389 sc->ti_if_flags & IFF_PROMISC) { 2390 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2391 TI_CMD_CODE_PROMISC_DIS, 0); 2392 } else 2393 ti_init(sc); 2394 } else { 2395 if (ifp->if_flags & IFF_RUNNING) { 2396 ti_stop(sc); 2397 } 2398 } 2399 sc->ti_if_flags = ifp->if_flags; 2400 error = 0; 2401 break; 2402 case SIOCADDMULTI: 2403 case SIOCDELMULTI: 2404 if (ifp->if_flags & IFF_RUNNING) { 2405 ti_setmulti(sc); 2406 error = 0; 2407 } 2408 break; 2409 case SIOCSIFMEDIA: 2410 case SIOCGIFMEDIA: 2411 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2412 break; 2413 default: 2414 error = EINVAL; 2415 break; 2416 } 2417 2418 TI_UNLOCK(sc); 2419 2420 return(error); 2421 } 2422 2423 static void ti_watchdog(ifp) 2424 struct ifnet *ifp; 2425 { 2426 struct ti_softc *sc; 2427 2428 sc = ifp->if_softc; 2429 TI_LOCK(sc); 2430 2431 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2432 ti_stop(sc); 2433 ti_init(sc); 2434 2435 ifp->if_oerrors++; 2436 TI_UNLOCK(sc); 2437 2438 return; 2439 } 2440 2441 /* 2442 * Stop the adapter and free any mbufs allocated to the 2443 * RX and TX lists. 2444 */ 2445 static void ti_stop(sc) 2446 struct ti_softc *sc; 2447 { 2448 struct ifnet *ifp; 2449 struct ti_cmd_desc cmd; 2450 2451 TI_LOCK(sc); 2452 2453 ifp = &sc->arpcom.ac_if; 2454 2455 /* Disable host interrupts. */ 2456 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2457 /* 2458 * Tell firmware we're shutting down. 2459 */ 2460 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2461 2462 /* Halt and reinitialize. */ 2463 ti_chipinit(sc); 2464 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2465 ti_chipinit(sc); 2466 2467 /* Free the RX lists. */ 2468 ti_free_rx_ring_std(sc); 2469 2470 /* Free jumbo RX list. */ 2471 ti_free_rx_ring_jumbo(sc); 2472 2473 /* Free mini RX list. */ 2474 ti_free_rx_ring_mini(sc); 2475 2476 /* Free TX buffers. */ 2477 ti_free_tx_ring(sc); 2478 2479 sc->ti_ev_prodidx.ti_idx = 0; 2480 sc->ti_return_prodidx.ti_idx = 0; 2481 sc->ti_tx_considx.ti_idx = 0; 2482 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2483 2484 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2485 TI_UNLOCK(sc); 2486 2487 return; 2488 } 2489 2490 /* 2491 * Stop all chip I/O so that the kernel's probe routines don't 2492 * get confused by errant DMAs when rebooting. 2493 */ 2494 static void ti_shutdown(dev) 2495 device_t dev; 2496 { 2497 struct ti_softc *sc; 2498 2499 sc = device_get_softc(dev); 2500 TI_LOCK(sc); 2501 ti_chipinit(sc); 2502 TI_UNLOCK(sc); 2503 2504 return; 2505 } 2506