1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/queue.h> 91 92 #include <net/if.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <pci/pcireg.h> 119 #include <pci/pcivar.h> 120 121 #include <pci/if_tireg.h> 122 #include <pci/ti_fw.h> 123 #include <pci/ti_fw2.h> 124 125 #ifdef M_HWCKSUM 126 /*#define TI_CSUM_OFFLOAD*/ 127 #endif 128 129 #if !defined(lint) 130 static const char rcsid[] = 131 "$FreeBSD$"; 132 #endif 133 134 /* 135 * Various supported device vendors/types and their names. 136 */ 137 138 static struct ti_type ti_devs[] = { 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 140 "Alteon AceNIC Gigabit Ethernet" }, 141 { TC_VENDORID, TC_DEVICEID_3C985, 142 "3Com 3c985-SX Gigabit Ethernet" }, 143 { NG_VENDORID, NG_DEVICEID_GA620, 144 "Netgear GA620 Gigabit Ethernet" }, 145 { SGI_VENDORID, SGI_DEVICEID_TIGON, 146 "Silicon Graphics Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int ti_probe __P((device_t)); 151 static int ti_attach __P((device_t)); 152 static int ti_detach __P((device_t)); 153 static void ti_txeof __P((struct ti_softc *)); 154 static void ti_rxeof __P((struct ti_softc *)); 155 156 static void ti_stats_update __P((struct ti_softc *)); 157 static int ti_encap __P((struct ti_softc *, struct mbuf *, 158 u_int32_t *)); 159 160 static void ti_intr __P((void *)); 161 static void ti_start __P((struct ifnet *)); 162 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 163 static void ti_init __P((void *)); 164 static void ti_init2 __P((struct ti_softc *)); 165 static void ti_stop __P((struct ti_softc *)); 166 static void ti_watchdog __P((struct ifnet *)); 167 static void ti_shutdown __P((device_t)); 168 static int ti_ifmedia_upd __P((struct ifnet *)); 169 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 172 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 173 int, u_int8_t *)); 174 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 175 176 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 177 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 178 static void ti_setmulti __P((struct ti_softc *)); 179 180 static void ti_mem __P((struct ti_softc *, u_int32_t, 181 u_int32_t, caddr_t)); 182 static void ti_loadfw __P((struct ti_softc *)); 183 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 184 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 185 caddr_t, int)); 186 static void ti_handle_events __P((struct ti_softc *)); 187 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 188 static void *ti_jalloc __P((struct ti_softc *)); 189 static void ti_jfree __P((caddr_t, u_int)); 190 static void ti_jref __P((caddr_t, u_int)); 191 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 192 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 193 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 194 static int ti_init_rx_ring_std __P((struct ti_softc *)); 195 static void ti_free_rx_ring_std __P((struct ti_softc *)); 196 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 197 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 198 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 199 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 200 static void ti_free_tx_ring __P((struct ti_softc *)); 201 static int ti_init_tx_ring __P((struct ti_softc *)); 202 203 static int ti_64bitslot_war __P((struct ti_softc *)); 204 static int ti_chipinit __P((struct ti_softc *)); 205 static int ti_gibinit __P((struct ti_softc *)); 206 207 static device_method_t ti_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, ti_probe), 210 DEVMETHOD(device_attach, ti_attach), 211 DEVMETHOD(device_detach, ti_detach), 212 DEVMETHOD(device_shutdown, ti_shutdown), 213 { 0, 0 } 214 }; 215 216 static driver_t ti_driver = { 217 "ti", 218 ti_methods, 219 sizeof(struct ti_softc) 220 }; 221 222 static devclass_t ti_devclass; 223 224 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 225 226 /* 227 * Send an instruction or address to the EEPROM, check for ACK. 228 */ 229 static u_int32_t ti_eeprom_putbyte(sc, byte) 230 struct ti_softc *sc; 231 int byte; 232 { 233 register int i, ack = 0; 234 235 /* 236 * Make sure we're in TX mode. 237 */ 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Feed in each bit and stobe the clock. 242 */ 243 for (i = 0x80; i; i >>= 1) { 244 if (byte & i) { 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 246 } else { 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } 249 DELAY(1); 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 DELAY(1); 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 } 254 255 /* 256 * Turn off TX mode. 257 */ 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 259 260 /* 261 * Check for ack. 262 */ 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 267 return(ack); 268 } 269 270 /* 271 * Read a byte of data stored in the EEPROM at address 'addr.' 272 * We have to send two address bytes since the EEPROM can hold 273 * more than 256 bytes of data. 274 */ 275 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 276 struct ti_softc *sc; 277 int addr; 278 u_int8_t *dest; 279 { 280 register int i; 281 u_int8_t byte = 0; 282 283 EEPROM_START; 284 285 /* 286 * Send write control code to EEPROM. 287 */ 288 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 289 printf("ti%d: failed to send write command, status: %x\n", 290 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 291 return(1); 292 } 293 294 /* 295 * Send first byte of address of byte we want to read. 296 */ 297 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 298 printf("ti%d: failed to send address, status: %x\n", 299 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return(1); 301 } 302 /* 303 * Send second byte address of byte we want to read. 304 */ 305 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 306 printf("ti%d: failed to send address, status: %x\n", 307 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 EEPROM_STOP; 312 EEPROM_START; 313 /* 314 * Send read control code to EEPROM. 315 */ 316 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 317 printf("ti%d: failed to send read command, status: %x\n", 318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 319 return(1); 320 } 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 326 for (i = 0x80; i; i >>= 1) { 327 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 328 DELAY(1); 329 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 330 byte |= i; 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 332 DELAY(1); 333 } 334 335 EEPROM_STOP; 336 337 /* 338 * No ACK generated for read, so just return byte. 339 */ 340 341 *dest = byte; 342 343 return(0); 344 } 345 346 /* 347 * Read a sequence of bytes from the EEPROM. 348 */ 349 static int ti_read_eeprom(sc, dest, off, cnt) 350 struct ti_softc *sc; 351 caddr_t dest; 352 int off; 353 int cnt; 354 { 355 int err = 0, i; 356 u_int8_t byte = 0; 357 358 for (i = 0; i < cnt; i++) { 359 err = ti_eeprom_getbyte(sc, off + i, &byte); 360 if (err) 361 break; 362 *(dest + i) = byte; 363 } 364 365 return(err ? 1 : 0); 366 } 367 368 /* 369 * NIC memory access function. Can be used to either clear a section 370 * of NIC local memory or (if buf is non-NULL) copy data into it. 371 */ 372 static void ti_mem(sc, addr, len, buf) 373 struct ti_softc *sc; 374 u_int32_t addr, len; 375 caddr_t buf; 376 { 377 int segptr, segsize, cnt; 378 caddr_t ti_winbase, ptr; 379 380 segptr = addr; 381 cnt = len; 382 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 383 ptr = buf; 384 385 while(cnt) { 386 if (cnt < TI_WINLEN) 387 segsize = cnt; 388 else 389 segsize = TI_WINLEN - (segptr % TI_WINLEN); 390 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 391 if (buf == NULL) 392 bzero((char *)ti_winbase + (segptr & 393 (TI_WINLEN - 1)), segsize); 394 else { 395 bcopy((char *)ptr, (char *)ti_winbase + 396 (segptr & (TI_WINLEN - 1)), segsize); 397 ptr += segsize; 398 } 399 segptr += segsize; 400 cnt -= segsize; 401 } 402 403 return; 404 } 405 406 /* 407 * Load firmware image into the NIC. Check that the firmware revision 408 * is acceptable and see if we want the firmware for the Tigon 1 or 409 * Tigon 2. 410 */ 411 static void ti_loadfw(sc) 412 struct ti_softc *sc; 413 { 414 switch(sc->ti_hwrev) { 415 case TI_HWREV_TIGON: 416 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("ti%d: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 423 tigonFwReleaseMinor, tigonFwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 427 (caddr_t)tigonFwText); 428 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 429 (caddr_t)tigonFwData); 430 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 431 (caddr_t)tigonFwRodata); 432 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 433 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 434 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 435 break; 436 case TI_HWREV_TIGON_II: 437 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 438 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 439 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 440 printf("ti%d: firmware revision mismatch; want " 441 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 442 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 443 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 444 tigon2FwReleaseMinor, tigon2FwReleaseFix); 445 return; 446 } 447 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 448 (caddr_t)tigon2FwText); 449 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 450 (caddr_t)tigon2FwData); 451 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 452 (caddr_t)tigon2FwRodata); 453 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 454 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 455 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 456 break; 457 default: 458 printf("ti%d: can't load firmware: unknown hardware rev\n", 459 sc->ti_unit); 460 break; 461 } 462 463 return; 464 } 465 466 /* 467 * Send the NIC a command via the command ring. 468 */ 469 static void ti_cmd(sc, cmd) 470 struct ti_softc *sc; 471 struct ti_cmd_desc *cmd; 472 { 473 u_int32_t index; 474 475 if (sc->ti_rdata->ti_cmd_ring == NULL) 476 return; 477 478 index = sc->ti_cmd_saved_prodidx; 479 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 480 TI_INC(index, TI_CMD_RING_CNT); 481 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 482 sc->ti_cmd_saved_prodidx = index; 483 484 return; 485 } 486 487 /* 488 * Send the NIC an extended command. The 'len' parameter specifies the 489 * number of command slots to include after the initial command. 490 */ 491 static void ti_cmd_ext(sc, cmd, arg, len) 492 struct ti_softc *sc; 493 struct ti_cmd_desc *cmd; 494 caddr_t arg; 495 int len; 496 { 497 u_int32_t index; 498 register int i; 499 500 if (sc->ti_rdata->ti_cmd_ring == NULL) 501 return; 502 503 index = sc->ti_cmd_saved_prodidx; 504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 505 TI_INC(index, TI_CMD_RING_CNT); 506 for (i = 0; i < len; i++) { 507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 508 *(u_int32_t *)(&arg[i * 4])); 509 TI_INC(index, TI_CMD_RING_CNT); 510 } 511 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 512 sc->ti_cmd_saved_prodidx = index; 513 514 return; 515 } 516 517 /* 518 * Handle events that have triggered interrupts. 519 */ 520 static void ti_handle_events(sc) 521 struct ti_softc *sc; 522 { 523 struct ti_event_desc *e; 524 525 if (sc->ti_rdata->ti_event_ring == NULL) 526 return; 527 528 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 529 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 530 switch(e->ti_event) { 531 case TI_EV_LINKSTAT_CHANGED: 532 sc->ti_linkstat = e->ti_code; 533 if (e->ti_code == TI_EV_CODE_LINK_UP) 534 printf("ti%d: 10/100 link up\n", sc->ti_unit); 535 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 536 printf("ti%d: gigabit link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 538 printf("ti%d: link down\n", sc->ti_unit); 539 break; 540 case TI_EV_ERROR: 541 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 542 printf("ti%d: invalid command\n", sc->ti_unit); 543 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 544 printf("ti%d: unknown command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 546 printf("ti%d: bad config data\n", sc->ti_unit); 547 break; 548 case TI_EV_FIRMWARE_UP: 549 ti_init2(sc); 550 break; 551 case TI_EV_STATS_UPDATED: 552 ti_stats_update(sc); 553 break; 554 case TI_EV_RESET_JUMBO_RING: 555 case TI_EV_MCAST_UPDATED: 556 /* Who cares. */ 557 break; 558 default: 559 printf("ti%d: unknown event: %d\n", 560 sc->ti_unit, e->ti_event); 561 break; 562 } 563 /* Advance the consumer index. */ 564 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 565 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 566 } 567 568 return; 569 } 570 571 /* 572 * Memory management for the jumbo receive ring is a pain in the 573 * butt. We need to allocate at least 9018 bytes of space per frame, 574 * _and_ it has to be contiguous (unless you use the extended 575 * jumbo descriptor format). Using malloc() all the time won't 576 * work: malloc() allocates memory in powers of two, which means we 577 * would end up wasting a considerable amount of space by allocating 578 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 579 * to do our own memory management. 580 * 581 * The driver needs to allocate a contiguous chunk of memory at boot 582 * time. We then chop this up ourselves into 9K pieces and use them 583 * as external mbuf storage. 584 * 585 * One issue here is how much memory to allocate. The jumbo ring has 586 * 256 slots in it, but at 9K per slot than can consume over 2MB of 587 * RAM. This is a bit much, especially considering we also need 588 * RAM for the standard ring and mini ring (on the Tigon 2). To 589 * save space, we only actually allocate enough memory for 64 slots 590 * by default, which works out to between 500 and 600K. This can 591 * be tuned by changing a #define in if_tireg.h. 592 */ 593 594 static int ti_alloc_jumbo_mem(sc) 595 struct ti_softc *sc; 596 { 597 caddr_t ptr; 598 register int i; 599 struct ti_jpool_entry *entry; 600 601 /* Grab a big chunk o' storage. */ 602 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 603 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 604 605 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 606 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 607 return(ENOBUFS); 608 } 609 610 SLIST_INIT(&sc->ti_jfree_listhead); 611 SLIST_INIT(&sc->ti_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. Note that we play an evil trick here by using 616 * the first few bytes in the buffer to hold the the address 617 * of the softc structure for this interface. This is because 618 * ti_jfree() needs it, but it is called by the mbuf management 619 * code which will not pass it to us explicitly. 620 */ 621 ptr = sc->ti_cdata.ti_jumbo_buf; 622 for (i = 0; i < TI_JSLOTS; i++) { 623 u_int64_t **aptr; 624 aptr = (u_int64_t **)ptr; 625 aptr[0] = (u_int64_t *)sc; 626 ptr += sizeof(u_int64_t); 627 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 628 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 629 ptr += (TI_JLEN - sizeof(u_int64_t)); 630 entry = malloc(sizeof(struct ti_jpool_entry), 631 M_DEVBUF, M_NOWAIT); 632 if (entry == NULL) { 633 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 634 sc->ti_cdata.ti_jumbo_buf = NULL; 635 printf("ti%d: no memory for jumbo " 636 "buffer queue!\n", sc->ti_unit); 637 return(ENOBUFS); 638 } 639 entry->slot = i; 640 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 641 } 642 643 return(0); 644 } 645 646 /* 647 * Allocate a jumbo buffer. 648 */ 649 static void *ti_jalloc(sc) 650 struct ti_softc *sc; 651 { 652 struct ti_jpool_entry *entry; 653 654 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 655 656 if (entry == NULL) { 657 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 658 return(NULL); 659 } 660 661 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 662 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 663 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 664 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 665 } 666 667 /* 668 * Adjust usage count on a jumbo buffer. In general this doesn't 669 * get used much because our jumbo buffers don't get passed around 670 * too much, but it's implemented for correctness. 671 */ 672 static void ti_jref(buf, size) 673 caddr_t buf; 674 u_int size; 675 { 676 struct ti_softc *sc; 677 u_int64_t **aptr; 678 register int i; 679 680 /* Extract the softc struct pointer. */ 681 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 682 sc = (struct ti_softc *)(aptr[0]); 683 684 if (sc == NULL) 685 panic("ti_jref: can't find softc pointer!"); 686 687 if (size != TI_JUMBO_FRAMELEN) 688 panic("ti_jref: adjusting refcount of buf of wrong size!"); 689 690 /* calculate the slot this buffer belongs to */ 691 692 i = ((vm_offset_t)aptr 693 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 694 695 if ((i < 0) || (i >= TI_JSLOTS)) 696 panic("ti_jref: asked to reference buffer " 697 "that we don't manage!"); 698 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 699 panic("ti_jref: buffer already free!"); 700 else 701 sc->ti_cdata.ti_jslots[i].ti_inuse++; 702 703 return; 704 } 705 706 /* 707 * Release a jumbo buffer. 708 */ 709 static void ti_jfree(buf, size) 710 caddr_t buf; 711 u_int size; 712 { 713 struct ti_softc *sc; 714 u_int64_t **aptr; 715 int i; 716 struct ti_jpool_entry *entry; 717 718 /* Extract the softc struct pointer. */ 719 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 720 sc = (struct ti_softc *)(aptr[0]); 721 722 if (sc == NULL) 723 panic("ti_jfree: can't find softc pointer!"); 724 725 if (size != TI_JUMBO_FRAMELEN) 726 panic("ti_jfree: freeing buffer of wrong size!"); 727 728 /* calculate the slot this buffer belongs to */ 729 730 i = ((vm_offset_t)aptr 731 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 732 733 if ((i < 0) || (i >= TI_JSLOTS)) 734 panic("ti_jfree: asked to free buffer that we don't manage!"); 735 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 736 panic("ti_jfree: buffer already free!"); 737 else { 738 sc->ti_cdata.ti_jslots[i].ti_inuse--; 739 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 740 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 741 if (entry == NULL) 742 panic("ti_jfree: buffer not in use!"); 743 entry->slot = i; 744 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 745 jpool_entries); 746 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 747 entry, jpool_entries); 748 } 749 } 750 751 return; 752 } 753 754 755 /* 756 * Intialize a standard receive ring descriptor. 757 */ 758 static int ti_newbuf_std(sc, i, m) 759 struct ti_softc *sc; 760 int i; 761 struct mbuf *m; 762 { 763 struct mbuf *m_new = NULL; 764 struct ti_rx_desc *r; 765 766 if (m == NULL) { 767 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 printf("ti%d: mbuf allocation failed " 770 "-- packet dropped!\n", sc->ti_unit); 771 return(ENOBUFS); 772 } 773 774 MCLGET(m_new, M_DONTWAIT); 775 if (!(m_new->m_flags & M_EXT)) { 776 printf("ti%d: cluster allocation failed " 777 "-- packet dropped!\n", sc->ti_unit); 778 m_freem(m_new); 779 return(ENOBUFS); 780 } 781 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 782 } else { 783 m_new = m; 784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 785 m_new->m_data = m_new->m_ext.ext_buf; 786 } 787 788 m_adj(m_new, ETHER_ALIGN); 789 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 790 r = &sc->ti_rdata->ti_rx_std_ring[i]; 791 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 792 r->ti_type = TI_BDTYPE_RECV_BD; 793 #ifdef TI_CSUM_OFFLOAD 794 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 795 #else 796 r->ti_flags = 0; 797 #endif 798 r->ti_len = m_new->m_len; 799 r->ti_idx = i; 800 801 return(0); 802 } 803 804 /* 805 * Intialize a mini receive ring descriptor. This only applies to 806 * the Tigon 2. 807 */ 808 static int ti_newbuf_mini(sc, i, m) 809 struct ti_softc *sc; 810 int i; 811 struct mbuf *m; 812 { 813 struct mbuf *m_new = NULL; 814 struct ti_rx_desc *r; 815 816 if (m == NULL) { 817 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 818 if (m_new == NULL) { 819 printf("ti%d: mbuf allocation failed " 820 "-- packet dropped!\n", sc->ti_unit); 821 return(ENOBUFS); 822 } 823 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 824 } else { 825 m_new = m; 826 m_new->m_data = m_new->m_pktdat; 827 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 828 } 829 830 m_adj(m_new, ETHER_ALIGN); 831 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 832 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 833 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 834 r->ti_type = TI_BDTYPE_RECV_BD; 835 r->ti_flags = TI_BDFLAG_MINI_RING; 836 #ifdef TI_CSUM_OFFLOAD 837 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 838 #endif 839 r->ti_len = m_new->m_len; 840 r->ti_idx = i; 841 842 return(0); 843 } 844 845 /* 846 * Initialize a jumbo receive ring descriptor. This allocates 847 * a jumbo buffer from the pool managed internally by the driver. 848 */ 849 static int ti_newbuf_jumbo(sc, i, m) 850 struct ti_softc *sc; 851 int i; 852 struct mbuf *m; 853 { 854 struct mbuf *m_new = NULL; 855 struct ti_rx_desc *r; 856 857 if (m == NULL) { 858 caddr_t *buf = NULL; 859 860 /* Allocate the mbuf. */ 861 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 862 if (m_new == NULL) { 863 printf("ti%d: mbuf allocation failed " 864 "-- packet dropped!\n", sc->ti_unit); 865 return(ENOBUFS); 866 } 867 868 /* Allocate the jumbo buffer */ 869 buf = ti_jalloc(sc); 870 if (buf == NULL) { 871 m_freem(m_new); 872 printf("ti%d: jumbo allocation failed " 873 "-- packet dropped!\n", sc->ti_unit); 874 return(ENOBUFS); 875 } 876 877 /* Attach the buffer to the mbuf. */ 878 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 879 m_new->m_flags |= M_EXT; 880 m_new->m_len = m_new->m_pkthdr.len = 881 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 882 m_new->m_ext.ext_free = ti_jfree; 883 m_new->m_ext.ext_ref = ti_jref; 884 } else { 885 m_new = m; 886 m_new->m_data = m_new->m_ext.ext_buf; 887 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 888 } 889 890 m_adj(m_new, ETHER_ALIGN); 891 /* Set up the descriptor. */ 892 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 893 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 894 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 895 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 896 r->ti_flags = TI_BDFLAG_JUMBO_RING; 897 #ifdef TI_CSUM_OFFLOAD 898 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 899 #endif 900 r->ti_len = m_new->m_len; 901 r->ti_idx = i; 902 903 return(0); 904 } 905 906 /* 907 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 908 * that's 1MB or memory, which is a lot. For now, we fill only the first 909 * 256 ring entries and hope that our CPU is fast enough to keep up with 910 * the NIC. 911 */ 912 static int ti_init_rx_ring_std(sc) 913 struct ti_softc *sc; 914 { 915 register int i; 916 struct ti_cmd_desc cmd; 917 918 for (i = 0; i < TI_SSLOTS; i++) { 919 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 920 return(ENOBUFS); 921 }; 922 923 TI_UPDATE_STDPROD(sc, i - 1); 924 sc->ti_std = i - 1; 925 926 return(0); 927 } 928 929 static void ti_free_rx_ring_std(sc) 930 struct ti_softc *sc; 931 { 932 register int i; 933 934 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 935 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 936 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 937 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 938 } 939 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 940 sizeof(struct ti_rx_desc)); 941 } 942 943 return; 944 } 945 946 static int ti_init_rx_ring_jumbo(sc) 947 struct ti_softc *sc; 948 { 949 register int i; 950 struct ti_cmd_desc cmd; 951 952 for (i = 0; i < (TI_JSLOTS - 20); i++) { 953 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 954 return(ENOBUFS); 955 }; 956 957 TI_UPDATE_JUMBOPROD(sc, i - 1); 958 sc->ti_jumbo = i - 1; 959 960 return(0); 961 } 962 963 static void ti_free_rx_ring_jumbo(sc) 964 struct ti_softc *sc; 965 { 966 register int i; 967 968 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 969 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 970 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 971 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 972 } 973 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 974 sizeof(struct ti_rx_desc)); 975 } 976 977 return; 978 } 979 980 static int ti_init_rx_ring_mini(sc) 981 struct ti_softc *sc; 982 { 983 register int i; 984 985 for (i = 0; i < TI_MSLOTS; i++) { 986 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 987 return(ENOBUFS); 988 }; 989 990 TI_UPDATE_MINIPROD(sc, i - 1); 991 sc->ti_mini = i - 1; 992 993 return(0); 994 } 995 996 static void ti_free_rx_ring_mini(sc) 997 struct ti_softc *sc; 998 { 999 register int i; 1000 1001 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1002 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1003 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1004 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1005 } 1006 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1007 sizeof(struct ti_rx_desc)); 1008 } 1009 1010 return; 1011 } 1012 1013 static void ti_free_tx_ring(sc) 1014 struct ti_softc *sc; 1015 { 1016 register int i; 1017 1018 if (sc->ti_rdata->ti_tx_ring == NULL) 1019 return; 1020 1021 for (i = 0; i < TI_TX_RING_CNT; i++) { 1022 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1023 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1024 sc->ti_cdata.ti_tx_chain[i] = NULL; 1025 } 1026 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1027 sizeof(struct ti_tx_desc)); 1028 } 1029 1030 return; 1031 } 1032 1033 static int ti_init_tx_ring(sc) 1034 struct ti_softc *sc; 1035 { 1036 sc->ti_txcnt = 0; 1037 sc->ti_tx_saved_considx = 0; 1038 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1039 return(0); 1040 } 1041 1042 /* 1043 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1044 * but we have to support the old way too so that Tigon 1 cards will 1045 * work. 1046 */ 1047 void ti_add_mcast(sc, addr) 1048 struct ti_softc *sc; 1049 struct ether_addr *addr; 1050 { 1051 struct ti_cmd_desc cmd; 1052 u_int16_t *m; 1053 u_int32_t ext[2] = {0, 0}; 1054 1055 m = (u_int16_t *)&addr->octet[0]; 1056 1057 switch(sc->ti_hwrev) { 1058 case TI_HWREV_TIGON: 1059 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1060 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1061 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1062 break; 1063 case TI_HWREV_TIGON_II: 1064 ext[0] = htons(m[0]); 1065 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1066 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1067 break; 1068 default: 1069 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1070 break; 1071 } 1072 1073 return; 1074 } 1075 1076 void ti_del_mcast(sc, addr) 1077 struct ti_softc *sc; 1078 struct ether_addr *addr; 1079 { 1080 struct ti_cmd_desc cmd; 1081 u_int16_t *m; 1082 u_int32_t ext[2] = {0, 0}; 1083 1084 m = (u_int16_t *)&addr->octet[0]; 1085 1086 switch(sc->ti_hwrev) { 1087 case TI_HWREV_TIGON: 1088 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1089 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1090 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1091 break; 1092 case TI_HWREV_TIGON_II: 1093 ext[0] = htons(m[0]); 1094 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1095 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1096 break; 1097 default: 1098 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1099 break; 1100 } 1101 1102 return; 1103 } 1104 1105 /* 1106 * Configure the Tigon's multicast address filter. 1107 * 1108 * The actual multicast table management is a bit of a pain, thanks to 1109 * slight brain damage on the part of both Alteon and us. With our 1110 * multicast code, we are only alerted when the multicast address table 1111 * changes and at that point we only have the current list of addresses: 1112 * we only know the current state, not the previous state, so we don't 1113 * actually know what addresses were removed or added. The firmware has 1114 * state, but we can't get our grubby mits on it, and there is no 'delete 1115 * all multicast addresses' command. Hence, we have to maintain our own 1116 * state so we know what addresses have been programmed into the NIC at 1117 * any given time. 1118 */ 1119 static void ti_setmulti(sc) 1120 struct ti_softc *sc; 1121 { 1122 struct ifnet *ifp; 1123 struct ifmultiaddr *ifma; 1124 struct ti_cmd_desc cmd; 1125 struct ti_mc_entry *mc; 1126 u_int32_t intrs; 1127 1128 ifp = &sc->arpcom.ac_if; 1129 1130 if (ifp->if_flags & IFF_ALLMULTI) { 1131 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1132 return; 1133 } else { 1134 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1135 } 1136 1137 /* Disable interrupts. */ 1138 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1139 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1140 1141 /* First, zot all the existing filters. */ 1142 while (sc->ti_mc_listhead.slh_first != NULL) { 1143 mc = sc->ti_mc_listhead.slh_first; 1144 ti_del_mcast(sc, &mc->mc_addr); 1145 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1146 free(mc, M_DEVBUF); 1147 } 1148 1149 /* Now program new ones. */ 1150 for (ifma = ifp->if_multiaddrs.lh_first; 1151 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1152 if (ifma->ifma_addr->sa_family != AF_LINK) 1153 continue; 1154 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1155 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1156 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1157 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1158 ti_add_mcast(sc, &mc->mc_addr); 1159 } 1160 1161 /* Re-enable interrupts. */ 1162 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1163 1164 return; 1165 } 1166 1167 /* 1168 * Check to see if the BIOS has configured us for a 64 bit slot when 1169 * we aren't actually in one. If we detect this condition, we can work 1170 * around it on the Tigon 2 by setting a bit in the PCI state register, 1171 * but for the Tigon 1 we must give up and abort the interface attach. 1172 */ 1173 static int ti_64bitslot_war(sc) 1174 struct ti_softc *sc; 1175 { 1176 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1177 CSR_WRITE_4(sc, 0x600, 0); 1178 CSR_WRITE_4(sc, 0x604, 0); 1179 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1180 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1181 if (sc->ti_hwrev == TI_HWREV_TIGON) 1182 return(EINVAL); 1183 else { 1184 TI_SETBIT(sc, TI_PCI_STATE, 1185 TI_PCISTATE_32BIT_BUS); 1186 return(0); 1187 } 1188 } 1189 } 1190 1191 return(0); 1192 } 1193 1194 /* 1195 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1196 * self-test results. 1197 */ 1198 static int ti_chipinit(sc) 1199 struct ti_softc *sc; 1200 { 1201 u_int32_t cacheline; 1202 u_int32_t pci_writemax = 0; 1203 1204 /* Initialize link to down state. */ 1205 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1206 1207 /* Set endianness before we access any non-PCI registers. */ 1208 #if BYTE_ORDER == BIG_ENDIAN 1209 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1210 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1211 #else 1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1213 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1214 #endif 1215 1216 /* Check the ROM failed bit to see if self-tests passed. */ 1217 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1218 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1219 return(ENODEV); 1220 } 1221 1222 /* Halt the CPU. */ 1223 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1224 1225 /* Figure out the hardware revision. */ 1226 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1227 case TI_REV_TIGON_I: 1228 sc->ti_hwrev = TI_HWREV_TIGON; 1229 break; 1230 case TI_REV_TIGON_II: 1231 sc->ti_hwrev = TI_HWREV_TIGON_II; 1232 break; 1233 default: 1234 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1235 return(ENODEV); 1236 } 1237 1238 /* Do special setup for Tigon 2. */ 1239 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1240 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1241 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1242 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1243 } 1244 1245 /* Set up the PCI state register. */ 1246 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1247 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1248 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1249 } 1250 1251 /* Clear the read/write max DMA parameters. */ 1252 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1253 TI_PCISTATE_READ_MAXDMA)); 1254 1255 /* Get cache line size. */ 1256 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1257 1258 /* 1259 * If the system has set enabled the PCI memory write 1260 * and invalidate command in the command register, set 1261 * the write max parameter accordingly. This is necessary 1262 * to use MWI with the Tigon 2. 1263 */ 1264 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1265 switch(cacheline) { 1266 case 1: 1267 case 4: 1268 case 8: 1269 case 16: 1270 case 32: 1271 case 64: 1272 break; 1273 default: 1274 /* Disable PCI memory write and invalidate. */ 1275 if (bootverbose) 1276 printf("ti%d: cache line size %d not " 1277 "supported; disabling PCI MWI\n", 1278 sc->ti_unit, cacheline); 1279 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1280 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1281 break; 1282 } 1283 } 1284 1285 #ifdef __brokenalpha__ 1286 /* 1287 * From the Alteon sample driver: 1288 * Must insure that we do not cross an 8K (bytes) boundary 1289 * for DMA reads. Our highest limit is 1K bytes. This is a 1290 * restriction on some ALPHA platforms with early revision 1291 * 21174 PCI chipsets, such as the AlphaPC 164lx 1292 */ 1293 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1294 #else 1295 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1296 #endif 1297 1298 /* This sets the min dma param all the way up (0xff). */ 1299 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1300 1301 /* Configure DMA variables. */ 1302 #if BYTE_ORDER == BIG_ENDIAN 1303 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1304 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1305 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1306 TI_OPMODE_DONT_FRAG_JUMBO); 1307 #else 1308 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1309 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1310 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1311 #endif 1312 1313 /* 1314 * Only allow 1 DMA channel to be active at a time. 1315 * I don't think this is a good idea, but without it 1316 * the firmware racks up lots of nicDmaReadRingFull 1317 * errors. 1318 */ 1319 #ifndef TI_CSUM_OFFLOAD 1320 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1321 #endif 1322 1323 /* Recommended settings from Tigon manual. */ 1324 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1325 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1326 1327 if (ti_64bitslot_war(sc)) { 1328 printf("ti%d: bios thinks we're in a 64 bit slot, " 1329 "but we aren't", sc->ti_unit); 1330 return(EINVAL); 1331 } 1332 1333 return(0); 1334 } 1335 1336 /* 1337 * Initialize the general information block and firmware, and 1338 * start the CPU(s) running. 1339 */ 1340 static int ti_gibinit(sc) 1341 struct ti_softc *sc; 1342 { 1343 struct ti_rcb *rcb; 1344 int i; 1345 struct ifnet *ifp; 1346 1347 ifp = &sc->arpcom.ac_if; 1348 1349 /* Disable interrupts for now. */ 1350 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1351 1352 /* Tell the chip where to find the general information block. */ 1353 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1354 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1355 1356 /* Load the firmware into SRAM. */ 1357 ti_loadfw(sc); 1358 1359 /* Set up the contents of the general info and ring control blocks. */ 1360 1361 /* Set up the event ring and producer pointer. */ 1362 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1363 1364 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1365 rcb->ti_flags = 0; 1366 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1367 vtophys(&sc->ti_ev_prodidx); 1368 sc->ti_ev_prodidx.ti_idx = 0; 1369 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1370 sc->ti_ev_saved_considx = 0; 1371 1372 /* Set up the command ring and producer mailbox. */ 1373 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1374 1375 sc->ti_rdata->ti_cmd_ring = 1376 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1377 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1378 rcb->ti_flags = 0; 1379 rcb->ti_max_len = 0; 1380 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1381 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1382 } 1383 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1384 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1385 sc->ti_cmd_saved_prodidx = 0; 1386 1387 /* 1388 * Assign the address of the stats refresh buffer. 1389 * We re-use the current stats buffer for this to 1390 * conserve memory. 1391 */ 1392 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1393 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1394 1395 /* Set up the standard receive ring. */ 1396 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1397 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1398 rcb->ti_max_len = TI_FRAMELEN; 1399 rcb->ti_flags = 0; 1400 #ifdef TI_CSUM_OFFLOAD 1401 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1402 #endif 1403 #if NVLAN > 0 1404 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1405 #endif 1406 1407 /* Set up the jumbo receive ring. */ 1408 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1409 TI_HOSTADDR(rcb->ti_hostaddr) = 1410 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1411 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1412 rcb->ti_flags = 0; 1413 #ifdef TI_CSUM_OFFLOAD 1414 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1415 #endif 1416 #if NVLAN > 0 1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1418 #endif 1419 1420 /* 1421 * Set up the mini ring. Only activated on the 1422 * Tigon 2 but the slot in the config block is 1423 * still there on the Tigon 1. 1424 */ 1425 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1426 TI_HOSTADDR(rcb->ti_hostaddr) = 1427 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1428 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1429 if (sc->ti_hwrev == TI_HWREV_TIGON) 1430 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1431 else 1432 rcb->ti_flags = 0; 1433 #ifdef TI_CSUM_OFFLOAD 1434 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1435 #endif 1436 #if NVLAN > 0 1437 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1438 #endif 1439 1440 /* 1441 * Set up the receive return ring. 1442 */ 1443 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1444 TI_HOSTADDR(rcb->ti_hostaddr) = 1445 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1446 rcb->ti_flags = 0; 1447 rcb->ti_max_len = TI_RETURN_RING_CNT; 1448 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1449 vtophys(&sc->ti_return_prodidx); 1450 1451 /* 1452 * Set up the tx ring. Note: for the Tigon 2, we have the option 1453 * of putting the transmit ring in the host's address space and 1454 * letting the chip DMA it instead of leaving the ring in the NIC's 1455 * memory and accessing it through the shared memory region. We 1456 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1457 * so we have to revert to the shared memory scheme if we detect 1458 * a Tigon 1 chip. 1459 */ 1460 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1461 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1462 sc->ti_rdata->ti_tx_ring_nic = 1463 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1464 } 1465 bzero((char *)sc->ti_rdata->ti_tx_ring, 1466 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1467 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1468 if (sc->ti_hwrev == TI_HWREV_TIGON) 1469 rcb->ti_flags = 0; 1470 else 1471 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1472 #if NVLAN > 0 1473 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1474 #endif 1475 rcb->ti_max_len = TI_TX_RING_CNT; 1476 if (sc->ti_hwrev == TI_HWREV_TIGON) 1477 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1478 else 1479 TI_HOSTADDR(rcb->ti_hostaddr) = 1480 vtophys(&sc->ti_rdata->ti_tx_ring); 1481 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1482 vtophys(&sc->ti_tx_considx); 1483 1484 /* Set up tuneables */ 1485 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1486 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1487 (sc->ti_rx_coal_ticks / 10)); 1488 else 1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1490 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1491 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1492 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1493 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1494 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1495 1496 /* Turn interrupts on. */ 1497 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1498 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1499 1500 /* Start CPU. */ 1501 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1502 1503 return(0); 1504 } 1505 1506 /* 1507 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1508 * against our list and return its name if we find a match. 1509 */ 1510 static int ti_probe(dev) 1511 device_t dev; 1512 { 1513 struct ti_type *t; 1514 1515 t = ti_devs; 1516 1517 while(t->ti_name != NULL) { 1518 if ((pci_get_vendor(dev) == t->ti_vid) && 1519 (pci_get_device(dev) == t->ti_did)) { 1520 device_set_desc(dev, t->ti_name); 1521 return(0); 1522 } 1523 t++; 1524 } 1525 1526 return(ENXIO); 1527 } 1528 1529 static int ti_attach(dev) 1530 device_t dev; 1531 { 1532 int s; 1533 u_int32_t command; 1534 struct ifnet *ifp; 1535 struct ti_softc *sc; 1536 int unit, error = 0, rid; 1537 1538 s = splimp(); 1539 1540 sc = device_get_softc(dev); 1541 unit = device_get_unit(dev); 1542 bzero(sc, sizeof(struct ti_softc)); 1543 1544 /* 1545 * Map control/status registers. 1546 */ 1547 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1548 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1549 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1550 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1551 1552 if (!(command & PCIM_CMD_MEMEN)) { 1553 printf("ti%d: failed to enable memory mapping!\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 rid = TI_PCI_LOMEM; 1559 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1560 0, ~0, 1, RF_ACTIVE); 1561 1562 if (sc->ti_res == NULL) { 1563 printf ("ti%d: couldn't map memory\n", unit); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 sc->ti_btag = rman_get_bustag(sc->ti_res); 1569 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1570 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1571 1572 /* 1573 * XXX FIXME: rman_get_virtual() on the alpha is currently 1574 * broken and returns a physical address instead of a kernel 1575 * virtual address. Consequently, we need to do a little 1576 * extra mangling of the vhandle on the alpha. This should 1577 * eventually be fixed! The whole idea here is to get rid 1578 * of platform dependencies. 1579 */ 1580 #ifdef __alpha__ 1581 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1582 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1583 else 1584 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1585 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1586 #endif 1587 1588 /* Allocate interrupt */ 1589 rid = 0; 1590 1591 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1592 RF_SHAREABLE | RF_ACTIVE); 1593 1594 if (sc->ti_irq == NULL) { 1595 printf("ti%d: couldn't map interrupt\n", unit); 1596 error = ENXIO; 1597 goto fail; 1598 } 1599 1600 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1601 ti_intr, sc, &sc->ti_intrhand); 1602 1603 if (error) { 1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1605 bus_release_resource(dev, SYS_RES_MEMORY, 1606 TI_PCI_LOMEM, sc->ti_res); 1607 printf("ti%d: couldn't set up irq\n", unit); 1608 goto fail; 1609 } 1610 1611 sc->ti_unit = unit; 1612 1613 if (ti_chipinit(sc)) { 1614 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1615 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1617 bus_release_resource(dev, SYS_RES_MEMORY, 1618 TI_PCI_LOMEM, sc->ti_res); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 1623 /* Zero out the NIC's on-board SRAM. */ 1624 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1625 1626 /* Init again -- zeroing memory may have clobbered some registers. */ 1627 if (ti_chipinit(sc)) { 1628 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1629 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1631 bus_release_resource(dev, SYS_RES_MEMORY, 1632 TI_PCI_LOMEM, sc->ti_res); 1633 error = ENXIO; 1634 goto fail; 1635 } 1636 1637 /* 1638 * Get station address from the EEPROM. Note: the manual states 1639 * that the MAC address is at offset 0x8c, however the data is 1640 * stored as two longwords (since that's how it's loaded into 1641 * the NIC). This means the MAC address is actually preceeded 1642 * by two zero bytes. We need to skip over those. 1643 */ 1644 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1645 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1646 printf("ti%d: failed to read station address\n", unit); 1647 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1649 bus_release_resource(dev, SYS_RES_MEMORY, 1650 TI_PCI_LOMEM, sc->ti_res); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 1655 /* 1656 * A Tigon chip was detected. Inform the world. 1657 */ 1658 printf("ti%d: Ethernet address: %6D\n", unit, 1659 sc->arpcom.ac_enaddr, ":"); 1660 1661 /* Allocate the general information block and ring buffers. */ 1662 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1663 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1664 1665 if (sc->ti_rdata == NULL) { 1666 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1668 bus_release_resource(dev, SYS_RES_MEMORY, 1669 TI_PCI_LOMEM, sc->ti_res); 1670 error = ENXIO; 1671 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1672 goto fail; 1673 } 1674 1675 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1676 1677 /* Try to allocate memory for jumbo buffers. */ 1678 if (ti_alloc_jumbo_mem(sc)) { 1679 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1680 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1681 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1682 bus_release_resource(dev, SYS_RES_MEMORY, 1683 TI_PCI_LOMEM, sc->ti_res); 1684 free(sc->ti_rdata, M_DEVBUF); 1685 error = ENXIO; 1686 goto fail; 1687 } 1688 1689 /* Set default tuneable values. */ 1690 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1691 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1692 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1693 sc->ti_rx_max_coal_bds = 64; 1694 sc->ti_tx_max_coal_bds = 128; 1695 sc->ti_tx_buf_ratio = 21; 1696 1697 /* Set up ifnet structure */ 1698 ifp = &sc->arpcom.ac_if; 1699 ifp->if_softc = sc; 1700 ifp->if_unit = sc->ti_unit; 1701 ifp->if_name = "ti"; 1702 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1703 ifp->if_ioctl = ti_ioctl; 1704 ifp->if_output = ether_output; 1705 ifp->if_start = ti_start; 1706 ifp->if_watchdog = ti_watchdog; 1707 ifp->if_init = ti_init; 1708 ifp->if_mtu = ETHERMTU; 1709 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1710 1711 /* Set up ifmedia support. */ 1712 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1713 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1714 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1715 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1720 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1721 1722 /* 1723 * Call MI attach routines. 1724 */ 1725 if_attach(ifp); 1726 ether_ifattach(ifp); 1727 1728 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1729 1730 fail: 1731 splx(s); 1732 1733 return(error); 1734 } 1735 1736 static int ti_detach(dev) 1737 device_t dev; 1738 { 1739 struct ti_softc *sc; 1740 struct ifnet *ifp; 1741 int s; 1742 1743 s = splimp(); 1744 1745 sc = device_get_softc(dev); 1746 ifp = &sc->arpcom.ac_if; 1747 1748 if_detach(ifp); 1749 ti_stop(sc); 1750 1751 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1752 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1753 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1754 1755 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1756 free(sc->ti_rdata, M_DEVBUF); 1757 ifmedia_removeall(&sc->ifmedia); 1758 1759 splx(s); 1760 1761 return(0); 1762 } 1763 1764 /* 1765 * Frame reception handling. This is called if there's a frame 1766 * on the receive return list. 1767 * 1768 * Note: we have to be able to handle three possibilities here: 1769 * 1) the frame is from the mini receive ring (can only happen) 1770 * on Tigon 2 boards) 1771 * 2) the frame is from the jumbo recieve ring 1772 * 3) the frame is from the standard receive ring 1773 */ 1774 1775 static void ti_rxeof(sc) 1776 struct ti_softc *sc; 1777 { 1778 struct ifnet *ifp; 1779 struct ti_cmd_desc cmd; 1780 1781 ifp = &sc->arpcom.ac_if; 1782 1783 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1784 struct ti_rx_desc *cur_rx; 1785 u_int32_t rxidx; 1786 struct ether_header *eh; 1787 struct mbuf *m = NULL; 1788 #if NVLAN > 0 1789 u_int16_t vlan_tag = 0; 1790 int have_tag = 0; 1791 #endif 1792 #ifdef TI_CSUM_OFFLOAD 1793 struct ip *ip; 1794 #endif 1795 1796 cur_rx = 1797 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1798 rxidx = cur_rx->ti_idx; 1799 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1800 1801 #if NVLAN > 0 1802 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1803 have_tag = 1; 1804 vlan_tag = cur_rx->ti_vlan_tag; 1805 } 1806 #endif 1807 1808 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1809 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1810 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1811 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1812 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1813 ifp->if_ierrors++; 1814 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1815 continue; 1816 } 1817 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1818 ifp->if_ierrors++; 1819 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1820 continue; 1821 } 1822 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1823 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1824 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1825 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1826 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1827 ifp->if_ierrors++; 1828 ti_newbuf_mini(sc, sc->ti_mini, m); 1829 continue; 1830 } 1831 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1832 ifp->if_ierrors++; 1833 ti_newbuf_mini(sc, sc->ti_mini, m); 1834 continue; 1835 } 1836 } else { 1837 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1838 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1839 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1840 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1841 ifp->if_ierrors++; 1842 ti_newbuf_std(sc, sc->ti_std, m); 1843 continue; 1844 } 1845 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1846 ifp->if_ierrors++; 1847 ti_newbuf_std(sc, sc->ti_std, m); 1848 continue; 1849 } 1850 } 1851 1852 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1853 ifp->if_ipackets++; 1854 eh = mtod(m, struct ether_header *); 1855 m->m_pkthdr.rcvif = ifp; 1856 1857 /* 1858 * Handle BPF listeners. Let the BPF user see the packet, but 1859 * don't pass it up to the ether_input() layer unless it's 1860 * a broadcast packet, multicast packet, matches our ethernet 1861 * address or the interface is in promiscuous mode. 1862 */ 1863 if (ifp->if_bpf) { 1864 bpf_mtap(ifp, m); 1865 if (ifp->if_flags & IFF_PROMISC && 1866 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1867 ETHER_ADDR_LEN) && 1868 (eh->ether_dhost[0] & 1) == 0)) { 1869 m_freem(m); 1870 continue; 1871 } 1872 } 1873 1874 /* Remove header from mbuf and pass it on. */ 1875 m_adj(m, sizeof(struct ether_header)); 1876 1877 #ifdef TI_CSUM_OFFLOAD 1878 ip = mtod(m, struct ip *); 1879 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1880 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1881 m->m_flags |= M_HWCKSUM; 1882 #endif 1883 1884 #if NVLAN > 0 1885 /* 1886 * If we received a packet with a vlan tag, pass it 1887 * to vlan_input() instead of ether_input(). 1888 */ 1889 if (have_tag) { 1890 vlan_input_tag(eh, m, vlan_tag); 1891 have_tag = vlan_tag = 0; 1892 continue; 1893 } 1894 #endif 1895 ether_input(ifp, eh, m); 1896 } 1897 1898 /* Only necessary on the Tigon 1. */ 1899 if (sc->ti_hwrev == TI_HWREV_TIGON) 1900 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1901 sc->ti_rx_saved_considx); 1902 1903 TI_UPDATE_STDPROD(sc, sc->ti_std); 1904 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1905 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1906 1907 return; 1908 } 1909 1910 static void ti_txeof(sc) 1911 struct ti_softc *sc; 1912 { 1913 struct ti_tx_desc *cur_tx = NULL; 1914 struct ifnet *ifp; 1915 1916 ifp = &sc->arpcom.ac_if; 1917 1918 /* 1919 * Go through our tx ring and free mbufs for those 1920 * frames that have been sent. 1921 */ 1922 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1923 u_int32_t idx = 0; 1924 1925 idx = sc->ti_tx_saved_considx; 1926 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1927 if (idx > 383) 1928 CSR_WRITE_4(sc, TI_WINBASE, 1929 TI_TX_RING_BASE + 6144); 1930 else if (idx > 255) 1931 CSR_WRITE_4(sc, TI_WINBASE, 1932 TI_TX_RING_BASE + 4096); 1933 else if (idx > 127) 1934 CSR_WRITE_4(sc, TI_WINBASE, 1935 TI_TX_RING_BASE + 2048); 1936 else 1937 CSR_WRITE_4(sc, TI_WINBASE, 1938 TI_TX_RING_BASE); 1939 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1940 } else 1941 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1942 if (cur_tx->ti_flags & TI_BDFLAG_END) 1943 ifp->if_opackets++; 1944 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1945 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1946 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1947 } 1948 sc->ti_txcnt--; 1949 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1950 ifp->if_timer = 0; 1951 } 1952 1953 if (cur_tx != NULL) 1954 ifp->if_flags &= ~IFF_OACTIVE; 1955 1956 return; 1957 } 1958 1959 static void ti_intr(xsc) 1960 void *xsc; 1961 { 1962 struct ti_softc *sc; 1963 struct ifnet *ifp; 1964 1965 sc = xsc; 1966 ifp = &sc->arpcom.ac_if; 1967 1968 #ifdef notdef 1969 /* Avoid this for now -- checking this register is expensive. */ 1970 /* Make sure this is really our interrupt. */ 1971 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1972 return; 1973 #endif 1974 1975 /* Ack interrupt and stop others from occuring. */ 1976 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1977 1978 if (ifp->if_flags & IFF_RUNNING) { 1979 /* Check RX return ring producer/consumer */ 1980 ti_rxeof(sc); 1981 1982 /* Check TX ring producer/consumer */ 1983 ti_txeof(sc); 1984 } 1985 1986 ti_handle_events(sc); 1987 1988 /* Re-enable interrupts. */ 1989 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1990 1991 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1992 ti_start(ifp); 1993 1994 return; 1995 } 1996 1997 static void ti_stats_update(sc) 1998 struct ti_softc *sc; 1999 { 2000 struct ifnet *ifp; 2001 2002 ifp = &sc->arpcom.ac_if; 2003 2004 ifp->if_collisions += 2005 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2006 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2007 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2008 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2009 ifp->if_collisions; 2010 2011 return; 2012 } 2013 2014 /* 2015 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2016 * pointers to descriptors. 2017 */ 2018 static int ti_encap(sc, m_head, txidx) 2019 struct ti_softc *sc; 2020 struct mbuf *m_head; 2021 u_int32_t *txidx; 2022 { 2023 struct ti_tx_desc *f = NULL; 2024 struct mbuf *m; 2025 u_int32_t frag, cur, cnt = 0; 2026 #if NVLAN > 0 2027 struct ifvlan *ifv = NULL; 2028 2029 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2030 m_head->m_pkthdr.rcvif != NULL && 2031 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2032 ifv = m_head->m_pkthdr.rcvif->if_softc; 2033 #endif 2034 2035 m = m_head; 2036 cur = frag = *txidx; 2037 2038 /* 2039 * Start packing the mbufs in this chain into 2040 * the fragment pointers. Stop when we run out 2041 * of fragments or hit the end of the mbuf chain. 2042 */ 2043 for (m = m_head; m != NULL; m = m->m_next) { 2044 if (m->m_len != 0) { 2045 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2046 if (frag > 383) 2047 CSR_WRITE_4(sc, TI_WINBASE, 2048 TI_TX_RING_BASE + 6144); 2049 else if (frag > 255) 2050 CSR_WRITE_4(sc, TI_WINBASE, 2051 TI_TX_RING_BASE + 4096); 2052 else if (frag > 127) 2053 CSR_WRITE_4(sc, TI_WINBASE, 2054 TI_TX_RING_BASE + 2048); 2055 else 2056 CSR_WRITE_4(sc, TI_WINBASE, 2057 TI_TX_RING_BASE); 2058 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2059 } else 2060 f = &sc->ti_rdata->ti_tx_ring[frag]; 2061 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2062 break; 2063 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2064 f->ti_len = m->m_len; 2065 f->ti_flags = 0; 2066 #if NVLAN > 0 2067 if (ifv != NULL) { 2068 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2069 f->ti_vlan_tag = ifv->ifv_tag; 2070 } else { 2071 f->ti_vlan_tag = 0; 2072 } 2073 #endif 2074 /* 2075 * Sanity check: avoid coming within 16 descriptors 2076 * of the end of the ring. 2077 */ 2078 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2079 return(ENOBUFS); 2080 cur = frag; 2081 TI_INC(frag, TI_TX_RING_CNT); 2082 cnt++; 2083 } 2084 } 2085 2086 if (m != NULL) 2087 return(ENOBUFS); 2088 2089 if (frag == sc->ti_tx_saved_considx) 2090 return(ENOBUFS); 2091 2092 if (sc->ti_hwrev == TI_HWREV_TIGON) 2093 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2094 TI_BDFLAG_END; 2095 else 2096 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2097 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2098 sc->ti_txcnt += cnt; 2099 2100 *txidx = frag; 2101 2102 return(0); 2103 } 2104 2105 /* 2106 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2107 * to the mbuf data regions directly in the transmit descriptors. 2108 */ 2109 static void ti_start(ifp) 2110 struct ifnet *ifp; 2111 { 2112 struct ti_softc *sc; 2113 struct mbuf *m_head = NULL; 2114 u_int32_t prodidx = 0; 2115 2116 sc = ifp->if_softc; 2117 2118 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2119 2120 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2121 IF_DEQUEUE(&ifp->if_snd, m_head); 2122 if (m_head == NULL) 2123 break; 2124 2125 /* 2126 * Pack the data into the transmit ring. If we 2127 * don't have room, set the OACTIVE flag and wait 2128 * for the NIC to drain the ring. 2129 */ 2130 if (ti_encap(sc, m_head, &prodidx)) { 2131 IF_PREPEND(&ifp->if_snd, m_head); 2132 ifp->if_flags |= IFF_OACTIVE; 2133 break; 2134 } 2135 2136 /* 2137 * If there's a BPF listener, bounce a copy of this frame 2138 * to him. 2139 */ 2140 if (ifp->if_bpf) 2141 bpf_mtap(ifp, m_head); 2142 } 2143 2144 /* Transmit */ 2145 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2146 2147 /* 2148 * Set a timeout in case the chip goes out to lunch. 2149 */ 2150 ifp->if_timer = 5; 2151 2152 return; 2153 } 2154 2155 static void ti_init(xsc) 2156 void *xsc; 2157 { 2158 struct ti_softc *sc = xsc; 2159 int s; 2160 2161 s = splimp(); 2162 2163 /* Cancel pending I/O and flush buffers. */ 2164 ti_stop(sc); 2165 2166 /* Init the gen info block, ring control blocks and firmware. */ 2167 if (ti_gibinit(sc)) { 2168 printf("ti%d: initialization failure\n", sc->ti_unit); 2169 splx(s); 2170 return; 2171 } 2172 2173 splx(s); 2174 2175 return; 2176 } 2177 2178 static void ti_init2(sc) 2179 struct ti_softc *sc; 2180 { 2181 struct ti_cmd_desc cmd; 2182 struct ifnet *ifp; 2183 u_int16_t *m; 2184 struct ifmedia *ifm; 2185 int tmp; 2186 2187 ifp = &sc->arpcom.ac_if; 2188 2189 /* Specify MTU and interface index. */ 2190 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2191 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2192 ETHER_HDR_LEN + ETHER_CRC_LEN); 2193 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2194 2195 /* Load our MAC address. */ 2196 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2197 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2198 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2199 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2200 2201 /* Enable or disable promiscuous mode as needed. */ 2202 if (ifp->if_flags & IFF_PROMISC) { 2203 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2204 } else { 2205 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2206 } 2207 2208 /* Program multicast filter. */ 2209 ti_setmulti(sc); 2210 2211 /* 2212 * If this is a Tigon 1, we should tell the 2213 * firmware to use software packet filtering. 2214 */ 2215 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2216 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2217 } 2218 2219 /* Init RX ring. */ 2220 ti_init_rx_ring_std(sc); 2221 2222 /* Init jumbo RX ring. */ 2223 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2224 ti_init_rx_ring_jumbo(sc); 2225 2226 /* 2227 * If this is a Tigon 2, we can also configure the 2228 * mini ring. 2229 */ 2230 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2231 ti_init_rx_ring_mini(sc); 2232 2233 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2234 sc->ti_rx_saved_considx = 0; 2235 2236 /* Init TX ring. */ 2237 ti_init_tx_ring(sc); 2238 2239 /* Tell firmware we're alive. */ 2240 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2241 2242 /* Enable host interrupts. */ 2243 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2244 2245 ifp->if_flags |= IFF_RUNNING; 2246 ifp->if_flags &= ~IFF_OACTIVE; 2247 2248 /* 2249 * Make sure to set media properly. We have to do this 2250 * here since we have to issue commands in order to set 2251 * the link negotiation and we can't issue commands until 2252 * the firmware is running. 2253 */ 2254 ifm = &sc->ifmedia; 2255 tmp = ifm->ifm_media; 2256 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2257 ti_ifmedia_upd(ifp); 2258 ifm->ifm_media = tmp; 2259 2260 return; 2261 } 2262 2263 /* 2264 * Set media options. 2265 */ 2266 static int ti_ifmedia_upd(ifp) 2267 struct ifnet *ifp; 2268 { 2269 struct ti_softc *sc; 2270 struct ifmedia *ifm; 2271 struct ti_cmd_desc cmd; 2272 2273 sc = ifp->if_softc; 2274 ifm = &sc->ifmedia; 2275 2276 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2277 return(EINVAL); 2278 2279 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2280 case IFM_AUTO: 2281 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2282 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2283 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2284 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2285 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2286 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2287 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2288 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2289 break; 2290 case IFM_1000_SX: 2291 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2292 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2293 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2294 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2295 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2296 break; 2297 case IFM_100_FX: 2298 case IFM_10_FL: 2299 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2300 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2301 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2302 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2303 } else { 2304 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2305 } 2306 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2307 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2308 } else { 2309 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2310 } 2311 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2312 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2313 break; 2314 } 2315 2316 return(0); 2317 } 2318 2319 /* 2320 * Report current media status. 2321 */ 2322 static void ti_ifmedia_sts(ifp, ifmr) 2323 struct ifnet *ifp; 2324 struct ifmediareq *ifmr; 2325 { 2326 struct ti_softc *sc; 2327 2328 sc = ifp->if_softc; 2329 2330 ifmr->ifm_status = IFM_AVALID; 2331 ifmr->ifm_active = IFM_ETHER; 2332 2333 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2334 return; 2335 2336 ifmr->ifm_status |= IFM_ACTIVE; 2337 2338 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2339 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2340 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2341 u_int32_t media; 2342 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2343 if (media & TI_LNK_100MB) 2344 ifmr->ifm_active |= IFM_100_FX; 2345 if (media & TI_LNK_10MB) 2346 ifmr->ifm_active |= IFM_10_FL; 2347 if (media & TI_LNK_FULL_DUPLEX) 2348 ifmr->ifm_active |= IFM_FDX; 2349 if (media & TI_LNK_HALF_DUPLEX) 2350 ifmr->ifm_active |= IFM_HDX; 2351 } 2352 2353 return; 2354 } 2355 2356 static int ti_ioctl(ifp, command, data) 2357 struct ifnet *ifp; 2358 u_long command; 2359 caddr_t data; 2360 { 2361 struct ti_softc *sc = ifp->if_softc; 2362 struct ifreq *ifr = (struct ifreq *) data; 2363 int s, error = 0; 2364 struct ti_cmd_desc cmd; 2365 2366 s = splimp(); 2367 2368 switch(command) { 2369 case SIOCSIFADDR: 2370 case SIOCGIFADDR: 2371 error = ether_ioctl(ifp, command, data); 2372 break; 2373 case SIOCSIFMTU: 2374 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2375 error = EINVAL; 2376 else { 2377 ifp->if_mtu = ifr->ifr_mtu; 2378 ti_init(sc); 2379 } 2380 break; 2381 case SIOCSIFFLAGS: 2382 if (ifp->if_flags & IFF_UP) { 2383 /* 2384 * If only the state of the PROMISC flag changed, 2385 * then just use the 'set promisc mode' command 2386 * instead of reinitializing the entire NIC. Doing 2387 * a full re-init means reloading the firmware and 2388 * waiting for it to start up, which may take a 2389 * second or two. 2390 */ 2391 if (ifp->if_flags & IFF_RUNNING && 2392 ifp->if_flags & IFF_PROMISC && 2393 !(sc->ti_if_flags & IFF_PROMISC)) { 2394 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2395 TI_CMD_CODE_PROMISC_ENB, 0); 2396 } else if (ifp->if_flags & IFF_RUNNING && 2397 !(ifp->if_flags & IFF_PROMISC) && 2398 sc->ti_if_flags & IFF_PROMISC) { 2399 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2400 TI_CMD_CODE_PROMISC_DIS, 0); 2401 } else 2402 ti_init(sc); 2403 } else { 2404 if (ifp->if_flags & IFF_RUNNING) { 2405 ti_stop(sc); 2406 } 2407 } 2408 sc->ti_if_flags = ifp->if_flags; 2409 error = 0; 2410 break; 2411 case SIOCADDMULTI: 2412 case SIOCDELMULTI: 2413 if (ifp->if_flags & IFF_RUNNING) { 2414 ti_setmulti(sc); 2415 error = 0; 2416 } 2417 break; 2418 case SIOCSIFMEDIA: 2419 case SIOCGIFMEDIA: 2420 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2421 break; 2422 default: 2423 error = EINVAL; 2424 break; 2425 } 2426 2427 (void)splx(s); 2428 2429 return(error); 2430 } 2431 2432 static void ti_watchdog(ifp) 2433 struct ifnet *ifp; 2434 { 2435 struct ti_softc *sc; 2436 2437 sc = ifp->if_softc; 2438 2439 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2440 ti_stop(sc); 2441 ti_init(sc); 2442 2443 ifp->if_oerrors++; 2444 2445 return; 2446 } 2447 2448 /* 2449 * Stop the adapter and free any mbufs allocated to the 2450 * RX and TX lists. 2451 */ 2452 static void ti_stop(sc) 2453 struct ti_softc *sc; 2454 { 2455 struct ifnet *ifp; 2456 struct ti_cmd_desc cmd; 2457 2458 ifp = &sc->arpcom.ac_if; 2459 2460 /* Disable host interrupts. */ 2461 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2462 /* 2463 * Tell firmware we're shutting down. 2464 */ 2465 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2466 2467 /* Halt and reinitialize. */ 2468 ti_chipinit(sc); 2469 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2470 ti_chipinit(sc); 2471 2472 /* Free the RX lists. */ 2473 ti_free_rx_ring_std(sc); 2474 2475 /* Free jumbo RX list. */ 2476 ti_free_rx_ring_jumbo(sc); 2477 2478 /* Free mini RX list. */ 2479 ti_free_rx_ring_mini(sc); 2480 2481 /* Free TX buffers. */ 2482 ti_free_tx_ring(sc); 2483 2484 sc->ti_ev_prodidx.ti_idx = 0; 2485 sc->ti_return_prodidx.ti_idx = 0; 2486 sc->ti_tx_considx.ti_idx = 0; 2487 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2488 2489 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2490 2491 return; 2492 } 2493 2494 /* 2495 * Stop all chip I/O so that the kernel's probe routines don't 2496 * get confused by errant DMAs when rebooting. 2497 */ 2498 static void ti_shutdown(dev) 2499 device_t dev; 2500 { 2501 struct ti_softc *sc; 2502 2503 sc = device_get_softc(dev); 2504 2505 ti_chipinit(sc); 2506 2507 return; 2508 } 2509