1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring descriptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include <sys/cdefs.h> 82 __FBSDID("$FreeBSD$"); 83 84 #include "opt_ti.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/sockio.h> 89 #include <sys/mbuf.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/module.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 #include <sys/conf.h> 96 #include <sys/sf_buf.h> 97 98 #include <net/if.h> 99 #include <net/if_var.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <netinet/in_systm.h> 110 #include <netinet/in.h> 111 #include <netinet/ip.h> 112 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #ifdef TI_SF_BUF_JUMBO 119 #include <vm/vm.h> 120 #include <vm/vm_page.h> 121 #endif 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #include <sys/tiio.h> 127 #include <dev/ti/if_tireg.h> 128 #include <dev/ti/ti_fw.h> 129 #include <dev/ti/ti_fw2.h> 130 131 #include <sys/sysctl.h> 132 133 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 134 /* 135 * We can only turn on header splitting if we're using extended receive 136 * BDs. 137 */ 138 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 139 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 140 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 141 142 typedef enum { 143 TI_SWAP_HTON, 144 TI_SWAP_NTOH 145 } ti_swap_type; 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 151 static const struct ti_type ti_devs[] = { 152 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 153 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 154 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 155 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 156 { TC_VENDORID, TC_DEVICEID_3C985, 157 "3Com 3c985-SX Gigabit Ethernet" }, 158 { NG_VENDORID, NG_DEVICEID_GA620, 159 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 160 { NG_VENDORID, NG_DEVICEID_GA620T, 161 "Netgear GA620 1000baseT Gigabit Ethernet" }, 162 { SGI_VENDORID, SGI_DEVICEID_TIGON, 163 "Silicon Graphics Gigabit Ethernet" }, 164 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 165 "Farallon PN9000SX Gigabit Ethernet" }, 166 { 0, 0, NULL } 167 }; 168 169 static d_open_t ti_open; 170 static d_close_t ti_close; 171 static d_ioctl_t ti_ioctl2; 172 173 static struct cdevsw ti_cdevsw = { 174 .d_version = D_VERSION, 175 .d_flags = 0, 176 .d_open = ti_open, 177 .d_close = ti_close, 178 .d_ioctl = ti_ioctl2, 179 .d_name = "ti", 180 }; 181 182 static int ti_probe(device_t); 183 static int ti_attach(device_t); 184 static int ti_detach(device_t); 185 static void ti_txeof(struct ti_softc *); 186 static void ti_rxeof(struct ti_softc *); 187 188 static int ti_encap(struct ti_softc *, struct mbuf **); 189 190 static void ti_intr(void *); 191 static void ti_start(struct ifnet *); 192 static void ti_start_locked(struct ifnet *); 193 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 194 static uint64_t ti_get_counter(struct ifnet *, ift_counter); 195 static void ti_init(void *); 196 static void ti_init_locked(void *); 197 static void ti_init2(struct ti_softc *); 198 static void ti_stop(struct ti_softc *); 199 static void ti_watchdog(void *); 200 static int ti_shutdown(device_t); 201 static int ti_ifmedia_upd(struct ifnet *); 202 static int ti_ifmedia_upd_locked(struct ti_softc *); 203 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 205 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 206 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 207 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 208 209 static u_int ti_add_mcast(void *, struct sockaddr_dl *, u_int); 210 static u_int ti_del_mcast(void *, struct sockaddr_dl *, u_int); 211 static void ti_setmulti(struct ti_softc *); 212 213 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 214 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 215 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 216 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 217 int); 218 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 219 int, int, int); 220 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 221 static void ti_loadfw(struct ti_softc *); 222 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 223 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 224 static void ti_handle_events(struct ti_softc *); 225 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 226 static int ti_dma_alloc(struct ti_softc *); 227 static void ti_dma_free(struct ti_softc *); 228 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 229 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 230 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 231 bus_dmamap_t, bus_addr_t *); 232 static int ti_newbuf_std(struct ti_softc *, int); 233 static int ti_newbuf_mini(struct ti_softc *, int); 234 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 235 static int ti_init_rx_ring_std(struct ti_softc *); 236 static void ti_free_rx_ring_std(struct ti_softc *); 237 static int ti_init_rx_ring_jumbo(struct ti_softc *); 238 static void ti_free_rx_ring_jumbo(struct ti_softc *); 239 static int ti_init_rx_ring_mini(struct ti_softc *); 240 static void ti_free_rx_ring_mini(struct ti_softc *); 241 static void ti_free_tx_ring(struct ti_softc *); 242 static int ti_init_tx_ring(struct ti_softc *); 243 static void ti_discard_std(struct ti_softc *, int); 244 #ifndef TI_SF_BUF_JUMBO 245 static void ti_discard_jumbo(struct ti_softc *, int); 246 #endif 247 static void ti_discard_mini(struct ti_softc *, int); 248 249 static int ti_64bitslot_war(struct ti_softc *); 250 static int ti_chipinit(struct ti_softc *); 251 static int ti_gibinit(struct ti_softc *); 252 253 #ifdef TI_JUMBO_HDRSPLIT 254 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 255 int idx); 256 #endif /* TI_JUMBO_HDRSPLIT */ 257 258 static void ti_sysctl_node(struct ti_softc *); 259 260 static device_method_t ti_methods[] = { 261 /* Device interface */ 262 DEVMETHOD(device_probe, ti_probe), 263 DEVMETHOD(device_attach, ti_attach), 264 DEVMETHOD(device_detach, ti_detach), 265 DEVMETHOD(device_shutdown, ti_shutdown), 266 { 0, 0 } 267 }; 268 269 static driver_t ti_driver = { 270 "ti", 271 ti_methods, 272 sizeof(struct ti_softc) 273 }; 274 275 static devclass_t ti_devclass; 276 277 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 278 MODULE_DEPEND(ti, pci, 1, 1, 1); 279 MODULE_DEPEND(ti, ether, 1, 1, 1); 280 281 /* 282 * Send an instruction or address to the EEPROM, check for ACK. 283 */ 284 static uint32_t 285 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 286 { 287 int i, ack = 0; 288 289 /* 290 * Make sure we're in TX mode. 291 */ 292 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 293 294 /* 295 * Feed in each bit and stobe the clock. 296 */ 297 for (i = 0x80; i; i >>= 1) { 298 if (byte & i) { 299 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 300 } else { 301 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 302 } 303 DELAY(1); 304 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 305 DELAY(1); 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 307 } 308 309 /* 310 * Turn off TX mode. 311 */ 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 313 314 /* 315 * Check for ack. 316 */ 317 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 318 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 320 321 return (ack); 322 } 323 324 /* 325 * Read a byte of data stored in the EEPROM at address 'addr.' 326 * We have to send two address bytes since the EEPROM can hold 327 * more than 256 bytes of data. 328 */ 329 static uint8_t 330 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 331 { 332 int i; 333 uint8_t byte = 0; 334 335 EEPROM_START; 336 337 /* 338 * Send write control code to EEPROM. 339 */ 340 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 341 device_printf(sc->ti_dev, 342 "failed to send write command, status: %x\n", 343 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 344 return (1); 345 } 346 347 /* 348 * Send first byte of address of byte we want to read. 349 */ 350 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 351 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353 return (1); 354 } 355 /* 356 * Send second byte address of byte we want to read. 357 */ 358 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 359 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 360 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 361 return (1); 362 } 363 364 EEPROM_STOP; 365 EEPROM_START; 366 /* 367 * Send read control code to EEPROM. 368 */ 369 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 370 device_printf(sc->ti_dev, 371 "failed to send read command, status: %x\n", 372 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 373 return (1); 374 } 375 376 /* 377 * Start reading bits from EEPROM. 378 */ 379 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 380 for (i = 0x80; i; i >>= 1) { 381 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 382 DELAY(1); 383 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 384 byte |= i; 385 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 386 DELAY(1); 387 } 388 389 EEPROM_STOP; 390 391 /* 392 * No ACK generated for read, so just return byte. 393 */ 394 395 *dest = byte; 396 397 return (0); 398 } 399 400 /* 401 * Read a sequence of bytes from the EEPROM. 402 */ 403 static int 404 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 405 { 406 int err = 0, i; 407 uint8_t byte = 0; 408 409 for (i = 0; i < cnt; i++) { 410 err = ti_eeprom_getbyte(sc, off + i, &byte); 411 if (err) 412 break; 413 *(dest + i) = byte; 414 } 415 416 return (err ? 1 : 0); 417 } 418 419 /* 420 * NIC memory read function. 421 * Can be used to copy data from NIC local memory. 422 */ 423 static void 424 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 425 { 426 int segptr, segsize, cnt; 427 char *ptr; 428 429 segptr = addr; 430 cnt = len; 431 ptr = buf; 432 433 while (cnt) { 434 if (cnt < TI_WINLEN) 435 segsize = cnt; 436 else 437 segsize = TI_WINLEN - (segptr % TI_WINLEN); 438 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 439 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 440 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 441 segsize / 4); 442 ptr += segsize; 443 segptr += segsize; 444 cnt -= segsize; 445 } 446 } 447 448 /* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452 static void 453 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 454 { 455 int segptr, segsize, cnt; 456 char *ptr; 457 458 segptr = addr; 459 cnt = len; 460 ptr = buf; 461 462 while (cnt) { 463 if (cnt < TI_WINLEN) 464 segsize = cnt; 465 else 466 segsize = TI_WINLEN - (segptr % TI_WINLEN); 467 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 468 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 469 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 470 segsize / 4); 471 ptr += segsize; 472 segptr += segsize; 473 cnt -= segsize; 474 } 475 } 476 477 /* 478 * NIC memory read function. 479 * Can be used to clear a section of NIC local memory. 480 */ 481 static void 482 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 483 { 484 int segptr, segsize, cnt; 485 486 segptr = addr; 487 cnt = len; 488 489 while (cnt) { 490 if (cnt < TI_WINLEN) 491 segsize = cnt; 492 else 493 segsize = TI_WINLEN - (segptr % TI_WINLEN); 494 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 495 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 496 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 497 segptr += segsize; 498 cnt -= segsize; 499 } 500 } 501 502 static int 503 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 504 caddr_t buf, int useraddr, int readdata) 505 { 506 int segptr, segsize, cnt; 507 caddr_t ptr; 508 uint32_t origwin; 509 int resid, segresid; 510 int first_pass; 511 512 TI_LOCK_ASSERT(sc); 513 514 /* 515 * At the moment, we don't handle non-aligned cases, we just bail. 516 * If this proves to be a problem, it will be fixed. 517 */ 518 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 519 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 520 "word-aligned\n", __func__, tigon_addr); 521 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 522 "yet supported\n", __func__); 523 return (EINVAL); 524 } 525 526 segptr = tigon_addr & ~0x3; 527 segresid = tigon_addr - segptr; 528 529 /* 530 * This is the non-aligned amount left over that we'll need to 531 * copy. 532 */ 533 resid = len & 0x3; 534 535 /* Add in the left over amount at the front of the buffer */ 536 resid += segresid; 537 538 cnt = len & ~0x3; 539 /* 540 * If resid + segresid is >= 4, add multiples of 4 to the count and 541 * decrease the residual by that much. 542 */ 543 cnt += resid & ~0x3; 544 resid -= resid & ~0x3; 545 546 ptr = buf; 547 548 first_pass = 1; 549 550 /* 551 * Save the old window base value. 552 */ 553 origwin = CSR_READ_4(sc, TI_WINBASE); 554 555 while (cnt) { 556 bus_size_t ti_offset; 557 558 if (cnt < TI_WINLEN) 559 segsize = cnt; 560 else 561 segsize = TI_WINLEN - (segptr % TI_WINLEN); 562 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 563 564 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 565 566 if (readdata) { 567 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 568 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 569 if (useraddr) { 570 /* 571 * Yeah, this is a little on the kludgy 572 * side, but at least this code is only 573 * used for debugging. 574 */ 575 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 576 segsize, TI_SWAP_NTOH); 577 578 TI_UNLOCK(sc); 579 if (first_pass) { 580 copyout(&sc->ti_membuf2[segresid], ptr, 581 segsize - segresid); 582 first_pass = 0; 583 } else 584 copyout(sc->ti_membuf2, ptr, segsize); 585 TI_LOCK(sc); 586 } else { 587 if (first_pass) { 588 ti_bcopy_swap(sc->ti_membuf, 589 sc->ti_membuf2, segsize, 590 TI_SWAP_NTOH); 591 TI_UNLOCK(sc); 592 bcopy(&sc->ti_membuf2[segresid], ptr, 593 segsize - segresid); 594 TI_LOCK(sc); 595 first_pass = 0; 596 } else 597 ti_bcopy_swap(sc->ti_membuf, ptr, 598 segsize, TI_SWAP_NTOH); 599 } 600 601 } else { 602 if (useraddr) { 603 TI_UNLOCK(sc); 604 copyin(ptr, sc->ti_membuf2, segsize); 605 TI_LOCK(sc); 606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 607 segsize, TI_SWAP_HTON); 608 } else 609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 610 TI_SWAP_HTON); 611 612 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 613 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 614 } 615 segptr += segsize; 616 ptr += segsize; 617 cnt -= segsize; 618 } 619 620 /* 621 * Handle leftover, non-word-aligned bytes. 622 */ 623 if (resid != 0) { 624 uint32_t tmpval, tmpval2; 625 bus_size_t ti_offset; 626 627 /* 628 * Set the segment pointer. 629 */ 630 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 631 632 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 633 634 /* 635 * First, grab whatever is in our source/destination. 636 * We'll obviously need this for reads, but also for 637 * writes, since we'll be doing read/modify/write. 638 */ 639 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 640 ti_offset, &tmpval, 1); 641 642 /* 643 * Next, translate this from little-endian to big-endian 644 * (at least on i386 boxes). 645 */ 646 tmpval2 = ntohl(tmpval); 647 648 if (readdata) { 649 /* 650 * If we're reading, just copy the leftover number 651 * of bytes from the host byte order buffer to 652 * the user's buffer. 653 */ 654 if (useraddr) { 655 TI_UNLOCK(sc); 656 copyout(&tmpval2, ptr, resid); 657 TI_LOCK(sc); 658 } else 659 bcopy(&tmpval2, ptr, resid); 660 } else { 661 /* 662 * If we're writing, first copy the bytes to be 663 * written into the network byte order buffer, 664 * leaving the rest of the buffer with whatever was 665 * originally in there. Then, swap the bytes 666 * around into host order and write them out. 667 * 668 * XXX KDM the read side of this has been verified 669 * to work, but the write side of it has not been 670 * verified. So user beware. 671 */ 672 if (useraddr) { 673 TI_UNLOCK(sc); 674 copyin(ptr, &tmpval2, resid); 675 TI_LOCK(sc); 676 } else 677 bcopy(ptr, &tmpval2, resid); 678 679 tmpval = htonl(tmpval2); 680 681 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 682 ti_offset, &tmpval, 1); 683 } 684 } 685 686 CSR_WRITE_4(sc, TI_WINBASE, origwin); 687 688 return (0); 689 } 690 691 static int 692 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 693 caddr_t buf, int useraddr, int readdata, int cpu) 694 { 695 uint32_t segptr; 696 int cnt; 697 uint32_t tmpval, tmpval2; 698 caddr_t ptr; 699 700 TI_LOCK_ASSERT(sc); 701 702 /* 703 * At the moment, we don't handle non-aligned cases, we just bail. 704 * If this proves to be a problem, it will be fixed. 705 */ 706 if (tigon_addr & 0x3) { 707 device_printf(sc->ti_dev, "%s: tigon address %#x " 708 "isn't word-aligned\n", __func__, tigon_addr); 709 return (EINVAL); 710 } 711 712 if (len & 0x3) { 713 device_printf(sc->ti_dev, "%s: transfer length %d " 714 "isn't word-aligned\n", __func__, len); 715 return (EINVAL); 716 } 717 718 segptr = tigon_addr; 719 cnt = len; 720 ptr = buf; 721 722 while (cnt) { 723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 724 725 if (readdata) { 726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 727 728 tmpval = ntohl(tmpval2); 729 730 /* 731 * Note: I've used this debugging interface 732 * extensively with Alteon's 12.3.15 firmware, 733 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 734 * 735 * When you compile the firmware without 736 * optimization, which is necessary sometimes in 737 * order to properly step through it, you sometimes 738 * read out a bogus value of 0xc0017c instead of 739 * whatever was supposed to be in that scratchpad 740 * location. That value is on the stack somewhere, 741 * but I've never been able to figure out what was 742 * causing the problem. 743 * 744 * The address seems to pop up in random places, 745 * often not in the same place on two subsequent 746 * reads. 747 * 748 * In any case, the underlying data doesn't seem 749 * to be affected, just the value read out. 750 * 751 * KDM, 3/7/2000 752 */ 753 754 if (tmpval2 == 0xc0017c) 755 device_printf(sc->ti_dev, "found 0xc0017c at " 756 "%#x (tmpval2)\n", segptr); 757 758 if (tmpval == 0xc0017c) 759 device_printf(sc->ti_dev, "found 0xc0017c at " 760 "%#x (tmpval)\n", segptr); 761 762 if (useraddr) 763 copyout(&tmpval, ptr, 4); 764 else 765 bcopy(&tmpval, ptr, 4); 766 } else { 767 if (useraddr) 768 copyin(ptr, &tmpval2, 4); 769 else 770 bcopy(ptr, &tmpval2, 4); 771 772 tmpval = htonl(tmpval2); 773 774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 775 } 776 777 cnt -= 4; 778 segptr += 4; 779 ptr += 4; 780 } 781 782 return (0); 783 } 784 785 static int 786 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 787 { 788 const uint8_t *tmpsrc; 789 uint8_t *tmpdst; 790 size_t tmplen; 791 792 if (len & 0x3) { 793 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 794 return (-1); 795 } 796 797 tmpsrc = src; 798 tmpdst = dst; 799 tmplen = len; 800 801 while (tmplen) { 802 if (swap_type == TI_SWAP_NTOH) 803 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 804 else 805 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 806 tmpsrc += 4; 807 tmpdst += 4; 808 tmplen -= 4; 809 } 810 811 return (0); 812 } 813 814 /* 815 * Load firmware image into the NIC. Check that the firmware revision 816 * is acceptable and see if we want the firmware for the Tigon 1 or 817 * Tigon 2. 818 */ 819 static void 820 ti_loadfw(struct ti_softc *sc) 821 { 822 823 TI_LOCK_ASSERT(sc); 824 825 switch (sc->ti_hwrev) { 826 case TI_HWREV_TIGON: 827 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 828 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 829 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 830 device_printf(sc->ti_dev, "firmware revision mismatch; " 831 "want %d.%d.%d, got %d.%d.%d\n", 832 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 833 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 834 tigonFwReleaseMinor, tigonFwReleaseFix); 835 return; 836 } 837 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 838 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 839 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 840 tigonFwRodata); 841 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 842 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 843 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 844 break; 845 case TI_HWREV_TIGON_II: 846 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 847 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 848 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 849 device_printf(sc->ti_dev, "firmware revision mismatch; " 850 "want %d.%d.%d, got %d.%d.%d\n", 851 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 852 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 853 tigon2FwReleaseMinor, tigon2FwReleaseFix); 854 return; 855 } 856 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 857 tigon2FwText); 858 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 859 tigon2FwData); 860 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 861 tigon2FwRodata); 862 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 863 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 864 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 865 break; 866 default: 867 device_printf(sc->ti_dev, 868 "can't load firmware: unknown hardware rev\n"); 869 break; 870 } 871 } 872 873 /* 874 * Send the NIC a command via the command ring. 875 */ 876 static void 877 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 878 { 879 int index; 880 881 index = sc->ti_cmd_saved_prodidx; 882 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 883 TI_INC(index, TI_CMD_RING_CNT); 884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 885 sc->ti_cmd_saved_prodidx = index; 886 } 887 888 /* 889 * Send the NIC an extended command. The 'len' parameter specifies the 890 * number of command slots to include after the initial command. 891 */ 892 static void 893 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 894 { 895 int index; 896 int i; 897 898 index = sc->ti_cmd_saved_prodidx; 899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 900 TI_INC(index, TI_CMD_RING_CNT); 901 for (i = 0; i < len; i++) { 902 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 903 *(uint32_t *)(&arg[i * 4])); 904 TI_INC(index, TI_CMD_RING_CNT); 905 } 906 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 907 sc->ti_cmd_saved_prodidx = index; 908 } 909 910 /* 911 * Handle events that have triggered interrupts. 912 */ 913 static void 914 ti_handle_events(struct ti_softc *sc) 915 { 916 struct ti_event_desc *e; 917 918 if (sc->ti_rdata.ti_event_ring == NULL) 919 return; 920 921 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 922 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 923 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 924 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 925 switch (TI_EVENT_EVENT(e)) { 926 case TI_EV_LINKSTAT_CHANGED: 927 sc->ti_linkstat = TI_EVENT_CODE(e); 928 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 929 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 930 sc->ti_ifp->if_baudrate = IF_Mbps(100); 931 if (bootverbose) 932 device_printf(sc->ti_dev, 933 "10/100 link up\n"); 934 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "gigabit link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 941 if_link_state_change(sc->ti_ifp, 942 LINK_STATE_DOWN); 943 sc->ti_ifp->if_baudrate = 0; 944 if (bootverbose) 945 device_printf(sc->ti_dev, 946 "link down\n"); 947 } 948 break; 949 case TI_EV_ERROR: 950 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 951 device_printf(sc->ti_dev, "invalid command\n"); 952 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 953 device_printf(sc->ti_dev, "unknown command\n"); 954 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 955 device_printf(sc->ti_dev, "bad config data\n"); 956 break; 957 case TI_EV_FIRMWARE_UP: 958 ti_init2(sc); 959 break; 960 case TI_EV_STATS_UPDATED: 961 case TI_EV_RESET_JUMBO_RING: 962 case TI_EV_MCAST_UPDATED: 963 /* Who cares. */ 964 break; 965 default: 966 device_printf(sc->ti_dev, "unknown event: %d\n", 967 TI_EVENT_EVENT(e)); 968 break; 969 } 970 /* Advance the consumer index. */ 971 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 972 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 973 } 974 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 975 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 976 } 977 978 struct ti_dmamap_arg { 979 bus_addr_t ti_busaddr; 980 }; 981 982 static void 983 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 984 { 985 struct ti_dmamap_arg *ctx; 986 987 if (error) 988 return; 989 990 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 991 992 ctx = arg; 993 ctx->ti_busaddr = segs->ds_addr; 994 } 995 996 static int 997 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 998 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 999 const char *msg) 1000 { 1001 struct ti_dmamap_arg ctx; 1002 int error; 1003 1004 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1005 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1006 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1007 if (error != 0) { 1008 device_printf(sc->ti_dev, 1009 "could not create %s dma tag\n", msg); 1010 return (error); 1011 } 1012 /* Allocate DMA'able memory for ring. */ 1013 error = bus_dmamem_alloc(*tag, (void **)ring, 1014 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1015 if (error != 0) { 1016 device_printf(sc->ti_dev, 1017 "could not allocate DMA'able memory for %s\n", msg); 1018 return (error); 1019 } 1020 /* Load the address of the ring. */ 1021 ctx.ti_busaddr = 0; 1022 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1023 &ctx, BUS_DMA_NOWAIT); 1024 if (error != 0) { 1025 device_printf(sc->ti_dev, 1026 "could not load DMA'able memory for %s\n", msg); 1027 return (error); 1028 } 1029 *paddr = ctx.ti_busaddr; 1030 return (0); 1031 } 1032 1033 static void 1034 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1035 bus_dmamap_t map, bus_addr_t *paddr) 1036 { 1037 1038 if (*paddr != 0) { 1039 bus_dmamap_unload(*tag, map); 1040 *paddr = 0; 1041 } 1042 if (*ring != NULL) { 1043 bus_dmamem_free(*tag, *ring, map); 1044 *ring = NULL; 1045 } 1046 if (*tag) { 1047 bus_dma_tag_destroy(*tag); 1048 *tag = NULL; 1049 } 1050 } 1051 1052 static int 1053 ti_dma_alloc(struct ti_softc *sc) 1054 { 1055 bus_addr_t lowaddr; 1056 int i, error; 1057 1058 lowaddr = BUS_SPACE_MAXADDR; 1059 if (sc->ti_dac == 0) 1060 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1061 1062 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1063 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1064 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1065 &sc->ti_cdata.ti_parent_tag); 1066 if (error != 0) { 1067 device_printf(sc->ti_dev, 1068 "could not allocate parent dma tag\n"); 1069 return (ENOMEM); 1070 } 1071 1072 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1073 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1074 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1075 if (error) 1076 return (error); 1077 1078 /* Producer/consumer status */ 1079 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1080 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1081 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1082 "event ring"); 1083 if (error) 1084 return (error); 1085 1086 /* Event ring */ 1087 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1088 &sc->ti_cdata.ti_event_ring_tag, 1089 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1090 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1091 "event ring"); 1092 if (error) 1093 return (error); 1094 1095 /* Command ring lives in shared memory so no need to create DMA area. */ 1096 1097 /* Standard RX ring */ 1098 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1099 &sc->ti_cdata.ti_rx_std_ring_tag, 1100 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1101 &sc->ti_cdata.ti_rx_std_ring_map, 1102 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1103 if (error) 1104 return (error); 1105 1106 /* Jumbo RX ring */ 1107 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1108 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1109 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1110 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1111 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1112 if (error) 1113 return (error); 1114 1115 /* RX return ring */ 1116 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1117 &sc->ti_cdata.ti_rx_return_ring_tag, 1118 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1119 &sc->ti_cdata.ti_rx_return_ring_map, 1120 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1121 if (error) 1122 return (error); 1123 1124 /* Create DMA tag for standard RX mbufs. */ 1125 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1126 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1127 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1128 if (error) { 1129 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1130 return (error); 1131 } 1132 1133 /* Create DMA tag for jumbo RX mbufs. */ 1134 #ifdef TI_SF_BUF_JUMBO 1135 /* 1136 * The VM system will take care of providing aligned pages. Alignment 1137 * is set to 1 here so that busdma resources won't be wasted. 1138 */ 1139 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1140 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1141 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1142 #else 1143 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1144 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1145 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1146 #endif 1147 if (error) { 1148 device_printf(sc->ti_dev, 1149 "could not allocate jumbo RX dma tag\n"); 1150 return (error); 1151 } 1152 1153 /* Create DMA tag for TX mbufs. */ 1154 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1155 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1156 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1157 &sc->ti_cdata.ti_tx_tag); 1158 if (error) { 1159 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1160 return (ENOMEM); 1161 } 1162 1163 /* Create DMA maps for RX buffers. */ 1164 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1165 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1166 &sc->ti_cdata.ti_rx_std_maps[i]); 1167 if (error) { 1168 device_printf(sc->ti_dev, 1169 "could not create DMA map for RX\n"); 1170 return (error); 1171 } 1172 } 1173 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1174 &sc->ti_cdata.ti_rx_std_sparemap); 1175 if (error) { 1176 device_printf(sc->ti_dev, 1177 "could not create spare DMA map for RX\n"); 1178 return (error); 1179 } 1180 1181 /* Create DMA maps for jumbo RX buffers. */ 1182 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1183 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1184 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1185 if (error) { 1186 device_printf(sc->ti_dev, 1187 "could not create DMA map for jumbo RX\n"); 1188 return (error); 1189 } 1190 } 1191 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1192 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1193 if (error) { 1194 device_printf(sc->ti_dev, 1195 "could not create spare DMA map for jumbo RX\n"); 1196 return (error); 1197 } 1198 1199 /* Create DMA maps for TX buffers. */ 1200 for (i = 0; i < TI_TX_RING_CNT; i++) { 1201 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1202 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1203 if (error) { 1204 device_printf(sc->ti_dev, 1205 "could not create DMA map for TX\n"); 1206 return (ENOMEM); 1207 } 1208 } 1209 1210 /* Mini ring and TX ring is not available on Tigon 1. */ 1211 if (sc->ti_hwrev == TI_HWREV_TIGON) 1212 return (0); 1213 1214 /* TX ring */ 1215 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1216 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1217 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1218 "TX ring"); 1219 if (error) 1220 return (error); 1221 1222 /* Mini RX ring */ 1223 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1224 &sc->ti_cdata.ti_rx_mini_ring_tag, 1225 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1226 &sc->ti_cdata.ti_rx_mini_ring_map, 1227 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1228 if (error) 1229 return (error); 1230 1231 /* Create DMA tag for mini RX mbufs. */ 1232 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1233 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1234 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1235 if (error) { 1236 device_printf(sc->ti_dev, 1237 "could not allocate mini RX dma tag\n"); 1238 return (error); 1239 } 1240 1241 /* Create DMA maps for mini RX buffers. */ 1242 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1243 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1244 &sc->ti_cdata.ti_rx_mini_maps[i]); 1245 if (error) { 1246 device_printf(sc->ti_dev, 1247 "could not create DMA map for mini RX\n"); 1248 return (error); 1249 } 1250 } 1251 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1252 &sc->ti_cdata.ti_rx_mini_sparemap); 1253 if (error) { 1254 device_printf(sc->ti_dev, 1255 "could not create spare DMA map for mini RX\n"); 1256 return (error); 1257 } 1258 1259 return (0); 1260 } 1261 1262 static void 1263 ti_dma_free(struct ti_softc *sc) 1264 { 1265 int i; 1266 1267 /* Destroy DMA maps for RX buffers. */ 1268 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1269 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1270 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1271 sc->ti_cdata.ti_rx_std_maps[i]); 1272 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1273 } 1274 } 1275 if (sc->ti_cdata.ti_rx_std_sparemap) { 1276 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1277 sc->ti_cdata.ti_rx_std_sparemap); 1278 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1279 } 1280 if (sc->ti_cdata.ti_rx_std_tag) { 1281 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1282 sc->ti_cdata.ti_rx_std_tag = NULL; 1283 } 1284 1285 /* Destroy DMA maps for jumbo RX buffers. */ 1286 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1287 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1288 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1289 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1290 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1291 } 1292 } 1293 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1294 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1295 sc->ti_cdata.ti_rx_jumbo_sparemap); 1296 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1297 } 1298 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1299 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1300 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1301 } 1302 1303 /* Destroy DMA maps for mini RX buffers. */ 1304 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1305 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1306 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1307 sc->ti_cdata.ti_rx_mini_maps[i]); 1308 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1309 } 1310 } 1311 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1312 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1313 sc->ti_cdata.ti_rx_mini_sparemap); 1314 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1315 } 1316 if (sc->ti_cdata.ti_rx_mini_tag) { 1317 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1318 sc->ti_cdata.ti_rx_mini_tag = NULL; 1319 } 1320 1321 /* Destroy DMA maps for TX buffers. */ 1322 for (i = 0; i < TI_TX_RING_CNT; i++) { 1323 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1324 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1325 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1327 } 1328 } 1329 if (sc->ti_cdata.ti_tx_tag) { 1330 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1331 sc->ti_cdata.ti_tx_tag = NULL; 1332 } 1333 1334 /* Destroy standard RX ring. */ 1335 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1336 (void *)&sc->ti_rdata.ti_rx_std_ring, 1337 sc->ti_cdata.ti_rx_std_ring_map, 1338 &sc->ti_rdata.ti_rx_std_ring_paddr); 1339 /* Destroy jumbo RX ring. */ 1340 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1341 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1342 sc->ti_cdata.ti_rx_jumbo_ring_map, 1343 &sc->ti_rdata.ti_rx_jumbo_ring_paddr); 1344 /* Destroy mini RX ring. */ 1345 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1346 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1347 sc->ti_cdata.ti_rx_mini_ring_map, 1348 &sc->ti_rdata.ti_rx_mini_ring_paddr); 1349 /* Destroy RX return ring. */ 1350 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1351 (void *)&sc->ti_rdata.ti_rx_return_ring, 1352 sc->ti_cdata.ti_rx_return_ring_map, 1353 &sc->ti_rdata.ti_rx_return_ring_paddr); 1354 /* Destroy TX ring. */ 1355 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1356 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map, 1357 &sc->ti_rdata.ti_tx_ring_paddr); 1358 /* Destroy status block. */ 1359 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1360 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map, 1361 &sc->ti_rdata.ti_status_paddr); 1362 /* Destroy event ring. */ 1363 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1364 (void *)&sc->ti_rdata.ti_event_ring, 1365 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr); 1366 /* Destroy GIB */ 1367 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1368 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map, 1369 &sc->ti_rdata.ti_info_paddr); 1370 1371 /* Destroy the parent tag. */ 1372 if (sc->ti_cdata.ti_parent_tag) { 1373 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1374 sc->ti_cdata.ti_parent_tag = NULL; 1375 } 1376 } 1377 1378 /* 1379 * Intialize a standard receive ring descriptor. 1380 */ 1381 static int 1382 ti_newbuf_std(struct ti_softc *sc, int i) 1383 { 1384 bus_dmamap_t map; 1385 bus_dma_segment_t segs[1]; 1386 struct mbuf *m; 1387 struct ti_rx_desc *r; 1388 int error, nsegs; 1389 1390 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1391 if (m == NULL) 1392 return (ENOBUFS); 1393 m->m_len = m->m_pkthdr.len = MCLBYTES; 1394 m_adj(m, ETHER_ALIGN); 1395 1396 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1397 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1398 if (error != 0) { 1399 m_freem(m); 1400 return (error); 1401 } 1402 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1403 1404 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1405 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1406 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1407 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1408 sc->ti_cdata.ti_rx_std_maps[i]); 1409 } 1410 1411 map = sc->ti_cdata.ti_rx_std_maps[i]; 1412 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1413 sc->ti_cdata.ti_rx_std_sparemap = map; 1414 sc->ti_cdata.ti_rx_std_chain[i] = m; 1415 1416 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1417 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1418 r->ti_len = segs[0].ds_len; 1419 r->ti_type = TI_BDTYPE_RECV_BD; 1420 r->ti_flags = 0; 1421 r->ti_vlan_tag = 0; 1422 r->ti_tcp_udp_cksum = 0; 1423 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1424 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1425 r->ti_idx = i; 1426 1427 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1428 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1429 return (0); 1430 } 1431 1432 /* 1433 * Intialize a mini receive ring descriptor. This only applies to 1434 * the Tigon 2. 1435 */ 1436 static int 1437 ti_newbuf_mini(struct ti_softc *sc, int i) 1438 { 1439 bus_dmamap_t map; 1440 bus_dma_segment_t segs[1]; 1441 struct mbuf *m; 1442 struct ti_rx_desc *r; 1443 int error, nsegs; 1444 1445 MGETHDR(m, M_NOWAIT, MT_DATA); 1446 if (m == NULL) 1447 return (ENOBUFS); 1448 m->m_len = m->m_pkthdr.len = MHLEN; 1449 m_adj(m, ETHER_ALIGN); 1450 1451 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1452 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1453 if (error != 0) { 1454 m_freem(m); 1455 return (error); 1456 } 1457 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1458 1459 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1460 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1461 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1462 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1463 sc->ti_cdata.ti_rx_mini_maps[i]); 1464 } 1465 1466 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1467 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1468 sc->ti_cdata.ti_rx_mini_sparemap = map; 1469 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1470 1471 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1472 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1473 r->ti_len = segs[0].ds_len; 1474 r->ti_type = TI_BDTYPE_RECV_BD; 1475 r->ti_flags = TI_BDFLAG_MINI_RING; 1476 r->ti_vlan_tag = 0; 1477 r->ti_tcp_udp_cksum = 0; 1478 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1479 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1480 r->ti_idx = i; 1481 1482 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1483 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1484 return (0); 1485 } 1486 1487 #ifndef TI_SF_BUF_JUMBO 1488 1489 /* 1490 * Initialize a jumbo receive ring descriptor. This allocates 1491 * a jumbo buffer from the pool managed internally by the driver. 1492 */ 1493 static int 1494 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1495 { 1496 bus_dmamap_t map; 1497 bus_dma_segment_t segs[1]; 1498 struct mbuf *m; 1499 struct ti_rx_desc *r; 1500 int error, nsegs; 1501 1502 (void)dummy; 1503 1504 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1505 if (m == NULL) 1506 return (ENOBUFS); 1507 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1508 m_adj(m, ETHER_ALIGN); 1509 1510 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1511 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1512 if (error != 0) { 1513 m_freem(m); 1514 return (error); 1515 } 1516 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1517 1518 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1519 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1520 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1521 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1522 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1523 } 1524 1525 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1526 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1527 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1528 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1529 1530 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1531 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1532 r->ti_len = segs[0].ds_len; 1533 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1534 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1535 r->ti_vlan_tag = 0; 1536 r->ti_tcp_udp_cksum = 0; 1537 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1538 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1539 r->ti_idx = i; 1540 1541 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1542 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1543 return (0); 1544 } 1545 1546 #else 1547 1548 #if (PAGE_SIZE == 4096) 1549 #define NPAYLOAD 2 1550 #else 1551 #define NPAYLOAD 1 1552 #endif 1553 1554 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1555 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1556 #define NFS_HDR_LEN (UDP_HDR_LEN) 1557 static int HDR_LEN = TCP_HDR_LEN; 1558 1559 /* 1560 * Initialize a jumbo receive ring descriptor. This allocates 1561 * a jumbo buffer from the pool managed internally by the driver. 1562 */ 1563 static int 1564 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1565 { 1566 bus_dmamap_t map; 1567 struct mbuf *cur, *m_new = NULL; 1568 struct mbuf *m[3] = {NULL, NULL, NULL}; 1569 struct ti_rx_desc_ext *r; 1570 vm_page_t frame; 1571 /* 1 extra buf to make nobufs easy*/ 1572 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1573 int i; 1574 bus_dma_segment_t segs[4]; 1575 int nsegs; 1576 1577 if (m_old != NULL) { 1578 m_new = m_old; 1579 cur = m_old->m_next; 1580 for (i = 0; i <= NPAYLOAD; i++){ 1581 m[i] = cur; 1582 cur = cur->m_next; 1583 } 1584 } else { 1585 /* Allocate the mbufs. */ 1586 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1587 if (m_new == NULL) { 1588 device_printf(sc->ti_dev, "mbuf allocation failed " 1589 "-- packet dropped!\n"); 1590 goto nobufs; 1591 } 1592 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA); 1593 if (m[NPAYLOAD] == NULL) { 1594 device_printf(sc->ti_dev, "cluster mbuf allocation " 1595 "failed -- packet dropped!\n"); 1596 goto nobufs; 1597 } 1598 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) { 1599 device_printf(sc->ti_dev, "mbuf allocation failed " 1600 "-- packet dropped!\n"); 1601 goto nobufs; 1602 } 1603 m[NPAYLOAD]->m_len = MCLBYTES; 1604 1605 for (i = 0; i < NPAYLOAD; i++){ 1606 MGET(m[i], M_NOWAIT, MT_DATA); 1607 if (m[i] == NULL) { 1608 device_printf(sc->ti_dev, "mbuf allocation " 1609 "failed -- packet dropped!\n"); 1610 goto nobufs; 1611 } 1612 frame = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | 1613 VM_ALLOC_WIRED); 1614 if (frame == NULL) { 1615 device_printf(sc->ti_dev, "buffer allocation " 1616 "failed -- packet dropped!\n"); 1617 printf(" index %d page %d\n", idx, i); 1618 goto nobufs; 1619 } 1620 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1621 if (sf[i] == NULL) { 1622 vm_page_unwire_noq(frame); 1623 vm_page_free(frame); 1624 device_printf(sc->ti_dev, "buffer allocation " 1625 "failed -- packet dropped!\n"); 1626 printf(" index %d page %d\n", idx, i); 1627 goto nobufs; 1628 } 1629 } 1630 for (i = 0; i < NPAYLOAD; i++){ 1631 /* Attach the buffer to the mbuf. */ 1632 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1633 m[i]->m_len = PAGE_SIZE; 1634 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1635 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i], 1636 0, EXT_DISPOSABLE); 1637 m[i]->m_next = m[i+1]; 1638 } 1639 /* link the buffers to the header */ 1640 m_new->m_next = m[0]; 1641 m_new->m_data += ETHER_ALIGN; 1642 if (sc->ti_hdrsplit) 1643 m_new->m_len = MHLEN - ETHER_ALIGN; 1644 else 1645 m_new->m_len = HDR_LEN; 1646 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1647 } 1648 1649 /* Set up the descriptor. */ 1650 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1651 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1652 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1653 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1654 segs, &nsegs, 0)) 1655 return (ENOBUFS); 1656 if ((nsegs < 1) || (nsegs > 4)) 1657 return (ENOBUFS); 1658 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1659 r->ti_len0 = m_new->m_len; 1660 1661 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1662 r->ti_len1 = PAGE_SIZE; 1663 1664 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1665 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1666 1667 if (PAGE_SIZE == 4096) { 1668 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1669 r->ti_len3 = MCLBYTES; 1670 } else { 1671 r->ti_len3 = 0; 1672 } 1673 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1674 1675 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1676 1677 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1678 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1679 1680 r->ti_idx = idx; 1681 1682 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1683 return (0); 1684 1685 nobufs: 1686 1687 /* 1688 * Warning! : 1689 * This can only be called before the mbufs are strung together. 1690 * If the mbufs are strung together, m_freem() will free the chain, 1691 * so that the later mbufs will be freed multiple times. 1692 */ 1693 if (m_new) 1694 m_freem(m_new); 1695 1696 for (i = 0; i < 3; i++) { 1697 if (m[i]) 1698 m_freem(m[i]); 1699 if (sf[i]) 1700 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]); 1701 } 1702 return (ENOBUFS); 1703 } 1704 #endif 1705 1706 /* 1707 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1708 * that's 1MB or memory, which is a lot. For now, we fill only the first 1709 * 256 ring entries and hope that our CPU is fast enough to keep up with 1710 * the NIC. 1711 */ 1712 static int 1713 ti_init_rx_ring_std(struct ti_softc *sc) 1714 { 1715 int i; 1716 struct ti_cmd_desc cmd; 1717 1718 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1719 if (ti_newbuf_std(sc, i) != 0) 1720 return (ENOBUFS); 1721 } 1722 1723 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1724 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1725 1726 return (0); 1727 } 1728 1729 static void 1730 ti_free_rx_ring_std(struct ti_softc *sc) 1731 { 1732 bus_dmamap_t map; 1733 int i; 1734 1735 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1736 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1737 map = sc->ti_cdata.ti_rx_std_maps[i]; 1738 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1739 BUS_DMASYNC_POSTREAD); 1740 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1741 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1742 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1743 } 1744 } 1745 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1746 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1747 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1748 } 1749 1750 static int 1751 ti_init_rx_ring_jumbo(struct ti_softc *sc) 1752 { 1753 struct ti_cmd_desc cmd; 1754 int i; 1755 1756 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1757 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1758 return (ENOBUFS); 1759 } 1760 1761 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1762 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1763 1764 return (0); 1765 } 1766 1767 static void 1768 ti_free_rx_ring_jumbo(struct ti_softc *sc) 1769 { 1770 bus_dmamap_t map; 1771 int i; 1772 1773 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1774 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1775 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1776 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1777 BUS_DMASYNC_POSTREAD); 1778 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1779 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1780 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1781 } 1782 } 1783 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1784 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1785 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1786 } 1787 1788 static int 1789 ti_init_rx_ring_mini(struct ti_softc *sc) 1790 { 1791 int i; 1792 1793 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1794 if (ti_newbuf_mini(sc, i) != 0) 1795 return (ENOBUFS); 1796 } 1797 1798 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1799 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1800 1801 return (0); 1802 } 1803 1804 static void 1805 ti_free_rx_ring_mini(struct ti_softc *sc) 1806 { 1807 bus_dmamap_t map; 1808 int i; 1809 1810 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1811 return; 1812 1813 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1814 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1815 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1816 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1817 BUS_DMASYNC_POSTREAD); 1818 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1819 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1820 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1821 } 1822 } 1823 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1824 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1825 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1826 } 1827 1828 static void 1829 ti_free_tx_ring(struct ti_softc *sc) 1830 { 1831 struct ti_txdesc *txd; 1832 int i; 1833 1834 if (sc->ti_rdata.ti_tx_ring == NULL) 1835 return; 1836 1837 for (i = 0; i < TI_TX_RING_CNT; i++) { 1838 txd = &sc->ti_cdata.ti_txdesc[i]; 1839 if (txd->tx_m != NULL) { 1840 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1841 BUS_DMASYNC_POSTWRITE); 1842 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1843 txd->tx_dmamap); 1844 m_freem(txd->tx_m); 1845 txd->tx_m = NULL; 1846 } 1847 } 1848 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1849 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1850 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1851 } 1852 1853 static int 1854 ti_init_tx_ring(struct ti_softc *sc) 1855 { 1856 struct ti_txdesc *txd; 1857 int i; 1858 1859 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1860 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1861 for (i = 0; i < TI_TX_RING_CNT; i++) { 1862 txd = &sc->ti_cdata.ti_txdesc[i]; 1863 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1864 } 1865 sc->ti_txcnt = 0; 1866 sc->ti_tx_saved_considx = 0; 1867 sc->ti_tx_saved_prodidx = 0; 1868 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1869 return (0); 1870 } 1871 1872 /* 1873 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1874 * but we have to support the old way too so that Tigon 1 cards will 1875 * work. 1876 */ 1877 static u_int 1878 ti_add_mcast(void *arg, struct sockaddr_dl *sdl, u_int count) 1879 { 1880 struct ti_softc *sc = arg; 1881 struct ti_cmd_desc cmd; 1882 uint16_t *m; 1883 uint32_t ext[2] = {0, 0}; 1884 1885 m = (uint16_t *)LLADDR(sdl); 1886 1887 switch (sc->ti_hwrev) { 1888 case TI_HWREV_TIGON: 1889 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1890 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1891 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1892 break; 1893 case TI_HWREV_TIGON_II: 1894 ext[0] = htons(m[0]); 1895 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1896 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1897 break; 1898 default: 1899 device_printf(sc->ti_dev, "unknown hwrev\n"); 1900 return (0); 1901 } 1902 return (1); 1903 } 1904 1905 static u_int 1906 ti_del_mcast(void *arg, struct sockaddr_dl *sdl, u_int count) 1907 { 1908 struct ti_softc *sc = arg; 1909 struct ti_cmd_desc cmd; 1910 uint16_t *m; 1911 uint32_t ext[2] = {0, 0}; 1912 1913 m = (uint16_t *)LLADDR(sdl); 1914 1915 switch (sc->ti_hwrev) { 1916 case TI_HWREV_TIGON: 1917 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1918 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1919 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1920 break; 1921 case TI_HWREV_TIGON_II: 1922 ext[0] = htons(m[0]); 1923 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1924 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1925 break; 1926 default: 1927 device_printf(sc->ti_dev, "unknown hwrev\n"); 1928 return (0); 1929 } 1930 1931 return (1); 1932 } 1933 1934 /* 1935 * Configure the Tigon's multicast address filter. 1936 * 1937 * The actual multicast table management is a bit of a pain, thanks to 1938 * slight brain damage on the part of both Alteon and us. With our 1939 * multicast code, we are only alerted when the multicast address table 1940 * changes and at that point we only have the current list of addresses: 1941 * we only know the current state, not the previous state, so we don't 1942 * actually know what addresses were removed or added. The firmware has 1943 * state, but we can't get our grubby mits on it, and there is no 'delete 1944 * all multicast addresses' command. Hence, we have to maintain our own 1945 * state so we know what addresses have been programmed into the NIC at 1946 * any given time. 1947 */ 1948 static void 1949 ti_setmulti(struct ti_softc *sc) 1950 { 1951 struct ifnet *ifp; 1952 struct ti_cmd_desc cmd; 1953 uint32_t intrs; 1954 1955 TI_LOCK_ASSERT(sc); 1956 1957 ifp = sc->ti_ifp; 1958 1959 if (ifp->if_flags & IFF_ALLMULTI) { 1960 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1961 return; 1962 } else { 1963 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1964 } 1965 1966 /* Disable interrupts. */ 1967 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1968 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1969 1970 /* First, zot all the existing filters. */ 1971 if_foreach_llmaddr(ifp, ti_del_mcast, sc); 1972 1973 /* Now program new ones. */ 1974 if_foreach_llmaddr(ifp, ti_add_mcast, sc); 1975 1976 /* Re-enable interrupts. */ 1977 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1978 } 1979 1980 /* 1981 * Check to see if the BIOS has configured us for a 64 bit slot when 1982 * we aren't actually in one. If we detect this condition, we can work 1983 * around it on the Tigon 2 by setting a bit in the PCI state register, 1984 * but for the Tigon 1 we must give up and abort the interface attach. 1985 */ 1986 static int 1987 ti_64bitslot_war(struct ti_softc *sc) 1988 { 1989 1990 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1991 CSR_WRITE_4(sc, 0x600, 0); 1992 CSR_WRITE_4(sc, 0x604, 0); 1993 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1994 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1995 if (sc->ti_hwrev == TI_HWREV_TIGON) 1996 return (EINVAL); 1997 else { 1998 TI_SETBIT(sc, TI_PCI_STATE, 1999 TI_PCISTATE_32BIT_BUS); 2000 return (0); 2001 } 2002 } 2003 } 2004 2005 return (0); 2006 } 2007 2008 /* 2009 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2010 * self-test results. 2011 */ 2012 static int 2013 ti_chipinit(struct ti_softc *sc) 2014 { 2015 uint32_t cacheline; 2016 uint32_t pci_writemax = 0; 2017 uint32_t hdrsplit; 2018 2019 /* Initialize link to down state. */ 2020 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2021 2022 /* Set endianness before we access any non-PCI registers. */ 2023 #if 0 && BYTE_ORDER == BIG_ENDIAN 2024 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2025 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2026 #else 2027 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2028 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2029 #endif 2030 2031 /* Check the ROM failed bit to see if self-tests passed. */ 2032 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2033 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2034 return (ENODEV); 2035 } 2036 2037 /* Halt the CPU. */ 2038 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2039 2040 /* Figure out the hardware revision. */ 2041 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2042 case TI_REV_TIGON_I: 2043 sc->ti_hwrev = TI_HWREV_TIGON; 2044 break; 2045 case TI_REV_TIGON_II: 2046 sc->ti_hwrev = TI_HWREV_TIGON_II; 2047 break; 2048 default: 2049 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2050 return (ENODEV); 2051 } 2052 2053 /* Do special setup for Tigon 2. */ 2054 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2055 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2056 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2057 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2058 } 2059 2060 /* 2061 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2062 * can't do header splitting. 2063 */ 2064 #ifdef TI_JUMBO_HDRSPLIT 2065 if (sc->ti_hwrev != TI_HWREV_TIGON) 2066 sc->ti_hdrsplit = 1; 2067 else 2068 device_printf(sc->ti_dev, 2069 "can't do header splitting on a Tigon I board\n"); 2070 #endif /* TI_JUMBO_HDRSPLIT */ 2071 2072 /* Set up the PCI state register. */ 2073 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2074 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2075 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2076 } 2077 2078 /* Clear the read/write max DMA parameters. */ 2079 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2080 TI_PCISTATE_READ_MAXDMA)); 2081 2082 /* Get cache line size. */ 2083 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2084 2085 /* 2086 * If the system has set enabled the PCI memory write 2087 * and invalidate command in the command register, set 2088 * the write max parameter accordingly. This is necessary 2089 * to use MWI with the Tigon 2. 2090 */ 2091 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2092 switch (cacheline) { 2093 case 1: 2094 case 4: 2095 case 8: 2096 case 16: 2097 case 32: 2098 case 64: 2099 break; 2100 default: 2101 /* Disable PCI memory write and invalidate. */ 2102 if (bootverbose) 2103 device_printf(sc->ti_dev, "cache line size %d" 2104 " not supported; disabling PCI MWI\n", 2105 cacheline); 2106 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2107 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2108 break; 2109 } 2110 } 2111 2112 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2113 2114 /* This sets the min dma param all the way up (0xff). */ 2115 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2116 2117 if (sc->ti_hdrsplit) 2118 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2119 else 2120 hdrsplit = 0; 2121 2122 /* Configure DMA variables. */ 2123 #if BYTE_ORDER == BIG_ENDIAN 2124 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2125 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2126 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2127 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2128 #else /* BYTE_ORDER */ 2129 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2130 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2131 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2132 #endif /* BYTE_ORDER */ 2133 2134 /* 2135 * Only allow 1 DMA channel to be active at a time. 2136 * I don't think this is a good idea, but without it 2137 * the firmware racks up lots of nicDmaReadRingFull 2138 * errors. This is not compatible with hardware checksums. 2139 */ 2140 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2141 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2142 2143 /* Recommended settings from Tigon manual. */ 2144 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2145 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2146 2147 if (ti_64bitslot_war(sc)) { 2148 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2149 "but we aren't"); 2150 return (EINVAL); 2151 } 2152 2153 return (0); 2154 } 2155 2156 /* 2157 * Initialize the general information block and firmware, and 2158 * start the CPU(s) running. 2159 */ 2160 static int 2161 ti_gibinit(struct ti_softc *sc) 2162 { 2163 struct ifnet *ifp; 2164 struct ti_rcb *rcb; 2165 int i; 2166 2167 TI_LOCK_ASSERT(sc); 2168 2169 ifp = sc->ti_ifp; 2170 2171 /* Disable interrupts for now. */ 2172 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2173 2174 /* Tell the chip where to find the general information block. */ 2175 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2176 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2177 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2178 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2179 2180 /* Load the firmware into SRAM. */ 2181 ti_loadfw(sc); 2182 2183 /* Set up the contents of the general info and ring control blocks. */ 2184 2185 /* Set up the event ring and producer pointer. */ 2186 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2187 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2188 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2189 rcb->ti_flags = 0; 2190 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2191 sc->ti_rdata.ti_status_paddr + 2192 offsetof(struct ti_status, ti_ev_prodidx_r)); 2193 sc->ti_ev_prodidx.ti_idx = 0; 2194 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2195 sc->ti_ev_saved_considx = 0; 2196 2197 /* Set up the command ring and producer mailbox. */ 2198 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2199 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2200 rcb->ti_flags = 0; 2201 rcb->ti_max_len = 0; 2202 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2203 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2204 } 2205 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2206 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2207 sc->ti_cmd_saved_prodidx = 0; 2208 2209 /* 2210 * Assign the address of the stats refresh buffer. 2211 * We re-use the current stats buffer for this to 2212 * conserve memory. 2213 */ 2214 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2215 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2216 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2217 2218 /* Set up the standard receive ring. */ 2219 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2220 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2221 rcb->ti_max_len = TI_FRAMELEN; 2222 rcb->ti_flags = 0; 2223 if (ifp->if_capenable & IFCAP_RXCSUM) 2224 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2225 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2226 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2227 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2228 2229 /* Set up the jumbo receive ring. */ 2230 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2231 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2232 2233 #ifndef TI_SF_BUF_JUMBO 2234 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2235 rcb->ti_flags = 0; 2236 #else 2237 rcb->ti_max_len = PAGE_SIZE; 2238 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2239 #endif 2240 if (ifp->if_capenable & IFCAP_RXCSUM) 2241 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2242 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2243 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2244 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2245 2246 /* 2247 * Set up the mini ring. Only activated on the 2248 * Tigon 2 but the slot in the config block is 2249 * still there on the Tigon 1. 2250 */ 2251 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2252 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2253 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2254 if (sc->ti_hwrev == TI_HWREV_TIGON) 2255 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2256 else 2257 rcb->ti_flags = 0; 2258 if (ifp->if_capenable & IFCAP_RXCSUM) 2259 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2260 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2261 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2262 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2263 2264 /* 2265 * Set up the receive return ring. 2266 */ 2267 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2268 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2269 rcb->ti_flags = 0; 2270 rcb->ti_max_len = TI_RETURN_RING_CNT; 2271 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2272 sc->ti_rdata.ti_status_paddr + 2273 offsetof(struct ti_status, ti_return_prodidx_r)); 2274 2275 /* 2276 * Set up the tx ring. Note: for the Tigon 2, we have the option 2277 * of putting the transmit ring in the host's address space and 2278 * letting the chip DMA it instead of leaving the ring in the NIC's 2279 * memory and accessing it through the shared memory region. We 2280 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2281 * so we have to revert to the shared memory scheme if we detect 2282 * a Tigon 1 chip. 2283 */ 2284 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2285 if (sc->ti_rdata.ti_tx_ring != NULL) 2286 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2287 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2288 if (sc->ti_hwrev == TI_HWREV_TIGON) 2289 rcb->ti_flags = 0; 2290 else 2291 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2292 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2293 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2294 if (ifp->if_capenable & IFCAP_TXCSUM) 2295 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2296 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2297 rcb->ti_max_len = TI_TX_RING_CNT; 2298 if (sc->ti_hwrev == TI_HWREV_TIGON) 2299 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2300 else 2301 ti_hostaddr64(&rcb->ti_hostaddr, 2302 sc->ti_rdata.ti_tx_ring_paddr); 2303 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2304 sc->ti_rdata.ti_status_paddr + 2305 offsetof(struct ti_status, ti_tx_considx_r)); 2306 2307 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2309 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2310 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2311 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2312 sc->ti_cdata.ti_event_ring_map, 2313 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2314 if (sc->ti_rdata.ti_tx_ring != NULL) 2315 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2316 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2317 2318 /* Set up tunables */ 2319 #if 0 2320 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2321 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2322 (sc->ti_rx_coal_ticks / 10)); 2323 else 2324 #endif 2325 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2326 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2327 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2328 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2329 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2330 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2331 2332 /* Turn interrupts on. */ 2333 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2334 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2335 2336 /* Start CPU. */ 2337 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2338 2339 return (0); 2340 } 2341 2342 /* 2343 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2344 * against our list and return its name if we find a match. 2345 */ 2346 static int 2347 ti_probe(device_t dev) 2348 { 2349 const struct ti_type *t; 2350 2351 t = ti_devs; 2352 2353 while (t->ti_name != NULL) { 2354 if ((pci_get_vendor(dev) == t->ti_vid) && 2355 (pci_get_device(dev) == t->ti_did)) { 2356 device_set_desc(dev, t->ti_name); 2357 return (BUS_PROBE_DEFAULT); 2358 } 2359 t++; 2360 } 2361 2362 return (ENXIO); 2363 } 2364 2365 static int 2366 ti_attach(device_t dev) 2367 { 2368 struct ifnet *ifp; 2369 struct ti_softc *sc; 2370 int error = 0, rid; 2371 u_char eaddr[6]; 2372 2373 sc = device_get_softc(dev); 2374 sc->ti_dev = dev; 2375 2376 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2377 MTX_DEF); 2378 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2379 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2380 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2381 if (ifp == NULL) { 2382 device_printf(dev, "can not if_alloc()\n"); 2383 error = ENOSPC; 2384 goto fail; 2385 } 2386 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2387 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2388 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2389 2390 /* 2391 * Map control/status registers. 2392 */ 2393 pci_enable_busmaster(dev); 2394 2395 rid = PCIR_BAR(0); 2396 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2397 RF_ACTIVE); 2398 2399 if (sc->ti_res == NULL) { 2400 device_printf(dev, "couldn't map memory\n"); 2401 error = ENXIO; 2402 goto fail; 2403 } 2404 2405 sc->ti_btag = rman_get_bustag(sc->ti_res); 2406 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2407 2408 /* Allocate interrupt */ 2409 rid = 0; 2410 2411 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2412 RF_SHAREABLE | RF_ACTIVE); 2413 2414 if (sc->ti_irq == NULL) { 2415 device_printf(dev, "couldn't map interrupt\n"); 2416 error = ENXIO; 2417 goto fail; 2418 } 2419 2420 if (ti_chipinit(sc)) { 2421 device_printf(dev, "chip initialization failed\n"); 2422 error = ENXIO; 2423 goto fail; 2424 } 2425 2426 /* Zero out the NIC's on-board SRAM. */ 2427 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2428 2429 /* Init again -- zeroing memory may have clobbered some registers. */ 2430 if (ti_chipinit(sc)) { 2431 device_printf(dev, "chip initialization failed\n"); 2432 error = ENXIO; 2433 goto fail; 2434 } 2435 2436 /* 2437 * Get station address from the EEPROM. Note: the manual states 2438 * that the MAC address is at offset 0x8c, however the data is 2439 * stored as two longwords (since that's how it's loaded into 2440 * the NIC). This means the MAC address is actually preceded 2441 * by two zero bytes. We need to skip over those. 2442 */ 2443 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2444 device_printf(dev, "failed to read station address\n"); 2445 error = ENXIO; 2446 goto fail; 2447 } 2448 2449 /* Allocate working area for memory dump. */ 2450 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2451 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2452 M_NOWAIT); 2453 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2454 device_printf(dev, "cannot allocate memory buffer\n"); 2455 error = ENOMEM; 2456 goto fail; 2457 } 2458 if ((error = ti_dma_alloc(sc)) != 0) 2459 goto fail; 2460 2461 /* 2462 * We really need a better way to tell a 1000baseTX card 2463 * from a 1000baseSX one, since in theory there could be 2464 * OEMed 1000baseTX cards from lame vendors who aren't 2465 * clever enough to change the PCI ID. For the moment 2466 * though, the AceNIC is the only copper card available. 2467 */ 2468 if (pci_get_vendor(dev) == ALT_VENDORID && 2469 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2470 sc->ti_copper = 1; 2471 /* Ok, it's not the only copper card available. */ 2472 if (pci_get_vendor(dev) == NG_VENDORID && 2473 pci_get_device(dev) == NG_DEVICEID_GA620T) 2474 sc->ti_copper = 1; 2475 2476 /* Set default tunable values. */ 2477 ti_sysctl_node(sc); 2478 2479 /* Set up ifnet structure */ 2480 ifp->if_softc = sc; 2481 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2482 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2483 ifp->if_ioctl = ti_ioctl; 2484 ifp->if_start = ti_start; 2485 ifp->if_init = ti_init; 2486 ifp->if_get_counter = ti_get_counter; 2487 ifp->if_baudrate = IF_Gbps(1UL); 2488 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2489 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2490 IFQ_SET_READY(&ifp->if_snd); 2491 2492 /* Set up ifmedia support. */ 2493 if (sc->ti_copper) { 2494 /* 2495 * Copper cards allow manual 10/100 mode selection, 2496 * but not manual 1000baseTX mode selection. Why? 2497 * Because currently there's no way to specify the 2498 * master/slave setting through the firmware interface, 2499 * so Alteon decided to just bag it and handle it 2500 * via autonegotiation. 2501 */ 2502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2503 ifmedia_add(&sc->ifmedia, 2504 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2506 ifmedia_add(&sc->ifmedia, 2507 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2508 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2509 ifmedia_add(&sc->ifmedia, 2510 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2511 } else { 2512 /* Fiber cards don't support 10/100 modes. */ 2513 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2514 ifmedia_add(&sc->ifmedia, 2515 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2516 } 2517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2518 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2519 2520 /* 2521 * We're assuming here that card initialization is a sequential 2522 * thing. If it isn't, multiple cards probing at the same time 2523 * could stomp on the list of softcs here. 2524 */ 2525 2526 /* Register the device */ 2527 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2528 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2529 sc->dev->si_drv1 = sc; 2530 2531 /* 2532 * Call MI attach routine. 2533 */ 2534 ether_ifattach(ifp, eaddr); 2535 2536 /* VLAN capability setup. */ 2537 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2538 IFCAP_VLAN_HWTAGGING; 2539 ifp->if_capenable = ifp->if_capabilities; 2540 /* Tell the upper layer we support VLAN over-sized frames. */ 2541 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2542 2543 /* Driver supports link state tracking. */ 2544 ifp->if_capabilities |= IFCAP_LINKSTATE; 2545 ifp->if_capenable |= IFCAP_LINKSTATE; 2546 2547 /* Hook interrupt last to avoid having to lock softc */ 2548 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2549 NULL, ti_intr, sc, &sc->ti_intrhand); 2550 2551 if (error) { 2552 device_printf(dev, "couldn't set up irq\n"); 2553 goto fail; 2554 } 2555 2556 fail: 2557 if (error) 2558 ti_detach(dev); 2559 2560 return (error); 2561 } 2562 2563 /* 2564 * Shutdown hardware and free up resources. This can be called any 2565 * time after the mutex has been initialized. It is called in both 2566 * the error case in attach and the normal detach case so it needs 2567 * to be careful about only freeing resources that have actually been 2568 * allocated. 2569 */ 2570 static int 2571 ti_detach(device_t dev) 2572 { 2573 struct ti_softc *sc; 2574 struct ifnet *ifp; 2575 2576 sc = device_get_softc(dev); 2577 if (sc->dev) 2578 destroy_dev(sc->dev); 2579 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2580 ifp = sc->ti_ifp; 2581 if (device_is_attached(dev)) { 2582 ether_ifdetach(ifp); 2583 TI_LOCK(sc); 2584 ti_stop(sc); 2585 TI_UNLOCK(sc); 2586 } 2587 2588 /* These should only be active if attach succeeded */ 2589 callout_drain(&sc->ti_watchdog); 2590 bus_generic_detach(dev); 2591 ti_dma_free(sc); 2592 ifmedia_removeall(&sc->ifmedia); 2593 2594 if (sc->ti_intrhand) 2595 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2596 if (sc->ti_irq) 2597 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2598 if (sc->ti_res) { 2599 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2600 sc->ti_res); 2601 } 2602 if (ifp) 2603 if_free(ifp); 2604 if (sc->ti_membuf) 2605 free(sc->ti_membuf, M_DEVBUF); 2606 if (sc->ti_membuf2) 2607 free(sc->ti_membuf2, M_DEVBUF); 2608 2609 mtx_destroy(&sc->ti_mtx); 2610 2611 return (0); 2612 } 2613 2614 #ifdef TI_JUMBO_HDRSPLIT 2615 /* 2616 * If hdr_len is 0, that means that header splitting wasn't done on 2617 * this packet for some reason. The two most likely reasons are that 2618 * the protocol isn't a supported protocol for splitting, or this 2619 * packet had a fragment offset that wasn't 0. 2620 * 2621 * The header length, if it is non-zero, will always be the length of 2622 * the headers on the packet, but that length could be longer than the 2623 * first mbuf. So we take the minimum of the two as the actual 2624 * length. 2625 */ 2626 static __inline void 2627 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2628 { 2629 int i = 0; 2630 int lengths[4] = {0, 0, 0, 0}; 2631 struct mbuf *m, *mp; 2632 2633 if (hdr_len != 0) 2634 top->m_len = min(hdr_len, top->m_len); 2635 pkt_len -= top->m_len; 2636 lengths[i++] = top->m_len; 2637 2638 mp = top; 2639 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2640 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2641 pkt_len -= m->m_len; 2642 lengths[i++] = m->m_len; 2643 mp = m; 2644 } 2645 2646 #if 0 2647 if (hdr_len != 0) 2648 printf("got split packet: "); 2649 else 2650 printf("got non-split packet: "); 2651 2652 printf("%d,%d,%d,%d = %d\n", lengths[0], 2653 lengths[1], lengths[2], lengths[3], 2654 lengths[0] + lengths[1] + lengths[2] + 2655 lengths[3]); 2656 #endif 2657 2658 if (pkt_len) 2659 panic("header splitting didn't"); 2660 2661 if (m) { 2662 m_freem(m); 2663 mp->m_next = NULL; 2664 } 2665 if (mp->m_next != NULL) 2666 panic("ti_hdr_split: last mbuf in chain should be null"); 2667 } 2668 #endif /* TI_JUMBO_HDRSPLIT */ 2669 2670 static void 2671 ti_discard_std(struct ti_softc *sc, int i) 2672 { 2673 2674 struct ti_rx_desc *r; 2675 2676 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2677 r->ti_len = MCLBYTES - ETHER_ALIGN; 2678 r->ti_type = TI_BDTYPE_RECV_BD; 2679 r->ti_flags = 0; 2680 r->ti_vlan_tag = 0; 2681 r->ti_tcp_udp_cksum = 0; 2682 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2683 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2684 r->ti_idx = i; 2685 } 2686 2687 static void 2688 ti_discard_mini(struct ti_softc *sc, int i) 2689 { 2690 2691 struct ti_rx_desc *r; 2692 2693 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2694 r->ti_len = MHLEN - ETHER_ALIGN; 2695 r->ti_type = TI_BDTYPE_RECV_BD; 2696 r->ti_flags = TI_BDFLAG_MINI_RING; 2697 r->ti_vlan_tag = 0; 2698 r->ti_tcp_udp_cksum = 0; 2699 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2700 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2701 r->ti_idx = i; 2702 } 2703 2704 #ifndef TI_SF_BUF_JUMBO 2705 static void 2706 ti_discard_jumbo(struct ti_softc *sc, int i) 2707 { 2708 2709 struct ti_rx_desc *r; 2710 2711 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2712 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2713 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2714 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2715 r->ti_vlan_tag = 0; 2716 r->ti_tcp_udp_cksum = 0; 2717 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2718 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2719 r->ti_idx = i; 2720 } 2721 #endif 2722 2723 /* 2724 * Frame reception handling. This is called if there's a frame 2725 * on the receive return list. 2726 * 2727 * Note: we have to be able to handle three possibilities here: 2728 * 1) the frame is from the mini receive ring (can only happen) 2729 * on Tigon 2 boards) 2730 * 2) the frame is from the jumbo receive ring 2731 * 3) the frame is from the standard receive ring 2732 */ 2733 2734 static void 2735 ti_rxeof(struct ti_softc *sc) 2736 { 2737 struct ifnet *ifp; 2738 #ifdef TI_SF_BUF_JUMBO 2739 bus_dmamap_t map; 2740 #endif 2741 struct ti_cmd_desc cmd; 2742 int jumbocnt, minicnt, stdcnt, ti_len; 2743 2744 TI_LOCK_ASSERT(sc); 2745 2746 ifp = sc->ti_ifp; 2747 2748 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2749 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2750 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2751 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2752 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2753 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2754 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2755 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2756 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2757 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2758 2759 jumbocnt = minicnt = stdcnt = 0; 2760 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2761 struct ti_rx_desc *cur_rx; 2762 uint32_t rxidx; 2763 struct mbuf *m = NULL; 2764 uint16_t vlan_tag = 0; 2765 int have_tag = 0; 2766 2767 cur_rx = 2768 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2769 rxidx = cur_rx->ti_idx; 2770 ti_len = cur_rx->ti_len; 2771 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2772 2773 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2774 have_tag = 1; 2775 vlan_tag = cur_rx->ti_vlan_tag; 2776 } 2777 2778 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2779 jumbocnt++; 2780 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2781 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2782 #ifndef TI_SF_BUF_JUMBO 2783 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2784 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2785 ti_discard_jumbo(sc, rxidx); 2786 continue; 2787 } 2788 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2789 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2790 ti_discard_jumbo(sc, rxidx); 2791 continue; 2792 } 2793 m->m_len = ti_len; 2794 #else /* !TI_SF_BUF_JUMBO */ 2795 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2796 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2797 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2798 BUS_DMASYNC_POSTREAD); 2799 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2800 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2801 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2802 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2803 continue; 2804 } 2805 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2806 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2807 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2808 continue; 2809 } 2810 #ifdef TI_JUMBO_HDRSPLIT 2811 if (sc->ti_hdrsplit) 2812 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2813 ti_len, rxidx); 2814 else 2815 #endif /* TI_JUMBO_HDRSPLIT */ 2816 m_adj(m, ti_len - m->m_pkthdr.len); 2817 #endif /* TI_SF_BUF_JUMBO */ 2818 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2819 minicnt++; 2820 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2821 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2822 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2823 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2824 ti_discard_mini(sc, rxidx); 2825 continue; 2826 } 2827 if (ti_newbuf_mini(sc, rxidx) != 0) { 2828 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2829 ti_discard_mini(sc, rxidx); 2830 continue; 2831 } 2832 m->m_len = ti_len; 2833 } else { 2834 stdcnt++; 2835 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2836 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2837 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2838 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2839 ti_discard_std(sc, rxidx); 2840 continue; 2841 } 2842 if (ti_newbuf_std(sc, rxidx) != 0) { 2843 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2844 ti_discard_std(sc, rxidx); 2845 continue; 2846 } 2847 m->m_len = ti_len; 2848 } 2849 2850 m->m_pkthdr.len = ti_len; 2851 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2852 m->m_pkthdr.rcvif = ifp; 2853 2854 if (ifp->if_capenable & IFCAP_RXCSUM) { 2855 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2856 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2857 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2858 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2859 } 2860 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2861 m->m_pkthdr.csum_data = 2862 cur_rx->ti_tcp_udp_cksum; 2863 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2864 } 2865 } 2866 2867 /* 2868 * If we received a packet with a vlan tag, 2869 * tag it before passing the packet upward. 2870 */ 2871 if (have_tag) { 2872 m->m_pkthdr.ether_vtag = vlan_tag; 2873 m->m_flags |= M_VLANTAG; 2874 } 2875 TI_UNLOCK(sc); 2876 (*ifp->if_input)(ifp, m); 2877 TI_LOCK(sc); 2878 } 2879 2880 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2881 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2882 /* Only necessary on the Tigon 1. */ 2883 if (sc->ti_hwrev == TI_HWREV_TIGON) 2884 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2885 sc->ti_rx_saved_considx); 2886 2887 if (stdcnt > 0) { 2888 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2889 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2890 TI_UPDATE_STDPROD(sc, sc->ti_std); 2891 } 2892 if (minicnt > 0) { 2893 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2894 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2895 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2896 } 2897 if (jumbocnt > 0) { 2898 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2899 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2900 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2901 } 2902 } 2903 2904 static void 2905 ti_txeof(struct ti_softc *sc) 2906 { 2907 struct ti_txdesc *txd; 2908 struct ti_tx_desc txdesc; 2909 struct ti_tx_desc *cur_tx = NULL; 2910 struct ifnet *ifp; 2911 int idx; 2912 2913 ifp = sc->ti_ifp; 2914 2915 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2916 if (txd == NULL) 2917 return; 2918 2919 if (sc->ti_rdata.ti_tx_ring != NULL) 2920 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2921 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2922 /* 2923 * Go through our tx ring and free mbufs for those 2924 * frames that have been sent. 2925 */ 2926 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2927 TI_INC(idx, TI_TX_RING_CNT)) { 2928 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2929 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2930 sizeof(txdesc), &txdesc); 2931 cur_tx = &txdesc; 2932 } else 2933 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2934 sc->ti_txcnt--; 2935 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2936 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2937 continue; 2938 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2939 BUS_DMASYNC_POSTWRITE); 2940 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2941 2942 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2943 m_freem(txd->tx_m); 2944 txd->tx_m = NULL; 2945 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2946 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2947 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2948 } 2949 sc->ti_tx_saved_considx = idx; 2950 if (sc->ti_txcnt == 0) 2951 sc->ti_timer = 0; 2952 } 2953 2954 static void 2955 ti_intr(void *xsc) 2956 { 2957 struct ti_softc *sc; 2958 struct ifnet *ifp; 2959 2960 sc = xsc; 2961 TI_LOCK(sc); 2962 ifp = sc->ti_ifp; 2963 2964 /* Make sure this is really our interrupt. */ 2965 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2966 TI_UNLOCK(sc); 2967 return; 2968 } 2969 2970 /* Ack interrupt and stop others from occurring. */ 2971 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2972 2973 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2974 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2975 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2976 /* Check RX return ring producer/consumer */ 2977 ti_rxeof(sc); 2978 2979 /* Check TX ring producer/consumer */ 2980 ti_txeof(sc); 2981 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2982 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2983 } 2984 2985 ti_handle_events(sc); 2986 2987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2988 /* Re-enable interrupts. */ 2989 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2990 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2991 ti_start_locked(ifp); 2992 } 2993 2994 TI_UNLOCK(sc); 2995 } 2996 2997 static uint64_t 2998 ti_get_counter(struct ifnet *ifp, ift_counter cnt) 2999 { 3000 3001 switch (cnt) { 3002 case IFCOUNTER_COLLISIONS: 3003 { 3004 struct ti_softc *sc; 3005 struct ti_stats *s; 3006 uint64_t rv; 3007 3008 sc = if_getsoftc(ifp); 3009 s = &sc->ti_rdata.ti_info->ti_stats; 3010 3011 TI_LOCK(sc); 3012 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3013 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3014 rv = s->dot3StatsSingleCollisionFrames + 3015 s->dot3StatsMultipleCollisionFrames + 3016 s->dot3StatsExcessiveCollisions + 3017 s->dot3StatsLateCollisions; 3018 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3019 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3020 TI_UNLOCK(sc); 3021 return (rv); 3022 } 3023 default: 3024 return (if_get_counter_default(ifp, cnt)); 3025 } 3026 } 3027 3028 /* 3029 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3030 * pointers to descriptors. 3031 */ 3032 static int 3033 ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3034 { 3035 struct ti_txdesc *txd; 3036 struct ti_tx_desc *f; 3037 struct ti_tx_desc txdesc; 3038 struct mbuf *m; 3039 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3040 uint16_t csum_flags; 3041 int error, frag, i, nseg; 3042 3043 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3044 return (ENOBUFS); 3045 3046 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3047 *m_head, txsegs, &nseg, 0); 3048 if (error == EFBIG) { 3049 m = m_defrag(*m_head, M_NOWAIT); 3050 if (m == NULL) { 3051 m_freem(*m_head); 3052 *m_head = NULL; 3053 return (ENOMEM); 3054 } 3055 *m_head = m; 3056 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3057 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3058 if (error) { 3059 m_freem(*m_head); 3060 *m_head = NULL; 3061 return (error); 3062 } 3063 } else if (error != 0) 3064 return (error); 3065 if (nseg == 0) { 3066 m_freem(*m_head); 3067 *m_head = NULL; 3068 return (EIO); 3069 } 3070 3071 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3072 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3073 return (ENOBUFS); 3074 } 3075 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3076 BUS_DMASYNC_PREWRITE); 3077 3078 m = *m_head; 3079 csum_flags = 0; 3080 if (m->m_pkthdr.csum_flags & CSUM_IP) 3081 csum_flags |= TI_BDFLAG_IP_CKSUM; 3082 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3083 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3084 3085 frag = sc->ti_tx_saved_prodidx; 3086 for (i = 0; i < nseg; i++) { 3087 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3088 bzero(&txdesc, sizeof(txdesc)); 3089 f = &txdesc; 3090 } else 3091 f = &sc->ti_rdata.ti_tx_ring[frag]; 3092 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3093 f->ti_len = txsegs[i].ds_len; 3094 f->ti_flags = csum_flags; 3095 if (m->m_flags & M_VLANTAG) { 3096 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3097 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3098 } else { 3099 f->ti_vlan_tag = 0; 3100 } 3101 3102 if (sc->ti_hwrev == TI_HWREV_TIGON) 3103 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3104 sizeof(txdesc), sizeof(txdesc), &txdesc); 3105 TI_INC(frag, TI_TX_RING_CNT); 3106 } 3107 3108 sc->ti_tx_saved_prodidx = frag; 3109 /* set TI_BDFLAG_END on the last descriptor */ 3110 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3111 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3112 txdesc.ti_flags |= TI_BDFLAG_END; 3113 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3114 sizeof(txdesc), &txdesc); 3115 } else 3116 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3117 3118 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3119 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3120 txd->tx_m = m; 3121 sc->ti_txcnt += nseg; 3122 3123 return (0); 3124 } 3125 3126 static void 3127 ti_start(struct ifnet *ifp) 3128 { 3129 struct ti_softc *sc; 3130 3131 sc = ifp->if_softc; 3132 TI_LOCK(sc); 3133 ti_start_locked(ifp); 3134 TI_UNLOCK(sc); 3135 } 3136 3137 /* 3138 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3139 * to the mbuf data regions directly in the transmit descriptors. 3140 */ 3141 static void 3142 ti_start_locked(struct ifnet *ifp) 3143 { 3144 struct ti_softc *sc; 3145 struct mbuf *m_head = NULL; 3146 int enq = 0; 3147 3148 sc = ifp->if_softc; 3149 3150 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3151 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3152 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3153 if (m_head == NULL) 3154 break; 3155 3156 /* 3157 * Pack the data into the transmit ring. If we 3158 * don't have room, set the OACTIVE flag and wait 3159 * for the NIC to drain the ring. 3160 */ 3161 if (ti_encap(sc, &m_head)) { 3162 if (m_head == NULL) 3163 break; 3164 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3165 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3166 break; 3167 } 3168 3169 enq++; 3170 /* 3171 * If there's a BPF listener, bounce a copy of this frame 3172 * to him. 3173 */ 3174 ETHER_BPF_MTAP(ifp, m_head); 3175 } 3176 3177 if (enq > 0) { 3178 if (sc->ti_rdata.ti_tx_ring != NULL) 3179 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3180 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3181 /* Transmit */ 3182 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3183 3184 /* 3185 * Set a timeout in case the chip goes out to lunch. 3186 */ 3187 sc->ti_timer = 5; 3188 } 3189 } 3190 3191 static void 3192 ti_init(void *xsc) 3193 { 3194 struct ti_softc *sc; 3195 3196 sc = xsc; 3197 TI_LOCK(sc); 3198 ti_init_locked(sc); 3199 TI_UNLOCK(sc); 3200 } 3201 3202 static void 3203 ti_init_locked(void *xsc) 3204 { 3205 struct ti_softc *sc = xsc; 3206 3207 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3208 return; 3209 3210 /* Cancel pending I/O and flush buffers. */ 3211 ti_stop(sc); 3212 3213 /* Init the gen info block, ring control blocks and firmware. */ 3214 if (ti_gibinit(sc)) { 3215 device_printf(sc->ti_dev, "initialization failure\n"); 3216 return; 3217 } 3218 } 3219 3220 static void ti_init2(struct ti_softc *sc) 3221 { 3222 struct ti_cmd_desc cmd; 3223 struct ifnet *ifp; 3224 uint8_t *ea; 3225 struct ifmedia *ifm; 3226 int tmp; 3227 3228 TI_LOCK_ASSERT(sc); 3229 3230 ifp = sc->ti_ifp; 3231 3232 /* Specify MTU and interface index. */ 3233 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3234 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3235 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3236 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3237 3238 /* Load our MAC address. */ 3239 ea = IF_LLADDR(sc->ti_ifp); 3240 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3241 CSR_WRITE_4(sc, TI_GCR_PAR1, 3242 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3243 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3244 3245 /* Enable or disable promiscuous mode as needed. */ 3246 if (ifp->if_flags & IFF_PROMISC) { 3247 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3248 } else { 3249 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3250 } 3251 3252 /* Program multicast filter. */ 3253 ti_setmulti(sc); 3254 3255 /* 3256 * If this is a Tigon 1, we should tell the 3257 * firmware to use software packet filtering. 3258 */ 3259 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3260 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3261 } 3262 3263 /* Init RX ring. */ 3264 if (ti_init_rx_ring_std(sc) != 0) { 3265 /* XXX */ 3266 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3267 return; 3268 } 3269 3270 /* Init jumbo RX ring. */ 3271 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3272 if (ti_init_rx_ring_jumbo(sc) != 0) { 3273 /* XXX */ 3274 device_printf(sc->ti_dev, 3275 "no memory for jumbo Rx buffers.\n"); 3276 return; 3277 } 3278 } 3279 3280 /* 3281 * If this is a Tigon 2, we can also configure the 3282 * mini ring. 3283 */ 3284 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3285 if (ti_init_rx_ring_mini(sc) != 0) { 3286 /* XXX */ 3287 device_printf(sc->ti_dev, 3288 "no memory for mini Rx buffers.\n"); 3289 return; 3290 } 3291 } 3292 3293 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3294 sc->ti_rx_saved_considx = 0; 3295 3296 /* Init TX ring. */ 3297 ti_init_tx_ring(sc); 3298 3299 /* Tell firmware we're alive. */ 3300 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3301 3302 /* Enable host interrupts. */ 3303 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3304 3305 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3307 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3308 3309 /* 3310 * Make sure to set media properly. We have to do this 3311 * here since we have to issue commands in order to set 3312 * the link negotiation and we can't issue commands until 3313 * the firmware is running. 3314 */ 3315 ifm = &sc->ifmedia; 3316 tmp = ifm->ifm_media; 3317 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3318 ti_ifmedia_upd_locked(sc); 3319 ifm->ifm_media = tmp; 3320 } 3321 3322 /* 3323 * Set media options. 3324 */ 3325 static int 3326 ti_ifmedia_upd(struct ifnet *ifp) 3327 { 3328 struct ti_softc *sc; 3329 int error; 3330 3331 sc = ifp->if_softc; 3332 TI_LOCK(sc); 3333 error = ti_ifmedia_upd_locked(sc); 3334 TI_UNLOCK(sc); 3335 3336 return (error); 3337 } 3338 3339 static int 3340 ti_ifmedia_upd_locked(struct ti_softc *sc) 3341 { 3342 struct ifmedia *ifm; 3343 struct ti_cmd_desc cmd; 3344 uint32_t flowctl; 3345 3346 ifm = &sc->ifmedia; 3347 3348 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3349 return (EINVAL); 3350 3351 flowctl = 0; 3352 3353 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3354 case IFM_AUTO: 3355 /* 3356 * Transmit flow control doesn't work on the Tigon 1. 3357 */ 3358 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3359 3360 /* 3361 * Transmit flow control can also cause problems on the 3362 * Tigon 2, apparently with both the copper and fiber 3363 * boards. The symptom is that the interface will just 3364 * hang. This was reproduced with Alteon 180 switches. 3365 */ 3366 #if 0 3367 if (sc->ti_hwrev != TI_HWREV_TIGON) 3368 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3369 #endif 3370 3371 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3372 TI_GLNK_FULL_DUPLEX| flowctl | 3373 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3374 3375 flowctl = TI_LNK_RX_FLOWCTL_Y; 3376 #if 0 3377 if (sc->ti_hwrev != TI_HWREV_TIGON) 3378 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3379 #endif 3380 3381 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3382 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3383 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3384 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3385 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3386 break; 3387 case IFM_1000_SX: 3388 case IFM_1000_T: 3389 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3390 #if 0 3391 if (sc->ti_hwrev != TI_HWREV_TIGON) 3392 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3393 #endif 3394 3395 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3396 flowctl |TI_GLNK_ENB); 3397 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3398 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3399 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3400 } 3401 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3402 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3403 break; 3404 case IFM_100_FX: 3405 case IFM_10_FL: 3406 case IFM_100_TX: 3407 case IFM_10_T: 3408 flowctl = TI_LNK_RX_FLOWCTL_Y; 3409 #if 0 3410 if (sc->ti_hwrev != TI_HWREV_TIGON) 3411 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3412 #endif 3413 3414 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3415 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3416 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3417 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3418 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3419 } else { 3420 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3421 } 3422 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3423 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3424 } else { 3425 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3426 } 3427 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3428 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3429 break; 3430 } 3431 3432 return (0); 3433 } 3434 3435 /* 3436 * Report current media status. 3437 */ 3438 static void 3439 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3440 { 3441 struct ti_softc *sc; 3442 uint32_t media = 0; 3443 3444 sc = ifp->if_softc; 3445 3446 TI_LOCK(sc); 3447 3448 ifmr->ifm_status = IFM_AVALID; 3449 ifmr->ifm_active = IFM_ETHER; 3450 3451 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3452 TI_UNLOCK(sc); 3453 return; 3454 } 3455 3456 ifmr->ifm_status |= IFM_ACTIVE; 3457 3458 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3459 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3460 if (sc->ti_copper) 3461 ifmr->ifm_active |= IFM_1000_T; 3462 else 3463 ifmr->ifm_active |= IFM_1000_SX; 3464 if (media & TI_GLNK_FULL_DUPLEX) 3465 ifmr->ifm_active |= IFM_FDX; 3466 else 3467 ifmr->ifm_active |= IFM_HDX; 3468 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3469 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3470 if (sc->ti_copper) { 3471 if (media & TI_LNK_100MB) 3472 ifmr->ifm_active |= IFM_100_TX; 3473 if (media & TI_LNK_10MB) 3474 ifmr->ifm_active |= IFM_10_T; 3475 } else { 3476 if (media & TI_LNK_100MB) 3477 ifmr->ifm_active |= IFM_100_FX; 3478 if (media & TI_LNK_10MB) 3479 ifmr->ifm_active |= IFM_10_FL; 3480 } 3481 if (media & TI_LNK_FULL_DUPLEX) 3482 ifmr->ifm_active |= IFM_FDX; 3483 if (media & TI_LNK_HALF_DUPLEX) 3484 ifmr->ifm_active |= IFM_HDX; 3485 } 3486 TI_UNLOCK(sc); 3487 } 3488 3489 static int 3490 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3491 { 3492 struct ti_softc *sc = ifp->if_softc; 3493 struct ifreq *ifr = (struct ifreq *) data; 3494 struct ti_cmd_desc cmd; 3495 int mask, error = 0; 3496 3497 switch (command) { 3498 case SIOCSIFMTU: 3499 TI_LOCK(sc); 3500 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3501 error = EINVAL; 3502 else { 3503 ifp->if_mtu = ifr->ifr_mtu; 3504 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3505 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3506 ti_init_locked(sc); 3507 } 3508 } 3509 TI_UNLOCK(sc); 3510 break; 3511 case SIOCSIFFLAGS: 3512 TI_LOCK(sc); 3513 if (ifp->if_flags & IFF_UP) { 3514 /* 3515 * If only the state of the PROMISC flag changed, 3516 * then just use the 'set promisc mode' command 3517 * instead of reinitializing the entire NIC. Doing 3518 * a full re-init means reloading the firmware and 3519 * waiting for it to start up, which may take a 3520 * second or two. 3521 */ 3522 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3523 ifp->if_flags & IFF_PROMISC && 3524 !(sc->ti_if_flags & IFF_PROMISC)) { 3525 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3526 TI_CMD_CODE_PROMISC_ENB, 0); 3527 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3528 !(ifp->if_flags & IFF_PROMISC) && 3529 sc->ti_if_flags & IFF_PROMISC) { 3530 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3531 TI_CMD_CODE_PROMISC_DIS, 0); 3532 } else 3533 ti_init_locked(sc); 3534 } else { 3535 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3536 ti_stop(sc); 3537 } 3538 } 3539 sc->ti_if_flags = ifp->if_flags; 3540 TI_UNLOCK(sc); 3541 break; 3542 case SIOCADDMULTI: 3543 case SIOCDELMULTI: 3544 TI_LOCK(sc); 3545 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3546 ti_setmulti(sc); 3547 TI_UNLOCK(sc); 3548 break; 3549 case SIOCSIFMEDIA: 3550 case SIOCGIFMEDIA: 3551 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3552 break; 3553 case SIOCSIFCAP: 3554 TI_LOCK(sc); 3555 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3556 if ((mask & IFCAP_TXCSUM) != 0 && 3557 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3558 ifp->if_capenable ^= IFCAP_TXCSUM; 3559 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3560 ifp->if_hwassist |= TI_CSUM_FEATURES; 3561 else 3562 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3563 } 3564 if ((mask & IFCAP_RXCSUM) != 0 && 3565 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3566 ifp->if_capenable ^= IFCAP_RXCSUM; 3567 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3568 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3569 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3570 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3571 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3572 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3573 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3574 IFCAP_VLAN_HWTAGGING)) != 0) { 3575 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3576 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3577 ti_init_locked(sc); 3578 } 3579 } 3580 TI_UNLOCK(sc); 3581 VLAN_CAPABILITIES(ifp); 3582 break; 3583 default: 3584 error = ether_ioctl(ifp, command, data); 3585 break; 3586 } 3587 3588 return (error); 3589 } 3590 3591 static int 3592 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3593 { 3594 struct ti_softc *sc; 3595 3596 sc = dev->si_drv1; 3597 if (sc == NULL) 3598 return (ENODEV); 3599 3600 TI_LOCK(sc); 3601 sc->ti_flags |= TI_FLAG_DEBUGING; 3602 TI_UNLOCK(sc); 3603 3604 return (0); 3605 } 3606 3607 static int 3608 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3609 { 3610 struct ti_softc *sc; 3611 3612 sc = dev->si_drv1; 3613 if (sc == NULL) 3614 return (ENODEV); 3615 3616 TI_LOCK(sc); 3617 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3618 TI_UNLOCK(sc); 3619 3620 return (0); 3621 } 3622 3623 /* 3624 * This ioctl routine goes along with the Tigon character device. 3625 */ 3626 static int 3627 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3628 struct thread *td) 3629 { 3630 struct ti_softc *sc; 3631 int error; 3632 3633 sc = dev->si_drv1; 3634 if (sc == NULL) 3635 return (ENODEV); 3636 3637 error = 0; 3638 3639 switch (cmd) { 3640 case TIIOCGETSTATS: 3641 { 3642 struct ti_stats *outstats; 3643 3644 outstats = (struct ti_stats *)addr; 3645 3646 TI_LOCK(sc); 3647 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3648 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3649 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3650 sizeof(struct ti_stats)); 3651 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3652 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3653 TI_UNLOCK(sc); 3654 break; 3655 } 3656 case TIIOCGETPARAMS: 3657 { 3658 struct ti_params *params; 3659 3660 params = (struct ti_params *)addr; 3661 3662 TI_LOCK(sc); 3663 params->ti_stat_ticks = sc->ti_stat_ticks; 3664 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3665 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3666 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3667 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3668 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3669 params->param_mask = TI_PARAM_ALL; 3670 TI_UNLOCK(sc); 3671 break; 3672 } 3673 case TIIOCSETPARAMS: 3674 { 3675 struct ti_params *params; 3676 3677 params = (struct ti_params *)addr; 3678 3679 TI_LOCK(sc); 3680 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3681 sc->ti_stat_ticks = params->ti_stat_ticks; 3682 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3683 } 3684 3685 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3686 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3687 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3688 sc->ti_rx_coal_ticks); 3689 } 3690 3691 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3692 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3693 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3694 sc->ti_tx_coal_ticks); 3695 } 3696 3697 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3698 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3699 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3700 sc->ti_rx_max_coal_bds); 3701 } 3702 3703 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3704 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3705 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3706 sc->ti_tx_max_coal_bds); 3707 } 3708 3709 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3710 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3711 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3712 sc->ti_tx_buf_ratio); 3713 } 3714 TI_UNLOCK(sc); 3715 break; 3716 } 3717 case TIIOCSETTRACE: { 3718 ti_trace_type trace_type; 3719 3720 trace_type = *(ti_trace_type *)addr; 3721 3722 /* 3723 * Set tracing to whatever the user asked for. Setting 3724 * this register to 0 should have the effect of disabling 3725 * tracing. 3726 */ 3727 TI_LOCK(sc); 3728 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3729 TI_UNLOCK(sc); 3730 break; 3731 } 3732 case TIIOCGETTRACE: { 3733 struct ti_trace_buf *trace_buf; 3734 uint32_t trace_start, cur_trace_ptr, trace_len; 3735 3736 trace_buf = (struct ti_trace_buf *)addr; 3737 3738 TI_LOCK(sc); 3739 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3740 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3741 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3742 #if 0 3743 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3744 "trace_len = %d\n", trace_start, 3745 cur_trace_ptr, trace_len); 3746 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3747 trace_buf->buf_len); 3748 #endif 3749 error = ti_copy_mem(sc, trace_start, min(trace_len, 3750 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3751 if (error == 0) { 3752 trace_buf->fill_len = min(trace_len, 3753 trace_buf->buf_len); 3754 if (cur_trace_ptr < trace_start) 3755 trace_buf->cur_trace_ptr = 3756 trace_start - cur_trace_ptr; 3757 else 3758 trace_buf->cur_trace_ptr = 3759 cur_trace_ptr - trace_start; 3760 } else 3761 trace_buf->fill_len = 0; 3762 TI_UNLOCK(sc); 3763 break; 3764 } 3765 3766 /* 3767 * For debugging, five ioctls are needed: 3768 * ALT_ATTACH 3769 * ALT_READ_TG_REG 3770 * ALT_WRITE_TG_REG 3771 * ALT_READ_TG_MEM 3772 * ALT_WRITE_TG_MEM 3773 */ 3774 case ALT_ATTACH: 3775 /* 3776 * From what I can tell, Alteon's Solaris Tigon driver 3777 * only has one character device, so you have to attach 3778 * to the Tigon board you're interested in. This seems 3779 * like a not-so-good way to do things, since unless you 3780 * subsequently specify the unit number of the device 3781 * you're interested in every ioctl, you'll only be 3782 * able to debug one board at a time. 3783 */ 3784 break; 3785 case ALT_READ_TG_MEM: 3786 case ALT_WRITE_TG_MEM: 3787 { 3788 struct tg_mem *mem_param; 3789 uint32_t sram_end, scratch_end; 3790 3791 mem_param = (struct tg_mem *)addr; 3792 3793 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3794 sram_end = TI_END_SRAM_I; 3795 scratch_end = TI_END_SCRATCH_I; 3796 } else { 3797 sram_end = TI_END_SRAM_II; 3798 scratch_end = TI_END_SCRATCH_II; 3799 } 3800 3801 /* 3802 * For now, we'll only handle accessing regular SRAM, 3803 * nothing else. 3804 */ 3805 TI_LOCK(sc); 3806 if (mem_param->tgAddr >= TI_BEG_SRAM && 3807 mem_param->tgAddr + mem_param->len <= sram_end) { 3808 /* 3809 * In this instance, we always copy to/from user 3810 * space, so the user space argument is set to 1. 3811 */ 3812 error = ti_copy_mem(sc, mem_param->tgAddr, 3813 mem_param->len, mem_param->userAddr, 1, 3814 cmd == ALT_READ_TG_MEM ? 1 : 0); 3815 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3816 mem_param->tgAddr <= scratch_end) { 3817 error = ti_copy_scratch(sc, mem_param->tgAddr, 3818 mem_param->len, mem_param->userAddr, 1, 3819 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3820 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3821 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3822 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3823 if_printf(sc->ti_ifp, 3824 "invalid memory range for Tigon I\n"); 3825 error = EINVAL; 3826 break; 3827 } 3828 error = ti_copy_scratch(sc, mem_param->tgAddr - 3829 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3830 mem_param->userAddr, 1, 3831 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3832 } else { 3833 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3834 "out of supported range\n", 3835 mem_param->tgAddr, mem_param->len); 3836 error = EINVAL; 3837 } 3838 TI_UNLOCK(sc); 3839 break; 3840 } 3841 case ALT_READ_TG_REG: 3842 case ALT_WRITE_TG_REG: 3843 { 3844 struct tg_reg *regs; 3845 uint32_t tmpval; 3846 3847 regs = (struct tg_reg *)addr; 3848 3849 /* 3850 * Make sure the address in question isn't out of range. 3851 */ 3852 if (regs->addr > TI_REG_MAX) { 3853 error = EINVAL; 3854 break; 3855 } 3856 TI_LOCK(sc); 3857 if (cmd == ALT_READ_TG_REG) { 3858 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3859 regs->addr, &tmpval, 1); 3860 regs->data = ntohl(tmpval); 3861 #if 0 3862 if ((regs->addr == TI_CPU_STATE) 3863 || (regs->addr == TI_CPU_CTL_B)) { 3864 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3865 regs->addr, tmpval); 3866 } 3867 #endif 3868 } else { 3869 tmpval = htonl(regs->data); 3870 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3871 regs->addr, &tmpval, 1); 3872 } 3873 TI_UNLOCK(sc); 3874 break; 3875 } 3876 default: 3877 error = ENOTTY; 3878 break; 3879 } 3880 return (error); 3881 } 3882 3883 static void 3884 ti_watchdog(void *arg) 3885 { 3886 struct ti_softc *sc; 3887 struct ifnet *ifp; 3888 3889 sc = arg; 3890 TI_LOCK_ASSERT(sc); 3891 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3892 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3893 return; 3894 3895 /* 3896 * When we're debugging, the chip is often stopped for long periods 3897 * of time, and that would normally cause the watchdog timer to fire. 3898 * Since that impedes debugging, we don't want to do that. 3899 */ 3900 if (sc->ti_flags & TI_FLAG_DEBUGING) 3901 return; 3902 3903 ifp = sc->ti_ifp; 3904 if_printf(ifp, "watchdog timeout -- resetting\n"); 3905 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3906 ti_init_locked(sc); 3907 3908 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3909 } 3910 3911 /* 3912 * Stop the adapter and free any mbufs allocated to the 3913 * RX and TX lists. 3914 */ 3915 static void 3916 ti_stop(struct ti_softc *sc) 3917 { 3918 struct ifnet *ifp; 3919 struct ti_cmd_desc cmd; 3920 3921 TI_LOCK_ASSERT(sc); 3922 3923 ifp = sc->ti_ifp; 3924 3925 /* Disable host interrupts. */ 3926 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3927 /* 3928 * Tell firmware we're shutting down. 3929 */ 3930 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3931 3932 /* Halt and reinitialize. */ 3933 if (ti_chipinit(sc) == 0) { 3934 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3935 /* XXX ignore init errors. */ 3936 ti_chipinit(sc); 3937 } 3938 3939 /* Free the RX lists. */ 3940 ti_free_rx_ring_std(sc); 3941 3942 /* Free jumbo RX list. */ 3943 ti_free_rx_ring_jumbo(sc); 3944 3945 /* Free mini RX list. */ 3946 ti_free_rx_ring_mini(sc); 3947 3948 /* Free TX buffers. */ 3949 ti_free_tx_ring(sc); 3950 3951 sc->ti_ev_prodidx.ti_idx = 0; 3952 sc->ti_return_prodidx.ti_idx = 0; 3953 sc->ti_tx_considx.ti_idx = 0; 3954 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3955 3956 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3957 callout_stop(&sc->ti_watchdog); 3958 } 3959 3960 /* 3961 * Stop all chip I/O so that the kernel's probe routines don't 3962 * get confused by errant DMAs when rebooting. 3963 */ 3964 static int 3965 ti_shutdown(device_t dev) 3966 { 3967 struct ti_softc *sc; 3968 3969 sc = device_get_softc(dev); 3970 TI_LOCK(sc); 3971 ti_chipinit(sc); 3972 TI_UNLOCK(sc); 3973 3974 return (0); 3975 } 3976 3977 static void 3978 ti_sysctl_node(struct ti_softc *sc) 3979 { 3980 struct sysctl_ctx_list *ctx; 3981 struct sysctl_oid_list *child; 3982 char tname[32]; 3983 3984 ctx = device_get_sysctl_ctx(sc->ti_dev); 3985 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 3986 3987 /* Use DAC */ 3988 sc->ti_dac = 1; 3989 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 3990 device_get_unit(sc->ti_dev)); 3991 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 3992 3993 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 3994 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 3995 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 3996 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 3997 3998 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 3999 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4000 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4001 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4002 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4003 &sc->ti_tx_buf_ratio, 0, 4004 "Ratio of NIC memory devoted to TX buffer"); 4005 4006 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4007 &sc->ti_stat_ticks, 0, 4008 "Number of clock ticks for statistics update interval"); 4009 4010 /* Pull in device tunables. */ 4011 sc->ti_rx_coal_ticks = 170; 4012 resource_int_value(device_get_name(sc->ti_dev), 4013 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4014 &sc->ti_rx_coal_ticks); 4015 sc->ti_rx_max_coal_bds = 64; 4016 resource_int_value(device_get_name(sc->ti_dev), 4017 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4018 &sc->ti_rx_max_coal_bds); 4019 4020 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4021 resource_int_value(device_get_name(sc->ti_dev), 4022 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4023 &sc->ti_tx_coal_ticks); 4024 sc->ti_tx_max_coal_bds = 32; 4025 resource_int_value(device_get_name(sc->ti_dev), 4026 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4027 &sc->ti_tx_max_coal_bds); 4028 sc->ti_tx_buf_ratio = 21; 4029 resource_int_value(device_get_name(sc->ti_dev), 4030 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4031 &sc->ti_tx_buf_ratio); 4032 4033 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4034 resource_int_value(device_get_name(sc->ti_dev), 4035 device_get_unit(sc->ti_dev), "stat_ticks", 4036 &sc->ti_stat_ticks); 4037 } 4038