1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/queue.h> 91 92 #include <net/if.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <pci/pcireg.h> 119 #include <pci/pcivar.h> 120 121 #include <pci/if_tireg.h> 122 #include <pci/ti_fw.h> 123 #include <pci/ti_fw2.h> 124 125 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 126 127 #if !defined(lint) 128 static const char rcsid[] = 129 "$FreeBSD$"; 130 #endif 131 132 /* 133 * Various supported device vendors/types and their names. 134 */ 135 136 static struct ti_type ti_devs[] = { 137 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 138 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 139 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 140 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 141 { TC_VENDORID, TC_DEVICEID_3C985, 142 "3Com 3c985-SX Gigabit Ethernet" }, 143 { NG_VENDORID, NG_DEVICEID_GA620, 144 "Netgear GA620 Gigabit Ethernet" }, 145 { SGI_VENDORID, SGI_DEVICEID_TIGON, 146 "Silicon Graphics Gigabit Ethernet" }, 147 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 148 "Farallon PN9000SX Gigabit Ethernet" }, 149 { 0, 0, NULL } 150 }; 151 152 static int ti_probe __P((device_t)); 153 static int ti_attach __P((device_t)); 154 static int ti_detach __P((device_t)); 155 static void ti_txeof __P((struct ti_softc *)); 156 static void ti_rxeof __P((struct ti_softc *)); 157 158 static void ti_stats_update __P((struct ti_softc *)); 159 static int ti_encap __P((struct ti_softc *, struct mbuf *, 160 u_int32_t *)); 161 162 static void ti_intr __P((void *)); 163 static void ti_start __P((struct ifnet *)); 164 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 165 static void ti_init __P((void *)); 166 static void ti_init2 __P((struct ti_softc *)); 167 static void ti_stop __P((struct ti_softc *)); 168 static void ti_watchdog __P((struct ifnet *)); 169 static void ti_shutdown __P((device_t)); 170 static int ti_ifmedia_upd __P((struct ifnet *)); 171 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 172 173 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 174 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 175 int, u_int8_t *)); 176 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 177 178 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 179 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 180 static void ti_setmulti __P((struct ti_softc *)); 181 182 static void ti_mem __P((struct ti_softc *, u_int32_t, 183 u_int32_t, caddr_t)); 184 static void ti_loadfw __P((struct ti_softc *)); 185 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 186 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 187 caddr_t, int)); 188 static void ti_handle_events __P((struct ti_softc *)); 189 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 190 static void *ti_jalloc __P((struct ti_softc *)); 191 static void ti_jfree __P((caddr_t, u_int)); 192 static void ti_jref __P((caddr_t, u_int)); 193 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 194 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 195 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 196 static int ti_init_rx_ring_std __P((struct ti_softc *)); 197 static void ti_free_rx_ring_std __P((struct ti_softc *)); 198 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 199 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 200 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 201 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 202 static void ti_free_tx_ring __P((struct ti_softc *)); 203 static int ti_init_tx_ring __P((struct ti_softc *)); 204 205 static int ti_64bitslot_war __P((struct ti_softc *)); 206 static int ti_chipinit __P((struct ti_softc *)); 207 static int ti_gibinit __P((struct ti_softc *)); 208 209 static device_method_t ti_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ti_probe), 212 DEVMETHOD(device_attach, ti_attach), 213 DEVMETHOD(device_detach, ti_detach), 214 DEVMETHOD(device_shutdown, ti_shutdown), 215 { 0, 0 } 216 }; 217 218 static driver_t ti_driver = { 219 "ti", 220 ti_methods, 221 sizeof(struct ti_softc) 222 }; 223 224 static devclass_t ti_devclass; 225 226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 227 228 /* 229 * Send an instruction or address to the EEPROM, check for ACK. 230 */ 231 static u_int32_t ti_eeprom_putbyte(sc, byte) 232 struct ti_softc *sc; 233 int byte; 234 { 235 register int i, ack = 0; 236 237 /* 238 * Make sure we're in TX mode. 239 */ 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 241 242 /* 243 * Feed in each bit and stobe the clock. 244 */ 245 for (i = 0x80; i; i >>= 1) { 246 if (byte & i) { 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } else { 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 250 } 251 DELAY(1); 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 DELAY(1); 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 } 256 257 /* 258 * Turn off TX mode. 259 */ 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 261 262 /* 263 * Check for ack. 264 */ 265 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 267 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 268 269 return(ack); 270 } 271 272 /* 273 * Read a byte of data stored in the EEPROM at address 'addr.' 274 * We have to send two address bytes since the EEPROM can hold 275 * more than 256 bytes of data. 276 */ 277 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 278 struct ti_softc *sc; 279 int addr; 280 u_int8_t *dest; 281 { 282 register int i; 283 u_int8_t byte = 0; 284 285 EEPROM_START; 286 287 /* 288 * Send write control code to EEPROM. 289 */ 290 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 291 printf("ti%d: failed to send write command, status: %x\n", 292 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 /* 297 * Send first byte of address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 300 printf("ti%d: failed to send address, status: %x\n", 301 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 /* 305 * Send second byte address of byte we want to read. 306 */ 307 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 308 printf("ti%d: failed to send address, status: %x\n", 309 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 310 return(1); 311 } 312 313 EEPROM_STOP; 314 EEPROM_START; 315 /* 316 * Send read control code to EEPROM. 317 */ 318 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 319 printf("ti%d: failed to send read command, status: %x\n", 320 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 321 return(1); 322 } 323 324 /* 325 * Start reading bits from EEPROM. 326 */ 327 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 328 for (i = 0x80; i; i >>= 1) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 330 DELAY(1); 331 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 332 byte |= i; 333 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 334 DELAY(1); 335 } 336 337 EEPROM_STOP; 338 339 /* 340 * No ACK generated for read, so just return byte. 341 */ 342 343 *dest = byte; 344 345 return(0); 346 } 347 348 /* 349 * Read a sequence of bytes from the EEPROM. 350 */ 351 static int ti_read_eeprom(sc, dest, off, cnt) 352 struct ti_softc *sc; 353 caddr_t dest; 354 int off; 355 int cnt; 356 { 357 int err = 0, i; 358 u_int8_t byte = 0; 359 360 for (i = 0; i < cnt; i++) { 361 err = ti_eeprom_getbyte(sc, off + i, &byte); 362 if (err) 363 break; 364 *(dest + i) = byte; 365 } 366 367 return(err ? 1 : 0); 368 } 369 370 /* 371 * NIC memory access function. Can be used to either clear a section 372 * of NIC local memory or (if buf is non-NULL) copy data into it. 373 */ 374 static void ti_mem(sc, addr, len, buf) 375 struct ti_softc *sc; 376 u_int32_t addr, len; 377 caddr_t buf; 378 { 379 int segptr, segsize, cnt; 380 caddr_t ti_winbase, ptr; 381 382 segptr = addr; 383 cnt = len; 384 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 385 ptr = buf; 386 387 while(cnt) { 388 if (cnt < TI_WINLEN) 389 segsize = cnt; 390 else 391 segsize = TI_WINLEN - (segptr % TI_WINLEN); 392 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 393 if (buf == NULL) 394 bzero((char *)ti_winbase + (segptr & 395 (TI_WINLEN - 1)), segsize); 396 else { 397 bcopy((char *)ptr, (char *)ti_winbase + 398 (segptr & (TI_WINLEN - 1)), segsize); 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406 } 407 408 /* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413 static void ti_loadfw(sc) 414 struct ti_softc *sc; 415 { 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("ti%d: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("ti%d: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("ti%d: can't load firmware: unknown hardware rev\n", 461 sc->ti_unit); 462 break; 463 } 464 465 return; 466 } 467 468 /* 469 * Send the NIC a command via the command ring. 470 */ 471 static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474 { 475 u_int32_t index; 476 477 if (sc->ti_rdata->ti_cmd_ring == NULL) 478 return; 479 480 index = sc->ti_cmd_saved_prodidx; 481 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 482 TI_INC(index, TI_CMD_RING_CNT); 483 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 484 sc->ti_cmd_saved_prodidx = index; 485 486 return; 487 } 488 489 /* 490 * Send the NIC an extended command. The 'len' parameter specifies the 491 * number of command slots to include after the initial command. 492 */ 493 static void ti_cmd_ext(sc, cmd, arg, len) 494 struct ti_softc *sc; 495 struct ti_cmd_desc *cmd; 496 caddr_t arg; 497 int len; 498 { 499 u_int32_t index; 500 register int i; 501 502 if (sc->ti_rdata->ti_cmd_ring == NULL) 503 return; 504 505 index = sc->ti_cmd_saved_prodidx; 506 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 507 TI_INC(index, TI_CMD_RING_CNT); 508 for (i = 0; i < len; i++) { 509 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 510 *(u_int32_t *)(&arg[i * 4])); 511 TI_INC(index, TI_CMD_RING_CNT); 512 } 513 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 514 sc->ti_cmd_saved_prodidx = index; 515 516 return; 517 } 518 519 /* 520 * Handle events that have triggered interrupts. 521 */ 522 static void ti_handle_events(sc) 523 struct ti_softc *sc; 524 { 525 struct ti_event_desc *e; 526 527 if (sc->ti_rdata->ti_event_ring == NULL) 528 return; 529 530 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 531 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 532 switch(e->ti_event) { 533 case TI_EV_LINKSTAT_CHANGED: 534 sc->ti_linkstat = e->ti_code; 535 if (e->ti_code == TI_EV_CODE_LINK_UP) 536 printf("ti%d: 10/100 link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 538 printf("ti%d: gigabit link up\n", sc->ti_unit); 539 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 540 printf("ti%d: link down\n", sc->ti_unit); 541 break; 542 case TI_EV_ERROR: 543 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 544 printf("ti%d: invalid command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 546 printf("ti%d: unknown command\n", sc->ti_unit); 547 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 548 printf("ti%d: bad config data\n", sc->ti_unit); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("ti%d: unknown event: %d\n", 562 sc->ti_unit, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571 } 572 573 /* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596 static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598 { 599 caddr_t ptr; 600 register int i; 601 struct ti_jpool_entry *entry; 602 603 /* Grab a big chunk o' storage. */ 604 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 605 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 606 607 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 608 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 609 return(ENOBUFS); 610 } 611 612 SLIST_INIT(&sc->ti_jfree_listhead); 613 SLIST_INIT(&sc->ti_jinuse_listhead); 614 615 /* 616 * Now divide it up into 9K pieces and save the addresses 617 * in an array. Note that we play an evil trick here by using 618 * the first few bytes in the buffer to hold the the address 619 * of the softc structure for this interface. This is because 620 * ti_jfree() needs it, but it is called by the mbuf management 621 * code which will not pass it to us explicitly. 622 */ 623 ptr = sc->ti_cdata.ti_jumbo_buf; 624 for (i = 0; i < TI_JSLOTS; i++) { 625 u_int64_t **aptr; 626 aptr = (u_int64_t **)ptr; 627 aptr[0] = (u_int64_t *)sc; 628 ptr += sizeof(u_int64_t); 629 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 630 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 631 ptr += (TI_JLEN - sizeof(u_int64_t)); 632 entry = malloc(sizeof(struct ti_jpool_entry), 633 M_DEVBUF, M_NOWAIT); 634 if (entry == NULL) { 635 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 636 M_DEVBUF); 637 sc->ti_cdata.ti_jumbo_buf = NULL; 638 printf("ti%d: no memory for jumbo " 639 "buffer queue!\n", sc->ti_unit); 640 return(ENOBUFS); 641 } 642 entry->slot = i; 643 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 644 } 645 646 return(0); 647 } 648 649 /* 650 * Allocate a jumbo buffer. 651 */ 652 static void *ti_jalloc(sc) 653 struct ti_softc *sc; 654 { 655 struct ti_jpool_entry *entry; 656 657 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 658 659 if (entry == NULL) { 660 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 661 return(NULL); 662 } 663 664 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 665 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 666 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 667 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 668 } 669 670 /* 671 * Adjust usage count on a jumbo buffer. In general this doesn't 672 * get used much because our jumbo buffers don't get passed around 673 * too much, but it's implemented for correctness. 674 */ 675 static void ti_jref(buf, size) 676 caddr_t buf; 677 u_int size; 678 { 679 struct ti_softc *sc; 680 u_int64_t **aptr; 681 register int i; 682 683 /* Extract the softc struct pointer. */ 684 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 685 sc = (struct ti_softc *)(aptr[0]); 686 687 if (sc == NULL) 688 panic("ti_jref: can't find softc pointer!"); 689 690 if (size != TI_JUMBO_FRAMELEN) 691 panic("ti_jref: adjusting refcount of buf of wrong size!"); 692 693 /* calculate the slot this buffer belongs to */ 694 695 i = ((vm_offset_t)aptr 696 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 697 698 if ((i < 0) || (i >= TI_JSLOTS)) 699 panic("ti_jref: asked to reference buffer " 700 "that we don't manage!"); 701 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 702 panic("ti_jref: buffer already free!"); 703 else 704 sc->ti_cdata.ti_jslots[i].ti_inuse++; 705 706 return; 707 } 708 709 /* 710 * Release a jumbo buffer. 711 */ 712 static void ti_jfree(buf, size) 713 caddr_t buf; 714 u_int size; 715 { 716 struct ti_softc *sc; 717 u_int64_t **aptr; 718 int i; 719 struct ti_jpool_entry *entry; 720 721 /* Extract the softc struct pointer. */ 722 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 723 sc = (struct ti_softc *)(aptr[0]); 724 725 if (sc == NULL) 726 panic("ti_jfree: can't find softc pointer!"); 727 728 if (size != TI_JUMBO_FRAMELEN) 729 panic("ti_jfree: freeing buffer of wrong size!"); 730 731 /* calculate the slot this buffer belongs to */ 732 733 i = ((vm_offset_t)aptr 734 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 735 736 if ((i < 0) || (i >= TI_JSLOTS)) 737 panic("ti_jfree: asked to free buffer that we don't manage!"); 738 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 739 panic("ti_jfree: buffer already free!"); 740 else { 741 sc->ti_cdata.ti_jslots[i].ti_inuse--; 742 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 743 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 744 if (entry == NULL) 745 panic("ti_jfree: buffer not in use!"); 746 entry->slot = i; 747 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 748 jpool_entries); 749 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 750 entry, jpool_entries); 751 } 752 } 753 754 return; 755 } 756 757 758 /* 759 * Intialize a standard receive ring descriptor. 760 */ 761 static int ti_newbuf_std(sc, i, m) 762 struct ti_softc *sc; 763 int i; 764 struct mbuf *m; 765 { 766 struct mbuf *m_new = NULL; 767 struct ti_rx_desc *r; 768 769 if (m == NULL) { 770 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 771 if (m_new == NULL) { 772 printf("ti%d: mbuf allocation failed " 773 "-- packet dropped!\n", sc->ti_unit); 774 return(ENOBUFS); 775 } 776 777 MCLGET(m_new, M_DONTWAIT); 778 if (!(m_new->m_flags & M_EXT)) { 779 printf("ti%d: cluster allocation failed " 780 "-- packet dropped!\n", sc->ti_unit); 781 m_freem(m_new); 782 return(ENOBUFS); 783 } 784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 785 } else { 786 m_new = m; 787 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 788 m_new->m_data = m_new->m_ext.ext_buf; 789 } 790 791 m_adj(m_new, ETHER_ALIGN); 792 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 793 r = &sc->ti_rdata->ti_rx_std_ring[i]; 794 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 795 r->ti_type = TI_BDTYPE_RECV_BD; 796 r->ti_flags = 0; 797 if (sc->arpcom.ac_if.if_hwassist) 798 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 799 r->ti_len = m_new->m_len; 800 r->ti_idx = i; 801 802 return(0); 803 } 804 805 /* 806 * Intialize a mini receive ring descriptor. This only applies to 807 * the Tigon 2. 808 */ 809 static int ti_newbuf_mini(sc, i, m) 810 struct ti_softc *sc; 811 int i; 812 struct mbuf *m; 813 { 814 struct mbuf *m_new = NULL; 815 struct ti_rx_desc *r; 816 817 if (m == NULL) { 818 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 819 if (m_new == NULL) { 820 printf("ti%d: mbuf allocation failed " 821 "-- packet dropped!\n", sc->ti_unit); 822 return(ENOBUFS); 823 } 824 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 825 } else { 826 m_new = m; 827 m_new->m_data = m_new->m_pktdat; 828 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 829 } 830 831 m_adj(m_new, ETHER_ALIGN); 832 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 833 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 834 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 835 r->ti_type = TI_BDTYPE_RECV_BD; 836 r->ti_flags = TI_BDFLAG_MINI_RING; 837 if (sc->arpcom.ac_if.if_hwassist) 838 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 839 r->ti_len = m_new->m_len; 840 r->ti_idx = i; 841 842 return(0); 843 } 844 845 /* 846 * Initialize a jumbo receive ring descriptor. This allocates 847 * a jumbo buffer from the pool managed internally by the driver. 848 */ 849 static int ti_newbuf_jumbo(sc, i, m) 850 struct ti_softc *sc; 851 int i; 852 struct mbuf *m; 853 { 854 struct mbuf *m_new = NULL; 855 struct ti_rx_desc *r; 856 857 if (m == NULL) { 858 caddr_t *buf = NULL; 859 860 /* Allocate the mbuf. */ 861 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 862 if (m_new == NULL) { 863 printf("ti%d: mbuf allocation failed " 864 "-- packet dropped!\n", sc->ti_unit); 865 return(ENOBUFS); 866 } 867 868 /* Allocate the jumbo buffer */ 869 buf = ti_jalloc(sc); 870 if (buf == NULL) { 871 m_freem(m_new); 872 printf("ti%d: jumbo allocation failed " 873 "-- packet dropped!\n", sc->ti_unit); 874 return(ENOBUFS); 875 } 876 877 /* Attach the buffer to the mbuf. */ 878 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 879 m_new->m_flags |= M_EXT; 880 m_new->m_len = m_new->m_pkthdr.len = 881 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 882 m_new->m_ext.ext_free = ti_jfree; 883 m_new->m_ext.ext_ref = ti_jref; 884 } else { 885 m_new = m; 886 m_new->m_data = m_new->m_ext.ext_buf; 887 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 888 } 889 890 m_adj(m_new, ETHER_ALIGN); 891 /* Set up the descriptor. */ 892 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 893 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 894 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 895 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 896 r->ti_flags = TI_BDFLAG_JUMBO_RING; 897 if (sc->arpcom.ac_if.if_hwassist) 898 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 899 r->ti_len = m_new->m_len; 900 r->ti_idx = i; 901 902 return(0); 903 } 904 905 /* 906 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 907 * that's 1MB or memory, which is a lot. For now, we fill only the first 908 * 256 ring entries and hope that our CPU is fast enough to keep up with 909 * the NIC. 910 */ 911 static int ti_init_rx_ring_std(sc) 912 struct ti_softc *sc; 913 { 914 register int i; 915 struct ti_cmd_desc cmd; 916 917 for (i = 0; i < TI_SSLOTS; i++) { 918 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 919 return(ENOBUFS); 920 }; 921 922 TI_UPDATE_STDPROD(sc, i - 1); 923 sc->ti_std = i - 1; 924 925 return(0); 926 } 927 928 static void ti_free_rx_ring_std(sc) 929 struct ti_softc *sc; 930 { 931 register int i; 932 933 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 934 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 935 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 936 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 937 } 938 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 939 sizeof(struct ti_rx_desc)); 940 } 941 942 return; 943 } 944 945 static int ti_init_rx_ring_jumbo(sc) 946 struct ti_softc *sc; 947 { 948 register int i; 949 struct ti_cmd_desc cmd; 950 951 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 952 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 953 return(ENOBUFS); 954 }; 955 956 TI_UPDATE_JUMBOPROD(sc, i - 1); 957 sc->ti_jumbo = i - 1; 958 959 return(0); 960 } 961 962 static void ti_free_rx_ring_jumbo(sc) 963 struct ti_softc *sc; 964 { 965 register int i; 966 967 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 968 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 969 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 970 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 971 } 972 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 973 sizeof(struct ti_rx_desc)); 974 } 975 976 return; 977 } 978 979 static int ti_init_rx_ring_mini(sc) 980 struct ti_softc *sc; 981 { 982 register int i; 983 984 for (i = 0; i < TI_MSLOTS; i++) { 985 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 986 return(ENOBUFS); 987 }; 988 989 TI_UPDATE_MINIPROD(sc, i - 1); 990 sc->ti_mini = i - 1; 991 992 return(0); 993 } 994 995 static void ti_free_rx_ring_mini(sc) 996 struct ti_softc *sc; 997 { 998 register int i; 999 1000 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1001 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1002 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1003 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1004 } 1005 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1006 sizeof(struct ti_rx_desc)); 1007 } 1008 1009 return; 1010 } 1011 1012 static void ti_free_tx_ring(sc) 1013 struct ti_softc *sc; 1014 { 1015 register int i; 1016 1017 if (sc->ti_rdata->ti_tx_ring == NULL) 1018 return; 1019 1020 for (i = 0; i < TI_TX_RING_CNT; i++) { 1021 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1022 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1023 sc->ti_cdata.ti_tx_chain[i] = NULL; 1024 } 1025 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1026 sizeof(struct ti_tx_desc)); 1027 } 1028 1029 return; 1030 } 1031 1032 static int ti_init_tx_ring(sc) 1033 struct ti_softc *sc; 1034 { 1035 sc->ti_txcnt = 0; 1036 sc->ti_tx_saved_considx = 0; 1037 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1038 return(0); 1039 } 1040 1041 /* 1042 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1043 * but we have to support the old way too so that Tigon 1 cards will 1044 * work. 1045 */ 1046 void ti_add_mcast(sc, addr) 1047 struct ti_softc *sc; 1048 struct ether_addr *addr; 1049 { 1050 struct ti_cmd_desc cmd; 1051 u_int16_t *m; 1052 u_int32_t ext[2] = {0, 0}; 1053 1054 m = (u_int16_t *)&addr->octet[0]; 1055 1056 switch(sc->ti_hwrev) { 1057 case TI_HWREV_TIGON: 1058 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1059 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1060 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1061 break; 1062 case TI_HWREV_TIGON_II: 1063 ext[0] = htons(m[0]); 1064 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1065 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1066 break; 1067 default: 1068 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1069 break; 1070 } 1071 1072 return; 1073 } 1074 1075 void ti_del_mcast(sc, addr) 1076 struct ti_softc *sc; 1077 struct ether_addr *addr; 1078 { 1079 struct ti_cmd_desc cmd; 1080 u_int16_t *m; 1081 u_int32_t ext[2] = {0, 0}; 1082 1083 m = (u_int16_t *)&addr->octet[0]; 1084 1085 switch(sc->ti_hwrev) { 1086 case TI_HWREV_TIGON: 1087 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1088 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1089 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1090 break; 1091 case TI_HWREV_TIGON_II: 1092 ext[0] = htons(m[0]); 1093 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1094 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1095 break; 1096 default: 1097 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1098 break; 1099 } 1100 1101 return; 1102 } 1103 1104 /* 1105 * Configure the Tigon's multicast address filter. 1106 * 1107 * The actual multicast table management is a bit of a pain, thanks to 1108 * slight brain damage on the part of both Alteon and us. With our 1109 * multicast code, we are only alerted when the multicast address table 1110 * changes and at that point we only have the current list of addresses: 1111 * we only know the current state, not the previous state, so we don't 1112 * actually know what addresses were removed or added. The firmware has 1113 * state, but we can't get our grubby mits on it, and there is no 'delete 1114 * all multicast addresses' command. Hence, we have to maintain our own 1115 * state so we know what addresses have been programmed into the NIC at 1116 * any given time. 1117 */ 1118 static void ti_setmulti(sc) 1119 struct ti_softc *sc; 1120 { 1121 struct ifnet *ifp; 1122 struct ifmultiaddr *ifma; 1123 struct ti_cmd_desc cmd; 1124 struct ti_mc_entry *mc; 1125 u_int32_t intrs; 1126 1127 ifp = &sc->arpcom.ac_if; 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) { 1130 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1131 return; 1132 } else { 1133 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1134 } 1135 1136 /* Disable interrupts. */ 1137 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1138 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1139 1140 /* First, zot all the existing filters. */ 1141 while (sc->ti_mc_listhead.slh_first != NULL) { 1142 mc = sc->ti_mc_listhead.slh_first; 1143 ti_del_mcast(sc, &mc->mc_addr); 1144 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1145 free(mc, M_DEVBUF); 1146 } 1147 1148 /* Now program new ones. */ 1149 for (ifma = ifp->if_multiaddrs.lh_first; 1150 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1151 if (ifma->ifma_addr->sa_family != AF_LINK) 1152 continue; 1153 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1154 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1155 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1156 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1157 ti_add_mcast(sc, &mc->mc_addr); 1158 } 1159 1160 /* Re-enable interrupts. */ 1161 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1162 1163 return; 1164 } 1165 1166 /* 1167 * Check to see if the BIOS has configured us for a 64 bit slot when 1168 * we aren't actually in one. If we detect this condition, we can work 1169 * around it on the Tigon 2 by setting a bit in the PCI state register, 1170 * but for the Tigon 1 we must give up and abort the interface attach. 1171 */ 1172 static int ti_64bitslot_war(sc) 1173 struct ti_softc *sc; 1174 { 1175 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1176 CSR_WRITE_4(sc, 0x600, 0); 1177 CSR_WRITE_4(sc, 0x604, 0); 1178 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1179 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1180 if (sc->ti_hwrev == TI_HWREV_TIGON) 1181 return(EINVAL); 1182 else { 1183 TI_SETBIT(sc, TI_PCI_STATE, 1184 TI_PCISTATE_32BIT_BUS); 1185 return(0); 1186 } 1187 } 1188 } 1189 1190 return(0); 1191 } 1192 1193 /* 1194 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1195 * self-test results. 1196 */ 1197 static int ti_chipinit(sc) 1198 struct ti_softc *sc; 1199 { 1200 u_int32_t cacheline; 1201 u_int32_t pci_writemax = 0; 1202 1203 /* Initialize link to down state. */ 1204 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1205 1206 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1207 1208 /* Set endianness before we access any non-PCI registers. */ 1209 #if BYTE_ORDER == BIG_ENDIAN 1210 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1211 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1212 #else 1213 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1214 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1215 #endif 1216 1217 /* Check the ROM failed bit to see if self-tests passed. */ 1218 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1219 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1220 return(ENODEV); 1221 } 1222 1223 /* Halt the CPU. */ 1224 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1225 1226 /* Figure out the hardware revision. */ 1227 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1228 case TI_REV_TIGON_I: 1229 sc->ti_hwrev = TI_HWREV_TIGON; 1230 break; 1231 case TI_REV_TIGON_II: 1232 sc->ti_hwrev = TI_HWREV_TIGON_II; 1233 break; 1234 default: 1235 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1236 return(ENODEV); 1237 } 1238 1239 /* Do special setup for Tigon 2. */ 1240 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1241 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1243 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1244 } 1245 1246 /* Set up the PCI state register. */ 1247 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1248 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1249 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1250 } 1251 1252 /* Clear the read/write max DMA parameters. */ 1253 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1254 TI_PCISTATE_READ_MAXDMA)); 1255 1256 /* Get cache line size. */ 1257 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1258 1259 /* 1260 * If the system has set enabled the PCI memory write 1261 * and invalidate command in the command register, set 1262 * the write max parameter accordingly. This is necessary 1263 * to use MWI with the Tigon 2. 1264 */ 1265 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1266 switch(cacheline) { 1267 case 1: 1268 case 4: 1269 case 8: 1270 case 16: 1271 case 32: 1272 case 64: 1273 break; 1274 default: 1275 /* Disable PCI memory write and invalidate. */ 1276 if (bootverbose) 1277 printf("ti%d: cache line size %d not " 1278 "supported; disabling PCI MWI\n", 1279 sc->ti_unit, cacheline); 1280 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1281 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1282 break; 1283 } 1284 } 1285 1286 #ifdef __brokenalpha__ 1287 /* 1288 * From the Alteon sample driver: 1289 * Must insure that we do not cross an 8K (bytes) boundary 1290 * for DMA reads. Our highest limit is 1K bytes. This is a 1291 * restriction on some ALPHA platforms with early revision 1292 * 21174 PCI chipsets, such as the AlphaPC 164lx 1293 */ 1294 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1295 #else 1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1297 #endif 1298 1299 /* This sets the min dma param all the way up (0xff). */ 1300 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1301 1302 /* Configure DMA variables. */ 1303 #if BYTE_ORDER == BIG_ENDIAN 1304 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1305 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1306 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1307 TI_OPMODE_DONT_FRAG_JUMBO); 1308 #else 1309 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1310 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1311 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1312 #endif 1313 1314 /* 1315 * Only allow 1 DMA channel to be active at a time. 1316 * I don't think this is a good idea, but without it 1317 * the firmware racks up lots of nicDmaReadRingFull 1318 * errors. This is not compatible with hardware checksums. 1319 */ 1320 if (sc->arpcom.ac_if.if_hwassist == 0) 1321 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1322 1323 /* Recommended settings from Tigon manual. */ 1324 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1325 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1326 1327 if (ti_64bitslot_war(sc)) { 1328 printf("ti%d: bios thinks we're in a 64 bit slot, " 1329 "but we aren't", sc->ti_unit); 1330 return(EINVAL); 1331 } 1332 1333 return(0); 1334 } 1335 1336 /* 1337 * Initialize the general information block and firmware, and 1338 * start the CPU(s) running. 1339 */ 1340 static int ti_gibinit(sc) 1341 struct ti_softc *sc; 1342 { 1343 struct ti_rcb *rcb; 1344 int i; 1345 struct ifnet *ifp; 1346 1347 ifp = &sc->arpcom.ac_if; 1348 1349 /* Disable interrupts for now. */ 1350 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1351 1352 /* Tell the chip where to find the general information block. */ 1353 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1354 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1355 1356 /* Load the firmware into SRAM. */ 1357 ti_loadfw(sc); 1358 1359 /* Set up the contents of the general info and ring control blocks. */ 1360 1361 /* Set up the event ring and producer pointer. */ 1362 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1363 1364 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1365 rcb->ti_flags = 0; 1366 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1367 vtophys(&sc->ti_ev_prodidx); 1368 sc->ti_ev_prodidx.ti_idx = 0; 1369 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1370 sc->ti_ev_saved_considx = 0; 1371 1372 /* Set up the command ring and producer mailbox. */ 1373 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1374 1375 sc->ti_rdata->ti_cmd_ring = 1376 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1377 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1378 rcb->ti_flags = 0; 1379 rcb->ti_max_len = 0; 1380 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1381 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1382 } 1383 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1384 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1385 sc->ti_cmd_saved_prodidx = 0; 1386 1387 /* 1388 * Assign the address of the stats refresh buffer. 1389 * We re-use the current stats buffer for this to 1390 * conserve memory. 1391 */ 1392 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1393 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1394 1395 /* Set up the standard receive ring. */ 1396 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1397 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1398 rcb->ti_max_len = TI_FRAMELEN; 1399 rcb->ti_flags = 0; 1400 if (sc->arpcom.ac_if.if_hwassist) 1401 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1402 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1403 #if NVLAN > 0 1404 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1405 #endif 1406 1407 /* Set up the jumbo receive ring. */ 1408 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1409 TI_HOSTADDR(rcb->ti_hostaddr) = 1410 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1411 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1412 rcb->ti_flags = 0; 1413 if (sc->arpcom.ac_if.if_hwassist) 1414 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1415 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1416 #if NVLAN > 0 1417 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1418 #endif 1419 1420 /* 1421 * Set up the mini ring. Only activated on the 1422 * Tigon 2 but the slot in the config block is 1423 * still there on the Tigon 1. 1424 */ 1425 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1426 TI_HOSTADDR(rcb->ti_hostaddr) = 1427 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1428 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1429 if (sc->ti_hwrev == TI_HWREV_TIGON) 1430 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1431 else 1432 rcb->ti_flags = 0; 1433 if (sc->arpcom.ac_if.if_hwassist) 1434 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1435 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1436 #if NVLAN > 0 1437 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1438 #endif 1439 1440 /* 1441 * Set up the receive return ring. 1442 */ 1443 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1444 TI_HOSTADDR(rcb->ti_hostaddr) = 1445 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1446 rcb->ti_flags = 0; 1447 rcb->ti_max_len = TI_RETURN_RING_CNT; 1448 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1449 vtophys(&sc->ti_return_prodidx); 1450 1451 /* 1452 * Set up the tx ring. Note: for the Tigon 2, we have the option 1453 * of putting the transmit ring in the host's address space and 1454 * letting the chip DMA it instead of leaving the ring in the NIC's 1455 * memory and accessing it through the shared memory region. We 1456 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1457 * so we have to revert to the shared memory scheme if we detect 1458 * a Tigon 1 chip. 1459 */ 1460 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1461 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1462 sc->ti_rdata->ti_tx_ring_nic = 1463 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1464 } 1465 bzero((char *)sc->ti_rdata->ti_tx_ring, 1466 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1467 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1468 if (sc->ti_hwrev == TI_HWREV_TIGON) 1469 rcb->ti_flags = 0; 1470 else 1471 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1472 #if NVLAN > 0 1473 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1474 #endif 1475 if (sc->arpcom.ac_if.if_hwassist) 1476 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1477 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1478 rcb->ti_max_len = TI_TX_RING_CNT; 1479 if (sc->ti_hwrev == TI_HWREV_TIGON) 1480 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1481 else 1482 TI_HOSTADDR(rcb->ti_hostaddr) = 1483 vtophys(&sc->ti_rdata->ti_tx_ring); 1484 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1485 vtophys(&sc->ti_tx_considx); 1486 1487 /* Set up tuneables */ 1488 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1490 (sc->ti_rx_coal_ticks / 10)); 1491 else 1492 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1493 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1494 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1495 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1496 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1497 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1498 1499 /* Turn interrupts on. */ 1500 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1501 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1502 1503 /* Start CPU. */ 1504 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1505 1506 return(0); 1507 } 1508 1509 /* 1510 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1511 * against our list and return its name if we find a match. 1512 */ 1513 static int ti_probe(dev) 1514 device_t dev; 1515 { 1516 struct ti_type *t; 1517 1518 t = ti_devs; 1519 1520 while(t->ti_name != NULL) { 1521 if ((pci_get_vendor(dev) == t->ti_vid) && 1522 (pci_get_device(dev) == t->ti_did)) { 1523 device_set_desc(dev, t->ti_name); 1524 return(0); 1525 } 1526 t++; 1527 } 1528 1529 return(ENXIO); 1530 } 1531 1532 static int ti_attach(dev) 1533 device_t dev; 1534 { 1535 int s; 1536 u_int32_t command; 1537 struct ifnet *ifp; 1538 struct ti_softc *sc; 1539 int unit, error = 0, rid; 1540 1541 s = splimp(); 1542 1543 sc = device_get_softc(dev); 1544 unit = device_get_unit(dev); 1545 bzero(sc, sizeof(struct ti_softc)); 1546 1547 /* 1548 * Map control/status registers. 1549 */ 1550 command = pci_read_config(dev, PCIR_COMMAND, 4); 1551 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1552 pci_write_config(dev, PCIR_COMMAND, command, 4); 1553 command = pci_read_config(dev, PCIR_COMMAND, 4); 1554 1555 if (!(command & PCIM_CMD_MEMEN)) { 1556 printf("ti%d: failed to enable memory mapping!\n", unit); 1557 error = ENXIO; 1558 goto fail; 1559 } 1560 1561 rid = TI_PCI_LOMEM; 1562 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1563 0, ~0, 1, RF_ACTIVE); 1564 1565 if (sc->ti_res == NULL) { 1566 printf ("ti%d: couldn't map memory\n", unit); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 sc->ti_btag = rman_get_bustag(sc->ti_res); 1572 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1573 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1574 1575 /* 1576 * XXX FIXME: rman_get_virtual() on the alpha is currently 1577 * broken and returns a physical address instead of a kernel 1578 * virtual address. Consequently, we need to do a little 1579 * extra mangling of the vhandle on the alpha. This should 1580 * eventually be fixed! The whole idea here is to get rid 1581 * of platform dependencies. 1582 */ 1583 #ifdef __alpha__ 1584 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1585 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1586 else 1587 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1588 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1589 #endif 1590 1591 /* Allocate interrupt */ 1592 rid = 0; 1593 1594 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1595 RF_SHAREABLE | RF_ACTIVE); 1596 1597 if (sc->ti_irq == NULL) { 1598 printf("ti%d: couldn't map interrupt\n", unit); 1599 error = ENXIO; 1600 goto fail; 1601 } 1602 1603 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1604 ti_intr, sc, &sc->ti_intrhand); 1605 1606 if (error) { 1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1608 bus_release_resource(dev, SYS_RES_MEMORY, 1609 TI_PCI_LOMEM, sc->ti_res); 1610 printf("ti%d: couldn't set up irq\n", unit); 1611 goto fail; 1612 } 1613 1614 sc->ti_unit = unit; 1615 1616 if (ti_chipinit(sc)) { 1617 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1618 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1619 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1620 bus_release_resource(dev, SYS_RES_MEMORY, 1621 TI_PCI_LOMEM, sc->ti_res); 1622 error = ENXIO; 1623 goto fail; 1624 } 1625 1626 /* Zero out the NIC's on-board SRAM. */ 1627 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1628 1629 /* Init again -- zeroing memory may have clobbered some registers. */ 1630 if (ti_chipinit(sc)) { 1631 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1632 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1633 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1634 bus_release_resource(dev, SYS_RES_MEMORY, 1635 TI_PCI_LOMEM, sc->ti_res); 1636 error = ENXIO; 1637 goto fail; 1638 } 1639 1640 /* 1641 * Get station address from the EEPROM. Note: the manual states 1642 * that the MAC address is at offset 0x8c, however the data is 1643 * stored as two longwords (since that's how it's loaded into 1644 * the NIC). This means the MAC address is actually preceeded 1645 * by two zero bytes. We need to skip over those. 1646 */ 1647 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1648 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1649 printf("ti%d: failed to read station address\n", unit); 1650 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1651 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1652 bus_release_resource(dev, SYS_RES_MEMORY, 1653 TI_PCI_LOMEM, sc->ti_res); 1654 error = ENXIO; 1655 goto fail; 1656 } 1657 1658 /* 1659 * A Tigon chip was detected. Inform the world. 1660 */ 1661 printf("ti%d: Ethernet address: %6D\n", unit, 1662 sc->arpcom.ac_enaddr, ":"); 1663 1664 /* Allocate the general information block and ring buffers. */ 1665 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1666 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1667 1668 if (sc->ti_rdata == NULL) { 1669 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1670 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1671 bus_release_resource(dev, SYS_RES_MEMORY, 1672 TI_PCI_LOMEM, sc->ti_res); 1673 error = ENXIO; 1674 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1675 goto fail; 1676 } 1677 1678 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1679 1680 /* Try to allocate memory for jumbo buffers. */ 1681 if (ti_alloc_jumbo_mem(sc)) { 1682 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1683 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1684 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1685 bus_release_resource(dev, SYS_RES_MEMORY, 1686 TI_PCI_LOMEM, sc->ti_res); 1687 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 1688 M_DEVBUF); 1689 error = ENXIO; 1690 goto fail; 1691 } 1692 1693 /* 1694 * We really need a better way to tell a 1000baseTX card 1695 * from a 1000baseSX one, since in theory there could be 1696 * OEMed 1000baseTX cards from lame vendors who aren't 1697 * clever enough to change the PCI ID. For the moment 1698 * though, the AceNIC is the only copper card available. 1699 */ 1700 if (pci_get_vendor(dev) == ALT_VENDORID && 1701 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 1702 sc->ti_copper = 1; 1703 1704 /* Set default tuneable values. */ 1705 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1706 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1707 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1708 sc->ti_rx_max_coal_bds = 64; 1709 sc->ti_tx_max_coal_bds = 128; 1710 sc->ti_tx_buf_ratio = 21; 1711 1712 /* Set up ifnet structure */ 1713 ifp = &sc->arpcom.ac_if; 1714 ifp->if_softc = sc; 1715 ifp->if_unit = sc->ti_unit; 1716 ifp->if_name = "ti"; 1717 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1718 ifp->if_ioctl = ti_ioctl; 1719 ifp->if_output = ether_output; 1720 ifp->if_start = ti_start; 1721 ifp->if_watchdog = ti_watchdog; 1722 ifp->if_init = ti_init; 1723 ifp->if_mtu = ETHERMTU; 1724 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1725 1726 /* Set up ifmedia support. */ 1727 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1728 if (sc->ti_copper) { 1729 /* 1730 * Copper cards allow manual 10/100 mode selection, 1731 * but not manual 1000baseTX mode selection. Why? 1732 * Becuase currently there's no way to specify the 1733 * master/slave setting through the firmware interface, 1734 * so Alteon decided to just bag it and handle it 1735 * via autonegotiation. 1736 */ 1737 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1738 ifmedia_add(&sc->ifmedia, 1739 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1740 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1741 ifmedia_add(&sc->ifmedia, 1742 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1743 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL); 1744 ifmedia_add(&sc->ifmedia, 1745 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL); 1746 } else { 1747 /* Fiber cards don't support 10/100 modes. */ 1748 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1749 ifmedia_add(&sc->ifmedia, 1750 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1751 } 1752 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1753 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1754 1755 /* 1756 * Call MI attach routine. 1757 */ 1758 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1759 1760 fail: 1761 splx(s); 1762 1763 return(error); 1764 } 1765 1766 static int ti_detach(dev) 1767 device_t dev; 1768 { 1769 struct ti_softc *sc; 1770 struct ifnet *ifp; 1771 int s; 1772 1773 s = splimp(); 1774 1775 sc = device_get_softc(dev); 1776 ifp = &sc->arpcom.ac_if; 1777 1778 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1779 ti_stop(sc); 1780 1781 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1782 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1783 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1784 1785 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 1786 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 1787 ifmedia_removeall(&sc->ifmedia); 1788 1789 splx(s); 1790 1791 return(0); 1792 } 1793 1794 /* 1795 * Frame reception handling. This is called if there's a frame 1796 * on the receive return list. 1797 * 1798 * Note: we have to be able to handle three possibilities here: 1799 * 1) the frame is from the mini receive ring (can only happen) 1800 * on Tigon 2 boards) 1801 * 2) the frame is from the jumbo recieve ring 1802 * 3) the frame is from the standard receive ring 1803 */ 1804 1805 static void ti_rxeof(sc) 1806 struct ti_softc *sc; 1807 { 1808 struct ifnet *ifp; 1809 struct ti_cmd_desc cmd; 1810 1811 ifp = &sc->arpcom.ac_if; 1812 1813 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1814 struct ti_rx_desc *cur_rx; 1815 u_int32_t rxidx; 1816 struct ether_header *eh; 1817 struct mbuf *m = NULL; 1818 #if NVLAN > 0 1819 u_int16_t vlan_tag = 0; 1820 int have_tag = 0; 1821 #endif 1822 1823 cur_rx = 1824 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1825 rxidx = cur_rx->ti_idx; 1826 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1827 1828 #if NVLAN > 0 1829 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1830 have_tag = 1; 1831 vlan_tag = cur_rx->ti_vlan_tag; 1832 } 1833 #endif 1834 1835 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1836 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1837 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1838 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1839 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1840 ifp->if_ierrors++; 1841 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1842 continue; 1843 } 1844 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1845 ifp->if_ierrors++; 1846 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1847 continue; 1848 } 1849 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1850 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1851 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1852 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1853 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1854 ifp->if_ierrors++; 1855 ti_newbuf_mini(sc, sc->ti_mini, m); 1856 continue; 1857 } 1858 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1859 ifp->if_ierrors++; 1860 ti_newbuf_mini(sc, sc->ti_mini, m); 1861 continue; 1862 } 1863 } else { 1864 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1865 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1866 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1867 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1868 ifp->if_ierrors++; 1869 ti_newbuf_std(sc, sc->ti_std, m); 1870 continue; 1871 } 1872 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1873 ifp->if_ierrors++; 1874 ti_newbuf_std(sc, sc->ti_std, m); 1875 continue; 1876 } 1877 } 1878 1879 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1880 ifp->if_ipackets++; 1881 eh = mtod(m, struct ether_header *); 1882 m->m_pkthdr.rcvif = ifp; 1883 1884 /* Remove header from mbuf and pass it on. */ 1885 m_adj(m, sizeof(struct ether_header)); 1886 1887 if (ifp->if_hwassist) { 1888 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1889 CSUM_DATA_VALID; 1890 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1891 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1892 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1893 } 1894 1895 #if NVLAN > 0 1896 /* 1897 * If we received a packet with a vlan tag, pass it 1898 * to vlan_input() instead of ether_input(). 1899 */ 1900 if (have_tag) { 1901 vlan_input_tag(eh, m, vlan_tag); 1902 have_tag = vlan_tag = 0; 1903 continue; 1904 } 1905 #endif 1906 ether_input(ifp, eh, m); 1907 } 1908 1909 /* Only necessary on the Tigon 1. */ 1910 if (sc->ti_hwrev == TI_HWREV_TIGON) 1911 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1912 sc->ti_rx_saved_considx); 1913 1914 TI_UPDATE_STDPROD(sc, sc->ti_std); 1915 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1916 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1917 1918 return; 1919 } 1920 1921 static void ti_txeof(sc) 1922 struct ti_softc *sc; 1923 { 1924 struct ti_tx_desc *cur_tx = NULL; 1925 struct ifnet *ifp; 1926 1927 ifp = &sc->arpcom.ac_if; 1928 1929 /* 1930 * Go through our tx ring and free mbufs for those 1931 * frames that have been sent. 1932 */ 1933 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1934 u_int32_t idx = 0; 1935 1936 idx = sc->ti_tx_saved_considx; 1937 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1938 if (idx > 383) 1939 CSR_WRITE_4(sc, TI_WINBASE, 1940 TI_TX_RING_BASE + 6144); 1941 else if (idx > 255) 1942 CSR_WRITE_4(sc, TI_WINBASE, 1943 TI_TX_RING_BASE + 4096); 1944 else if (idx > 127) 1945 CSR_WRITE_4(sc, TI_WINBASE, 1946 TI_TX_RING_BASE + 2048); 1947 else 1948 CSR_WRITE_4(sc, TI_WINBASE, 1949 TI_TX_RING_BASE); 1950 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1951 } else 1952 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1953 if (cur_tx->ti_flags & TI_BDFLAG_END) 1954 ifp->if_opackets++; 1955 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1956 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1957 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1958 } 1959 sc->ti_txcnt--; 1960 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1961 ifp->if_timer = 0; 1962 } 1963 1964 if (cur_tx != NULL) 1965 ifp->if_flags &= ~IFF_OACTIVE; 1966 1967 return; 1968 } 1969 1970 static void ti_intr(xsc) 1971 void *xsc; 1972 { 1973 struct ti_softc *sc; 1974 struct ifnet *ifp; 1975 1976 sc = xsc; 1977 ifp = &sc->arpcom.ac_if; 1978 1979 #ifdef notdef 1980 /* Avoid this for now -- checking this register is expensive. */ 1981 /* Make sure this is really our interrupt. */ 1982 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1983 return; 1984 #endif 1985 1986 /* Ack interrupt and stop others from occuring. */ 1987 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1988 1989 if (ifp->if_flags & IFF_RUNNING) { 1990 /* Check RX return ring producer/consumer */ 1991 ti_rxeof(sc); 1992 1993 /* Check TX ring producer/consumer */ 1994 ti_txeof(sc); 1995 } 1996 1997 ti_handle_events(sc); 1998 1999 /* Re-enable interrupts. */ 2000 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2001 2002 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2003 ti_start(ifp); 2004 2005 return; 2006 } 2007 2008 static void ti_stats_update(sc) 2009 struct ti_softc *sc; 2010 { 2011 struct ifnet *ifp; 2012 2013 ifp = &sc->arpcom.ac_if; 2014 2015 ifp->if_collisions += 2016 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2017 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2018 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2019 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2020 ifp->if_collisions; 2021 2022 return; 2023 } 2024 2025 /* 2026 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2027 * pointers to descriptors. 2028 */ 2029 static int ti_encap(sc, m_head, txidx) 2030 struct ti_softc *sc; 2031 struct mbuf *m_head; 2032 u_int32_t *txidx; 2033 { 2034 struct ti_tx_desc *f = NULL; 2035 struct mbuf *m; 2036 u_int32_t frag, cur, cnt = 0; 2037 u_int16_t csum_flags = 0; 2038 #if NVLAN > 0 2039 struct ifvlan *ifv = NULL; 2040 2041 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2042 m_head->m_pkthdr.rcvif != NULL && 2043 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2044 ifv = m_head->m_pkthdr.rcvif->if_softc; 2045 #endif 2046 2047 m = m_head; 2048 cur = frag = *txidx; 2049 2050 if (m_head->m_pkthdr.csum_flags) { 2051 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2052 csum_flags |= TI_BDFLAG_IP_CKSUM; 2053 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2054 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2055 if (m_head->m_flags & M_LASTFRAG) 2056 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2057 else if (m_head->m_flags & M_FRAG) 2058 csum_flags |= TI_BDFLAG_IP_FRAG; 2059 } 2060 /* 2061 * Start packing the mbufs in this chain into 2062 * the fragment pointers. Stop when we run out 2063 * of fragments or hit the end of the mbuf chain. 2064 */ 2065 for (m = m_head; m != NULL; m = m->m_next) { 2066 if (m->m_len != 0) { 2067 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2068 if (frag > 383) 2069 CSR_WRITE_4(sc, TI_WINBASE, 2070 TI_TX_RING_BASE + 6144); 2071 else if (frag > 255) 2072 CSR_WRITE_4(sc, TI_WINBASE, 2073 TI_TX_RING_BASE + 4096); 2074 else if (frag > 127) 2075 CSR_WRITE_4(sc, TI_WINBASE, 2076 TI_TX_RING_BASE + 2048); 2077 else 2078 CSR_WRITE_4(sc, TI_WINBASE, 2079 TI_TX_RING_BASE); 2080 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2081 } else 2082 f = &sc->ti_rdata->ti_tx_ring[frag]; 2083 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2084 break; 2085 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2086 f->ti_len = m->m_len; 2087 f->ti_flags = csum_flags; 2088 #if NVLAN > 0 2089 if (ifv != NULL) { 2090 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2091 f->ti_vlan_tag = ifv->ifv_tag; 2092 } else { 2093 f->ti_vlan_tag = 0; 2094 } 2095 #endif 2096 /* 2097 * Sanity check: avoid coming within 16 descriptors 2098 * of the end of the ring. 2099 */ 2100 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2101 return(ENOBUFS); 2102 cur = frag; 2103 TI_INC(frag, TI_TX_RING_CNT); 2104 cnt++; 2105 } 2106 } 2107 2108 if (m != NULL) 2109 return(ENOBUFS); 2110 2111 if (frag == sc->ti_tx_saved_considx) 2112 return(ENOBUFS); 2113 2114 if (sc->ti_hwrev == TI_HWREV_TIGON) 2115 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2116 TI_BDFLAG_END; 2117 else 2118 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2119 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2120 sc->ti_txcnt += cnt; 2121 2122 *txidx = frag; 2123 2124 return(0); 2125 } 2126 2127 /* 2128 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2129 * to the mbuf data regions directly in the transmit descriptors. 2130 */ 2131 static void ti_start(ifp) 2132 struct ifnet *ifp; 2133 { 2134 struct ti_softc *sc; 2135 struct mbuf *m_head = NULL; 2136 u_int32_t prodidx = 0; 2137 2138 sc = ifp->if_softc; 2139 2140 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2141 2142 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2143 IF_DEQUEUE(&ifp->if_snd, m_head); 2144 if (m_head == NULL) 2145 break; 2146 2147 /* 2148 * XXX 2149 * safety overkill. If this is a fragmented packet chain 2150 * with delayed TCP/UDP checksums, then only encapsulate 2151 * it if we have enough descriptors to handle the entire 2152 * chain at once. 2153 * (paranoia -- may not actually be needed) 2154 */ 2155 if (m_head->m_flags & M_FIRSTFRAG && 2156 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2157 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2158 m_head->m_pkthdr.csum_data + 16) { 2159 IF_PREPEND(&ifp->if_snd, m_head); 2160 ifp->if_flags |= IFF_OACTIVE; 2161 break; 2162 } 2163 } 2164 2165 /* 2166 * Pack the data into the transmit ring. If we 2167 * don't have room, set the OACTIVE flag and wait 2168 * for the NIC to drain the ring. 2169 */ 2170 if (ti_encap(sc, m_head, &prodidx)) { 2171 IF_PREPEND(&ifp->if_snd, m_head); 2172 ifp->if_flags |= IFF_OACTIVE; 2173 break; 2174 } 2175 2176 /* 2177 * If there's a BPF listener, bounce a copy of this frame 2178 * to him. 2179 */ 2180 if (ifp->if_bpf) 2181 bpf_mtap(ifp, m_head); 2182 } 2183 2184 /* Transmit */ 2185 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2186 2187 /* 2188 * Set a timeout in case the chip goes out to lunch. 2189 */ 2190 ifp->if_timer = 5; 2191 2192 return; 2193 } 2194 2195 static void ti_init(xsc) 2196 void *xsc; 2197 { 2198 struct ti_softc *sc = xsc; 2199 int s; 2200 2201 s = splimp(); 2202 2203 /* Cancel pending I/O and flush buffers. */ 2204 ti_stop(sc); 2205 2206 /* Init the gen info block, ring control blocks and firmware. */ 2207 if (ti_gibinit(sc)) { 2208 printf("ti%d: initialization failure\n", sc->ti_unit); 2209 splx(s); 2210 return; 2211 } 2212 2213 splx(s); 2214 2215 return; 2216 } 2217 2218 static void ti_init2(sc) 2219 struct ti_softc *sc; 2220 { 2221 struct ti_cmd_desc cmd; 2222 struct ifnet *ifp; 2223 u_int16_t *m; 2224 struct ifmedia *ifm; 2225 int tmp; 2226 2227 ifp = &sc->arpcom.ac_if; 2228 2229 /* Specify MTU and interface index. */ 2230 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2231 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2232 ETHER_HDR_LEN + ETHER_CRC_LEN); 2233 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2234 2235 /* Load our MAC address. */ 2236 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2237 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2238 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2239 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2240 2241 /* Enable or disable promiscuous mode as needed. */ 2242 if (ifp->if_flags & IFF_PROMISC) { 2243 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2244 } else { 2245 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2246 } 2247 2248 /* Program multicast filter. */ 2249 ti_setmulti(sc); 2250 2251 /* 2252 * If this is a Tigon 1, we should tell the 2253 * firmware to use software packet filtering. 2254 */ 2255 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2256 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2257 } 2258 2259 /* Init RX ring. */ 2260 ti_init_rx_ring_std(sc); 2261 2262 /* Init jumbo RX ring. */ 2263 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2264 ti_init_rx_ring_jumbo(sc); 2265 2266 /* 2267 * If this is a Tigon 2, we can also configure the 2268 * mini ring. 2269 */ 2270 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2271 ti_init_rx_ring_mini(sc); 2272 2273 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2274 sc->ti_rx_saved_considx = 0; 2275 2276 /* Init TX ring. */ 2277 ti_init_tx_ring(sc); 2278 2279 /* Tell firmware we're alive. */ 2280 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2281 2282 /* Enable host interrupts. */ 2283 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2284 2285 ifp->if_flags |= IFF_RUNNING; 2286 ifp->if_flags &= ~IFF_OACTIVE; 2287 2288 /* 2289 * Make sure to set media properly. We have to do this 2290 * here since we have to issue commands in order to set 2291 * the link negotiation and we can't issue commands until 2292 * the firmware is running. 2293 */ 2294 ifm = &sc->ifmedia; 2295 tmp = ifm->ifm_media; 2296 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2297 ti_ifmedia_upd(ifp); 2298 ifm->ifm_media = tmp; 2299 2300 return; 2301 } 2302 2303 /* 2304 * Set media options. 2305 */ 2306 static int ti_ifmedia_upd(ifp) 2307 struct ifnet *ifp; 2308 { 2309 struct ti_softc *sc; 2310 struct ifmedia *ifm; 2311 struct ti_cmd_desc cmd; 2312 2313 sc = ifp->if_softc; 2314 ifm = &sc->ifmedia; 2315 2316 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2317 return(EINVAL); 2318 2319 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2320 case IFM_AUTO: 2321 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2322 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2323 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2324 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2325 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2326 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2327 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2328 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2329 break; 2330 case IFM_1000_SX: 2331 case IFM_1000_TX: 2332 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2333 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2334 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2335 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2336 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2337 } 2338 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2339 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2340 break; 2341 case IFM_100_FX: 2342 case IFM_10_FL: 2343 case IFM_100_TX: 2344 case IFM_10_T: 2345 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2346 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2347 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2348 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2349 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2350 } else { 2351 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2352 } 2353 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2354 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2355 } else { 2356 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2357 } 2358 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2359 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2360 break; 2361 } 2362 2363 return(0); 2364 } 2365 2366 /* 2367 * Report current media status. 2368 */ 2369 static void ti_ifmedia_sts(ifp, ifmr) 2370 struct ifnet *ifp; 2371 struct ifmediareq *ifmr; 2372 { 2373 struct ti_softc *sc; 2374 u_int32_t media = 0; 2375 2376 sc = ifp->if_softc; 2377 2378 ifmr->ifm_status = IFM_AVALID; 2379 ifmr->ifm_active = IFM_ETHER; 2380 2381 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2382 return; 2383 2384 ifmr->ifm_status |= IFM_ACTIVE; 2385 2386 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2387 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2388 if (sc->ti_copper) 2389 ifmr->ifm_active |= IFM_1000_TX; 2390 else 2391 ifmr->ifm_active |= IFM_1000_SX; 2392 if (media & TI_GLNK_FULL_DUPLEX) 2393 ifmr->ifm_active |= IFM_FDX; 2394 else 2395 ifmr->ifm_active |= IFM_HDX; 2396 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2397 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2398 if (sc->ti_copper) { 2399 if (media & TI_LNK_100MB) 2400 ifmr->ifm_active |= IFM_100_TX; 2401 if (media & TI_LNK_10MB) 2402 ifmr->ifm_active |= IFM_10_T; 2403 } else { 2404 if (media & TI_LNK_100MB) 2405 ifmr->ifm_active |= IFM_100_FX; 2406 if (media & TI_LNK_10MB) 2407 ifmr->ifm_active |= IFM_10_FL; 2408 } 2409 if (media & TI_LNK_FULL_DUPLEX) 2410 ifmr->ifm_active |= IFM_FDX; 2411 if (media & TI_LNK_HALF_DUPLEX) 2412 ifmr->ifm_active |= IFM_HDX; 2413 } 2414 2415 return; 2416 } 2417 2418 static int ti_ioctl(ifp, command, data) 2419 struct ifnet *ifp; 2420 u_long command; 2421 caddr_t data; 2422 { 2423 struct ti_softc *sc = ifp->if_softc; 2424 struct ifreq *ifr = (struct ifreq *) data; 2425 int s, error = 0; 2426 struct ti_cmd_desc cmd; 2427 2428 s = splimp(); 2429 2430 switch(command) { 2431 case SIOCSIFADDR: 2432 case SIOCGIFADDR: 2433 error = ether_ioctl(ifp, command, data); 2434 break; 2435 case SIOCSIFMTU: 2436 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2437 error = EINVAL; 2438 else { 2439 ifp->if_mtu = ifr->ifr_mtu; 2440 ti_init(sc); 2441 } 2442 break; 2443 case SIOCSIFFLAGS: 2444 if (ifp->if_flags & IFF_UP) { 2445 /* 2446 * If only the state of the PROMISC flag changed, 2447 * then just use the 'set promisc mode' command 2448 * instead of reinitializing the entire NIC. Doing 2449 * a full re-init means reloading the firmware and 2450 * waiting for it to start up, which may take a 2451 * second or two. 2452 */ 2453 if (ifp->if_flags & IFF_RUNNING && 2454 ifp->if_flags & IFF_PROMISC && 2455 !(sc->ti_if_flags & IFF_PROMISC)) { 2456 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2457 TI_CMD_CODE_PROMISC_ENB, 0); 2458 } else if (ifp->if_flags & IFF_RUNNING && 2459 !(ifp->if_flags & IFF_PROMISC) && 2460 sc->ti_if_flags & IFF_PROMISC) { 2461 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2462 TI_CMD_CODE_PROMISC_DIS, 0); 2463 } else 2464 ti_init(sc); 2465 } else { 2466 if (ifp->if_flags & IFF_RUNNING) { 2467 ti_stop(sc); 2468 } 2469 } 2470 sc->ti_if_flags = ifp->if_flags; 2471 error = 0; 2472 break; 2473 case SIOCADDMULTI: 2474 case SIOCDELMULTI: 2475 if (ifp->if_flags & IFF_RUNNING) { 2476 ti_setmulti(sc); 2477 error = 0; 2478 } 2479 break; 2480 case SIOCSIFMEDIA: 2481 case SIOCGIFMEDIA: 2482 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2483 break; 2484 default: 2485 error = EINVAL; 2486 break; 2487 } 2488 2489 (void)splx(s); 2490 2491 return(error); 2492 } 2493 2494 static void ti_watchdog(ifp) 2495 struct ifnet *ifp; 2496 { 2497 struct ti_softc *sc; 2498 2499 sc = ifp->if_softc; 2500 2501 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2502 ti_stop(sc); 2503 ti_init(sc); 2504 2505 ifp->if_oerrors++; 2506 2507 return; 2508 } 2509 2510 /* 2511 * Stop the adapter and free any mbufs allocated to the 2512 * RX and TX lists. 2513 */ 2514 static void ti_stop(sc) 2515 struct ti_softc *sc; 2516 { 2517 struct ifnet *ifp; 2518 struct ti_cmd_desc cmd; 2519 2520 ifp = &sc->arpcom.ac_if; 2521 2522 /* Disable host interrupts. */ 2523 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2524 /* 2525 * Tell firmware we're shutting down. 2526 */ 2527 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2528 2529 /* Halt and reinitialize. */ 2530 ti_chipinit(sc); 2531 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2532 ti_chipinit(sc); 2533 2534 /* Free the RX lists. */ 2535 ti_free_rx_ring_std(sc); 2536 2537 /* Free jumbo RX list. */ 2538 ti_free_rx_ring_jumbo(sc); 2539 2540 /* Free mini RX list. */ 2541 ti_free_rx_ring_mini(sc); 2542 2543 /* Free TX buffers. */ 2544 ti_free_tx_ring(sc); 2545 2546 sc->ti_ev_prodidx.ti_idx = 0; 2547 sc->ti_return_prodidx.ti_idx = 0; 2548 sc->ti_tx_considx.ti_idx = 0; 2549 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2550 2551 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2552 2553 return; 2554 } 2555 2556 /* 2557 * Stop all chip I/O so that the kernel's probe routines don't 2558 * get confused by errant DMAs when rebooting. 2559 */ 2560 static void ti_shutdown(dev) 2561 device_t dev; 2562 { 2563 struct ti_softc *sc; 2564 2565 sc = device_get_softc(dev); 2566 2567 ti_chipinit(sc); 2568 2569 return; 2570 } 2571