1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_types.h> 101 #include <net/if_vlan_var.h> 102 103 #include <net/bpf.h> 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 /* #define TI_PRIVATE_JUMBOS */ 118 119 #if !defined(TI_PRIVATE_JUMBOS) 120 #include <sys/sockio.h> 121 #include <sys/uio.h> 122 #include <sys/lock.h> 123 #include <vm/vm_extern.h> 124 #include <vm/pmap.h> 125 #include <vm/vm_map.h> 126 #include <vm/vm_map.h> 127 #include <vm/vm_param.h> 128 #include <vm/vm_pageout.h> 129 #include <sys/vmmeter.h> 130 #include <vm/vm_page.h> 131 #include <vm/vm_object.h> 132 #include <vm/vm_kern.h> 133 #include <sys/proc.h> 134 #include <sys/jumbo.h> 135 #endif /* !TI_PRIVATE_JUMBOS */ 136 137 #include <dev/pci/pcireg.h> 138 #include <dev/pci/pcivar.h> 139 140 #include <sys/tiio.h> 141 #include <pci/if_tireg.h> 142 #include <pci/ti_fw.h> 143 #include <pci/ti_fw2.h> 144 145 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 146 /* 147 * We can only turn on header splitting if we're using extended receive 148 * BDs. 149 */ 150 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 151 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 152 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 153 154 struct ti_softc *tis[8]; 155 156 typedef enum { 157 TI_SWAP_HTON, 158 TI_SWAP_NTOH 159 } ti_swap_type; 160 161 162 /* 163 * Various supported device vendors/types and their names. 164 */ 165 166 static struct ti_type ti_devs[] = { 167 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 170 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 171 { TC_VENDORID, TC_DEVICEID_3C985, 172 "3Com 3c985-SX Gigabit Ethernet" }, 173 { NG_VENDORID, NG_DEVICEID_GA620, 174 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 175 { NG_VENDORID, NG_DEVICEID_GA620T, 176 "Netgear GA620 1000baseT Gigabit Ethernet" }, 177 { SGI_VENDORID, SGI_DEVICEID_TIGON, 178 "Silicon Graphics Gigabit Ethernet" }, 179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 180 "Farallon PN9000SX Gigabit Ethernet" }, 181 { 0, 0, NULL } 182 }; 183 184 185 static d_open_t ti_open; 186 static d_close_t ti_close; 187 static d_ioctl_t ti_ioctl2; 188 189 static struct cdevsw ti_cdevsw = { 190 .d_version = D_VERSION, 191 .d_flags = D_NEEDGIANT, 192 .d_open = ti_open, 193 .d_close = ti_close, 194 .d_ioctl = ti_ioctl2, 195 .d_name = "ti", 196 }; 197 198 static int ti_probe (device_t); 199 static int ti_attach (device_t); 200 static int ti_detach (device_t); 201 static void ti_txeof (struct ti_softc *); 202 static void ti_rxeof (struct ti_softc *); 203 204 static void ti_stats_update (struct ti_softc *); 205 static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 206 207 static void ti_intr (void *); 208 static void ti_start (struct ifnet *); 209 static int ti_ioctl (struct ifnet *, u_long, caddr_t); 210 static void ti_init (void *); 211 static void ti_init2 (struct ti_softc *); 212 static void ti_stop (struct ti_softc *); 213 static void ti_watchdog (struct ifnet *); 214 static void ti_shutdown (device_t); 215 static int ti_ifmedia_upd (struct ifnet *); 216 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 219 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 220 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 221 222 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 223 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 224 static void ti_setmulti (struct ti_softc *); 225 226 static void ti_mem (struct ti_softc *, u_int32_t, 227 u_int32_t, caddr_t); 228 static int ti_copy_mem (struct ti_softc *, u_int32_t, 229 u_int32_t, caddr_t, int, int); 230 static int ti_copy_scratch (struct ti_softc *, u_int32_t, 231 u_int32_t, caddr_t, int, int, int); 232 static int ti_bcopy_swap (const void *, void *, size_t, 233 ti_swap_type); 234 static void ti_loadfw (struct ti_softc *); 235 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 236 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 237 caddr_t, int); 238 static void ti_handle_events (struct ti_softc *); 239 #ifdef TI_PRIVATE_JUMBOS 240 static int ti_alloc_jumbo_mem (struct ti_softc *); 241 static void *ti_jalloc (struct ti_softc *); 242 static void ti_jfree (void *, void *); 243 #endif /* TI_PRIVATE_JUMBOS */ 244 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 245 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 246 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 247 static int ti_init_rx_ring_std (struct ti_softc *); 248 static void ti_free_rx_ring_std (struct ti_softc *); 249 static int ti_init_rx_ring_jumbo (struct ti_softc *); 250 static void ti_free_rx_ring_jumbo (struct ti_softc *); 251 static int ti_init_rx_ring_mini (struct ti_softc *); 252 static void ti_free_rx_ring_mini (struct ti_softc *); 253 static void ti_free_tx_ring (struct ti_softc *); 254 static int ti_init_tx_ring (struct ti_softc *); 255 256 static int ti_64bitslot_war (struct ti_softc *); 257 static int ti_chipinit (struct ti_softc *); 258 static int ti_gibinit (struct ti_softc *); 259 260 #ifdef TI_JUMBO_HDRSPLIT 261 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 262 int pkt_len, int idx); 263 #endif /* TI_JUMBO_HDRSPLIT */ 264 265 static device_method_t ti_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, ti_probe), 268 DEVMETHOD(device_attach, ti_attach), 269 DEVMETHOD(device_detach, ti_detach), 270 DEVMETHOD(device_shutdown, ti_shutdown), 271 { 0, 0 } 272 }; 273 274 static driver_t ti_driver = { 275 "ti", 276 ti_methods, 277 sizeof(struct ti_softc) 278 }; 279 280 static devclass_t ti_devclass; 281 282 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 283 MODULE_DEPEND(ti, pci, 1, 1, 1); 284 MODULE_DEPEND(ti, ether, 1, 1, 1); 285 286 /* 287 * Send an instruction or address to the EEPROM, check for ACK. 288 */ 289 static u_int32_t ti_eeprom_putbyte(sc, byte) 290 struct ti_softc *sc; 291 int byte; 292 { 293 register int i, ack = 0; 294 295 /* 296 * Make sure we're in TX mode. 297 */ 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 299 300 /* 301 * Feed in each bit and stobe the clock. 302 */ 303 for (i = 0x80; i; i >>= 1) { 304 if (byte & i) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 306 } else { 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 308 } 309 DELAY(1); 310 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 311 DELAY(1); 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 } 314 315 /* 316 * Turn off TX mode. 317 */ 318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 319 320 /* 321 * Check for ack. 322 */ 323 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 324 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 327 return (ack); 328 } 329 330 /* 331 * Read a byte of data stored in the EEPROM at address 'addr.' 332 * We have to send two address bytes since the EEPROM can hold 333 * more than 256 bytes of data. 334 */ 335 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 336 struct ti_softc *sc; 337 int addr; 338 u_int8_t *dest; 339 { 340 register int i; 341 u_int8_t byte = 0; 342 343 EEPROM_START; 344 345 /* 346 * Send write control code to EEPROM. 347 */ 348 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 349 printf("ti%d: failed to send write command, status: %x\n", 350 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 354 /* 355 * Send first byte of address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 358 printf("ti%d: failed to send address, status: %x\n", 359 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return (1); 361 } 362 /* 363 * Send second byte address of byte we want to read. 364 */ 365 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 366 printf("ti%d: failed to send address, status: %x\n", 367 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 368 return (1); 369 } 370 371 EEPROM_STOP; 372 EEPROM_START; 373 /* 374 * Send read control code to EEPROM. 375 */ 376 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 377 printf("ti%d: failed to send read command, status: %x\n", 378 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 379 return (1); 380 } 381 382 /* 383 * Start reading bits from EEPROM. 384 */ 385 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 386 for (i = 0x80; i; i >>= 1) { 387 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 388 DELAY(1); 389 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 390 byte |= i; 391 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 392 DELAY(1); 393 } 394 395 EEPROM_STOP; 396 397 /* 398 * No ACK generated for read, so just return byte. 399 */ 400 401 *dest = byte; 402 403 return (0); 404 } 405 406 /* 407 * Read a sequence of bytes from the EEPROM. 408 */ 409 static int 410 ti_read_eeprom(sc, dest, off, cnt) 411 struct ti_softc *sc; 412 caddr_t dest; 413 int off; 414 int cnt; 415 { 416 int err = 0, i; 417 u_int8_t byte = 0; 418 419 for (i = 0; i < cnt; i++) { 420 err = ti_eeprom_getbyte(sc, off + i, &byte); 421 if (err) 422 break; 423 *(dest + i) = byte; 424 } 425 426 return (err ? 1 : 0); 427 } 428 429 /* 430 * NIC memory access function. Can be used to either clear a section 431 * of NIC local memory or (if buf is non-NULL) copy data into it. 432 */ 433 static void 434 ti_mem(sc, addr, len, buf) 435 struct ti_softc *sc; 436 u_int32_t addr, len; 437 caddr_t buf; 438 { 439 int segptr, segsize, cnt; 440 caddr_t ti_winbase, ptr; 441 442 segptr = addr; 443 cnt = len; 444 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 445 ptr = buf; 446 447 while (cnt) { 448 if (cnt < TI_WINLEN) 449 segsize = cnt; 450 else 451 segsize = TI_WINLEN - (segptr % TI_WINLEN); 452 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 453 if (buf == NULL) 454 bzero((char *)ti_winbase + (segptr & 455 (TI_WINLEN - 1)), segsize); 456 else { 457 bcopy((char *)ptr, (char *)ti_winbase + 458 (segptr & (TI_WINLEN - 1)), segsize); 459 ptr += segsize; 460 } 461 segptr += segsize; 462 cnt -= segsize; 463 } 464 } 465 466 static int 467 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 468 struct ti_softc *sc; 469 u_int32_t tigon_addr, len; 470 caddr_t buf; 471 int useraddr, readdata; 472 { 473 int segptr, segsize, cnt; 474 caddr_t ptr; 475 u_int32_t origwin; 476 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 477 int resid, segresid; 478 int first_pass; 479 480 /* 481 * At the moment, we don't handle non-aligned cases, we just bail. 482 * If this proves to be a problem, it will be fixed. 483 */ 484 if ((readdata == 0) 485 && (tigon_addr & 0x3)) { 486 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 487 "word-aligned\n", sc->ti_unit, tigon_addr); 488 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 489 "supported\n", sc->ti_unit); 490 return (EINVAL); 491 } 492 493 segptr = tigon_addr & ~0x3; 494 segresid = tigon_addr - segptr; 495 496 /* 497 * This is the non-aligned amount left over that we'll need to 498 * copy. 499 */ 500 resid = len & 0x3; 501 502 /* Add in the left over amount at the front of the buffer */ 503 resid += segresid; 504 505 cnt = len & ~0x3; 506 /* 507 * If resid + segresid is >= 4, add multiples of 4 to the count and 508 * decrease the residual by that much. 509 */ 510 cnt += resid & ~0x3; 511 resid -= resid & ~0x3; 512 513 ptr = buf; 514 515 first_pass = 1; 516 517 /* 518 * Make sure we aren't interrupted while we're changing the window 519 * pointer. 520 */ 521 TI_LOCK(sc); 522 523 /* 524 * Save the old window base value. 525 */ 526 origwin = CSR_READ_4(sc, TI_WINBASE); 527 528 while (cnt) { 529 bus_size_t ti_offset; 530 531 if (cnt < TI_WINLEN) 532 segsize = cnt; 533 else 534 segsize = TI_WINLEN - (segptr % TI_WINLEN); 535 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 536 537 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 538 539 if (readdata) { 540 541 bus_space_read_region_4(sc->ti_btag, 542 sc->ti_bhandle, ti_offset, 543 (u_int32_t *)tmparray, 544 segsize >> 2); 545 if (useraddr) { 546 /* 547 * Yeah, this is a little on the kludgy 548 * side, but at least this code is only 549 * used for debugging. 550 */ 551 ti_bcopy_swap(tmparray, tmparray2, segsize, 552 TI_SWAP_NTOH); 553 554 if (first_pass) { 555 copyout(&tmparray2[segresid], ptr, 556 segsize - segresid); 557 first_pass = 0; 558 } else 559 copyout(tmparray2, ptr, segsize); 560 } else { 561 if (first_pass) { 562 563 ti_bcopy_swap(tmparray, tmparray2, 564 segsize, TI_SWAP_NTOH); 565 bcopy(&tmparray2[segresid], ptr, 566 segsize - segresid); 567 first_pass = 0; 568 } else 569 ti_bcopy_swap(tmparray, ptr, segsize, 570 TI_SWAP_NTOH); 571 } 572 573 } else { 574 if (useraddr) { 575 copyin(ptr, tmparray2, segsize); 576 ti_bcopy_swap(tmparray2, tmparray, segsize, 577 TI_SWAP_HTON); 578 } else 579 ti_bcopy_swap(ptr, tmparray, segsize, 580 TI_SWAP_HTON); 581 582 bus_space_write_region_4(sc->ti_btag, 583 sc->ti_bhandle, ti_offset, 584 (u_int32_t *)tmparray, 585 segsize >> 2); 586 } 587 segptr += segsize; 588 ptr += segsize; 589 cnt -= segsize; 590 } 591 592 /* 593 * Handle leftover, non-word-aligned bytes. 594 */ 595 if (resid != 0) { 596 u_int32_t tmpval, tmpval2; 597 bus_size_t ti_offset; 598 599 /* 600 * Set the segment pointer. 601 */ 602 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 603 604 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 605 606 /* 607 * First, grab whatever is in our source/destination. 608 * We'll obviously need this for reads, but also for 609 * writes, since we'll be doing read/modify/write. 610 */ 611 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 612 ti_offset, &tmpval, 1); 613 614 /* 615 * Next, translate this from little-endian to big-endian 616 * (at least on i386 boxes). 617 */ 618 tmpval2 = ntohl(tmpval); 619 620 if (readdata) { 621 /* 622 * If we're reading, just copy the leftover number 623 * of bytes from the host byte order buffer to 624 * the user's buffer. 625 */ 626 if (useraddr) 627 copyout(&tmpval2, ptr, resid); 628 else 629 bcopy(&tmpval2, ptr, resid); 630 } else { 631 /* 632 * If we're writing, first copy the bytes to be 633 * written into the network byte order buffer, 634 * leaving the rest of the buffer with whatever was 635 * originally in there. Then, swap the bytes 636 * around into host order and write them out. 637 * 638 * XXX KDM the read side of this has been verified 639 * to work, but the write side of it has not been 640 * verified. So user beware. 641 */ 642 if (useraddr) 643 copyin(ptr, &tmpval2, resid); 644 else 645 bcopy(ptr, &tmpval2, resid); 646 647 tmpval = htonl(tmpval2); 648 649 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 650 ti_offset, &tmpval, 1); 651 } 652 } 653 654 CSR_WRITE_4(sc, TI_WINBASE, origwin); 655 656 TI_UNLOCK(sc); 657 658 return (0); 659 } 660 661 static int 662 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 663 struct ti_softc *sc; 664 u_int32_t tigon_addr, len; 665 caddr_t buf; 666 int useraddr, readdata; 667 int cpu; 668 { 669 u_int32_t segptr; 670 int cnt; 671 u_int32_t tmpval, tmpval2; 672 caddr_t ptr; 673 674 /* 675 * At the moment, we don't handle non-aligned cases, we just bail. 676 * If this proves to be a problem, it will be fixed. 677 */ 678 if (tigon_addr & 0x3) { 679 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 680 "word-aligned\n", sc->ti_unit, tigon_addr); 681 return (EINVAL); 682 } 683 684 if (len & 0x3) { 685 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 686 "word-aligned\n", sc->ti_unit, len); 687 return (EINVAL); 688 } 689 690 segptr = tigon_addr; 691 cnt = len; 692 ptr = buf; 693 694 TI_LOCK(sc); 695 696 while (cnt) { 697 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 698 699 if (readdata) { 700 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 701 702 tmpval = ntohl(tmpval2); 703 704 /* 705 * Note: I've used this debugging interface 706 * extensively with Alteon's 12.3.15 firmware, 707 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 708 * 709 * When you compile the firmware without 710 * optimization, which is necessary sometimes in 711 * order to properly step through it, you sometimes 712 * read out a bogus value of 0xc0017c instead of 713 * whatever was supposed to be in that scratchpad 714 * location. That value is on the stack somewhere, 715 * but I've never been able to figure out what was 716 * causing the problem. 717 * 718 * The address seems to pop up in random places, 719 * often not in the same place on two subsequent 720 * reads. 721 * 722 * In any case, the underlying data doesn't seem 723 * to be affected, just the value read out. 724 * 725 * KDM, 3/7/2000 726 */ 727 728 if (tmpval2 == 0xc0017c) 729 printf("ti%d: found 0xc0017c at %#x " 730 "(tmpval2)\n", sc->ti_unit, segptr); 731 732 if (tmpval == 0xc0017c) 733 printf("ti%d: found 0xc0017c at %#x " 734 "(tmpval)\n", sc->ti_unit, segptr); 735 736 if (useraddr) 737 copyout(&tmpval, ptr, 4); 738 else 739 bcopy(&tmpval, ptr, 4); 740 } else { 741 if (useraddr) 742 copyin(ptr, &tmpval2, 4); 743 else 744 bcopy(ptr, &tmpval2, 4); 745 746 tmpval = htonl(tmpval2); 747 748 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 749 } 750 751 cnt -= 4; 752 segptr += 4; 753 ptr += 4; 754 } 755 756 TI_UNLOCK(sc); 757 758 return (0); 759 } 760 761 static int 762 ti_bcopy_swap(src, dst, len, swap_type) 763 const void *src; 764 void *dst; 765 size_t len; 766 ti_swap_type swap_type; 767 { 768 const u_int8_t *tmpsrc; 769 u_int8_t *tmpdst; 770 size_t tmplen; 771 772 if (len & 0x3) { 773 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 774 len); 775 return (-1); 776 } 777 778 tmpsrc = src; 779 tmpdst = dst; 780 tmplen = len; 781 782 while (tmplen) { 783 if (swap_type == TI_SWAP_NTOH) 784 *(u_int32_t *)tmpdst = 785 ntohl(*(const u_int32_t *)tmpsrc); 786 else 787 *(u_int32_t *)tmpdst = 788 htonl(*(const u_int32_t *)tmpsrc); 789 790 tmpsrc += 4; 791 tmpdst += 4; 792 tmplen -= 4; 793 } 794 795 return (0); 796 } 797 798 /* 799 * Load firmware image into the NIC. Check that the firmware revision 800 * is acceptable and see if we want the firmware for the Tigon 1 or 801 * Tigon 2. 802 */ 803 static void 804 ti_loadfw(sc) 805 struct ti_softc *sc; 806 { 807 switch (sc->ti_hwrev) { 808 case TI_HWREV_TIGON: 809 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 810 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 811 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 812 printf("ti%d: firmware revision mismatch; want " 813 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 814 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 815 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 816 tigonFwReleaseMinor, tigonFwReleaseFix); 817 return; 818 } 819 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 820 (caddr_t)tigonFwText); 821 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 822 (caddr_t)tigonFwData); 823 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 824 (caddr_t)tigonFwRodata); 825 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 826 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 827 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 828 break; 829 case TI_HWREV_TIGON_II: 830 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 831 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 832 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 833 printf("ti%d: firmware revision mismatch; want " 834 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 835 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 836 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 837 tigon2FwReleaseMinor, tigon2FwReleaseFix); 838 return; 839 } 840 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 841 (caddr_t)tigon2FwText); 842 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 843 (caddr_t)tigon2FwData); 844 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 845 (caddr_t)tigon2FwRodata); 846 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 847 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 848 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 849 break; 850 default: 851 printf("ti%d: can't load firmware: unknown hardware rev\n", 852 sc->ti_unit); 853 break; 854 } 855 } 856 857 /* 858 * Send the NIC a command via the command ring. 859 */ 860 static void 861 ti_cmd(sc, cmd) 862 struct ti_softc *sc; 863 struct ti_cmd_desc *cmd; 864 { 865 u_int32_t index; 866 867 if (sc->ti_rdata->ti_cmd_ring == NULL) 868 return; 869 870 index = sc->ti_cmd_saved_prodidx; 871 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 872 TI_INC(index, TI_CMD_RING_CNT); 873 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 874 sc->ti_cmd_saved_prodidx = index; 875 } 876 877 /* 878 * Send the NIC an extended command. The 'len' parameter specifies the 879 * number of command slots to include after the initial command. 880 */ 881 static void 882 ti_cmd_ext(sc, cmd, arg, len) 883 struct ti_softc *sc; 884 struct ti_cmd_desc *cmd; 885 caddr_t arg; 886 int len; 887 { 888 u_int32_t index; 889 register int i; 890 891 if (sc->ti_rdata->ti_cmd_ring == NULL) 892 return; 893 894 index = sc->ti_cmd_saved_prodidx; 895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 896 TI_INC(index, TI_CMD_RING_CNT); 897 for (i = 0; i < len; i++) { 898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 899 *(u_int32_t *)(&arg[i * 4])); 900 TI_INC(index, TI_CMD_RING_CNT); 901 } 902 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 903 sc->ti_cmd_saved_prodidx = index; 904 } 905 906 /* 907 * Handle events that have triggered interrupts. 908 */ 909 static void 910 ti_handle_events(sc) 911 struct ti_softc *sc; 912 { 913 struct ti_event_desc *e; 914 915 if (sc->ti_rdata->ti_event_ring == NULL) 916 return; 917 918 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 919 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 920 switch (e->ti_event) { 921 case TI_EV_LINKSTAT_CHANGED: 922 sc->ti_linkstat = e->ti_code; 923 if (e->ti_code == TI_EV_CODE_LINK_UP) 924 printf("ti%d: 10/100 link up\n", sc->ti_unit); 925 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 926 printf("ti%d: gigabit link up\n", sc->ti_unit); 927 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 928 printf("ti%d: link down\n", sc->ti_unit); 929 break; 930 case TI_EV_ERROR: 931 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 932 printf("ti%d: invalid command\n", sc->ti_unit); 933 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 934 printf("ti%d: unknown command\n", sc->ti_unit); 935 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 936 printf("ti%d: bad config data\n", sc->ti_unit); 937 break; 938 case TI_EV_FIRMWARE_UP: 939 ti_init2(sc); 940 break; 941 case TI_EV_STATS_UPDATED: 942 ti_stats_update(sc); 943 break; 944 case TI_EV_RESET_JUMBO_RING: 945 case TI_EV_MCAST_UPDATED: 946 /* Who cares. */ 947 break; 948 default: 949 printf("ti%d: unknown event: %d\n", 950 sc->ti_unit, e->ti_event); 951 break; 952 } 953 /* Advance the consumer index. */ 954 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 955 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 956 } 957 } 958 959 #ifdef TI_PRIVATE_JUMBOS 960 961 /* 962 * Memory management for the jumbo receive ring is a pain in the 963 * butt. We need to allocate at least 9018 bytes of space per frame, 964 * _and_ it has to be contiguous (unless you use the extended 965 * jumbo descriptor format). Using malloc() all the time won't 966 * work: malloc() allocates memory in powers of two, which means we 967 * would end up wasting a considerable amount of space by allocating 968 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 969 * to do our own memory management. 970 * 971 * The driver needs to allocate a contiguous chunk of memory at boot 972 * time. We then chop this up ourselves into 9K pieces and use them 973 * as external mbuf storage. 974 * 975 * One issue here is how much memory to allocate. The jumbo ring has 976 * 256 slots in it, but at 9K per slot than can consume over 2MB of 977 * RAM. This is a bit much, especially considering we also need 978 * RAM for the standard ring and mini ring (on the Tigon 2). To 979 * save space, we only actually allocate enough memory for 64 slots 980 * by default, which works out to between 500 and 600K. This can 981 * be tuned by changing a #define in if_tireg.h. 982 */ 983 984 static int 985 ti_alloc_jumbo_mem(sc) 986 struct ti_softc *sc; 987 { 988 caddr_t ptr; 989 register int i; 990 struct ti_jpool_entry *entry; 991 992 /* Grab a big chunk o' storage. */ 993 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 994 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 995 996 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 997 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 998 return (ENOBUFS); 999 } 1000 1001 SLIST_INIT(&sc->ti_jfree_listhead); 1002 SLIST_INIT(&sc->ti_jinuse_listhead); 1003 1004 /* 1005 * Now divide it up into 9K pieces and save the addresses 1006 * in an array. 1007 */ 1008 ptr = sc->ti_cdata.ti_jumbo_buf; 1009 for (i = 0; i < TI_JSLOTS; i++) { 1010 sc->ti_cdata.ti_jslots[i] = ptr; 1011 ptr += TI_JLEN; 1012 entry = malloc(sizeof(struct ti_jpool_entry), 1013 M_DEVBUF, M_NOWAIT); 1014 if (entry == NULL) { 1015 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1016 M_DEVBUF); 1017 sc->ti_cdata.ti_jumbo_buf = NULL; 1018 printf("ti%d: no memory for jumbo " 1019 "buffer queue!\n", sc->ti_unit); 1020 return (ENOBUFS); 1021 } 1022 entry->slot = i; 1023 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1024 } 1025 1026 return (0); 1027 } 1028 1029 /* 1030 * Allocate a jumbo buffer. 1031 */ 1032 static void *ti_jalloc(sc) 1033 struct ti_softc *sc; 1034 { 1035 struct ti_jpool_entry *entry; 1036 1037 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1038 1039 if (entry == NULL) { 1040 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1041 return (NULL); 1042 } 1043 1044 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1045 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1046 return (sc->ti_cdata.ti_jslots[entry->slot]); 1047 } 1048 1049 /* 1050 * Release a jumbo buffer. 1051 */ 1052 static void 1053 ti_jfree(buf, args) 1054 void *buf; 1055 void *args; 1056 { 1057 struct ti_softc *sc; 1058 int i; 1059 struct ti_jpool_entry *entry; 1060 1061 /* Extract the softc struct pointer. */ 1062 sc = (struct ti_softc *)args; 1063 1064 if (sc == NULL) 1065 panic("ti_jfree: didn't get softc pointer!"); 1066 1067 /* calculate the slot this buffer belongs to */ 1068 i = ((vm_offset_t)buf 1069 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1070 1071 if ((i < 0) || (i >= TI_JSLOTS)) 1072 panic("ti_jfree: asked to free buffer that we don't manage!"); 1073 1074 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1075 if (entry == NULL) 1076 panic("ti_jfree: buffer not in use!"); 1077 entry->slot = i; 1078 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1079 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1080 } 1081 1082 #endif /* TI_PRIVATE_JUMBOS */ 1083 1084 /* 1085 * Intialize a standard receive ring descriptor. 1086 */ 1087 static int 1088 ti_newbuf_std(sc, i, m) 1089 struct ti_softc *sc; 1090 int i; 1091 struct mbuf *m; 1092 { 1093 struct mbuf *m_new = NULL; 1094 struct ti_rx_desc *r; 1095 1096 if (m == NULL) { 1097 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1098 if (m_new == NULL) 1099 return (ENOBUFS); 1100 1101 MCLGET(m_new, M_DONTWAIT); 1102 if (!(m_new->m_flags & M_EXT)) { 1103 m_freem(m_new); 1104 return (ENOBUFS); 1105 } 1106 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1107 } else { 1108 m_new = m; 1109 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1110 m_new->m_data = m_new->m_ext.ext_buf; 1111 } 1112 1113 m_adj(m_new, ETHER_ALIGN); 1114 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1115 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1116 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1117 r->ti_type = TI_BDTYPE_RECV_BD; 1118 r->ti_flags = 0; 1119 if (sc->arpcom.ac_if.if_hwassist) 1120 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1121 r->ti_len = m_new->m_len; 1122 r->ti_idx = i; 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * Intialize a mini receive ring descriptor. This only applies to 1129 * the Tigon 2. 1130 */ 1131 static int 1132 ti_newbuf_mini(sc, i, m) 1133 struct ti_softc *sc; 1134 int i; 1135 struct mbuf *m; 1136 { 1137 struct mbuf *m_new = NULL; 1138 struct ti_rx_desc *r; 1139 1140 if (m == NULL) { 1141 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1142 if (m_new == NULL) { 1143 return (ENOBUFS); 1144 } 1145 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1146 } else { 1147 m_new = m; 1148 m_new->m_data = m_new->m_pktdat; 1149 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1150 } 1151 1152 m_adj(m_new, ETHER_ALIGN); 1153 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1154 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1155 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1156 r->ti_type = TI_BDTYPE_RECV_BD; 1157 r->ti_flags = TI_BDFLAG_MINI_RING; 1158 if (sc->arpcom.ac_if.if_hwassist) 1159 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1160 r->ti_len = m_new->m_len; 1161 r->ti_idx = i; 1162 1163 return (0); 1164 } 1165 1166 #ifdef TI_PRIVATE_JUMBOS 1167 1168 /* 1169 * Initialize a jumbo receive ring descriptor. This allocates 1170 * a jumbo buffer from the pool managed internally by the driver. 1171 */ 1172 static int 1173 ti_newbuf_jumbo(sc, i, m) 1174 struct ti_softc *sc; 1175 int i; 1176 struct mbuf *m; 1177 { 1178 struct mbuf *m_new = NULL; 1179 struct ti_rx_desc *r; 1180 1181 if (m == NULL) { 1182 caddr_t *buf = NULL; 1183 1184 /* Allocate the mbuf. */ 1185 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1186 if (m_new == NULL) { 1187 return (ENOBUFS); 1188 } 1189 1190 /* Allocate the jumbo buffer */ 1191 buf = ti_jalloc(sc); 1192 if (buf == NULL) { 1193 m_freem(m_new); 1194 printf("ti%d: jumbo allocation failed " 1195 "-- packet dropped!\n", sc->ti_unit); 1196 return (ENOBUFS); 1197 } 1198 1199 /* Attach the buffer to the mbuf. */ 1200 m_new->m_data = (void *) buf; 1201 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1202 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1203 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1204 } else { 1205 m_new = m; 1206 m_new->m_data = m_new->m_ext.ext_buf; 1207 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1208 } 1209 1210 m_adj(m_new, ETHER_ALIGN); 1211 /* Set up the descriptor. */ 1212 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1213 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1214 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1215 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1216 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1217 if (sc->arpcom.ac_if.if_hwassist) 1218 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1219 r->ti_len = m_new->m_len; 1220 r->ti_idx = i; 1221 1222 return (0); 1223 } 1224 1225 #else 1226 #include <vm/vm_page.h> 1227 1228 #if (PAGE_SIZE == 4096) 1229 #define NPAYLOAD 2 1230 #else 1231 #define NPAYLOAD 1 1232 #endif 1233 1234 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1235 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1236 #define NFS_HDR_LEN (UDP_HDR_LEN) 1237 static int HDR_LEN = TCP_HDR_LEN; 1238 1239 1240 /* 1241 * Initialize a jumbo receive ring descriptor. This allocates 1242 * a jumbo buffer from the pool managed internally by the driver. 1243 */ 1244 static int 1245 ti_newbuf_jumbo(sc, idx, m_old) 1246 struct ti_softc *sc; 1247 int idx; 1248 struct mbuf *m_old; 1249 { 1250 struct mbuf *cur, *m_new = NULL; 1251 struct mbuf *m[3] = {NULL, NULL, NULL}; 1252 struct ti_rx_desc_ext *r; 1253 vm_page_t frame; 1254 /* 1 extra buf to make nobufs easy*/ 1255 caddr_t buf[3] = {NULL, NULL, NULL}; 1256 int i; 1257 1258 if (m_old != NULL) { 1259 m_new = m_old; 1260 cur = m_old->m_next; 1261 for (i = 0; i <= NPAYLOAD; i++){ 1262 m[i] = cur; 1263 cur = cur->m_next; 1264 } 1265 } else { 1266 /* Allocate the mbufs. */ 1267 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1268 if (m_new == NULL) { 1269 printf("ti%d: mbuf allocation failed " 1270 "-- packet dropped!\n", sc->ti_unit); 1271 goto nobufs; 1272 } 1273 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1274 if (m[NPAYLOAD] == NULL) { 1275 printf("ti%d: cluster mbuf allocation failed " 1276 "-- packet dropped!\n", sc->ti_unit); 1277 goto nobufs; 1278 } 1279 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1280 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1281 printf("ti%d: mbuf allocation failed " 1282 "-- packet dropped!\n", sc->ti_unit); 1283 goto nobufs; 1284 } 1285 m[NPAYLOAD]->m_len = MCLBYTES; 1286 1287 for (i = 0; i < NPAYLOAD; i++){ 1288 MGET(m[i], M_DONTWAIT, MT_DATA); 1289 if (m[i] == NULL) { 1290 printf("ti%d: mbuf allocation failed " 1291 "-- packet dropped!\n", sc->ti_unit); 1292 goto nobufs; 1293 } 1294 if (!(frame = jumbo_pg_alloc())){ 1295 printf("ti%d: buffer allocation failed " 1296 "-- packet dropped!\n", sc->ti_unit); 1297 printf(" index %d page %d\n", idx, i); 1298 goto nobufs; 1299 } 1300 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1301 } 1302 for (i = 0; i < NPAYLOAD; i++){ 1303 /* Attach the buffer to the mbuf. */ 1304 m[i]->m_data = (void *)buf[i]; 1305 m[i]->m_len = PAGE_SIZE; 1306 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1307 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1308 m[i]->m_next = m[i+1]; 1309 } 1310 /* link the buffers to the header */ 1311 m_new->m_next = m[0]; 1312 m_new->m_data += ETHER_ALIGN; 1313 if (sc->ti_hdrsplit) 1314 m_new->m_len = MHLEN - ETHER_ALIGN; 1315 else 1316 m_new->m_len = HDR_LEN; 1317 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1318 } 1319 1320 /* Set up the descriptor. */ 1321 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1322 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1323 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1324 r->ti_len0 = m_new->m_len; 1325 1326 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1327 r->ti_len1 = PAGE_SIZE; 1328 1329 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1330 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1331 1332 if (PAGE_SIZE == 4096) { 1333 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1334 r->ti_len3 = MCLBYTES; 1335 } else { 1336 r->ti_len3 = 0; 1337 } 1338 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1339 1340 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1341 1342 if (sc->arpcom.ac_if.if_hwassist) 1343 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1344 1345 r->ti_idx = idx; 1346 1347 return (0); 1348 1349 nobufs: 1350 1351 /* 1352 * Warning! : 1353 * This can only be called before the mbufs are strung together. 1354 * If the mbufs are strung together, m_freem() will free the chain, 1355 * so that the later mbufs will be freed multiple times. 1356 */ 1357 if (m_new) 1358 m_freem(m_new); 1359 1360 for (i = 0; i < 3; i++) { 1361 if (m[i]) 1362 m_freem(m[i]); 1363 if (buf[i]) 1364 jumbo_pg_free((vm_offset_t)buf[i]); 1365 } 1366 return (ENOBUFS); 1367 } 1368 #endif 1369 1370 1371 1372 /* 1373 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1374 * that's 1MB or memory, which is a lot. For now, we fill only the first 1375 * 256 ring entries and hope that our CPU is fast enough to keep up with 1376 * the NIC. 1377 */ 1378 static int 1379 ti_init_rx_ring_std(sc) 1380 struct ti_softc *sc; 1381 { 1382 register int i; 1383 struct ti_cmd_desc cmd; 1384 1385 for (i = 0; i < TI_SSLOTS; i++) { 1386 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1387 return (ENOBUFS); 1388 }; 1389 1390 TI_UPDATE_STDPROD(sc, i - 1); 1391 sc->ti_std = i - 1; 1392 1393 return (0); 1394 } 1395 1396 static void 1397 ti_free_rx_ring_std(sc) 1398 struct ti_softc *sc; 1399 { 1400 register int i; 1401 1402 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1403 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1404 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1405 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1406 } 1407 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1408 sizeof(struct ti_rx_desc)); 1409 } 1410 } 1411 1412 static int 1413 ti_init_rx_ring_jumbo(sc) 1414 struct ti_softc *sc; 1415 { 1416 register int i; 1417 struct ti_cmd_desc cmd; 1418 1419 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1420 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1421 return (ENOBUFS); 1422 }; 1423 1424 TI_UPDATE_JUMBOPROD(sc, i - 1); 1425 sc->ti_jumbo = i - 1; 1426 1427 return (0); 1428 } 1429 1430 static void 1431 ti_free_rx_ring_jumbo(sc) 1432 struct ti_softc *sc; 1433 { 1434 register int i; 1435 1436 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1437 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1438 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1439 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1440 } 1441 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1442 sizeof(struct ti_rx_desc)); 1443 } 1444 } 1445 1446 static int 1447 ti_init_rx_ring_mini(sc) 1448 struct ti_softc *sc; 1449 { 1450 register int i; 1451 1452 for (i = 0; i < TI_MSLOTS; i++) { 1453 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1454 return (ENOBUFS); 1455 }; 1456 1457 TI_UPDATE_MINIPROD(sc, i - 1); 1458 sc->ti_mini = i - 1; 1459 1460 return (0); 1461 } 1462 1463 static void 1464 ti_free_rx_ring_mini(sc) 1465 struct ti_softc *sc; 1466 { 1467 register int i; 1468 1469 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1470 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1471 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1472 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1473 } 1474 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1475 sizeof(struct ti_rx_desc)); 1476 } 1477 } 1478 1479 static void 1480 ti_free_tx_ring(sc) 1481 struct ti_softc *sc; 1482 { 1483 register int i; 1484 1485 if (sc->ti_rdata->ti_tx_ring == NULL) 1486 return; 1487 1488 for (i = 0; i < TI_TX_RING_CNT; i++) { 1489 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1490 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1491 sc->ti_cdata.ti_tx_chain[i] = NULL; 1492 } 1493 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1494 sizeof(struct ti_tx_desc)); 1495 } 1496 } 1497 1498 static int 1499 ti_init_tx_ring(sc) 1500 struct ti_softc *sc; 1501 { 1502 sc->ti_txcnt = 0; 1503 sc->ti_tx_saved_considx = 0; 1504 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1505 return (0); 1506 } 1507 1508 /* 1509 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1510 * but we have to support the old way too so that Tigon 1 cards will 1511 * work. 1512 */ 1513 static void 1514 ti_add_mcast(sc, addr) 1515 struct ti_softc *sc; 1516 struct ether_addr *addr; 1517 { 1518 struct ti_cmd_desc cmd; 1519 u_int16_t *m; 1520 u_int32_t ext[2] = {0, 0}; 1521 1522 m = (u_int16_t *)&addr->octet[0]; 1523 1524 switch (sc->ti_hwrev) { 1525 case TI_HWREV_TIGON: 1526 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1527 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1528 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1529 break; 1530 case TI_HWREV_TIGON_II: 1531 ext[0] = htons(m[0]); 1532 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1533 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1534 break; 1535 default: 1536 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1537 break; 1538 } 1539 } 1540 1541 static void 1542 ti_del_mcast(sc, addr) 1543 struct ti_softc *sc; 1544 struct ether_addr *addr; 1545 { 1546 struct ti_cmd_desc cmd; 1547 u_int16_t *m; 1548 u_int32_t ext[2] = {0, 0}; 1549 1550 m = (u_int16_t *)&addr->octet[0]; 1551 1552 switch (sc->ti_hwrev) { 1553 case TI_HWREV_TIGON: 1554 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1555 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1556 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1557 break; 1558 case TI_HWREV_TIGON_II: 1559 ext[0] = htons(m[0]); 1560 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1561 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1562 break; 1563 default: 1564 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1565 break; 1566 } 1567 } 1568 1569 /* 1570 * Configure the Tigon's multicast address filter. 1571 * 1572 * The actual multicast table management is a bit of a pain, thanks to 1573 * slight brain damage on the part of both Alteon and us. With our 1574 * multicast code, we are only alerted when the multicast address table 1575 * changes and at that point we only have the current list of addresses: 1576 * we only know the current state, not the previous state, so we don't 1577 * actually know what addresses were removed or added. The firmware has 1578 * state, but we can't get our grubby mits on it, and there is no 'delete 1579 * all multicast addresses' command. Hence, we have to maintain our own 1580 * state so we know what addresses have been programmed into the NIC at 1581 * any given time. 1582 */ 1583 static void 1584 ti_setmulti(sc) 1585 struct ti_softc *sc; 1586 { 1587 struct ifnet *ifp; 1588 struct ifmultiaddr *ifma; 1589 struct ti_cmd_desc cmd; 1590 struct ti_mc_entry *mc; 1591 u_int32_t intrs; 1592 1593 ifp = &sc->arpcom.ac_if; 1594 1595 if (ifp->if_flags & IFF_ALLMULTI) { 1596 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1597 return; 1598 } else { 1599 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1600 } 1601 1602 /* Disable interrupts. */ 1603 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1604 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1605 1606 /* First, zot all the existing filters. */ 1607 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1608 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1609 ti_del_mcast(sc, &mc->mc_addr); 1610 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1611 free(mc, M_DEVBUF); 1612 } 1613 1614 /* Now program new ones. */ 1615 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1616 if (ifma->ifma_addr->sa_family != AF_LINK) 1617 continue; 1618 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1619 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1620 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1621 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1622 ti_add_mcast(sc, &mc->mc_addr); 1623 } 1624 1625 /* Re-enable interrupts. */ 1626 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1627 } 1628 1629 /* 1630 * Check to see if the BIOS has configured us for a 64 bit slot when 1631 * we aren't actually in one. If we detect this condition, we can work 1632 * around it on the Tigon 2 by setting a bit in the PCI state register, 1633 * but for the Tigon 1 we must give up and abort the interface attach. 1634 */ 1635 static int ti_64bitslot_war(sc) 1636 struct ti_softc *sc; 1637 { 1638 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1639 CSR_WRITE_4(sc, 0x600, 0); 1640 CSR_WRITE_4(sc, 0x604, 0); 1641 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1642 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1643 if (sc->ti_hwrev == TI_HWREV_TIGON) 1644 return (EINVAL); 1645 else { 1646 TI_SETBIT(sc, TI_PCI_STATE, 1647 TI_PCISTATE_32BIT_BUS); 1648 return (0); 1649 } 1650 } 1651 } 1652 1653 return (0); 1654 } 1655 1656 /* 1657 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1658 * self-test results. 1659 */ 1660 static int 1661 ti_chipinit(sc) 1662 struct ti_softc *sc; 1663 { 1664 u_int32_t cacheline; 1665 u_int32_t pci_writemax = 0; 1666 u_int32_t hdrsplit; 1667 1668 /* Initialize link to down state. */ 1669 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1670 1671 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1672 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1673 else 1674 sc->arpcom.ac_if.if_hwassist = 0; 1675 1676 /* Set endianness before we access any non-PCI registers. */ 1677 #if BYTE_ORDER == BIG_ENDIAN 1678 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1679 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1680 #else 1681 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1682 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1683 #endif 1684 1685 /* Check the ROM failed bit to see if self-tests passed. */ 1686 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1687 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1688 return (ENODEV); 1689 } 1690 1691 /* Halt the CPU. */ 1692 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1693 1694 /* Figure out the hardware revision. */ 1695 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1696 case TI_REV_TIGON_I: 1697 sc->ti_hwrev = TI_HWREV_TIGON; 1698 break; 1699 case TI_REV_TIGON_II: 1700 sc->ti_hwrev = TI_HWREV_TIGON_II; 1701 break; 1702 default: 1703 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1704 return (ENODEV); 1705 } 1706 1707 /* Do special setup for Tigon 2. */ 1708 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1709 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1710 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1711 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1712 } 1713 1714 /* 1715 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1716 * can't do header splitting. 1717 */ 1718 #ifdef TI_JUMBO_HDRSPLIT 1719 if (sc->ti_hwrev != TI_HWREV_TIGON) 1720 sc->ti_hdrsplit = 1; 1721 else 1722 printf("ti%d: can't do header splitting on a Tigon I board\n", 1723 sc->ti_unit); 1724 #endif /* TI_JUMBO_HDRSPLIT */ 1725 1726 /* Set up the PCI state register. */ 1727 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1728 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1729 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1730 } 1731 1732 /* Clear the read/write max DMA parameters. */ 1733 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1734 TI_PCISTATE_READ_MAXDMA)); 1735 1736 /* Get cache line size. */ 1737 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1738 1739 /* 1740 * If the system has set enabled the PCI memory write 1741 * and invalidate command in the command register, set 1742 * the write max parameter accordingly. This is necessary 1743 * to use MWI with the Tigon 2. 1744 */ 1745 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1746 switch (cacheline) { 1747 case 1: 1748 case 4: 1749 case 8: 1750 case 16: 1751 case 32: 1752 case 64: 1753 break; 1754 default: 1755 /* Disable PCI memory write and invalidate. */ 1756 if (bootverbose) 1757 printf("ti%d: cache line size %d not " 1758 "supported; disabling PCI MWI\n", 1759 sc->ti_unit, cacheline); 1760 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1761 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1762 break; 1763 } 1764 } 1765 1766 #ifdef __brokenalpha__ 1767 /* 1768 * From the Alteon sample driver: 1769 * Must insure that we do not cross an 8K (bytes) boundary 1770 * for DMA reads. Our highest limit is 1K bytes. This is a 1771 * restriction on some ALPHA platforms with early revision 1772 * 21174 PCI chipsets, such as the AlphaPC 164lx 1773 */ 1774 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1775 #else 1776 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1777 #endif 1778 1779 /* This sets the min dma param all the way up (0xff). */ 1780 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1781 1782 if (sc->ti_hdrsplit) 1783 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1784 else 1785 hdrsplit = 0; 1786 1787 /* Configure DMA variables. */ 1788 #if BYTE_ORDER == BIG_ENDIAN 1789 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1790 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1791 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1792 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1793 #else /* BYTE_ORDER */ 1794 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1795 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1796 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1797 #endif /* BYTE_ORDER */ 1798 1799 /* 1800 * Only allow 1 DMA channel to be active at a time. 1801 * I don't think this is a good idea, but without it 1802 * the firmware racks up lots of nicDmaReadRingFull 1803 * errors. This is not compatible with hardware checksums. 1804 */ 1805 if (sc->arpcom.ac_if.if_hwassist == 0) 1806 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1807 1808 /* Recommended settings from Tigon manual. */ 1809 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1810 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1811 1812 if (ti_64bitslot_war(sc)) { 1813 printf("ti%d: bios thinks we're in a 64 bit slot, " 1814 "but we aren't", sc->ti_unit); 1815 return (EINVAL); 1816 } 1817 1818 return (0); 1819 } 1820 1821 /* 1822 * Initialize the general information block and firmware, and 1823 * start the CPU(s) running. 1824 */ 1825 static int 1826 ti_gibinit(sc) 1827 struct ti_softc *sc; 1828 { 1829 struct ti_rcb *rcb; 1830 int i; 1831 struct ifnet *ifp; 1832 1833 ifp = &sc->arpcom.ac_if; 1834 1835 /* Disable interrupts for now. */ 1836 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1837 1838 /* Tell the chip where to find the general information block. */ 1839 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1840 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1841 1842 /* Load the firmware into SRAM. */ 1843 ti_loadfw(sc); 1844 1845 /* Set up the contents of the general info and ring control blocks. */ 1846 1847 /* Set up the event ring and producer pointer. */ 1848 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1849 1850 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1851 rcb->ti_flags = 0; 1852 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1853 vtophys(&sc->ti_ev_prodidx); 1854 sc->ti_ev_prodidx.ti_idx = 0; 1855 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1856 sc->ti_ev_saved_considx = 0; 1857 1858 /* Set up the command ring and producer mailbox. */ 1859 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1860 1861 sc->ti_rdata->ti_cmd_ring = 1862 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1863 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1864 rcb->ti_flags = 0; 1865 rcb->ti_max_len = 0; 1866 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1867 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1868 } 1869 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1870 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1871 sc->ti_cmd_saved_prodidx = 0; 1872 1873 /* 1874 * Assign the address of the stats refresh buffer. 1875 * We re-use the current stats buffer for this to 1876 * conserve memory. 1877 */ 1878 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1879 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1880 1881 /* Set up the standard receive ring. */ 1882 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1883 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1884 rcb->ti_max_len = TI_FRAMELEN; 1885 rcb->ti_flags = 0; 1886 if (sc->arpcom.ac_if.if_hwassist) 1887 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1888 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1889 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1890 1891 /* Set up the jumbo receive ring. */ 1892 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1893 TI_HOSTADDR(rcb->ti_hostaddr) = 1894 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1895 1896 #ifdef TI_PRIVATE_JUMBOS 1897 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1898 rcb->ti_flags = 0; 1899 #else 1900 rcb->ti_max_len = PAGE_SIZE; 1901 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1902 #endif 1903 if (sc->arpcom.ac_if.if_hwassist) 1904 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1905 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1906 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1907 1908 /* 1909 * Set up the mini ring. Only activated on the 1910 * Tigon 2 but the slot in the config block is 1911 * still there on the Tigon 1. 1912 */ 1913 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1914 TI_HOSTADDR(rcb->ti_hostaddr) = 1915 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1916 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1917 if (sc->ti_hwrev == TI_HWREV_TIGON) 1918 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1919 else 1920 rcb->ti_flags = 0; 1921 if (sc->arpcom.ac_if.if_hwassist) 1922 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1923 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1924 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1925 1926 /* 1927 * Set up the receive return ring. 1928 */ 1929 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1930 TI_HOSTADDR(rcb->ti_hostaddr) = 1931 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1932 rcb->ti_flags = 0; 1933 rcb->ti_max_len = TI_RETURN_RING_CNT; 1934 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1935 vtophys(&sc->ti_return_prodidx); 1936 1937 /* 1938 * Set up the tx ring. Note: for the Tigon 2, we have the option 1939 * of putting the transmit ring in the host's address space and 1940 * letting the chip DMA it instead of leaving the ring in the NIC's 1941 * memory and accessing it through the shared memory region. We 1942 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1943 * so we have to revert to the shared memory scheme if we detect 1944 * a Tigon 1 chip. 1945 */ 1946 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1947 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1948 sc->ti_rdata->ti_tx_ring_nic = 1949 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1950 } 1951 bzero((char *)sc->ti_rdata->ti_tx_ring, 1952 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1953 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1954 if (sc->ti_hwrev == TI_HWREV_TIGON) 1955 rcb->ti_flags = 0; 1956 else 1957 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1958 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1959 if (sc->arpcom.ac_if.if_hwassist) 1960 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1961 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1962 rcb->ti_max_len = TI_TX_RING_CNT; 1963 if (sc->ti_hwrev == TI_HWREV_TIGON) 1964 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1965 else 1966 TI_HOSTADDR(rcb->ti_hostaddr) = 1967 vtophys(&sc->ti_rdata->ti_tx_ring); 1968 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1969 vtophys(&sc->ti_tx_considx); 1970 1971 /* Set up tuneables */ 1972 #if 0 1973 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1974 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1975 (sc->ti_rx_coal_ticks / 10)); 1976 else 1977 #endif 1978 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1979 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1980 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1981 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1982 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1983 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1984 1985 /* Turn interrupts on. */ 1986 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1987 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1988 1989 /* Start CPU. */ 1990 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1991 1992 return (0); 1993 } 1994 1995 /* 1996 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1997 * against our list and return its name if we find a match. 1998 */ 1999 static int 2000 ti_probe(dev) 2001 device_t dev; 2002 { 2003 struct ti_type *t; 2004 2005 t = ti_devs; 2006 2007 while (t->ti_name != NULL) { 2008 if ((pci_get_vendor(dev) == t->ti_vid) && 2009 (pci_get_device(dev) == t->ti_did)) { 2010 device_set_desc(dev, t->ti_name); 2011 return (0); 2012 } 2013 t++; 2014 } 2015 2016 return (ENXIO); 2017 } 2018 2019 static int 2020 ti_attach(dev) 2021 device_t dev; 2022 { 2023 struct ifnet *ifp; 2024 struct ti_softc *sc; 2025 int unit, error = 0, rid; 2026 2027 sc = device_get_softc(dev); 2028 unit = device_get_unit(dev); 2029 2030 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2031 MTX_DEF | MTX_RECURSE); 2032 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2033 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | 2034 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2035 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2036 2037 /* 2038 * Map control/status registers. 2039 */ 2040 pci_enable_busmaster(dev); 2041 2042 rid = TI_PCI_LOMEM; 2043 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2044 RF_ACTIVE|PCI_RF_DENSE); 2045 2046 if (sc->ti_res == NULL) { 2047 printf ("ti%d: couldn't map memory\n", unit); 2048 error = ENXIO; 2049 goto fail; 2050 } 2051 2052 sc->ti_btag = rman_get_bustag(sc->ti_res); 2053 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2054 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2055 2056 /* Allocate interrupt */ 2057 rid = 0; 2058 2059 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2060 RF_SHAREABLE | RF_ACTIVE); 2061 2062 if (sc->ti_irq == NULL) { 2063 printf("ti%d: couldn't map interrupt\n", unit); 2064 error = ENXIO; 2065 goto fail; 2066 } 2067 2068 sc->ti_unit = unit; 2069 2070 if (ti_chipinit(sc)) { 2071 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2072 error = ENXIO; 2073 goto fail; 2074 } 2075 2076 /* Zero out the NIC's on-board SRAM. */ 2077 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2078 2079 /* Init again -- zeroing memory may have clobbered some registers. */ 2080 if (ti_chipinit(sc)) { 2081 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2082 error = ENXIO; 2083 goto fail; 2084 } 2085 2086 /* 2087 * Get station address from the EEPROM. Note: the manual states 2088 * that the MAC address is at offset 0x8c, however the data is 2089 * stored as two longwords (since that's how it's loaded into 2090 * the NIC). This means the MAC address is actually preceded 2091 * by two zero bytes. We need to skip over those. 2092 */ 2093 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2094 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2095 printf("ti%d: failed to read station address\n", unit); 2096 error = ENXIO; 2097 goto fail; 2098 } 2099 2100 /* Allocate the general information block and ring buffers. */ 2101 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2102 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2103 2104 if (sc->ti_rdata == NULL) { 2105 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2106 error = ENXIO; 2107 goto fail; 2108 } 2109 2110 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2111 2112 /* Try to allocate memory for jumbo buffers. */ 2113 #ifdef TI_PRIVATE_JUMBOS 2114 if (ti_alloc_jumbo_mem(sc)) { 2115 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2116 error = ENXIO; 2117 goto fail; 2118 } 2119 #else 2120 if (!jumbo_vm_init()) { 2121 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2122 error = ENOMEM; 2123 goto fail; 2124 } 2125 #endif 2126 2127 /* 2128 * We really need a better way to tell a 1000baseTX card 2129 * from a 1000baseSX one, since in theory there could be 2130 * OEMed 1000baseTX cards from lame vendors who aren't 2131 * clever enough to change the PCI ID. For the moment 2132 * though, the AceNIC is the only copper card available. 2133 */ 2134 if (pci_get_vendor(dev) == ALT_VENDORID && 2135 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2136 sc->ti_copper = 1; 2137 /* Ok, it's not the only copper card available. */ 2138 if (pci_get_vendor(dev) == NG_VENDORID && 2139 pci_get_device(dev) == NG_DEVICEID_GA620T) 2140 sc->ti_copper = 1; 2141 2142 /* Set default tuneable values. */ 2143 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2144 #if 0 2145 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2146 #endif 2147 sc->ti_rx_coal_ticks = 170; 2148 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2149 sc->ti_rx_max_coal_bds = 64; 2150 #if 0 2151 sc->ti_tx_max_coal_bds = 128; 2152 #endif 2153 sc->ti_tx_max_coal_bds = 32; 2154 sc->ti_tx_buf_ratio = 21; 2155 2156 /* Set up ifnet structure */ 2157 ifp = &sc->arpcom.ac_if; 2158 ifp->if_softc = sc; 2159 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2160 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2161 IFF_NEEDSGIANT; 2162 tis[unit] = sc; 2163 ifp->if_ioctl = ti_ioctl; 2164 ifp->if_start = ti_start; 2165 ifp->if_watchdog = ti_watchdog; 2166 ifp->if_init = ti_init; 2167 ifp->if_mtu = ETHERMTU; 2168 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2169 2170 /* Set up ifmedia support. */ 2171 if (sc->ti_copper) { 2172 /* 2173 * Copper cards allow manual 10/100 mode selection, 2174 * but not manual 1000baseTX mode selection. Why? 2175 * Becuase currently there's no way to specify the 2176 * master/slave setting through the firmware interface, 2177 * so Alteon decided to just bag it and handle it 2178 * via autonegotiation. 2179 */ 2180 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2181 ifmedia_add(&sc->ifmedia, 2182 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2183 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2184 ifmedia_add(&sc->ifmedia, 2185 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2186 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2187 ifmedia_add(&sc->ifmedia, 2188 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2189 } else { 2190 /* Fiber cards don't support 10/100 modes. */ 2191 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2192 ifmedia_add(&sc->ifmedia, 2193 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2194 } 2195 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2196 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2197 2198 /* 2199 * We're assuming here that card initialization is a sequential 2200 * thing. If it isn't, multiple cards probing at the same time 2201 * could stomp on the list of softcs here. 2202 */ 2203 2204 /* Register the device */ 2205 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2206 0600, "ti%d", sc->ti_unit); 2207 sc->dev->si_drv1 = sc; 2208 2209 /* 2210 * Call MI attach routine. 2211 */ 2212 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2213 2214 /* Hook interrupt last to avoid having to lock softc */ 2215 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2216 ti_intr, sc, &sc->ti_intrhand); 2217 2218 if (error) { 2219 printf("ti%d: couldn't set up irq\n", unit); 2220 ether_ifdetach(ifp); 2221 goto fail; 2222 } 2223 2224 fail: 2225 if (sc && error) 2226 ti_detach(dev); 2227 2228 return (error); 2229 } 2230 2231 /* 2232 * Shutdown hardware and free up resources. This can be called any 2233 * time after the mutex has been initialized. It is called in both 2234 * the error case in attach and the normal detach case so it needs 2235 * to be careful about only freeing resources that have actually been 2236 * allocated. 2237 */ 2238 static int 2239 ti_detach(dev) 2240 device_t dev; 2241 { 2242 struct ti_softc *sc; 2243 struct ifnet *ifp; 2244 2245 sc = device_get_softc(dev); 2246 destroy_dev(sc->dev); 2247 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2248 TI_LOCK(sc); 2249 ifp = &sc->arpcom.ac_if; 2250 2251 /* These should only be active if attach succeeded */ 2252 if (device_is_attached(dev)) { 2253 ti_stop(sc); 2254 ether_ifdetach(ifp); 2255 bus_generic_detach(dev); 2256 } 2257 ifmedia_removeall(&sc->ifmedia); 2258 2259 if (sc->ti_intrhand) 2260 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2261 if (sc->ti_irq) 2262 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2263 if (sc->ti_res) { 2264 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2265 sc->ti_res); 2266 } 2267 2268 #ifdef TI_PRIVATE_JUMBOS 2269 if (sc->ti_cdata.ti_jumbo_buf) 2270 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2271 #endif 2272 if (sc->ti_rdata) 2273 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2274 2275 TI_UNLOCK(sc); 2276 mtx_destroy(&sc->ti_mtx); 2277 2278 return (0); 2279 } 2280 2281 #ifdef TI_JUMBO_HDRSPLIT 2282 /* 2283 * If hdr_len is 0, that means that header splitting wasn't done on 2284 * this packet for some reason. The two most likely reasons are that 2285 * the protocol isn't a supported protocol for splitting, or this 2286 * packet had a fragment offset that wasn't 0. 2287 * 2288 * The header length, if it is non-zero, will always be the length of 2289 * the headers on the packet, but that length could be longer than the 2290 * first mbuf. So we take the minimum of the two as the actual 2291 * length. 2292 */ 2293 static __inline void 2294 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2295 { 2296 int i = 0; 2297 int lengths[4] = {0, 0, 0, 0}; 2298 struct mbuf *m, *mp; 2299 2300 if (hdr_len != 0) 2301 top->m_len = min(hdr_len, top->m_len); 2302 pkt_len -= top->m_len; 2303 lengths[i++] = top->m_len; 2304 2305 mp = top; 2306 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2307 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2308 pkt_len -= m->m_len; 2309 lengths[i++] = m->m_len; 2310 mp = m; 2311 } 2312 2313 #if 0 2314 if (hdr_len != 0) 2315 printf("got split packet: "); 2316 else 2317 printf("got non-split packet: "); 2318 2319 printf("%d,%d,%d,%d = %d\n", lengths[0], 2320 lengths[1], lengths[2], lengths[3], 2321 lengths[0] + lengths[1] + lengths[2] + 2322 lengths[3]); 2323 #endif 2324 2325 if (pkt_len) 2326 panic("header splitting didn't"); 2327 2328 if (m) { 2329 m_freem(m); 2330 mp->m_next = NULL; 2331 2332 } 2333 if (mp->m_next != NULL) 2334 panic("ti_hdr_split: last mbuf in chain should be null"); 2335 } 2336 #endif /* TI_JUMBO_HDRSPLIT */ 2337 2338 /* 2339 * Frame reception handling. This is called if there's a frame 2340 * on the receive return list. 2341 * 2342 * Note: we have to be able to handle three possibilities here: 2343 * 1) the frame is from the mini receive ring (can only happen) 2344 * on Tigon 2 boards) 2345 * 2) the frame is from the jumbo recieve ring 2346 * 3) the frame is from the standard receive ring 2347 */ 2348 2349 static void 2350 ti_rxeof(sc) 2351 struct ti_softc *sc; 2352 { 2353 struct ifnet *ifp; 2354 struct ti_cmd_desc cmd; 2355 2356 TI_LOCK_ASSERT(sc); 2357 2358 ifp = &sc->arpcom.ac_if; 2359 2360 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2361 struct ti_rx_desc *cur_rx; 2362 u_int32_t rxidx; 2363 struct mbuf *m = NULL; 2364 u_int16_t vlan_tag = 0; 2365 int have_tag = 0; 2366 2367 cur_rx = 2368 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2369 rxidx = cur_rx->ti_idx; 2370 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2371 2372 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2373 have_tag = 1; 2374 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2375 } 2376 2377 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2378 2379 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2380 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2381 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2382 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2383 ifp->if_ierrors++; 2384 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2385 continue; 2386 } 2387 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2388 ifp->if_ierrors++; 2389 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2390 continue; 2391 } 2392 #ifdef TI_PRIVATE_JUMBOS 2393 m->m_len = cur_rx->ti_len; 2394 #else /* TI_PRIVATE_JUMBOS */ 2395 #ifdef TI_JUMBO_HDRSPLIT 2396 if (sc->ti_hdrsplit) 2397 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2398 cur_rx->ti_len, rxidx); 2399 else 2400 #endif /* TI_JUMBO_HDRSPLIT */ 2401 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2402 #endif /* TI_PRIVATE_JUMBOS */ 2403 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2404 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2405 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2406 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2407 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2408 ifp->if_ierrors++; 2409 ti_newbuf_mini(sc, sc->ti_mini, m); 2410 continue; 2411 } 2412 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2413 ifp->if_ierrors++; 2414 ti_newbuf_mini(sc, sc->ti_mini, m); 2415 continue; 2416 } 2417 m->m_len = cur_rx->ti_len; 2418 } else { 2419 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2420 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2421 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2422 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2423 ifp->if_ierrors++; 2424 ti_newbuf_std(sc, sc->ti_std, m); 2425 continue; 2426 } 2427 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2428 ifp->if_ierrors++; 2429 ti_newbuf_std(sc, sc->ti_std, m); 2430 continue; 2431 } 2432 m->m_len = cur_rx->ti_len; 2433 } 2434 2435 m->m_pkthdr.len = cur_rx->ti_len; 2436 ifp->if_ipackets++; 2437 m->m_pkthdr.rcvif = ifp; 2438 2439 if (ifp->if_hwassist) { 2440 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2441 CSUM_DATA_VALID; 2442 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2443 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2444 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2445 } 2446 2447 /* 2448 * If we received a packet with a vlan tag, 2449 * tag it before passing the packet upward. 2450 */ 2451 if (have_tag) 2452 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2453 TI_UNLOCK(sc); 2454 (*ifp->if_input)(ifp, m); 2455 TI_LOCK(sc); 2456 } 2457 2458 /* Only necessary on the Tigon 1. */ 2459 if (sc->ti_hwrev == TI_HWREV_TIGON) 2460 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2461 sc->ti_rx_saved_considx); 2462 2463 TI_UPDATE_STDPROD(sc, sc->ti_std); 2464 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2465 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2466 } 2467 2468 static void 2469 ti_txeof(sc) 2470 struct ti_softc *sc; 2471 { 2472 struct ti_tx_desc *cur_tx = NULL; 2473 struct ifnet *ifp; 2474 2475 ifp = &sc->arpcom.ac_if; 2476 2477 /* 2478 * Go through our tx ring and free mbufs for those 2479 * frames that have been sent. 2480 */ 2481 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2482 u_int32_t idx = 0; 2483 2484 idx = sc->ti_tx_saved_considx; 2485 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2486 if (idx > 383) 2487 CSR_WRITE_4(sc, TI_WINBASE, 2488 TI_TX_RING_BASE + 6144); 2489 else if (idx > 255) 2490 CSR_WRITE_4(sc, TI_WINBASE, 2491 TI_TX_RING_BASE + 4096); 2492 else if (idx > 127) 2493 CSR_WRITE_4(sc, TI_WINBASE, 2494 TI_TX_RING_BASE + 2048); 2495 else 2496 CSR_WRITE_4(sc, TI_WINBASE, 2497 TI_TX_RING_BASE); 2498 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2499 } else 2500 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2501 if (cur_tx->ti_flags & TI_BDFLAG_END) 2502 ifp->if_opackets++; 2503 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2504 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2505 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2506 } 2507 sc->ti_txcnt--; 2508 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2509 ifp->if_timer = 0; 2510 } 2511 2512 if (cur_tx != NULL) 2513 ifp->if_flags &= ~IFF_OACTIVE; 2514 } 2515 2516 static void 2517 ti_intr(xsc) 2518 void *xsc; 2519 { 2520 struct ti_softc *sc; 2521 struct ifnet *ifp; 2522 2523 sc = xsc; 2524 TI_LOCK(sc); 2525 ifp = &sc->arpcom.ac_if; 2526 2527 /*#ifdef notdef*/ 2528 /* Avoid this for now -- checking this register is expensive. */ 2529 /* Make sure this is really our interrupt. */ 2530 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2531 TI_UNLOCK(sc); 2532 return; 2533 } 2534 /*#endif*/ 2535 2536 /* Ack interrupt and stop others from occuring. */ 2537 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2538 2539 if (ifp->if_flags & IFF_RUNNING) { 2540 /* Check RX return ring producer/consumer */ 2541 ti_rxeof(sc); 2542 2543 /* Check TX ring producer/consumer */ 2544 ti_txeof(sc); 2545 } 2546 2547 ti_handle_events(sc); 2548 2549 /* Re-enable interrupts. */ 2550 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2551 2552 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2553 ti_start(ifp); 2554 2555 TI_UNLOCK(sc); 2556 } 2557 2558 static void 2559 ti_stats_update(sc) 2560 struct ti_softc *sc; 2561 { 2562 struct ifnet *ifp; 2563 2564 ifp = &sc->arpcom.ac_if; 2565 2566 ifp->if_collisions += 2567 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2568 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2569 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2570 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2571 ifp->if_collisions; 2572 } 2573 2574 /* 2575 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2576 * pointers to descriptors. 2577 */ 2578 static int 2579 ti_encap(sc, m_head, txidx) 2580 struct ti_softc *sc; 2581 struct mbuf *m_head; 2582 u_int32_t *txidx; 2583 { 2584 struct ti_tx_desc *f = NULL; 2585 struct mbuf *m; 2586 u_int32_t frag, cur, cnt = 0; 2587 u_int16_t csum_flags = 0; 2588 struct m_tag *mtag; 2589 2590 m = m_head; 2591 cur = frag = *txidx; 2592 2593 if (m_head->m_pkthdr.csum_flags) { 2594 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2595 csum_flags |= TI_BDFLAG_IP_CKSUM; 2596 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2597 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2598 if (m_head->m_flags & M_LASTFRAG) 2599 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2600 else if (m_head->m_flags & M_FRAG) 2601 csum_flags |= TI_BDFLAG_IP_FRAG; 2602 } 2603 2604 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2605 2606 /* 2607 * Start packing the mbufs in this chain into 2608 * the fragment pointers. Stop when we run out 2609 * of fragments or hit the end of the mbuf chain. 2610 */ 2611 for (m = m_head; m != NULL; m = m->m_next) { 2612 if (m->m_len != 0) { 2613 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2614 if (frag > 383) 2615 CSR_WRITE_4(sc, TI_WINBASE, 2616 TI_TX_RING_BASE + 6144); 2617 else if (frag > 255) 2618 CSR_WRITE_4(sc, TI_WINBASE, 2619 TI_TX_RING_BASE + 4096); 2620 else if (frag > 127) 2621 CSR_WRITE_4(sc, TI_WINBASE, 2622 TI_TX_RING_BASE + 2048); 2623 else 2624 CSR_WRITE_4(sc, TI_WINBASE, 2625 TI_TX_RING_BASE); 2626 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2627 } else 2628 f = &sc->ti_rdata->ti_tx_ring[frag]; 2629 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2630 break; 2631 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2632 f->ti_len = m->m_len; 2633 f->ti_flags = csum_flags; 2634 2635 if (mtag != NULL) { 2636 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2637 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2638 } else { 2639 f->ti_vlan_tag = 0; 2640 } 2641 2642 /* 2643 * Sanity check: avoid coming within 16 descriptors 2644 * of the end of the ring. 2645 */ 2646 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2647 return (ENOBUFS); 2648 cur = frag; 2649 TI_INC(frag, TI_TX_RING_CNT); 2650 cnt++; 2651 } 2652 } 2653 2654 if (m != NULL) 2655 return (ENOBUFS); 2656 2657 if (frag == sc->ti_tx_saved_considx) 2658 return (ENOBUFS); 2659 2660 if (sc->ti_hwrev == TI_HWREV_TIGON) 2661 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2662 TI_BDFLAG_END; 2663 else 2664 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2665 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2666 sc->ti_txcnt += cnt; 2667 2668 *txidx = frag; 2669 2670 return (0); 2671 } 2672 2673 /* 2674 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2675 * to the mbuf data regions directly in the transmit descriptors. 2676 */ 2677 static void 2678 ti_start(ifp) 2679 struct ifnet *ifp; 2680 { 2681 struct ti_softc *sc; 2682 struct mbuf *m_head = NULL; 2683 u_int32_t prodidx = 0; 2684 2685 sc = ifp->if_softc; 2686 TI_LOCK(sc); 2687 2688 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2689 2690 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2691 IF_DEQUEUE(&ifp->if_snd, m_head); 2692 if (m_head == NULL) 2693 break; 2694 2695 /* 2696 * XXX 2697 * safety overkill. If this is a fragmented packet chain 2698 * with delayed TCP/UDP checksums, then only encapsulate 2699 * it if we have enough descriptors to handle the entire 2700 * chain at once. 2701 * (paranoia -- may not actually be needed) 2702 */ 2703 if (m_head->m_flags & M_FIRSTFRAG && 2704 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2705 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2706 m_head->m_pkthdr.csum_data + 16) { 2707 IF_PREPEND(&ifp->if_snd, m_head); 2708 ifp->if_flags |= IFF_OACTIVE; 2709 break; 2710 } 2711 } 2712 2713 /* 2714 * Pack the data into the transmit ring. If we 2715 * don't have room, set the OACTIVE flag and wait 2716 * for the NIC to drain the ring. 2717 */ 2718 if (ti_encap(sc, m_head, &prodidx)) { 2719 IF_PREPEND(&ifp->if_snd, m_head); 2720 ifp->if_flags |= IFF_OACTIVE; 2721 break; 2722 } 2723 2724 /* 2725 * If there's a BPF listener, bounce a copy of this frame 2726 * to him. 2727 */ 2728 BPF_MTAP(ifp, m_head); 2729 } 2730 2731 /* Transmit */ 2732 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2733 2734 /* 2735 * Set a timeout in case the chip goes out to lunch. 2736 */ 2737 ifp->if_timer = 5; 2738 TI_UNLOCK(sc); 2739 } 2740 2741 static void 2742 ti_init(xsc) 2743 void *xsc; 2744 { 2745 struct ti_softc *sc = xsc; 2746 2747 /* Cancel pending I/O and flush buffers. */ 2748 ti_stop(sc); 2749 2750 TI_LOCK(sc); 2751 /* Init the gen info block, ring control blocks and firmware. */ 2752 if (ti_gibinit(sc)) { 2753 printf("ti%d: initialization failure\n", sc->ti_unit); 2754 TI_UNLOCK(sc); 2755 return; 2756 } 2757 2758 TI_UNLOCK(sc); 2759 } 2760 2761 static void ti_init2(sc) 2762 struct ti_softc *sc; 2763 { 2764 struct ti_cmd_desc cmd; 2765 struct ifnet *ifp; 2766 u_int16_t *m; 2767 struct ifmedia *ifm; 2768 int tmp; 2769 2770 ifp = &sc->arpcom.ac_if; 2771 2772 /* Specify MTU and interface index. */ 2773 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2774 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2775 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2776 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2777 2778 /* Load our MAC address. */ 2779 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2780 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2781 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2782 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2783 2784 /* Enable or disable promiscuous mode as needed. */ 2785 if (ifp->if_flags & IFF_PROMISC) { 2786 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2787 } else { 2788 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2789 } 2790 2791 /* Program multicast filter. */ 2792 ti_setmulti(sc); 2793 2794 /* 2795 * If this is a Tigon 1, we should tell the 2796 * firmware to use software packet filtering. 2797 */ 2798 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2799 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2800 } 2801 2802 /* Init RX ring. */ 2803 ti_init_rx_ring_std(sc); 2804 2805 /* Init jumbo RX ring. */ 2806 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2807 ti_init_rx_ring_jumbo(sc); 2808 2809 /* 2810 * If this is a Tigon 2, we can also configure the 2811 * mini ring. 2812 */ 2813 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2814 ti_init_rx_ring_mini(sc); 2815 2816 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2817 sc->ti_rx_saved_considx = 0; 2818 2819 /* Init TX ring. */ 2820 ti_init_tx_ring(sc); 2821 2822 /* Tell firmware we're alive. */ 2823 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2824 2825 /* Enable host interrupts. */ 2826 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2827 2828 ifp->if_flags |= IFF_RUNNING; 2829 ifp->if_flags &= ~IFF_OACTIVE; 2830 2831 /* 2832 * Make sure to set media properly. We have to do this 2833 * here since we have to issue commands in order to set 2834 * the link negotiation and we can't issue commands until 2835 * the firmware is running. 2836 */ 2837 ifm = &sc->ifmedia; 2838 tmp = ifm->ifm_media; 2839 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2840 ti_ifmedia_upd(ifp); 2841 ifm->ifm_media = tmp; 2842 } 2843 2844 /* 2845 * Set media options. 2846 */ 2847 static int 2848 ti_ifmedia_upd(ifp) 2849 struct ifnet *ifp; 2850 { 2851 struct ti_softc *sc; 2852 struct ifmedia *ifm; 2853 struct ti_cmd_desc cmd; 2854 u_int32_t flowctl; 2855 2856 sc = ifp->if_softc; 2857 ifm = &sc->ifmedia; 2858 2859 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2860 return (EINVAL); 2861 2862 flowctl = 0; 2863 2864 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2865 case IFM_AUTO: 2866 /* 2867 * Transmit flow control doesn't work on the Tigon 1. 2868 */ 2869 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2870 2871 /* 2872 * Transmit flow control can also cause problems on the 2873 * Tigon 2, apparantly with both the copper and fiber 2874 * boards. The symptom is that the interface will just 2875 * hang. This was reproduced with Alteon 180 switches. 2876 */ 2877 #if 0 2878 if (sc->ti_hwrev != TI_HWREV_TIGON) 2879 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2880 #endif 2881 2882 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2883 TI_GLNK_FULL_DUPLEX| flowctl | 2884 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2885 2886 flowctl = TI_LNK_RX_FLOWCTL_Y; 2887 #if 0 2888 if (sc->ti_hwrev != TI_HWREV_TIGON) 2889 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2890 #endif 2891 2892 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2893 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2894 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2895 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2896 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2897 break; 2898 case IFM_1000_SX: 2899 case IFM_1000_T: 2900 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2901 #if 0 2902 if (sc->ti_hwrev != TI_HWREV_TIGON) 2903 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2904 #endif 2905 2906 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2907 flowctl |TI_GLNK_ENB); 2908 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2909 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2910 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2911 } 2912 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2913 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2914 break; 2915 case IFM_100_FX: 2916 case IFM_10_FL: 2917 case IFM_100_TX: 2918 case IFM_10_T: 2919 flowctl = TI_LNK_RX_FLOWCTL_Y; 2920 #if 0 2921 if (sc->ti_hwrev != TI_HWREV_TIGON) 2922 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2923 #endif 2924 2925 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2926 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 2927 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2928 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2929 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2930 } else { 2931 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2932 } 2933 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2934 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2935 } else { 2936 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2937 } 2938 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2939 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2940 break; 2941 } 2942 2943 return (0); 2944 } 2945 2946 /* 2947 * Report current media status. 2948 */ 2949 static void 2950 ti_ifmedia_sts(ifp, ifmr) 2951 struct ifnet *ifp; 2952 struct ifmediareq *ifmr; 2953 { 2954 struct ti_softc *sc; 2955 u_int32_t media = 0; 2956 2957 sc = ifp->if_softc; 2958 2959 ifmr->ifm_status = IFM_AVALID; 2960 ifmr->ifm_active = IFM_ETHER; 2961 2962 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2963 return; 2964 2965 ifmr->ifm_status |= IFM_ACTIVE; 2966 2967 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2968 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2969 if (sc->ti_copper) 2970 ifmr->ifm_active |= IFM_1000_T; 2971 else 2972 ifmr->ifm_active |= IFM_1000_SX; 2973 if (media & TI_GLNK_FULL_DUPLEX) 2974 ifmr->ifm_active |= IFM_FDX; 2975 else 2976 ifmr->ifm_active |= IFM_HDX; 2977 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2978 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2979 if (sc->ti_copper) { 2980 if (media & TI_LNK_100MB) 2981 ifmr->ifm_active |= IFM_100_TX; 2982 if (media & TI_LNK_10MB) 2983 ifmr->ifm_active |= IFM_10_T; 2984 } else { 2985 if (media & TI_LNK_100MB) 2986 ifmr->ifm_active |= IFM_100_FX; 2987 if (media & TI_LNK_10MB) 2988 ifmr->ifm_active |= IFM_10_FL; 2989 } 2990 if (media & TI_LNK_FULL_DUPLEX) 2991 ifmr->ifm_active |= IFM_FDX; 2992 if (media & TI_LNK_HALF_DUPLEX) 2993 ifmr->ifm_active |= IFM_HDX; 2994 } 2995 } 2996 2997 static int 2998 ti_ioctl(ifp, command, data) 2999 struct ifnet *ifp; 3000 u_long command; 3001 caddr_t data; 3002 { 3003 struct ti_softc *sc = ifp->if_softc; 3004 struct ifreq *ifr = (struct ifreq *) data; 3005 int mask, error = 0; 3006 struct ti_cmd_desc cmd; 3007 3008 TI_LOCK(sc); 3009 3010 switch (command) { 3011 case SIOCSIFMTU: 3012 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3013 error = EINVAL; 3014 else { 3015 ifp->if_mtu = ifr->ifr_mtu; 3016 ti_init(sc); 3017 } 3018 break; 3019 case SIOCSIFFLAGS: 3020 if (ifp->if_flags & IFF_UP) { 3021 /* 3022 * If only the state of the PROMISC flag changed, 3023 * then just use the 'set promisc mode' command 3024 * instead of reinitializing the entire NIC. Doing 3025 * a full re-init means reloading the firmware and 3026 * waiting for it to start up, which may take a 3027 * second or two. 3028 */ 3029 if (ifp->if_flags & IFF_RUNNING && 3030 ifp->if_flags & IFF_PROMISC && 3031 !(sc->ti_if_flags & IFF_PROMISC)) { 3032 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3033 TI_CMD_CODE_PROMISC_ENB, 0); 3034 } else if (ifp->if_flags & IFF_RUNNING && 3035 !(ifp->if_flags & IFF_PROMISC) && 3036 sc->ti_if_flags & IFF_PROMISC) { 3037 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3038 TI_CMD_CODE_PROMISC_DIS, 0); 3039 } else 3040 ti_init(sc); 3041 } else { 3042 if (ifp->if_flags & IFF_RUNNING) { 3043 ti_stop(sc); 3044 } 3045 } 3046 sc->ti_if_flags = ifp->if_flags; 3047 error = 0; 3048 break; 3049 case SIOCADDMULTI: 3050 case SIOCDELMULTI: 3051 if (ifp->if_flags & IFF_RUNNING) { 3052 ti_setmulti(sc); 3053 error = 0; 3054 } 3055 break; 3056 case SIOCSIFMEDIA: 3057 case SIOCGIFMEDIA: 3058 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3059 break; 3060 case SIOCSIFCAP: 3061 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3062 if (mask & IFCAP_HWCSUM) { 3063 if (IFCAP_HWCSUM & ifp->if_capenable) 3064 ifp->if_capenable &= ~IFCAP_HWCSUM; 3065 else 3066 ifp->if_capenable |= IFCAP_HWCSUM; 3067 if (ifp->if_flags & IFF_RUNNING) 3068 ti_init(sc); 3069 } 3070 error = 0; 3071 break; 3072 default: 3073 error = ether_ioctl(ifp, command, data); 3074 break; 3075 } 3076 3077 TI_UNLOCK(sc); 3078 3079 return (error); 3080 } 3081 3082 static int 3083 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3084 { 3085 struct ti_softc *sc; 3086 3087 sc = dev->si_drv1; 3088 if (sc == NULL) 3089 return (ENODEV); 3090 3091 TI_LOCK(sc); 3092 sc->ti_flags |= TI_FLAG_DEBUGING; 3093 TI_UNLOCK(sc); 3094 3095 return (0); 3096 } 3097 3098 static int 3099 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3100 { 3101 struct ti_softc *sc; 3102 3103 sc = dev->si_drv1; 3104 if (sc == NULL) 3105 return (ENODEV); 3106 3107 TI_LOCK(sc); 3108 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3109 TI_UNLOCK(sc); 3110 3111 return (0); 3112 } 3113 3114 /* 3115 * This ioctl routine goes along with the Tigon character device. 3116 */ 3117 static int 3118 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3119 { 3120 int error; 3121 struct ti_softc *sc; 3122 3123 sc = dev->si_drv1; 3124 if (sc == NULL) 3125 return (ENODEV); 3126 3127 error = 0; 3128 3129 switch (cmd) { 3130 case TIIOCGETSTATS: 3131 { 3132 struct ti_stats *outstats; 3133 3134 outstats = (struct ti_stats *)addr; 3135 3136 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3137 sizeof(struct ti_stats)); 3138 break; 3139 } 3140 case TIIOCGETPARAMS: 3141 { 3142 struct ti_params *params; 3143 3144 params = (struct ti_params *)addr; 3145 3146 params->ti_stat_ticks = sc->ti_stat_ticks; 3147 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3148 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3149 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3150 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3151 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3152 params->param_mask = TI_PARAM_ALL; 3153 3154 error = 0; 3155 3156 break; 3157 } 3158 case TIIOCSETPARAMS: 3159 { 3160 struct ti_params *params; 3161 3162 params = (struct ti_params *)addr; 3163 3164 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3165 sc->ti_stat_ticks = params->ti_stat_ticks; 3166 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3167 } 3168 3169 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3170 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3171 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3172 sc->ti_rx_coal_ticks); 3173 } 3174 3175 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3176 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3177 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3178 sc->ti_tx_coal_ticks); 3179 } 3180 3181 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3182 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3183 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3184 sc->ti_rx_max_coal_bds); 3185 } 3186 3187 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3188 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3189 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3190 sc->ti_tx_max_coal_bds); 3191 } 3192 3193 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3194 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3195 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3196 sc->ti_tx_buf_ratio); 3197 } 3198 3199 error = 0; 3200 3201 break; 3202 } 3203 case TIIOCSETTRACE: { 3204 ti_trace_type trace_type; 3205 3206 trace_type = *(ti_trace_type *)addr; 3207 3208 /* 3209 * Set tracing to whatever the user asked for. Setting 3210 * this register to 0 should have the effect of disabling 3211 * tracing. 3212 */ 3213 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3214 3215 error = 0; 3216 3217 break; 3218 } 3219 case TIIOCGETTRACE: { 3220 struct ti_trace_buf *trace_buf; 3221 u_int32_t trace_start, cur_trace_ptr, trace_len; 3222 3223 trace_buf = (struct ti_trace_buf *)addr; 3224 3225 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3226 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3227 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3228 3229 #if 0 3230 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3231 "trace_len = %d\n", sc->ti_unit, trace_start, 3232 cur_trace_ptr, trace_len); 3233 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3234 trace_buf->buf_len); 3235 #endif 3236 3237 error = ti_copy_mem(sc, trace_start, min(trace_len, 3238 trace_buf->buf_len), 3239 (caddr_t)trace_buf->buf, 1, 1); 3240 3241 if (error == 0) { 3242 trace_buf->fill_len = min(trace_len, 3243 trace_buf->buf_len); 3244 if (cur_trace_ptr < trace_start) 3245 trace_buf->cur_trace_ptr = 3246 trace_start - cur_trace_ptr; 3247 else 3248 trace_buf->cur_trace_ptr = 3249 cur_trace_ptr - trace_start; 3250 } else 3251 trace_buf->fill_len = 0; 3252 3253 break; 3254 } 3255 3256 /* 3257 * For debugging, five ioctls are needed: 3258 * ALT_ATTACH 3259 * ALT_READ_TG_REG 3260 * ALT_WRITE_TG_REG 3261 * ALT_READ_TG_MEM 3262 * ALT_WRITE_TG_MEM 3263 */ 3264 case ALT_ATTACH: 3265 /* 3266 * From what I can tell, Alteon's Solaris Tigon driver 3267 * only has one character device, so you have to attach 3268 * to the Tigon board you're interested in. This seems 3269 * like a not-so-good way to do things, since unless you 3270 * subsequently specify the unit number of the device 3271 * you're interested in in every ioctl, you'll only be 3272 * able to debug one board at a time. 3273 */ 3274 error = 0; 3275 break; 3276 case ALT_READ_TG_MEM: 3277 case ALT_WRITE_TG_MEM: 3278 { 3279 struct tg_mem *mem_param; 3280 u_int32_t sram_end, scratch_end; 3281 3282 mem_param = (struct tg_mem *)addr; 3283 3284 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3285 sram_end = TI_END_SRAM_I; 3286 scratch_end = TI_END_SCRATCH_I; 3287 } else { 3288 sram_end = TI_END_SRAM_II; 3289 scratch_end = TI_END_SCRATCH_II; 3290 } 3291 3292 /* 3293 * For now, we'll only handle accessing regular SRAM, 3294 * nothing else. 3295 */ 3296 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3297 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3298 /* 3299 * In this instance, we always copy to/from user 3300 * space, so the user space argument is set to 1. 3301 */ 3302 error = ti_copy_mem(sc, mem_param->tgAddr, 3303 mem_param->len, 3304 mem_param->userAddr, 1, 3305 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3306 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3307 && (mem_param->tgAddr <= scratch_end)) { 3308 error = ti_copy_scratch(sc, mem_param->tgAddr, 3309 mem_param->len, 3310 mem_param->userAddr, 1, 3311 (cmd == ALT_READ_TG_MEM) ? 3312 1 : 0, TI_PROCESSOR_A); 3313 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3314 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3315 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3316 printf("ti%d: invalid memory range for " 3317 "Tigon I\n", sc->ti_unit); 3318 error = EINVAL; 3319 break; 3320 } 3321 error = ti_copy_scratch(sc, mem_param->tgAddr - 3322 TI_SCRATCH_DEBUG_OFF, 3323 mem_param->len, 3324 mem_param->userAddr, 1, 3325 (cmd == ALT_READ_TG_MEM) ? 3326 1 : 0, TI_PROCESSOR_B); 3327 } else { 3328 printf("ti%d: memory address %#x len %d is out of " 3329 "supported range\n", sc->ti_unit, 3330 mem_param->tgAddr, mem_param->len); 3331 error = EINVAL; 3332 } 3333 3334 break; 3335 } 3336 case ALT_READ_TG_REG: 3337 case ALT_WRITE_TG_REG: 3338 { 3339 struct tg_reg *regs; 3340 u_int32_t tmpval; 3341 3342 regs = (struct tg_reg *)addr; 3343 3344 /* 3345 * Make sure the address in question isn't out of range. 3346 */ 3347 if (regs->addr > TI_REG_MAX) { 3348 error = EINVAL; 3349 break; 3350 } 3351 if (cmd == ALT_READ_TG_REG) { 3352 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3353 regs->addr, &tmpval, 1); 3354 regs->data = ntohl(tmpval); 3355 #if 0 3356 if ((regs->addr == TI_CPU_STATE) 3357 || (regs->addr == TI_CPU_CTL_B)) { 3358 printf("ti%d: register %#x = %#x\n", 3359 sc->ti_unit, regs->addr, tmpval); 3360 } 3361 #endif 3362 } else { 3363 tmpval = htonl(regs->data); 3364 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3365 regs->addr, &tmpval, 1); 3366 } 3367 3368 break; 3369 } 3370 default: 3371 error = ENOTTY; 3372 break; 3373 } 3374 return (error); 3375 } 3376 3377 static void 3378 ti_watchdog(ifp) 3379 struct ifnet *ifp; 3380 { 3381 struct ti_softc *sc; 3382 3383 sc = ifp->if_softc; 3384 TI_LOCK(sc); 3385 3386 /* 3387 * When we're debugging, the chip is often stopped for long periods 3388 * of time, and that would normally cause the watchdog timer to fire. 3389 * Since that impedes debugging, we don't want to do that. 3390 */ 3391 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3392 TI_UNLOCK(sc); 3393 return; 3394 } 3395 3396 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3397 ti_stop(sc); 3398 ti_init(sc); 3399 3400 ifp->if_oerrors++; 3401 TI_UNLOCK(sc); 3402 } 3403 3404 /* 3405 * Stop the adapter and free any mbufs allocated to the 3406 * RX and TX lists. 3407 */ 3408 static void 3409 ti_stop(sc) 3410 struct ti_softc *sc; 3411 { 3412 struct ifnet *ifp; 3413 struct ti_cmd_desc cmd; 3414 3415 TI_LOCK(sc); 3416 3417 ifp = &sc->arpcom.ac_if; 3418 3419 /* Disable host interrupts. */ 3420 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3421 /* 3422 * Tell firmware we're shutting down. 3423 */ 3424 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3425 3426 /* Halt and reinitialize. */ 3427 ti_chipinit(sc); 3428 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3429 ti_chipinit(sc); 3430 3431 /* Free the RX lists. */ 3432 ti_free_rx_ring_std(sc); 3433 3434 /* Free jumbo RX list. */ 3435 ti_free_rx_ring_jumbo(sc); 3436 3437 /* Free mini RX list. */ 3438 ti_free_rx_ring_mini(sc); 3439 3440 /* Free TX buffers. */ 3441 ti_free_tx_ring(sc); 3442 3443 sc->ti_ev_prodidx.ti_idx = 0; 3444 sc->ti_return_prodidx.ti_idx = 0; 3445 sc->ti_tx_considx.ti_idx = 0; 3446 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3447 3448 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3449 TI_UNLOCK(sc); 3450 } 3451 3452 /* 3453 * Stop all chip I/O so that the kernel's probe routines don't 3454 * get confused by errant DMAs when rebooting. 3455 */ 3456 static void 3457 ti_shutdown(dev) 3458 device_t dev; 3459 { 3460 struct ti_softc *sc; 3461 3462 sc = device_get_softc(dev); 3463 TI_LOCK(sc); 3464 ti_chipinit(sc); 3465 TI_UNLOCK(sc); 3466 } 3467