1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "opt_ti.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/queue.h> 91 #include <sys/conf.h> 92 93 #include <net/if.h> 94 #include <net/if_arp.h> 95 #include <net/ethernet.h> 96 #include <net/if_dl.h> 97 #include <net/if_media.h> 98 #include <net/if_types.h> 99 #include <net/if_vlan_var.h> 100 101 #include <net/bpf.h> 102 103 #include <netinet/in_systm.h> 104 #include <netinet/in.h> 105 #include <netinet/ip.h> 106 107 #include <vm/vm.h> /* for vtophys */ 108 #include <vm/pmap.h> /* for vtophys */ 109 #include <machine/bus_memio.h> 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 /* #define TI_PRIVATE_JUMBOS */ 116 117 #if !defined(TI_PRIVATE_JUMBOS) 118 #include <sys/sockio.h> 119 #include <sys/uio.h> 120 #include <sys/lock.h> 121 #include <vm/vm_extern.h> 122 #include <vm/pmap.h> 123 #include <vm/vm_map.h> 124 #include <vm/vm_map.h> 125 #include <vm/vm_param.h> 126 #include <vm/vm_pageout.h> 127 #include <sys/vmmeter.h> 128 #include <vm/vm_page.h> 129 #include <vm/vm_object.h> 130 #include <vm/vm_kern.h> 131 #include <sys/proc.h> 132 #include <sys/jumbo.h> 133 #endif /* !TI_PRIVATE_JUMBOS */ 134 #include <sys/vnode.h> /* for vfindev, vgone */ 135 136 #include <pci/pcireg.h> 137 #include <pci/pcivar.h> 138 139 #include <sys/tiio.h> 140 #include <pci/if_tireg.h> 141 #include <pci/ti_fw.h> 142 #include <pci/ti_fw2.h> 143 144 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 145 /* 146 * We can only turn on header splitting if we're using extended receive 147 * BDs. 148 */ 149 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 150 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 151 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 152 153 #if !defined(lint) 154 static const char rcsid[] = 155 "$FreeBSD$"; 156 #endif 157 158 struct ti_softc *tis[8]; 159 160 typedef enum { 161 TI_SWAP_HTON, 162 TI_SWAP_NTOH 163 } ti_swap_type; 164 165 166 /* 167 * Various supported device vendors/types and their names. 168 */ 169 170 static struct ti_type ti_devs[] = { 171 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 172 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 173 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 174 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 175 { TC_VENDORID, TC_DEVICEID_3C985, 176 "3Com 3c985-SX Gigabit Ethernet" }, 177 { NG_VENDORID, NG_DEVICEID_GA620, 178 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 179 { NG_VENDORID, NG_DEVICEID_GA620T, 180 "Netgear GA620 1000baseT Gigabit Ethernet" }, 181 { SGI_VENDORID, SGI_DEVICEID_TIGON, 182 "Silicon Graphics Gigabit Ethernet" }, 183 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 184 "Farallon PN9000SX Gigabit Ethernet" }, 185 { 0, 0, NULL } 186 }; 187 188 #define TI_CDEV_MAJOR 153 189 190 static d_open_t ti_open; 191 static d_close_t ti_close; 192 static d_ioctl_t ti_ioctl2; 193 194 static struct cdevsw ti_cdevsw = { 195 /* open */ ti_open, 196 /* close */ ti_close, 197 /* read */ NULL, 198 /* write */ NULL, 199 /* ioctl */ ti_ioctl2, 200 /* poll */ seltrue, 201 /* mmap */ nommap, 202 /* strategy */ nostrategy, 203 /* name */ "ti", 204 /* maj */ TI_CDEV_MAJOR, 205 /* dump */ nodump, 206 /* psize */ nopsize, 207 /* flags */ 0, 208 }; 209 210 static int ti_probe (device_t); 211 static int ti_attach (device_t); 212 static int ti_detach (device_t); 213 static void ti_txeof (struct ti_softc *); 214 static void ti_rxeof (struct ti_softc *); 215 216 static void ti_stats_update (struct ti_softc *); 217 static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 218 219 static void ti_intr (void *); 220 static void ti_start (struct ifnet *); 221 static int ti_ioctl (struct ifnet *, u_long, caddr_t); 222 static void ti_init (void *); 223 static void ti_init2 (struct ti_softc *); 224 static void ti_stop (struct ti_softc *); 225 static void ti_watchdog (struct ifnet *); 226 static void ti_shutdown (device_t); 227 static int ti_ifmedia_upd (struct ifnet *); 228 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 229 230 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 231 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 232 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 233 234 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 235 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 236 static void ti_setmulti (struct ti_softc *); 237 238 static void ti_mem (struct ti_softc *, u_int32_t, 239 u_int32_t, caddr_t); 240 static int ti_copy_mem (struct ti_softc *, u_int32_t, 241 u_int32_t, caddr_t, int, int); 242 static int ti_copy_scratch (struct ti_softc *, u_int32_t, 243 u_int32_t, caddr_t, int, int, int); 244 static int ti_bcopy_swap (const void *, void *, size_t, 245 ti_swap_type); 246 static void ti_loadfw (struct ti_softc *); 247 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 248 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 249 caddr_t, int); 250 static void ti_handle_events (struct ti_softc *); 251 #ifdef TI_PRIVATE_JUMBOS 252 static int ti_alloc_jumbo_mem (struct ti_softc *); 253 static void *ti_jalloc (struct ti_softc *); 254 static void ti_jfree (void *, void *); 255 #endif /* TI_PRIVATE_JUMBOS */ 256 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 257 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 258 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 259 static int ti_init_rx_ring_std (struct ti_softc *); 260 static void ti_free_rx_ring_std (struct ti_softc *); 261 static int ti_init_rx_ring_jumbo (struct ti_softc *); 262 static void ti_free_rx_ring_jumbo (struct ti_softc *); 263 static int ti_init_rx_ring_mini (struct ti_softc *); 264 static void ti_free_rx_ring_mini (struct ti_softc *); 265 static void ti_free_tx_ring (struct ti_softc *); 266 static int ti_init_tx_ring (struct ti_softc *); 267 268 static int ti_64bitslot_war (struct ti_softc *); 269 static int ti_chipinit (struct ti_softc *); 270 static int ti_gibinit (struct ti_softc *); 271 272 #ifdef TI_JUMBO_HDRSPLIT 273 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 274 int pkt_len, int idx); 275 #endif /* TI_JUMBO_HDRSPLIT */ 276 277 static device_method_t ti_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, ti_probe), 280 DEVMETHOD(device_attach, ti_attach), 281 DEVMETHOD(device_detach, ti_detach), 282 DEVMETHOD(device_shutdown, ti_shutdown), 283 { 0, 0 } 284 }; 285 286 static driver_t ti_driver = { 287 "ti", 288 ti_methods, 289 sizeof(struct ti_softc) 290 }; 291 292 static devclass_t ti_devclass; 293 294 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 295 296 /* List of Tigon softcs */ 297 static STAILQ_HEAD(ti_softc_list, ti_softc) ti_sc_list; 298 299 static struct ti_softc * 300 ti_lookup_softc(int unit) 301 { 302 struct ti_softc *sc; 303 for (sc = STAILQ_FIRST(&ti_sc_list); sc != NULL; 304 sc = STAILQ_NEXT(sc, ti_links)) 305 if (sc->ti_unit == unit) 306 return(sc); 307 return(NULL); 308 } 309 310 /* 311 * Send an instruction or address to the EEPROM, check for ACK. 312 */ 313 static u_int32_t ti_eeprom_putbyte(sc, byte) 314 struct ti_softc *sc; 315 int byte; 316 { 317 register int i, ack = 0; 318 319 /* 320 * Make sure we're in TX mode. 321 */ 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 323 324 /* 325 * Feed in each bit and stobe the clock. 326 */ 327 for (i = 0x80; i; i >>= 1) { 328 if (byte & i) { 329 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 330 } else { 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 332 } 333 DELAY(1); 334 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 335 DELAY(1); 336 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 337 } 338 339 /* 340 * Turn off TX mode. 341 */ 342 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 343 344 /* 345 * Check for ack. 346 */ 347 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 348 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 349 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 350 351 return(ack); 352 } 353 354 /* 355 * Read a byte of data stored in the EEPROM at address 'addr.' 356 * We have to send two address bytes since the EEPROM can hold 357 * more than 256 bytes of data. 358 */ 359 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 360 struct ti_softc *sc; 361 int addr; 362 u_int8_t *dest; 363 { 364 register int i; 365 u_int8_t byte = 0; 366 367 EEPROM_START; 368 369 /* 370 * Send write control code to EEPROM. 371 */ 372 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 373 printf("ti%d: failed to send write command, status: %x\n", 374 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 375 return(1); 376 } 377 378 /* 379 * Send first byte of address of byte we want to read. 380 */ 381 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 382 printf("ti%d: failed to send address, status: %x\n", 383 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 384 return(1); 385 } 386 /* 387 * Send second byte address of byte we want to read. 388 */ 389 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 390 printf("ti%d: failed to send address, status: %x\n", 391 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 392 return(1); 393 } 394 395 EEPROM_STOP; 396 EEPROM_START; 397 /* 398 * Send read control code to EEPROM. 399 */ 400 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 401 printf("ti%d: failed to send read command, status: %x\n", 402 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 403 return(1); 404 } 405 406 /* 407 * Start reading bits from EEPROM. 408 */ 409 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 410 for (i = 0x80; i; i >>= 1) { 411 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 412 DELAY(1); 413 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 414 byte |= i; 415 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 416 DELAY(1); 417 } 418 419 EEPROM_STOP; 420 421 /* 422 * No ACK generated for read, so just return byte. 423 */ 424 425 *dest = byte; 426 427 return(0); 428 } 429 430 /* 431 * Read a sequence of bytes from the EEPROM. 432 */ 433 static int 434 ti_read_eeprom(sc, dest, off, cnt) 435 struct ti_softc *sc; 436 caddr_t dest; 437 int off; 438 int cnt; 439 { 440 int err = 0, i; 441 u_int8_t byte = 0; 442 443 for (i = 0; i < cnt; i++) { 444 err = ti_eeprom_getbyte(sc, off + i, &byte); 445 if (err) 446 break; 447 *(dest + i) = byte; 448 } 449 450 return(err ? 1 : 0); 451 } 452 453 /* 454 * NIC memory access function. Can be used to either clear a section 455 * of NIC local memory or (if buf is non-NULL) copy data into it. 456 */ 457 static void 458 ti_mem(sc, addr, len, buf) 459 struct ti_softc *sc; 460 u_int32_t addr, len; 461 caddr_t buf; 462 { 463 int segptr, segsize, cnt; 464 caddr_t ti_winbase, ptr; 465 466 segptr = addr; 467 cnt = len; 468 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 469 ptr = buf; 470 471 while(cnt) { 472 if (cnt < TI_WINLEN) 473 segsize = cnt; 474 else 475 segsize = TI_WINLEN - (segptr % TI_WINLEN); 476 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 477 if (buf == NULL) 478 bzero((char *)ti_winbase + (segptr & 479 (TI_WINLEN - 1)), segsize); 480 else { 481 bcopy((char *)ptr, (char *)ti_winbase + 482 (segptr & (TI_WINLEN - 1)), segsize); 483 ptr += segsize; 484 } 485 segptr += segsize; 486 cnt -= segsize; 487 } 488 489 return; 490 } 491 492 static int 493 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 494 struct ti_softc *sc; 495 u_int32_t tigon_addr, len; 496 caddr_t buf; 497 int useraddr, readdata; 498 { 499 int segptr, segsize, cnt; 500 caddr_t ptr; 501 u_int32_t origwin; 502 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 503 int resid, segresid; 504 int first_pass; 505 506 /* 507 * At the moment, we don't handle non-aligned cases, we just bail. 508 * If this proves to be a problem, it will be fixed. 509 */ 510 if ((readdata == 0) 511 && (tigon_addr & 0x3)) { 512 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 513 "word-aligned\n", sc->ti_unit, tigon_addr); 514 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 515 "supported\n", sc->ti_unit); 516 return(EINVAL); 517 } 518 519 segptr = tigon_addr & ~0x3; 520 segresid = tigon_addr - segptr; 521 522 /* 523 * This is the non-aligned amount left over that we'll need to 524 * copy. 525 */ 526 resid = len & 0x3; 527 528 /* Add in the left over amount at the front of the buffer */ 529 resid += segresid; 530 531 cnt = len & ~0x3; 532 /* 533 * If resid + segresid is >= 4, add multiples of 4 to the count and 534 * decrease the residual by that much. 535 */ 536 cnt += resid & ~0x3; 537 resid -= resid & ~0x3; 538 539 ptr = buf; 540 541 first_pass = 1; 542 543 /* 544 * Make sure we aren't interrupted while we're changing the window 545 * pointer. 546 */ 547 TI_LOCK(sc); 548 549 /* 550 * Save the old window base value. 551 */ 552 origwin = CSR_READ_4(sc, TI_WINBASE); 553 554 while(cnt) { 555 bus_size_t ti_offset; 556 557 if (cnt < TI_WINLEN) 558 segsize = cnt; 559 else 560 segsize = TI_WINLEN - (segptr % TI_WINLEN); 561 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 562 563 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 564 565 if (readdata) { 566 567 bus_space_read_region_4(sc->ti_btag, 568 sc->ti_bhandle, ti_offset, 569 (u_int32_t *)tmparray, 570 segsize >> 2); 571 if (useraddr) { 572 /* 573 * Yeah, this is a little on the kludgy 574 * side, but at least this code is only 575 * used for debugging. 576 */ 577 ti_bcopy_swap(tmparray, tmparray2, segsize, 578 TI_SWAP_NTOH); 579 580 if (first_pass) { 581 copyout(&tmparray2[segresid], ptr, 582 segsize - segresid); 583 first_pass = 0; 584 } else 585 copyout(tmparray2, ptr, segsize); 586 } else { 587 if (first_pass) { 588 589 ti_bcopy_swap(tmparray, tmparray2, 590 segsize, TI_SWAP_NTOH); 591 bcopy(&tmparray2[segresid], ptr, 592 segsize - segresid); 593 first_pass = 0; 594 } else 595 ti_bcopy_swap(tmparray, ptr, segsize, 596 TI_SWAP_NTOH); 597 } 598 599 } else { 600 if (useraddr) { 601 copyin(ptr, tmparray2, segsize); 602 ti_bcopy_swap(tmparray2, tmparray, segsize, 603 TI_SWAP_HTON); 604 } else 605 ti_bcopy_swap(ptr, tmparray, segsize, 606 TI_SWAP_HTON); 607 608 bus_space_write_region_4(sc->ti_btag, 609 sc->ti_bhandle, ti_offset, 610 (u_int32_t *)tmparray, 611 segsize >> 2); 612 } 613 segptr += segsize; 614 ptr += segsize; 615 cnt -= segsize; 616 } 617 618 /* 619 * Handle leftover, non-word-aligned bytes. 620 */ 621 if (resid != 0) { 622 u_int32_t tmpval, tmpval2; 623 bus_size_t ti_offset; 624 625 /* 626 * Set the segment pointer. 627 */ 628 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 629 630 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 631 632 /* 633 * First, grab whatever is in our source/destination. 634 * We'll obviously need this for reads, but also for 635 * writes, since we'll be doing read/modify/write. 636 */ 637 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 638 ti_offset, &tmpval, 1); 639 640 /* 641 * Next, translate this from little-endian to big-endian 642 * (at least on i386 boxes). 643 */ 644 tmpval2 = ntohl(tmpval); 645 646 if (readdata) { 647 /* 648 * If we're reading, just copy the leftover number 649 * of bytes from the host byte order buffer to 650 * the user's buffer. 651 */ 652 if (useraddr) 653 copyout(&tmpval2, ptr, resid); 654 else 655 bcopy(&tmpval2, ptr, resid); 656 } else { 657 /* 658 * If we're writing, first copy the bytes to be 659 * written into the network byte order buffer, 660 * leaving the rest of the buffer with whatever was 661 * originally in there. Then, swap the bytes 662 * around into host order and write them out. 663 * 664 * XXX KDM the read side of this has been verified 665 * to work, but the write side of it has not been 666 * verified. So user beware. 667 */ 668 if (useraddr) 669 copyin(ptr, &tmpval2, resid); 670 else 671 bcopy(ptr, &tmpval2, resid); 672 673 tmpval = htonl(tmpval2); 674 675 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 676 ti_offset, &tmpval, 1); 677 } 678 } 679 680 CSR_WRITE_4(sc, TI_WINBASE, origwin); 681 682 TI_UNLOCK(sc); 683 684 return(0); 685 } 686 687 static int 688 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 689 struct ti_softc *sc; 690 u_int32_t tigon_addr, len; 691 caddr_t buf; 692 int useraddr, readdata; 693 int cpu; 694 { 695 u_int32_t segptr; 696 int cnt; 697 u_int32_t tmpval, tmpval2; 698 caddr_t ptr; 699 700 /* 701 * At the moment, we don't handle non-aligned cases, we just bail. 702 * If this proves to be a problem, it will be fixed. 703 */ 704 if (tigon_addr & 0x3) { 705 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 706 "word-aligned\n", sc->ti_unit, tigon_addr); 707 return(EINVAL); 708 } 709 710 if (len & 0x3) { 711 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 712 "word-aligned\n", sc->ti_unit, len); 713 return(EINVAL); 714 } 715 716 segptr = tigon_addr; 717 cnt = len; 718 ptr = buf; 719 720 TI_LOCK(sc); 721 722 while (cnt) { 723 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 724 725 if (readdata) { 726 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 727 728 tmpval = ntohl(tmpval2); 729 730 /* 731 * Note: I've used this debugging interface 732 * extensively with Alteon's 12.3.15 firmware, 733 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 734 * 735 * When you compile the firmware without 736 * optimization, which is necessary sometimes in 737 * order to properly step through it, you sometimes 738 * read out a bogus value of 0xc0017c instead of 739 * whatever was supposed to be in that scratchpad 740 * location. That value is on the stack somewhere, 741 * but I've never been able to figure out what was 742 * causing the problem. 743 * 744 * The address seems to pop up in random places, 745 * often not in the same place on two subsequent 746 * reads. 747 * 748 * In any case, the underlying data doesn't seem 749 * to be affected, just the value read out. 750 * 751 * KDM, 3/7/2000 752 */ 753 754 if (tmpval2 == 0xc0017c) 755 printf("ti%d: found 0xc0017c at %#x " 756 "(tmpval2)\n", sc->ti_unit, segptr); 757 758 if (tmpval == 0xc0017c) 759 printf("ti%d: found 0xc0017c at %#x " 760 "(tmpval)\n", sc->ti_unit, segptr); 761 762 if (useraddr) 763 copyout(&tmpval, ptr, 4); 764 else 765 bcopy(&tmpval, ptr, 4); 766 } else { 767 if (useraddr) 768 copyin(ptr, &tmpval2, 4); 769 else 770 bcopy(ptr, &tmpval2, 4); 771 772 tmpval = htonl(tmpval2); 773 774 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 775 } 776 777 cnt -= 4; 778 segptr += 4; 779 ptr += 4; 780 } 781 782 TI_UNLOCK(sc); 783 784 return(0); 785 } 786 787 static int 788 ti_bcopy_swap(src, dst, len, swap_type) 789 const void *src; 790 void *dst; 791 size_t len; 792 ti_swap_type swap_type; 793 { 794 const u_int8_t *tmpsrc; 795 u_int8_t *tmpdst; 796 size_t tmplen; 797 798 if (len & 0x3) { 799 printf("ti_bcopy_swap: length %d isn't 32-bit aligned\n", 800 len); 801 return(-1); 802 } 803 804 tmpsrc = src; 805 tmpdst = dst; 806 tmplen = len; 807 808 while (tmplen) { 809 if (swap_type == TI_SWAP_NTOH) 810 *(u_int32_t *)tmpdst = 811 ntohl(*(const u_int32_t *)tmpsrc); 812 else 813 *(u_int32_t *)tmpdst = 814 htonl(*(const u_int32_t *)tmpsrc); 815 816 tmpsrc += 4; 817 tmpdst += 4; 818 tmplen -= 4; 819 } 820 821 return(0); 822 } 823 824 /* 825 * Load firmware image into the NIC. Check that the firmware revision 826 * is acceptable and see if we want the firmware for the Tigon 1 or 827 * Tigon 2. 828 */ 829 static void 830 ti_loadfw(sc) 831 struct ti_softc *sc; 832 { 833 switch(sc->ti_hwrev) { 834 case TI_HWREV_TIGON: 835 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 836 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 837 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 838 printf("ti%d: firmware revision mismatch; want " 839 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 840 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 841 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 842 tigonFwReleaseMinor, tigonFwReleaseFix); 843 return; 844 } 845 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 846 (caddr_t)tigonFwText); 847 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 848 (caddr_t)tigonFwData); 849 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 850 (caddr_t)tigonFwRodata); 851 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 852 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 853 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 854 break; 855 case TI_HWREV_TIGON_II: 856 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 857 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 858 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 859 printf("ti%d: firmware revision mismatch; want " 860 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 861 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 862 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 863 tigon2FwReleaseMinor, tigon2FwReleaseFix); 864 return; 865 } 866 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 867 (caddr_t)tigon2FwText); 868 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 869 (caddr_t)tigon2FwData); 870 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 871 (caddr_t)tigon2FwRodata); 872 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 873 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 874 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 875 break; 876 default: 877 printf("ti%d: can't load firmware: unknown hardware rev\n", 878 sc->ti_unit); 879 break; 880 } 881 882 return; 883 } 884 885 /* 886 * Send the NIC a command via the command ring. 887 */ 888 static void 889 ti_cmd(sc, cmd) 890 struct ti_softc *sc; 891 struct ti_cmd_desc *cmd; 892 { 893 u_int32_t index; 894 895 if (sc->ti_rdata->ti_cmd_ring == NULL) 896 return; 897 898 index = sc->ti_cmd_saved_prodidx; 899 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 900 TI_INC(index, TI_CMD_RING_CNT); 901 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 902 sc->ti_cmd_saved_prodidx = index; 903 904 return; 905 } 906 907 /* 908 * Send the NIC an extended command. The 'len' parameter specifies the 909 * number of command slots to include after the initial command. 910 */ 911 static void 912 ti_cmd_ext(sc, cmd, arg, len) 913 struct ti_softc *sc; 914 struct ti_cmd_desc *cmd; 915 caddr_t arg; 916 int len; 917 { 918 u_int32_t index; 919 register int i; 920 921 if (sc->ti_rdata->ti_cmd_ring == NULL) 922 return; 923 924 index = sc->ti_cmd_saved_prodidx; 925 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 926 TI_INC(index, TI_CMD_RING_CNT); 927 for (i = 0; i < len; i++) { 928 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 929 *(u_int32_t *)(&arg[i * 4])); 930 TI_INC(index, TI_CMD_RING_CNT); 931 } 932 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 933 sc->ti_cmd_saved_prodidx = index; 934 935 return; 936 } 937 938 /* 939 * Handle events that have triggered interrupts. 940 */ 941 static void 942 ti_handle_events(sc) 943 struct ti_softc *sc; 944 { 945 struct ti_event_desc *e; 946 947 if (sc->ti_rdata->ti_event_ring == NULL) 948 return; 949 950 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 951 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 952 switch(e->ti_event) { 953 case TI_EV_LINKSTAT_CHANGED: 954 sc->ti_linkstat = e->ti_code; 955 if (e->ti_code == TI_EV_CODE_LINK_UP) 956 printf("ti%d: 10/100 link up\n", sc->ti_unit); 957 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 958 printf("ti%d: gigabit link up\n", sc->ti_unit); 959 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 960 printf("ti%d: link down\n", sc->ti_unit); 961 break; 962 case TI_EV_ERROR: 963 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 964 printf("ti%d: invalid command\n", sc->ti_unit); 965 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 966 printf("ti%d: unknown command\n", sc->ti_unit); 967 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 968 printf("ti%d: bad config data\n", sc->ti_unit); 969 break; 970 case TI_EV_FIRMWARE_UP: 971 ti_init2(sc); 972 break; 973 case TI_EV_STATS_UPDATED: 974 ti_stats_update(sc); 975 break; 976 case TI_EV_RESET_JUMBO_RING: 977 case TI_EV_MCAST_UPDATED: 978 /* Who cares. */ 979 break; 980 default: 981 printf("ti%d: unknown event: %d\n", 982 sc->ti_unit, e->ti_event); 983 break; 984 } 985 /* Advance the consumer index. */ 986 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 987 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 988 } 989 990 return; 991 } 992 993 #ifdef TI_PRIVATE_JUMBOS 994 995 /* 996 * Memory management for the jumbo receive ring is a pain in the 997 * butt. We need to allocate at least 9018 bytes of space per frame, 998 * _and_ it has to be contiguous (unless you use the extended 999 * jumbo descriptor format). Using malloc() all the time won't 1000 * work: malloc() allocates memory in powers of two, which means we 1001 * would end up wasting a considerable amount of space by allocating 1002 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1003 * to do our own memory management. 1004 * 1005 * The driver needs to allocate a contiguous chunk of memory at boot 1006 * time. We then chop this up ourselves into 9K pieces and use them 1007 * as external mbuf storage. 1008 * 1009 * One issue here is how much memory to allocate. The jumbo ring has 1010 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1011 * RAM. This is a bit much, especially considering we also need 1012 * RAM for the standard ring and mini ring (on the Tigon 2). To 1013 * save space, we only actually allocate enough memory for 64 slots 1014 * by default, which works out to between 500 and 600K. This can 1015 * be tuned by changing a #define in if_tireg.h. 1016 */ 1017 1018 static int 1019 ti_alloc_jumbo_mem(sc) 1020 struct ti_softc *sc; 1021 { 1022 caddr_t ptr; 1023 register int i; 1024 struct ti_jpool_entry *entry; 1025 1026 /* Grab a big chunk o' storage. */ 1027 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1028 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1029 1030 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1031 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1032 return(ENOBUFS); 1033 } 1034 1035 SLIST_INIT(&sc->ti_jfree_listhead); 1036 SLIST_INIT(&sc->ti_jinuse_listhead); 1037 1038 /* 1039 * Now divide it up into 9K pieces and save the addresses 1040 * in an array. 1041 */ 1042 ptr = sc->ti_cdata.ti_jumbo_buf; 1043 for (i = 0; i < TI_JSLOTS; i++) { 1044 sc->ti_cdata.ti_jslots[i] = ptr; 1045 ptr += TI_JLEN; 1046 entry = malloc(sizeof(struct ti_jpool_entry), 1047 M_DEVBUF, M_NOWAIT); 1048 if (entry == NULL) { 1049 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1050 M_DEVBUF); 1051 sc->ti_cdata.ti_jumbo_buf = NULL; 1052 printf("ti%d: no memory for jumbo " 1053 "buffer queue!\n", sc->ti_unit); 1054 return(ENOBUFS); 1055 } 1056 entry->slot = i; 1057 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1058 } 1059 1060 return(0); 1061 } 1062 1063 /* 1064 * Allocate a jumbo buffer. 1065 */ 1066 static void *ti_jalloc(sc) 1067 struct ti_softc *sc; 1068 { 1069 struct ti_jpool_entry *entry; 1070 1071 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1072 1073 if (entry == NULL) { 1074 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1075 return(NULL); 1076 } 1077 1078 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1079 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1080 return(sc->ti_cdata.ti_jslots[entry->slot]); 1081 } 1082 1083 /* 1084 * Release a jumbo buffer. 1085 */ 1086 static void 1087 ti_jfree(buf, args) 1088 void *buf; 1089 void *args; 1090 { 1091 struct ti_softc *sc; 1092 int i; 1093 struct ti_jpool_entry *entry; 1094 1095 /* Extract the softc struct pointer. */ 1096 sc = (struct ti_softc *)args; 1097 1098 if (sc == NULL) 1099 panic("ti_jfree: didn't get softc pointer!"); 1100 1101 /* calculate the slot this buffer belongs to */ 1102 i = ((vm_offset_t)buf 1103 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1104 1105 if ((i < 0) || (i >= TI_JSLOTS)) 1106 panic("ti_jfree: asked to free buffer that we don't manage!"); 1107 1108 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1109 if (entry == NULL) 1110 panic("ti_jfree: buffer not in use!"); 1111 entry->slot = i; 1112 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1113 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1114 1115 return; 1116 } 1117 1118 #endif /* TI_PRIVATE_JUMBOS */ 1119 1120 /* 1121 * Intialize a standard receive ring descriptor. 1122 */ 1123 static int 1124 ti_newbuf_std(sc, i, m) 1125 struct ti_softc *sc; 1126 int i; 1127 struct mbuf *m; 1128 { 1129 struct mbuf *m_new = NULL; 1130 struct ti_rx_desc *r; 1131 1132 if (m == NULL) { 1133 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1134 if (m_new == NULL) 1135 return(ENOBUFS); 1136 1137 MCLGET(m_new, M_DONTWAIT); 1138 if (!(m_new->m_flags & M_EXT)) { 1139 m_freem(m_new); 1140 return(ENOBUFS); 1141 } 1142 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1143 } else { 1144 m_new = m; 1145 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1146 m_new->m_data = m_new->m_ext.ext_buf; 1147 } 1148 1149 m_adj(m_new, ETHER_ALIGN); 1150 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1151 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1152 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1153 r->ti_type = TI_BDTYPE_RECV_BD; 1154 r->ti_flags = 0; 1155 if (sc->arpcom.ac_if.if_hwassist) 1156 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1157 r->ti_len = m_new->m_len; 1158 r->ti_idx = i; 1159 1160 return(0); 1161 } 1162 1163 /* 1164 * Intialize a mini receive ring descriptor. This only applies to 1165 * the Tigon 2. 1166 */ 1167 static int 1168 ti_newbuf_mini(sc, i, m) 1169 struct ti_softc *sc; 1170 int i; 1171 struct mbuf *m; 1172 { 1173 struct mbuf *m_new = NULL; 1174 struct ti_rx_desc *r; 1175 1176 if (m == NULL) { 1177 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1178 if (m_new == NULL) { 1179 return(ENOBUFS); 1180 } 1181 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1182 } else { 1183 m_new = m; 1184 m_new->m_data = m_new->m_pktdat; 1185 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1186 } 1187 1188 m_adj(m_new, ETHER_ALIGN); 1189 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1190 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1191 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1192 r->ti_type = TI_BDTYPE_RECV_BD; 1193 r->ti_flags = TI_BDFLAG_MINI_RING; 1194 if (sc->arpcom.ac_if.if_hwassist) 1195 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1196 r->ti_len = m_new->m_len; 1197 r->ti_idx = i; 1198 1199 return(0); 1200 } 1201 1202 #ifdef TI_PRIVATE_JUMBOS 1203 1204 /* 1205 * Initialize a jumbo receive ring descriptor. This allocates 1206 * a jumbo buffer from the pool managed internally by the driver. 1207 */ 1208 static int 1209 ti_newbuf_jumbo(sc, i, m) 1210 struct ti_softc *sc; 1211 int i; 1212 struct mbuf *m; 1213 { 1214 struct mbuf *m_new = NULL; 1215 struct ti_rx_desc *r; 1216 1217 if (m == NULL) { 1218 caddr_t *buf = NULL; 1219 1220 /* Allocate the mbuf. */ 1221 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1222 if (m_new == NULL) { 1223 return(ENOBUFS); 1224 } 1225 1226 /* Allocate the jumbo buffer */ 1227 buf = ti_jalloc(sc); 1228 if (buf == NULL) { 1229 m_freem(m_new); 1230 printf("ti%d: jumbo allocation failed " 1231 "-- packet dropped!\n", sc->ti_unit); 1232 return(ENOBUFS); 1233 } 1234 1235 /* Attach the buffer to the mbuf. */ 1236 m_new->m_data = (void *) buf; 1237 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1238 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1239 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1240 } else { 1241 m_new = m; 1242 m_new->m_data = m_new->m_ext.ext_buf; 1243 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1244 } 1245 1246 m_adj(m_new, ETHER_ALIGN); 1247 /* Set up the descriptor. */ 1248 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1249 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1250 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1251 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1252 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1253 if (sc->arpcom.ac_if.if_hwassist) 1254 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1255 r->ti_len = m_new->m_len; 1256 r->ti_idx = i; 1257 1258 return(0); 1259 } 1260 1261 #else 1262 #include <vm/vm_page.h> 1263 1264 #if (PAGE_SIZE == 4096) 1265 #define NPAYLOAD 2 1266 #else 1267 #define NPAYLOAD 1 1268 #endif 1269 1270 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1271 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1272 #define NFS_HDR_LEN (UDP_HDR_LEN) 1273 static int HDR_LEN = TCP_HDR_LEN; 1274 1275 1276 /* 1277 * Initialize a jumbo receive ring descriptor. This allocates 1278 * a jumbo buffer from the pool managed internally by the driver. 1279 */ 1280 static int 1281 ti_newbuf_jumbo(sc, idx, m_old) 1282 struct ti_softc *sc; 1283 int idx; 1284 struct mbuf *m_old; 1285 { 1286 struct mbuf *cur, *m_new = NULL; 1287 struct mbuf *m[3] = {NULL, NULL, NULL}; 1288 struct ti_rx_desc_ext *r; 1289 vm_page_t frame; 1290 /* 1 extra buf to make nobufs easy*/ 1291 caddr_t buf[3] = {NULL, NULL, NULL}; 1292 int i; 1293 1294 if (m_old != NULL) { 1295 m_new = m_old; 1296 cur = m_old->m_next; 1297 for (i = 0; i <= NPAYLOAD; i++){ 1298 m[i] = cur; 1299 cur = cur->m_next; 1300 } 1301 } else { 1302 /* Allocate the mbufs. */ 1303 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1304 if (m_new == NULL) { 1305 printf("ti%d: mbuf allocation failed " 1306 "-- packet dropped!\n", sc->ti_unit); 1307 goto nobufs; 1308 } 1309 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1310 if (m[NPAYLOAD] == NULL) { 1311 printf("ti%d: cluster mbuf allocation failed " 1312 "-- packet dropped!\n", sc->ti_unit); 1313 goto nobufs; 1314 } 1315 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1316 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1317 printf("ti%d: mbuf allocation failed " 1318 "-- packet dropped!\n", sc->ti_unit); 1319 goto nobufs; 1320 } 1321 m[NPAYLOAD]->m_len = MCLBYTES; 1322 1323 for (i = 0; i < NPAYLOAD; i++){ 1324 MGET(m[i], M_DONTWAIT, MT_DATA); 1325 if (m[i] == NULL) { 1326 printf("ti%d: mbuf allocation failed " 1327 "-- packet dropped!\n", sc->ti_unit); 1328 goto nobufs; 1329 } 1330 if (!(frame = jumbo_pg_alloc())){ 1331 printf("ti%d: buffer allocation failed " 1332 "-- packet dropped!\n", sc->ti_unit); 1333 printf(" index %d page %d\n", idx, i); 1334 goto nobufs; 1335 } 1336 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1337 } 1338 for (i = 0; i < NPAYLOAD; i++){ 1339 /* Attach the buffer to the mbuf. */ 1340 m[i]->m_data = (void *)buf[i]; 1341 m[i]->m_len = PAGE_SIZE; 1342 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1343 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1344 m[i]->m_next = m[i+1]; 1345 } 1346 /* link the buffers to the header */ 1347 m_new->m_next = m[0]; 1348 m_new->m_data += ETHER_ALIGN; 1349 if (sc->ti_hdrsplit) 1350 m_new->m_len = MHLEN - ETHER_ALIGN; 1351 else 1352 m_new->m_len = HDR_LEN; 1353 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1354 } 1355 1356 /* Set up the descriptor. */ 1357 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1358 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1359 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1360 r->ti_len0 = m_new->m_len; 1361 1362 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1363 r->ti_len1 = PAGE_SIZE; 1364 1365 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1366 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1367 1368 if (PAGE_SIZE == 4096) { 1369 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1370 r->ti_len3 = MCLBYTES; 1371 } else { 1372 r->ti_len3 = 0; 1373 } 1374 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1375 1376 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1377 1378 if (sc->arpcom.ac_if.if_hwassist) 1379 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1380 1381 r->ti_idx = idx; 1382 1383 return(0); 1384 1385 nobufs: 1386 1387 /* 1388 * Warning! : 1389 * This can only be called before the mbufs are strung together. 1390 * If the mbufs are strung together, m_freem() will free the chain, 1391 * so that the later mbufs will be freed multiple times. 1392 */ 1393 if (m_new) 1394 m_freem(m_new); 1395 1396 for(i = 0; i < 3; i++){ 1397 if (m[i]) 1398 m_freem(m[i]); 1399 if (buf[i]) 1400 jumbo_pg_free((vm_offset_t)buf[i]); 1401 } 1402 return ENOBUFS; 1403 } 1404 #endif 1405 1406 1407 1408 /* 1409 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1410 * that's 1MB or memory, which is a lot. For now, we fill only the first 1411 * 256 ring entries and hope that our CPU is fast enough to keep up with 1412 * the NIC. 1413 */ 1414 static int 1415 ti_init_rx_ring_std(sc) 1416 struct ti_softc *sc; 1417 { 1418 register int i; 1419 struct ti_cmd_desc cmd; 1420 1421 for (i = 0; i < TI_SSLOTS; i++) { 1422 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1423 return(ENOBUFS); 1424 }; 1425 1426 TI_UPDATE_STDPROD(sc, i - 1); 1427 sc->ti_std = i - 1; 1428 1429 return(0); 1430 } 1431 1432 static void 1433 ti_free_rx_ring_std(sc) 1434 struct ti_softc *sc; 1435 { 1436 register int i; 1437 1438 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1439 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1440 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1441 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1442 } 1443 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1444 sizeof(struct ti_rx_desc)); 1445 } 1446 1447 return; 1448 } 1449 1450 static int 1451 ti_init_rx_ring_jumbo(sc) 1452 struct ti_softc *sc; 1453 { 1454 register int i; 1455 struct ti_cmd_desc cmd; 1456 1457 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1458 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1459 return(ENOBUFS); 1460 }; 1461 1462 TI_UPDATE_JUMBOPROD(sc, i - 1); 1463 sc->ti_jumbo = i - 1; 1464 1465 return(0); 1466 } 1467 1468 static void 1469 ti_free_rx_ring_jumbo(sc) 1470 struct ti_softc *sc; 1471 { 1472 register int i; 1473 1474 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1475 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1476 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1477 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1478 } 1479 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1480 sizeof(struct ti_rx_desc)); 1481 } 1482 1483 return; 1484 } 1485 1486 static int 1487 ti_init_rx_ring_mini(sc) 1488 struct ti_softc *sc; 1489 { 1490 register int i; 1491 1492 for (i = 0; i < TI_MSLOTS; i++) { 1493 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1494 return(ENOBUFS); 1495 }; 1496 1497 TI_UPDATE_MINIPROD(sc, i - 1); 1498 sc->ti_mini = i - 1; 1499 1500 return(0); 1501 } 1502 1503 static void 1504 ti_free_rx_ring_mini(sc) 1505 struct ti_softc *sc; 1506 { 1507 register int i; 1508 1509 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1510 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1511 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1512 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1513 } 1514 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1515 sizeof(struct ti_rx_desc)); 1516 } 1517 1518 return; 1519 } 1520 1521 static void 1522 ti_free_tx_ring(sc) 1523 struct ti_softc *sc; 1524 { 1525 register int i; 1526 1527 if (sc->ti_rdata->ti_tx_ring == NULL) 1528 return; 1529 1530 for (i = 0; i < TI_TX_RING_CNT; i++) { 1531 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1532 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1533 sc->ti_cdata.ti_tx_chain[i] = NULL; 1534 } 1535 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1536 sizeof(struct ti_tx_desc)); 1537 } 1538 1539 return; 1540 } 1541 1542 static int 1543 ti_init_tx_ring(sc) 1544 struct ti_softc *sc; 1545 { 1546 sc->ti_txcnt = 0; 1547 sc->ti_tx_saved_considx = 0; 1548 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1549 return(0); 1550 } 1551 1552 /* 1553 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1554 * but we have to support the old way too so that Tigon 1 cards will 1555 * work. 1556 */ 1557 static void 1558 ti_add_mcast(sc, addr) 1559 struct ti_softc *sc; 1560 struct ether_addr *addr; 1561 { 1562 struct ti_cmd_desc cmd; 1563 u_int16_t *m; 1564 u_int32_t ext[2] = {0, 0}; 1565 1566 m = (u_int16_t *)&addr->octet[0]; 1567 1568 switch(sc->ti_hwrev) { 1569 case TI_HWREV_TIGON: 1570 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1571 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1572 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1573 break; 1574 case TI_HWREV_TIGON_II: 1575 ext[0] = htons(m[0]); 1576 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1577 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1578 break; 1579 default: 1580 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1581 break; 1582 } 1583 1584 return; 1585 } 1586 1587 static void 1588 ti_del_mcast(sc, addr) 1589 struct ti_softc *sc; 1590 struct ether_addr *addr; 1591 { 1592 struct ti_cmd_desc cmd; 1593 u_int16_t *m; 1594 u_int32_t ext[2] = {0, 0}; 1595 1596 m = (u_int16_t *)&addr->octet[0]; 1597 1598 switch(sc->ti_hwrev) { 1599 case TI_HWREV_TIGON: 1600 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1601 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1602 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1603 break; 1604 case TI_HWREV_TIGON_II: 1605 ext[0] = htons(m[0]); 1606 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1607 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1608 break; 1609 default: 1610 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1611 break; 1612 } 1613 1614 return; 1615 } 1616 1617 /* 1618 * Configure the Tigon's multicast address filter. 1619 * 1620 * The actual multicast table management is a bit of a pain, thanks to 1621 * slight brain damage on the part of both Alteon and us. With our 1622 * multicast code, we are only alerted when the multicast address table 1623 * changes and at that point we only have the current list of addresses: 1624 * we only know the current state, not the previous state, so we don't 1625 * actually know what addresses were removed or added. The firmware has 1626 * state, but we can't get our grubby mits on it, and there is no 'delete 1627 * all multicast addresses' command. Hence, we have to maintain our own 1628 * state so we know what addresses have been programmed into the NIC at 1629 * any given time. 1630 */ 1631 static void 1632 ti_setmulti(sc) 1633 struct ti_softc *sc; 1634 { 1635 struct ifnet *ifp; 1636 struct ifmultiaddr *ifma; 1637 struct ti_cmd_desc cmd; 1638 struct ti_mc_entry *mc; 1639 u_int32_t intrs; 1640 1641 ifp = &sc->arpcom.ac_if; 1642 1643 if (ifp->if_flags & IFF_ALLMULTI) { 1644 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1645 return; 1646 } else { 1647 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1648 } 1649 1650 /* Disable interrupts. */ 1651 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1652 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1653 1654 /* First, zot all the existing filters. */ 1655 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1656 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1657 ti_del_mcast(sc, &mc->mc_addr); 1658 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1659 free(mc, M_DEVBUF); 1660 } 1661 1662 /* Now program new ones. */ 1663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1664 if (ifma->ifma_addr->sa_family != AF_LINK) 1665 continue; 1666 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1667 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1668 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1669 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1670 ti_add_mcast(sc, &mc->mc_addr); 1671 } 1672 1673 /* Re-enable interrupts. */ 1674 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1675 1676 return; 1677 } 1678 1679 /* 1680 * Check to see if the BIOS has configured us for a 64 bit slot when 1681 * we aren't actually in one. If we detect this condition, we can work 1682 * around it on the Tigon 2 by setting a bit in the PCI state register, 1683 * but for the Tigon 1 we must give up and abort the interface attach. 1684 */ 1685 static int ti_64bitslot_war(sc) 1686 struct ti_softc *sc; 1687 { 1688 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1689 CSR_WRITE_4(sc, 0x600, 0); 1690 CSR_WRITE_4(sc, 0x604, 0); 1691 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1692 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1693 if (sc->ti_hwrev == TI_HWREV_TIGON) 1694 return(EINVAL); 1695 else { 1696 TI_SETBIT(sc, TI_PCI_STATE, 1697 TI_PCISTATE_32BIT_BUS); 1698 return(0); 1699 } 1700 } 1701 } 1702 1703 return(0); 1704 } 1705 1706 /* 1707 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1708 * self-test results. 1709 */ 1710 static int 1711 ti_chipinit(sc) 1712 struct ti_softc *sc; 1713 { 1714 u_int32_t cacheline; 1715 u_int32_t pci_writemax = 0; 1716 u_int32_t hdrsplit; 1717 1718 /* Initialize link to down state. */ 1719 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1720 1721 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1722 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1723 else 1724 sc->arpcom.ac_if.if_hwassist = 0; 1725 1726 /* Set endianness before we access any non-PCI registers. */ 1727 #if BYTE_ORDER == BIG_ENDIAN 1728 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1729 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1730 #else 1731 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1732 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1733 #endif 1734 1735 /* Check the ROM failed bit to see if self-tests passed. */ 1736 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1737 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1738 return(ENODEV); 1739 } 1740 1741 /* Halt the CPU. */ 1742 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1743 1744 /* Figure out the hardware revision. */ 1745 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1746 case TI_REV_TIGON_I: 1747 sc->ti_hwrev = TI_HWREV_TIGON; 1748 break; 1749 case TI_REV_TIGON_II: 1750 sc->ti_hwrev = TI_HWREV_TIGON_II; 1751 break; 1752 default: 1753 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1754 return(ENODEV); 1755 } 1756 1757 /* Do special setup for Tigon 2. */ 1758 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1759 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1760 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1761 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1762 } 1763 1764 /* 1765 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1766 * can't do header splitting. 1767 */ 1768 #ifdef TI_JUMBO_HDRSPLIT 1769 if (sc->ti_hwrev != TI_HWREV_TIGON) 1770 sc->ti_hdrsplit = 1; 1771 else 1772 printf("ti%d: can't do header splitting on a Tigon I board\n", 1773 sc->ti_unit); 1774 #endif /* TI_JUMBO_HDRSPLIT */ 1775 1776 /* Set up the PCI state register. */ 1777 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1778 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1779 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1780 } 1781 1782 /* Clear the read/write max DMA parameters. */ 1783 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1784 TI_PCISTATE_READ_MAXDMA)); 1785 1786 /* Get cache line size. */ 1787 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1788 1789 /* 1790 * If the system has set enabled the PCI memory write 1791 * and invalidate command in the command register, set 1792 * the write max parameter accordingly. This is necessary 1793 * to use MWI with the Tigon 2. 1794 */ 1795 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1796 switch(cacheline) { 1797 case 1: 1798 case 4: 1799 case 8: 1800 case 16: 1801 case 32: 1802 case 64: 1803 break; 1804 default: 1805 /* Disable PCI memory write and invalidate. */ 1806 if (bootverbose) 1807 printf("ti%d: cache line size %d not " 1808 "supported; disabling PCI MWI\n", 1809 sc->ti_unit, cacheline); 1810 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1811 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1812 break; 1813 } 1814 } 1815 1816 #ifdef __brokenalpha__ 1817 /* 1818 * From the Alteon sample driver: 1819 * Must insure that we do not cross an 8K (bytes) boundary 1820 * for DMA reads. Our highest limit is 1K bytes. This is a 1821 * restriction on some ALPHA platforms with early revision 1822 * 21174 PCI chipsets, such as the AlphaPC 164lx 1823 */ 1824 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1825 #else 1826 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1827 #endif 1828 1829 /* This sets the min dma param all the way up (0xff). */ 1830 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1831 1832 if (sc->ti_hdrsplit) 1833 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1834 else 1835 hdrsplit = 0; 1836 1837 /* Configure DMA variables. */ 1838 #if BYTE_ORDER == BIG_ENDIAN 1839 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1840 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1841 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1842 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1843 #else /* BYTE_ORDER */ 1844 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1845 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1846 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1847 #endif /* BYTE_ORDER */ 1848 1849 /* 1850 * Only allow 1 DMA channel to be active at a time. 1851 * I don't think this is a good idea, but without it 1852 * the firmware racks up lots of nicDmaReadRingFull 1853 * errors. This is not compatible with hardware checksums. 1854 */ 1855 if (sc->arpcom.ac_if.if_hwassist == 0) 1856 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1857 1858 /* Recommended settings from Tigon manual. */ 1859 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1860 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1861 1862 if (ti_64bitslot_war(sc)) { 1863 printf("ti%d: bios thinks we're in a 64 bit slot, " 1864 "but we aren't", sc->ti_unit); 1865 return(EINVAL); 1866 } 1867 1868 return(0); 1869 } 1870 1871 /* 1872 * Initialize the general information block and firmware, and 1873 * start the CPU(s) running. 1874 */ 1875 static int 1876 ti_gibinit(sc) 1877 struct ti_softc *sc; 1878 { 1879 struct ti_rcb *rcb; 1880 int i; 1881 struct ifnet *ifp; 1882 1883 ifp = &sc->arpcom.ac_if; 1884 1885 /* Disable interrupts for now. */ 1886 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1887 1888 /* Tell the chip where to find the general information block. */ 1889 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1890 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1891 1892 /* Load the firmware into SRAM. */ 1893 ti_loadfw(sc); 1894 1895 /* Set up the contents of the general info and ring control blocks. */ 1896 1897 /* Set up the event ring and producer pointer. */ 1898 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1899 1900 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1901 rcb->ti_flags = 0; 1902 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1903 vtophys(&sc->ti_ev_prodidx); 1904 sc->ti_ev_prodidx.ti_idx = 0; 1905 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1906 sc->ti_ev_saved_considx = 0; 1907 1908 /* Set up the command ring and producer mailbox. */ 1909 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1910 1911 sc->ti_rdata->ti_cmd_ring = 1912 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1913 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1914 rcb->ti_flags = 0; 1915 rcb->ti_max_len = 0; 1916 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1917 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1918 } 1919 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1920 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1921 sc->ti_cmd_saved_prodidx = 0; 1922 1923 /* 1924 * Assign the address of the stats refresh buffer. 1925 * We re-use the current stats buffer for this to 1926 * conserve memory. 1927 */ 1928 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1929 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1930 1931 /* Set up the standard receive ring. */ 1932 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1933 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1934 rcb->ti_max_len = TI_FRAMELEN; 1935 rcb->ti_flags = 0; 1936 if (sc->arpcom.ac_if.if_hwassist) 1937 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1938 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1939 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1940 1941 /* Set up the jumbo receive ring. */ 1942 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1943 TI_HOSTADDR(rcb->ti_hostaddr) = 1944 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1945 1946 #ifdef TI_PRIVATE_JUMBOS 1947 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1948 rcb->ti_flags = 0; 1949 #else 1950 rcb->ti_max_len = PAGE_SIZE; 1951 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1952 #endif 1953 if (sc->arpcom.ac_if.if_hwassist) 1954 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1955 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1956 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1957 1958 /* 1959 * Set up the mini ring. Only activated on the 1960 * Tigon 2 but the slot in the config block is 1961 * still there on the Tigon 1. 1962 */ 1963 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1964 TI_HOSTADDR(rcb->ti_hostaddr) = 1965 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1966 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1967 if (sc->ti_hwrev == TI_HWREV_TIGON) 1968 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1969 else 1970 rcb->ti_flags = 0; 1971 if (sc->arpcom.ac_if.if_hwassist) 1972 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1973 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1974 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1975 1976 /* 1977 * Set up the receive return ring. 1978 */ 1979 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1980 TI_HOSTADDR(rcb->ti_hostaddr) = 1981 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1982 rcb->ti_flags = 0; 1983 rcb->ti_max_len = TI_RETURN_RING_CNT; 1984 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1985 vtophys(&sc->ti_return_prodidx); 1986 1987 /* 1988 * Set up the tx ring. Note: for the Tigon 2, we have the option 1989 * of putting the transmit ring in the host's address space and 1990 * letting the chip DMA it instead of leaving the ring in the NIC's 1991 * memory and accessing it through the shared memory region. We 1992 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1993 * so we have to revert to the shared memory scheme if we detect 1994 * a Tigon 1 chip. 1995 */ 1996 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1997 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1998 sc->ti_rdata->ti_tx_ring_nic = 1999 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 2000 } 2001 bzero((char *)sc->ti_rdata->ti_tx_ring, 2002 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2003 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2004 if (sc->ti_hwrev == TI_HWREV_TIGON) 2005 rcb->ti_flags = 0; 2006 else 2007 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2008 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2009 if (sc->arpcom.ac_if.if_hwassist) 2010 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2011 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2012 rcb->ti_max_len = TI_TX_RING_CNT; 2013 if (sc->ti_hwrev == TI_HWREV_TIGON) 2014 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2015 else 2016 TI_HOSTADDR(rcb->ti_hostaddr) = 2017 vtophys(&sc->ti_rdata->ti_tx_ring); 2018 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2019 vtophys(&sc->ti_tx_considx); 2020 2021 /* Set up tuneables */ 2022 #if 0 2023 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2024 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2025 (sc->ti_rx_coal_ticks / 10)); 2026 else 2027 #endif 2028 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2029 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2030 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2031 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2032 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2033 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2034 2035 /* Turn interrupts on. */ 2036 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2037 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2038 2039 /* Start CPU. */ 2040 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2041 2042 return(0); 2043 } 2044 2045 /* 2046 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2047 * against our list and return its name if we find a match. 2048 */ 2049 static int 2050 ti_probe(dev) 2051 device_t dev; 2052 { 2053 struct ti_type *t; 2054 2055 t = ti_devs; 2056 2057 while(t->ti_name != NULL) { 2058 if ((pci_get_vendor(dev) == t->ti_vid) && 2059 (pci_get_device(dev) == t->ti_did)) { 2060 device_set_desc(dev, t->ti_name); 2061 return(0); 2062 } 2063 t++; 2064 } 2065 2066 return(ENXIO); 2067 } 2068 2069 #ifdef KLD_MODULE 2070 static int 2071 log2rndup(int len) 2072 { 2073 int log2size = 0, t = len; 2074 while (t > 1) { 2075 log2size++; 2076 t >>= 1; 2077 } 2078 if (len != (1 << log2size)) 2079 log2size++; 2080 return log2size; 2081 } 2082 2083 static int 2084 ti_mbuf_sanity(device_t dev) 2085 { 2086 if ((mbstat.m_msize != MSIZE) || mbstat.m_mclbytes != MCLBYTES){ 2087 device_printf(dev, "\n"); 2088 device_printf(dev, "This module was compiled with " 2089 "-DMCLSHIFT=%d -DMSIZE=%d\n", MCLSHIFT, 2090 MSIZE); 2091 device_printf(dev, "The kernel was compiled with MCLSHIFT=%d," 2092 " MSIZE=%d\n", log2rndup(mbstat.m_mclbytes), 2093 (int)mbstat.m_msize); 2094 return(EINVAL); 2095 } 2096 return(0); 2097 } 2098 #endif 2099 2100 2101 static int 2102 ti_attach(dev) 2103 device_t dev; 2104 { 2105 u_int32_t command; 2106 struct ifnet *ifp; 2107 struct ti_softc *sc; 2108 int unit, error = 0, rid; 2109 2110 sc = NULL; 2111 2112 #ifdef KLD_MODULE 2113 if (ti_mbuf_sanity(dev)){ 2114 device_printf(dev, "Module mbuf constants do not match " 2115 "kernel constants!\n"); 2116 device_printf(dev, "Rebuild the module or the kernel so " 2117 "they match\n"); 2118 device_printf(dev, "\n"); 2119 error = EINVAL; 2120 goto fail; 2121 } 2122 #endif 2123 2124 sc = device_get_softc(dev); 2125 unit = device_get_unit(dev); 2126 bzero(sc, sizeof(struct ti_softc)); 2127 2128 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2129 MTX_DEF | MTX_RECURSE); 2130 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM; 2131 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2132 2133 /* 2134 * Map control/status registers. 2135 */ 2136 pci_enable_busmaster(dev); 2137 pci_enable_io(dev, SYS_RES_MEMORY); 2138 command = pci_read_config(dev, PCIR_COMMAND, 4); 2139 2140 if (!(command & PCIM_CMD_MEMEN)) { 2141 printf("ti%d: failed to enable memory mapping!\n", unit); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 2146 rid = TI_PCI_LOMEM; 2147 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2148 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2149 2150 if (sc->ti_res == NULL) { 2151 printf ("ti%d: couldn't map memory\n", unit); 2152 error = ENXIO; 2153 goto fail; 2154 } 2155 2156 sc->ti_btag = rman_get_bustag(sc->ti_res); 2157 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2158 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2159 2160 /* Allocate interrupt */ 2161 rid = 0; 2162 2163 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2164 RF_SHAREABLE | RF_ACTIVE); 2165 2166 if (sc->ti_irq == NULL) { 2167 printf("ti%d: couldn't map interrupt\n", unit); 2168 error = ENXIO; 2169 goto fail; 2170 } 2171 2172 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2173 ti_intr, sc, &sc->ti_intrhand); 2174 2175 if (error) { 2176 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2177 bus_release_resource(dev, SYS_RES_MEMORY, 2178 TI_PCI_LOMEM, sc->ti_res); 2179 printf("ti%d: couldn't set up irq\n", unit); 2180 goto fail; 2181 } 2182 2183 sc->ti_unit = unit; 2184 2185 if (ti_chipinit(sc)) { 2186 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2187 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2188 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2189 bus_release_resource(dev, SYS_RES_MEMORY, 2190 TI_PCI_LOMEM, sc->ti_res); 2191 error = ENXIO; 2192 goto fail; 2193 } 2194 2195 /* Zero out the NIC's on-board SRAM. */ 2196 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2197 2198 /* Init again -- zeroing memory may have clobbered some registers. */ 2199 if (ti_chipinit(sc)) { 2200 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2201 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2202 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2203 bus_release_resource(dev, SYS_RES_MEMORY, 2204 TI_PCI_LOMEM, sc->ti_res); 2205 error = ENXIO; 2206 goto fail; 2207 } 2208 2209 /* 2210 * Get station address from the EEPROM. Note: the manual states 2211 * that the MAC address is at offset 0x8c, however the data is 2212 * stored as two longwords (since that's how it's loaded into 2213 * the NIC). This means the MAC address is actually preceded 2214 * by two zero bytes. We need to skip over those. 2215 */ 2216 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2217 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2218 printf("ti%d: failed to read station address\n", unit); 2219 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2220 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2221 bus_release_resource(dev, SYS_RES_MEMORY, 2222 TI_PCI_LOMEM, sc->ti_res); 2223 error = ENXIO; 2224 goto fail; 2225 } 2226 2227 /* 2228 * A Tigon chip was detected. Inform the world. 2229 */ 2230 printf("ti%d: Ethernet address: %6D\n", unit, 2231 sc->arpcom.ac_enaddr, ":"); 2232 2233 /* Allocate the general information block and ring buffers. */ 2234 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2235 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2236 2237 if (sc->ti_rdata == NULL) { 2238 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2239 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2240 bus_release_resource(dev, SYS_RES_MEMORY, 2241 TI_PCI_LOMEM, sc->ti_res); 2242 error = ENXIO; 2243 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2244 goto fail; 2245 } 2246 2247 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2248 2249 /* Try to allocate memory for jumbo buffers. */ 2250 #ifdef TI_PRIVATE_JUMBOS 2251 if (ti_alloc_jumbo_mem(sc)) { 2252 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2253 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2254 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2255 bus_release_resource(dev, SYS_RES_MEMORY, 2256 TI_PCI_LOMEM, sc->ti_res); 2257 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), 2258 M_DEVBUF); 2259 error = ENXIO; 2260 goto fail; 2261 } 2262 #else 2263 if (!jumbo_vm_init()) { 2264 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2265 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2266 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2267 bus_release_resource(dev, SYS_RES_MEMORY, 2268 TI_PCI_LOMEM, sc->ti_res); 2269 free(sc->ti_rdata, M_DEVBUF); 2270 error = ENOMEM; 2271 goto fail; 2272 } 2273 #endif 2274 2275 /* 2276 * We really need a better way to tell a 1000baseTX card 2277 * from a 1000baseSX one, since in theory there could be 2278 * OEMed 1000baseTX cards from lame vendors who aren't 2279 * clever enough to change the PCI ID. For the moment 2280 * though, the AceNIC is the only copper card available. 2281 */ 2282 if (pci_get_vendor(dev) == ALT_VENDORID && 2283 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2284 sc->ti_copper = 1; 2285 /* Ok, it's not the only copper card available. */ 2286 if (pci_get_vendor(dev) == NG_VENDORID && 2287 pci_get_device(dev) == NG_DEVICEID_GA620T) 2288 sc->ti_copper = 1; 2289 2290 /* Set default tuneable values. */ 2291 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2292 #if 0 2293 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2294 #endif 2295 sc->ti_rx_coal_ticks = 170; 2296 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2297 sc->ti_rx_max_coal_bds = 64; 2298 #if 0 2299 sc->ti_tx_max_coal_bds = 128; 2300 #endif 2301 sc->ti_tx_max_coal_bds = 32; 2302 sc->ti_tx_buf_ratio = 21; 2303 2304 /* Set up ifnet structure */ 2305 ifp = &sc->arpcom.ac_if; 2306 ifp->if_softc = sc; 2307 ifp->if_unit = sc->ti_unit; 2308 ifp->if_name = "ti"; 2309 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2310 tis[unit] = sc; 2311 ifp->if_ioctl = ti_ioctl; 2312 ifp->if_output = ether_output; 2313 ifp->if_start = ti_start; 2314 ifp->if_watchdog = ti_watchdog; 2315 ifp->if_init = ti_init; 2316 ifp->if_mtu = ETHERMTU; 2317 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2318 2319 /* Set up ifmedia support. */ 2320 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2321 if (sc->ti_copper) { 2322 /* 2323 * Copper cards allow manual 10/100 mode selection, 2324 * but not manual 1000baseTX mode selection. Why? 2325 * Becuase currently there's no way to specify the 2326 * master/slave setting through the firmware interface, 2327 * so Alteon decided to just bag it and handle it 2328 * via autonegotiation. 2329 */ 2330 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2331 ifmedia_add(&sc->ifmedia, 2332 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2333 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2334 ifmedia_add(&sc->ifmedia, 2335 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2336 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2337 ifmedia_add(&sc->ifmedia, 2338 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2339 } else { 2340 /* Fiber cards don't support 10/100 modes. */ 2341 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2342 ifmedia_add(&sc->ifmedia, 2343 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2344 } 2345 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2346 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2347 2348 /* 2349 * We're assuming here that card initialization is a sequential 2350 * thing. If it isn't, multiple cards probing at the same time 2351 * could stomp on the list of softcs here. 2352 */ 2353 /* 2354 * If this is the first card to be initialized, initialize the 2355 * softc queue. 2356 */ 2357 if (unit == 0) 2358 STAILQ_INIT(&ti_sc_list); 2359 2360 STAILQ_INSERT_TAIL(&ti_sc_list, sc, ti_links); 2361 2362 /* Register the device */ 2363 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2364 0600, "ti%d", sc->ti_unit); 2365 2366 /* 2367 * Call MI attach routine. 2368 */ 2369 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2370 return(0); 2371 2372 fail: 2373 mtx_destroy(&sc->ti_mtx); 2374 return(error); 2375 } 2376 2377 /* 2378 * Verify that our character special device is not currently 2379 * open. Also track down any cached vnodes & kill them before 2380 * the module is unloaded 2381 */ 2382 static int 2383 ti_unref_special(device_t dev) 2384 { 2385 struct vnode *ti_vn; 2386 int count; 2387 struct ti_softc *sc = sc = device_get_softc(dev); 2388 2389 if (!vfinddev(sc->dev, VCHR, &ti_vn)) { 2390 return 0; 2391 } 2392 2393 if ((count = vcount(ti_vn))) { 2394 device_printf(dev, "%d refs to special device, " 2395 "denying unload\n", count); 2396 return count; 2397 } 2398 /* now we know that there's a vnode in the cache. We hunt it 2399 down and kill it now, before unloading */ 2400 vgone(ti_vn); 2401 return(0); 2402 } 2403 2404 2405 static int 2406 ti_detach(dev) 2407 device_t dev; 2408 { 2409 struct ti_softc *sc; 2410 struct ifnet *ifp; 2411 2412 if (ti_unref_special(dev)) 2413 return EBUSY; 2414 2415 sc = device_get_softc(dev); 2416 TI_LOCK(sc); 2417 ifp = &sc->arpcom.ac_if; 2418 2419 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2420 ti_stop(sc); 2421 2422 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2423 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2424 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 2425 2426 #ifdef TI_PRIVATE_JUMBOS 2427 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2428 #endif 2429 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2430 ifmedia_removeall(&sc->ifmedia); 2431 2432 TI_UNLOCK(sc); 2433 mtx_destroy(&sc->ti_mtx); 2434 2435 return(0); 2436 } 2437 2438 #ifdef TI_JUMBO_HDRSPLIT 2439 /* 2440 * If hdr_len is 0, that means that header splitting wasn't done on 2441 * this packet for some reason. The two most likely reasons are that 2442 * the protocol isn't a supported protocol for splitting, or this 2443 * packet had a fragment offset that wasn't 0. 2444 * 2445 * The header length, if it is non-zero, will always be the length of 2446 * the headers on the packet, but that length could be longer than the 2447 * first mbuf. So we take the minimum of the two as the actual 2448 * length. 2449 */ 2450 static __inline void 2451 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2452 { 2453 int i = 0; 2454 int lengths[4] = {0, 0, 0, 0}; 2455 struct mbuf *m, *mp; 2456 2457 if (hdr_len != 0) 2458 top->m_len = min(hdr_len, top->m_len); 2459 pkt_len -= top->m_len; 2460 lengths[i++] = top->m_len; 2461 2462 mp = top; 2463 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2464 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2465 pkt_len -= m->m_len; 2466 lengths[i++] = m->m_len; 2467 mp = m; 2468 } 2469 2470 #if 0 2471 if (hdr_len != 0) 2472 printf("got split packet: "); 2473 else 2474 printf("got non-split packet: "); 2475 2476 printf("%d,%d,%d,%d = %d\n", lengths[0], 2477 lengths[1], lengths[2], lengths[3], 2478 lengths[0] + lengths[1] + lengths[2] + 2479 lengths[3]); 2480 #endif 2481 2482 if (pkt_len) 2483 panic("header splitting didn't"); 2484 2485 if (m) { 2486 m_freem(m); 2487 mp->m_next = NULL; 2488 2489 } 2490 if (mp->m_next != NULL) 2491 panic("ti_hdr_split: last mbuf in chain should be null"); 2492 } 2493 #endif /* TI_JUMBO_HDRSPLIT */ 2494 2495 /* 2496 * Frame reception handling. This is called if there's a frame 2497 * on the receive return list. 2498 * 2499 * Note: we have to be able to handle three possibilities here: 2500 * 1) the frame is from the mini receive ring (can only happen) 2501 * on Tigon 2 boards) 2502 * 2) the frame is from the jumbo recieve ring 2503 * 3) the frame is from the standard receive ring 2504 */ 2505 2506 static void 2507 ti_rxeof(sc) 2508 struct ti_softc *sc; 2509 { 2510 struct ifnet *ifp; 2511 struct ti_cmd_desc cmd; 2512 2513 ifp = &sc->arpcom.ac_if; 2514 2515 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2516 struct ti_rx_desc *cur_rx; 2517 u_int32_t rxidx; 2518 struct ether_header *eh; 2519 struct mbuf *m = NULL; 2520 u_int16_t vlan_tag = 0; 2521 int have_tag = 0; 2522 2523 cur_rx = 2524 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2525 rxidx = cur_rx->ti_idx; 2526 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2527 2528 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2529 have_tag = 1; 2530 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2531 } 2532 2533 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2534 2535 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2536 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2537 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2538 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2539 ifp->if_ierrors++; 2540 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2541 continue; 2542 } 2543 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2544 ifp->if_ierrors++; 2545 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2546 continue; 2547 } 2548 #ifdef TI_PRIVATE_JUMBOS 2549 m->m_len = cur_rx->ti_len; 2550 #else /* TI_PRIVATE_JUMBOS */ 2551 #ifdef TI_JUMBO_HDRSPLIT 2552 if (sc->ti_hdrsplit) 2553 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2554 cur_rx->ti_len, rxidx); 2555 else 2556 #endif /* TI_JUMBO_HDRSPLIT */ 2557 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2558 #endif /* TI_PRIVATE_JUMBOS */ 2559 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2560 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2561 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2562 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2563 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2564 ifp->if_ierrors++; 2565 ti_newbuf_mini(sc, sc->ti_mini, m); 2566 continue; 2567 } 2568 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2569 ifp->if_ierrors++; 2570 ti_newbuf_mini(sc, sc->ti_mini, m); 2571 continue; 2572 } 2573 m->m_len = cur_rx->ti_len; 2574 } else { 2575 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2576 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2577 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2578 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2579 ifp->if_ierrors++; 2580 ti_newbuf_std(sc, sc->ti_std, m); 2581 continue; 2582 } 2583 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2584 ifp->if_ierrors++; 2585 ti_newbuf_std(sc, sc->ti_std, m); 2586 continue; 2587 } 2588 m->m_len = cur_rx->ti_len; 2589 } 2590 2591 m->m_pkthdr.len = cur_rx->ti_len; 2592 ifp->if_ipackets++; 2593 eh = mtod(m, struct ether_header *); 2594 m->m_pkthdr.rcvif = ifp; 2595 2596 /* Remove header from mbuf and pass it on. */ 2597 m_adj(m, sizeof(struct ether_header)); 2598 2599 if (ifp->if_hwassist) { 2600 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2601 CSUM_DATA_VALID; 2602 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2603 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2604 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2605 } 2606 2607 /* 2608 * If we received a packet with a vlan tag, pass it 2609 * to vlan_input() instead of ether_input(). 2610 */ 2611 if (have_tag) { 2612 VLAN_INPUT_TAG(eh, m, vlan_tag); 2613 have_tag = vlan_tag = 0; 2614 continue; 2615 } 2616 ether_input(ifp, eh, m); 2617 } 2618 2619 /* Only necessary on the Tigon 1. */ 2620 if (sc->ti_hwrev == TI_HWREV_TIGON) 2621 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2622 sc->ti_rx_saved_considx); 2623 2624 TI_UPDATE_STDPROD(sc, sc->ti_std); 2625 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2626 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2627 2628 return; 2629 } 2630 2631 static void 2632 ti_txeof(sc) 2633 struct ti_softc *sc; 2634 { 2635 struct ti_tx_desc *cur_tx = NULL; 2636 struct ifnet *ifp; 2637 2638 ifp = &sc->arpcom.ac_if; 2639 2640 /* 2641 * Go through our tx ring and free mbufs for those 2642 * frames that have been sent. 2643 */ 2644 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2645 u_int32_t idx = 0; 2646 2647 idx = sc->ti_tx_saved_considx; 2648 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2649 if (idx > 383) 2650 CSR_WRITE_4(sc, TI_WINBASE, 2651 TI_TX_RING_BASE + 6144); 2652 else if (idx > 255) 2653 CSR_WRITE_4(sc, TI_WINBASE, 2654 TI_TX_RING_BASE + 4096); 2655 else if (idx > 127) 2656 CSR_WRITE_4(sc, TI_WINBASE, 2657 TI_TX_RING_BASE + 2048); 2658 else 2659 CSR_WRITE_4(sc, TI_WINBASE, 2660 TI_TX_RING_BASE); 2661 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2662 } else 2663 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2664 if (cur_tx->ti_flags & TI_BDFLAG_END) 2665 ifp->if_opackets++; 2666 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2667 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2668 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2669 } 2670 sc->ti_txcnt--; 2671 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2672 ifp->if_timer = 0; 2673 } 2674 2675 if (cur_tx != NULL) 2676 ifp->if_flags &= ~IFF_OACTIVE; 2677 2678 return; 2679 } 2680 2681 static void 2682 ti_intr(xsc) 2683 void *xsc; 2684 { 2685 struct ti_softc *sc; 2686 struct ifnet *ifp; 2687 2688 sc = xsc; 2689 TI_LOCK(sc); 2690 ifp = &sc->arpcom.ac_if; 2691 2692 /*#ifdef notdef*/ 2693 /* Avoid this for now -- checking this register is expensive. */ 2694 /* Make sure this is really our interrupt. */ 2695 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2696 TI_UNLOCK(sc); 2697 return; 2698 } 2699 /*#endif*/ 2700 2701 /* Ack interrupt and stop others from occuring. */ 2702 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2703 2704 if (ifp->if_flags & IFF_RUNNING) { 2705 /* Check RX return ring producer/consumer */ 2706 ti_rxeof(sc); 2707 2708 /* Check TX ring producer/consumer */ 2709 ti_txeof(sc); 2710 } 2711 2712 ti_handle_events(sc); 2713 2714 /* Re-enable interrupts. */ 2715 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2716 2717 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2718 ti_start(ifp); 2719 2720 TI_UNLOCK(sc); 2721 2722 return; 2723 } 2724 2725 static void 2726 ti_stats_update(sc) 2727 struct ti_softc *sc; 2728 { 2729 struct ifnet *ifp; 2730 2731 ifp = &sc->arpcom.ac_if; 2732 2733 ifp->if_collisions += 2734 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2735 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2736 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2737 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2738 ifp->if_collisions; 2739 2740 return; 2741 } 2742 2743 /* 2744 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2745 * pointers to descriptors. 2746 */ 2747 static int 2748 ti_encap(sc, m_head, txidx) 2749 struct ti_softc *sc; 2750 struct mbuf *m_head; 2751 u_int32_t *txidx; 2752 { 2753 struct ti_tx_desc *f = NULL; 2754 struct mbuf *m; 2755 u_int32_t frag, cur, cnt = 0; 2756 u_int16_t csum_flags = 0; 2757 struct ifvlan *ifv = NULL; 2758 2759 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2760 m_head->m_pkthdr.rcvif != NULL && 2761 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2762 ifv = m_head->m_pkthdr.rcvif->if_softc; 2763 2764 m = m_head; 2765 cur = frag = *txidx; 2766 2767 if (m_head->m_pkthdr.csum_flags) { 2768 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2769 csum_flags |= TI_BDFLAG_IP_CKSUM; 2770 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2771 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2772 if (m_head->m_flags & M_LASTFRAG) 2773 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2774 else if (m_head->m_flags & M_FRAG) 2775 csum_flags |= TI_BDFLAG_IP_FRAG; 2776 } 2777 /* 2778 * Start packing the mbufs in this chain into 2779 * the fragment pointers. Stop when we run out 2780 * of fragments or hit the end of the mbuf chain. 2781 */ 2782 for (m = m_head; m != NULL; m = m->m_next) { 2783 if (m->m_len != 0) { 2784 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2785 if (frag > 383) 2786 CSR_WRITE_4(sc, TI_WINBASE, 2787 TI_TX_RING_BASE + 6144); 2788 else if (frag > 255) 2789 CSR_WRITE_4(sc, TI_WINBASE, 2790 TI_TX_RING_BASE + 4096); 2791 else if (frag > 127) 2792 CSR_WRITE_4(sc, TI_WINBASE, 2793 TI_TX_RING_BASE + 2048); 2794 else 2795 CSR_WRITE_4(sc, TI_WINBASE, 2796 TI_TX_RING_BASE); 2797 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2798 } else 2799 f = &sc->ti_rdata->ti_tx_ring[frag]; 2800 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2801 break; 2802 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2803 f->ti_len = m->m_len; 2804 f->ti_flags = csum_flags; 2805 2806 if (ifv != NULL) { 2807 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2808 f->ti_vlan_tag = ifv->ifv_tag & 0xfff; 2809 } else { 2810 f->ti_vlan_tag = 0; 2811 } 2812 2813 /* 2814 * Sanity check: avoid coming within 16 descriptors 2815 * of the end of the ring. 2816 */ 2817 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2818 return(ENOBUFS); 2819 cur = frag; 2820 TI_INC(frag, TI_TX_RING_CNT); 2821 cnt++; 2822 } 2823 } 2824 2825 if (m != NULL) 2826 return(ENOBUFS); 2827 2828 if (frag == sc->ti_tx_saved_considx) 2829 return(ENOBUFS); 2830 2831 if (sc->ti_hwrev == TI_HWREV_TIGON) 2832 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2833 TI_BDFLAG_END; 2834 else 2835 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2836 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2837 sc->ti_txcnt += cnt; 2838 2839 *txidx = frag; 2840 2841 return(0); 2842 } 2843 2844 /* 2845 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2846 * to the mbuf data regions directly in the transmit descriptors. 2847 */ 2848 static void 2849 ti_start(ifp) 2850 struct ifnet *ifp; 2851 { 2852 struct ti_softc *sc; 2853 struct mbuf *m_head = NULL; 2854 u_int32_t prodidx = 0; 2855 2856 sc = ifp->if_softc; 2857 TI_LOCK(sc); 2858 2859 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2860 2861 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2862 IF_DEQUEUE(&ifp->if_snd, m_head); 2863 if (m_head == NULL) 2864 break; 2865 2866 /* 2867 * XXX 2868 * safety overkill. If this is a fragmented packet chain 2869 * with delayed TCP/UDP checksums, then only encapsulate 2870 * it if we have enough descriptors to handle the entire 2871 * chain at once. 2872 * (paranoia -- may not actually be needed) 2873 */ 2874 if (m_head->m_flags & M_FIRSTFRAG && 2875 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2876 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2877 m_head->m_pkthdr.csum_data + 16) { 2878 IF_PREPEND(&ifp->if_snd, m_head); 2879 ifp->if_flags |= IFF_OACTIVE; 2880 break; 2881 } 2882 } 2883 2884 /* 2885 * Pack the data into the transmit ring. If we 2886 * don't have room, set the OACTIVE flag and wait 2887 * for the NIC to drain the ring. 2888 */ 2889 if (ti_encap(sc, m_head, &prodidx)) { 2890 IF_PREPEND(&ifp->if_snd, m_head); 2891 ifp->if_flags |= IFF_OACTIVE; 2892 break; 2893 } 2894 2895 /* 2896 * If there's a BPF listener, bounce a copy of this frame 2897 * to him. 2898 */ 2899 if (ifp->if_bpf) 2900 bpf_mtap(ifp, m_head); 2901 } 2902 2903 /* Transmit */ 2904 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2905 2906 /* 2907 * Set a timeout in case the chip goes out to lunch. 2908 */ 2909 ifp->if_timer = 5; 2910 TI_UNLOCK(sc); 2911 2912 return; 2913 } 2914 2915 static void 2916 ti_init(xsc) 2917 void *xsc; 2918 { 2919 struct ti_softc *sc = xsc; 2920 2921 /* Cancel pending I/O and flush buffers. */ 2922 ti_stop(sc); 2923 2924 TI_LOCK(sc); 2925 /* Init the gen info block, ring control blocks and firmware. */ 2926 if (ti_gibinit(sc)) { 2927 printf("ti%d: initialization failure\n", sc->ti_unit); 2928 TI_UNLOCK(sc); 2929 return; 2930 } 2931 2932 TI_UNLOCK(sc); 2933 2934 return; 2935 } 2936 2937 static void ti_init2(sc) 2938 struct ti_softc *sc; 2939 { 2940 struct ti_cmd_desc cmd; 2941 struct ifnet *ifp; 2942 u_int16_t *m; 2943 struct ifmedia *ifm; 2944 int tmp; 2945 2946 ifp = &sc->arpcom.ac_if; 2947 2948 /* Specify MTU and interface index. */ 2949 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2950 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2951 ETHER_HDR_LEN + ETHER_CRC_LEN); 2952 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2953 2954 /* Load our MAC address. */ 2955 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2956 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2957 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2958 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2959 2960 /* Enable or disable promiscuous mode as needed. */ 2961 if (ifp->if_flags & IFF_PROMISC) { 2962 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2963 } else { 2964 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2965 } 2966 2967 /* Program multicast filter. */ 2968 ti_setmulti(sc); 2969 2970 /* 2971 * If this is a Tigon 1, we should tell the 2972 * firmware to use software packet filtering. 2973 */ 2974 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2975 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2976 } 2977 2978 /* Init RX ring. */ 2979 ti_init_rx_ring_std(sc); 2980 2981 /* Init jumbo RX ring. */ 2982 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2983 ti_init_rx_ring_jumbo(sc); 2984 2985 /* 2986 * If this is a Tigon 2, we can also configure the 2987 * mini ring. 2988 */ 2989 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2990 ti_init_rx_ring_mini(sc); 2991 2992 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2993 sc->ti_rx_saved_considx = 0; 2994 2995 /* Init TX ring. */ 2996 ti_init_tx_ring(sc); 2997 2998 /* Tell firmware we're alive. */ 2999 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3000 3001 /* Enable host interrupts. */ 3002 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3003 3004 ifp->if_flags |= IFF_RUNNING; 3005 ifp->if_flags &= ~IFF_OACTIVE; 3006 3007 /* 3008 * Make sure to set media properly. We have to do this 3009 * here since we have to issue commands in order to set 3010 * the link negotiation and we can't issue commands until 3011 * the firmware is running. 3012 */ 3013 ifm = &sc->ifmedia; 3014 tmp = ifm->ifm_media; 3015 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3016 ti_ifmedia_upd(ifp); 3017 ifm->ifm_media = tmp; 3018 3019 return; 3020 } 3021 3022 /* 3023 * Set media options. 3024 */ 3025 static int 3026 ti_ifmedia_upd(ifp) 3027 struct ifnet *ifp; 3028 { 3029 struct ti_softc *sc; 3030 struct ifmedia *ifm; 3031 struct ti_cmd_desc cmd; 3032 u_int32_t flowctl; 3033 3034 sc = ifp->if_softc; 3035 ifm = &sc->ifmedia; 3036 3037 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3038 return(EINVAL); 3039 3040 flowctl = 0; 3041 3042 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3043 case IFM_AUTO: 3044 /* 3045 * Transmit flow control doesn't work on the Tigon 1. 3046 */ 3047 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3048 3049 /* 3050 * Transmit flow control can also cause problems on the 3051 * Tigon 2, apparantly with both the copper and fiber 3052 * boards. The symptom is that the interface will just 3053 * hang. This was reproduced with Alteon 180 switches. 3054 */ 3055 #if 0 3056 if (sc->ti_hwrev != TI_HWREV_TIGON) 3057 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3058 #endif 3059 3060 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3061 TI_GLNK_FULL_DUPLEX| flowctl | 3062 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3063 3064 flowctl = TI_LNK_RX_FLOWCTL_Y; 3065 #if 0 3066 if (sc->ti_hwrev != TI_HWREV_TIGON) 3067 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3068 #endif 3069 3070 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3071 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3072 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3073 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3074 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3075 break; 3076 case IFM_1000_SX: 3077 case IFM_1000_T: 3078 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3079 #if 0 3080 if (sc->ti_hwrev != TI_HWREV_TIGON) 3081 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3082 #endif 3083 3084 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3085 flowctl |TI_GLNK_ENB); 3086 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3087 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3088 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3089 } 3090 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3091 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3092 break; 3093 case IFM_100_FX: 3094 case IFM_10_FL: 3095 case IFM_100_TX: 3096 case IFM_10_T: 3097 flowctl = TI_LNK_RX_FLOWCTL_Y; 3098 #if 0 3099 if (sc->ti_hwrev != TI_HWREV_TIGON) 3100 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3101 #endif 3102 3103 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3104 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3105 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3106 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3107 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3108 } else { 3109 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3110 } 3111 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3112 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3113 } else { 3114 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3115 } 3116 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3117 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3118 break; 3119 } 3120 3121 return(0); 3122 } 3123 3124 /* 3125 * Report current media status. 3126 */ 3127 static void 3128 ti_ifmedia_sts(ifp, ifmr) 3129 struct ifnet *ifp; 3130 struct ifmediareq *ifmr; 3131 { 3132 struct ti_softc *sc; 3133 u_int32_t media = 0; 3134 3135 sc = ifp->if_softc; 3136 3137 ifmr->ifm_status = IFM_AVALID; 3138 ifmr->ifm_active = IFM_ETHER; 3139 3140 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3141 return; 3142 3143 ifmr->ifm_status |= IFM_ACTIVE; 3144 3145 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3146 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3147 if (sc->ti_copper) 3148 ifmr->ifm_active |= IFM_1000_T; 3149 else 3150 ifmr->ifm_active |= IFM_1000_SX; 3151 if (media & TI_GLNK_FULL_DUPLEX) 3152 ifmr->ifm_active |= IFM_FDX; 3153 else 3154 ifmr->ifm_active |= IFM_HDX; 3155 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3156 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3157 if (sc->ti_copper) { 3158 if (media & TI_LNK_100MB) 3159 ifmr->ifm_active |= IFM_100_TX; 3160 if (media & TI_LNK_10MB) 3161 ifmr->ifm_active |= IFM_10_T; 3162 } else { 3163 if (media & TI_LNK_100MB) 3164 ifmr->ifm_active |= IFM_100_FX; 3165 if (media & TI_LNK_10MB) 3166 ifmr->ifm_active |= IFM_10_FL; 3167 } 3168 if (media & TI_LNK_FULL_DUPLEX) 3169 ifmr->ifm_active |= IFM_FDX; 3170 if (media & TI_LNK_HALF_DUPLEX) 3171 ifmr->ifm_active |= IFM_HDX; 3172 } 3173 3174 return; 3175 } 3176 3177 static int 3178 ti_ioctl(ifp, command, data) 3179 struct ifnet *ifp; 3180 u_long command; 3181 caddr_t data; 3182 { 3183 struct ti_softc *sc = ifp->if_softc; 3184 struct ifreq *ifr = (struct ifreq *) data; 3185 int mask, error = 0; 3186 struct ti_cmd_desc cmd; 3187 3188 TI_LOCK(sc); 3189 3190 switch(command) { 3191 case SIOCSIFADDR: 3192 case SIOCGIFADDR: 3193 error = ether_ioctl(ifp, command, data); 3194 break; 3195 case SIOCSIFMTU: 3196 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3197 error = EINVAL; 3198 else { 3199 ifp->if_mtu = ifr->ifr_mtu; 3200 ti_init(sc); 3201 } 3202 break; 3203 case SIOCSIFFLAGS: 3204 if (ifp->if_flags & IFF_UP) { 3205 /* 3206 * If only the state of the PROMISC flag changed, 3207 * then just use the 'set promisc mode' command 3208 * instead of reinitializing the entire NIC. Doing 3209 * a full re-init means reloading the firmware and 3210 * waiting for it to start up, which may take a 3211 * second or two. 3212 */ 3213 if (ifp->if_flags & IFF_RUNNING && 3214 ifp->if_flags & IFF_PROMISC && 3215 !(sc->ti_if_flags & IFF_PROMISC)) { 3216 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3217 TI_CMD_CODE_PROMISC_ENB, 0); 3218 } else if (ifp->if_flags & IFF_RUNNING && 3219 !(ifp->if_flags & IFF_PROMISC) && 3220 sc->ti_if_flags & IFF_PROMISC) { 3221 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3222 TI_CMD_CODE_PROMISC_DIS, 0); 3223 } else 3224 ti_init(sc); 3225 } else { 3226 if (ifp->if_flags & IFF_RUNNING) { 3227 ti_stop(sc); 3228 } 3229 } 3230 sc->ti_if_flags = ifp->if_flags; 3231 error = 0; 3232 break; 3233 case SIOCADDMULTI: 3234 case SIOCDELMULTI: 3235 if (ifp->if_flags & IFF_RUNNING) { 3236 ti_setmulti(sc); 3237 error = 0; 3238 } 3239 break; 3240 case SIOCSIFMEDIA: 3241 case SIOCGIFMEDIA: 3242 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3243 break; 3244 case SIOCSIFCAP: 3245 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3246 if (mask & IFCAP_HWCSUM) { 3247 if (IFCAP_HWCSUM & ifp->if_capenable) 3248 ifp->if_capenable &= ~IFCAP_HWCSUM; 3249 else 3250 ifp->if_capenable |= IFCAP_HWCSUM; 3251 if (ifp->if_flags & IFF_RUNNING) 3252 ti_init(sc); 3253 } 3254 error = 0; 3255 break; 3256 default: 3257 error = EINVAL; 3258 break; 3259 } 3260 3261 TI_UNLOCK(sc); 3262 3263 return(error); 3264 } 3265 3266 static int 3267 ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3268 { 3269 int unit; 3270 struct ti_softc *sc; 3271 3272 unit = minor(dev) & 0xff; 3273 3274 sc = ti_lookup_softc(unit); 3275 3276 if (sc == NULL) 3277 return(ENODEV); 3278 3279 TI_LOCK(sc); 3280 sc->ti_flags |= TI_FLAG_DEBUGING; 3281 TI_UNLOCK(sc); 3282 3283 return(0); 3284 } 3285 3286 static int 3287 ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3288 { 3289 int unit; 3290 struct ti_softc *sc; 3291 3292 unit = minor(dev) & 0xff; 3293 3294 sc = ti_lookup_softc(unit); 3295 3296 if (sc == NULL) 3297 return(ENODEV); 3298 3299 TI_LOCK(sc); 3300 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3301 TI_UNLOCK(sc); 3302 3303 return(0); 3304 } 3305 3306 /* 3307 * This ioctl routine goes along with the Tigon character device. 3308 */ 3309 static int 3310 ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3311 { 3312 int unit, error; 3313 struct ti_softc *sc; 3314 3315 unit = minor(dev) & 0xff; 3316 3317 sc = ti_lookup_softc(unit); 3318 3319 if (sc == NULL) 3320 return(ENODEV); 3321 3322 error = 0; 3323 3324 switch(cmd) { 3325 case TIIOCGETSTATS: 3326 { 3327 struct ti_stats *outstats; 3328 3329 outstats = (struct ti_stats *)addr; 3330 3331 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3332 sizeof(struct ti_stats)); 3333 break; 3334 } 3335 case TIIOCGETPARAMS: 3336 { 3337 struct ti_params *params; 3338 3339 params = (struct ti_params *)addr; 3340 3341 params->ti_stat_ticks = sc->ti_stat_ticks; 3342 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3343 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3344 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3345 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3346 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3347 params->param_mask = TI_PARAM_ALL; 3348 3349 error = 0; 3350 3351 break; 3352 } 3353 case TIIOCSETPARAMS: 3354 { 3355 struct ti_params *params; 3356 3357 params = (struct ti_params *)addr; 3358 3359 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3360 sc->ti_stat_ticks = params->ti_stat_ticks; 3361 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3362 } 3363 3364 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3365 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3366 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3367 sc->ti_rx_coal_ticks); 3368 } 3369 3370 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3371 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3372 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3373 sc->ti_tx_coal_ticks); 3374 } 3375 3376 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3377 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3378 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3379 sc->ti_rx_max_coal_bds); 3380 } 3381 3382 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3383 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3384 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3385 sc->ti_tx_max_coal_bds); 3386 } 3387 3388 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3389 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3390 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3391 sc->ti_tx_buf_ratio); 3392 } 3393 3394 error = 0; 3395 3396 break; 3397 } 3398 case TIIOCSETTRACE: { 3399 ti_trace_type trace_type; 3400 3401 trace_type = *(ti_trace_type *)addr; 3402 3403 /* 3404 * Set tracing to whatever the user asked for. Setting 3405 * this register to 0 should have the effect of disabling 3406 * tracing. 3407 */ 3408 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3409 3410 error = 0; 3411 3412 break; 3413 } 3414 case TIIOCGETTRACE: { 3415 struct ti_trace_buf *trace_buf; 3416 u_int32_t trace_start, cur_trace_ptr, trace_len; 3417 3418 trace_buf = (struct ti_trace_buf *)addr; 3419 3420 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3421 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3422 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3423 3424 #if 0 3425 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3426 "trace_len = %d\n", sc->ti_unit, trace_start, 3427 cur_trace_ptr, trace_len); 3428 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3429 trace_buf->buf_len); 3430 #endif 3431 3432 error = ti_copy_mem(sc, trace_start, min(trace_len, 3433 trace_buf->buf_len), 3434 (caddr_t)trace_buf->buf, 1, 1); 3435 3436 if (error == 0) { 3437 trace_buf->fill_len = min(trace_len, 3438 trace_buf->buf_len); 3439 if (cur_trace_ptr < trace_start) 3440 trace_buf->cur_trace_ptr = 3441 trace_start - cur_trace_ptr; 3442 else 3443 trace_buf->cur_trace_ptr = 3444 cur_trace_ptr - trace_start; 3445 } else 3446 trace_buf->fill_len = 0; 3447 3448 3449 break; 3450 } 3451 3452 /* 3453 * For debugging, five ioctls are needed: 3454 * ALT_ATTACH 3455 * ALT_READ_TG_REG 3456 * ALT_WRITE_TG_REG 3457 * ALT_READ_TG_MEM 3458 * ALT_WRITE_TG_MEM 3459 */ 3460 case ALT_ATTACH: 3461 /* 3462 * From what I can tell, Alteon's Solaris Tigon driver 3463 * only has one character device, so you have to attach 3464 * to the Tigon board you're interested in. This seems 3465 * like a not-so-good way to do things, since unless you 3466 * subsequently specify the unit number of the device 3467 * you're interested in in every ioctl, you'll only be 3468 * able to debug one board at a time. 3469 */ 3470 error = 0; 3471 break; 3472 case ALT_READ_TG_MEM: 3473 case ALT_WRITE_TG_MEM: 3474 { 3475 struct tg_mem *mem_param; 3476 u_int32_t sram_end, scratch_end; 3477 3478 mem_param = (struct tg_mem *)addr; 3479 3480 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3481 sram_end = TI_END_SRAM_I; 3482 scratch_end = TI_END_SCRATCH_I; 3483 } else { 3484 sram_end = TI_END_SRAM_II; 3485 scratch_end = TI_END_SCRATCH_II; 3486 } 3487 3488 /* 3489 * For now, we'll only handle accessing regular SRAM, 3490 * nothing else. 3491 */ 3492 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3493 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3494 /* 3495 * In this instance, we always copy to/from user 3496 * space, so the user space argument is set to 1. 3497 */ 3498 error = ti_copy_mem(sc, mem_param->tgAddr, 3499 mem_param->len, 3500 mem_param->userAddr, 1, 3501 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3502 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3503 && (mem_param->tgAddr <= scratch_end)) { 3504 error = ti_copy_scratch(sc, mem_param->tgAddr, 3505 mem_param->len, 3506 mem_param->userAddr, 1, 3507 (cmd == ALT_READ_TG_MEM) ? 3508 1 : 0, TI_PROCESSOR_A); 3509 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3510 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3511 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3512 printf("ti%d: invalid memory range for " 3513 "Tigon I\n", sc->ti_unit); 3514 error = EINVAL; 3515 break; 3516 } 3517 error = ti_copy_scratch(sc, mem_param->tgAddr - 3518 TI_SCRATCH_DEBUG_OFF, 3519 mem_param->len, 3520 mem_param->userAddr, 1, 3521 (cmd == ALT_READ_TG_MEM) ? 3522 1 : 0, TI_PROCESSOR_B); 3523 } else { 3524 printf("ti%d: memory address %#x len %d is out of " 3525 "supported range\n", sc->ti_unit, 3526 mem_param->tgAddr, mem_param->len); 3527 error = EINVAL; 3528 } 3529 3530 break; 3531 } 3532 case ALT_READ_TG_REG: 3533 case ALT_WRITE_TG_REG: 3534 { 3535 struct tg_reg *regs; 3536 u_int32_t tmpval; 3537 3538 regs = (struct tg_reg *)addr; 3539 3540 /* 3541 * Make sure the address in question isn't out of range. 3542 */ 3543 if (regs->addr > TI_REG_MAX) { 3544 error = EINVAL; 3545 break; 3546 } 3547 if (cmd == ALT_READ_TG_REG) { 3548 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3549 regs->addr, &tmpval, 1); 3550 regs->data = ntohl(tmpval); 3551 #if 0 3552 if ((regs->addr == TI_CPU_STATE) 3553 || (regs->addr == TI_CPU_CTL_B)) { 3554 printf("ti%d: register %#x = %#x\n", 3555 sc->ti_unit, regs->addr, tmpval); 3556 } 3557 #endif 3558 } else { 3559 tmpval = htonl(regs->data); 3560 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3561 regs->addr, &tmpval, 1); 3562 } 3563 3564 break; 3565 } 3566 default: 3567 error = ENOTTY; 3568 break; 3569 } 3570 return(error); 3571 } 3572 3573 static void 3574 ti_watchdog(ifp) 3575 struct ifnet *ifp; 3576 { 3577 struct ti_softc *sc; 3578 3579 sc = ifp->if_softc; 3580 TI_LOCK(sc); 3581 3582 /* 3583 * When we're debugging, the chip is often stopped for long periods 3584 * of time, and that would normally cause the watchdog timer to fire. 3585 * Since that impedes debugging, we don't want to do that. 3586 */ 3587 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3588 TI_UNLOCK(sc); 3589 return; 3590 } 3591 3592 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3593 ti_stop(sc); 3594 ti_init(sc); 3595 3596 ifp->if_oerrors++; 3597 TI_UNLOCK(sc); 3598 3599 return; 3600 } 3601 3602 /* 3603 * Stop the adapter and free any mbufs allocated to the 3604 * RX and TX lists. 3605 */ 3606 static void 3607 ti_stop(sc) 3608 struct ti_softc *sc; 3609 { 3610 struct ifnet *ifp; 3611 struct ti_cmd_desc cmd; 3612 3613 TI_LOCK(sc); 3614 3615 ifp = &sc->arpcom.ac_if; 3616 3617 /* Disable host interrupts. */ 3618 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3619 /* 3620 * Tell firmware we're shutting down. 3621 */ 3622 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3623 3624 /* Halt and reinitialize. */ 3625 ti_chipinit(sc); 3626 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3627 ti_chipinit(sc); 3628 3629 /* Free the RX lists. */ 3630 ti_free_rx_ring_std(sc); 3631 3632 /* Free jumbo RX list. */ 3633 ti_free_rx_ring_jumbo(sc); 3634 3635 /* Free mini RX list. */ 3636 ti_free_rx_ring_mini(sc); 3637 3638 /* Free TX buffers. */ 3639 ti_free_tx_ring(sc); 3640 3641 sc->ti_ev_prodidx.ti_idx = 0; 3642 sc->ti_return_prodidx.ti_idx = 0; 3643 sc->ti_tx_considx.ti_idx = 0; 3644 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3645 3646 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3647 TI_UNLOCK(sc); 3648 3649 return; 3650 } 3651 3652 /* 3653 * Stop all chip I/O so that the kernel's probe routines don't 3654 * get confused by errant DMAs when rebooting. 3655 */ 3656 static void 3657 ti_shutdown(dev) 3658 device_t dev; 3659 { 3660 struct ti_softc *sc; 3661 3662 sc = device_get_softc(dev); 3663 TI_LOCK(sc); 3664 ti_chipinit(sc); 3665 TI_UNLOCK(sc); 3666 3667 return; 3668 } 3669