1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 #include <sys/sf_buf.h> 95 96 #include <net/if.h> 97 #include <net/if_var.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_types.h> 103 #include <net/if_vlan_var.h> 104 105 #include <net/bpf.h> 106 107 #include <netinet/in_systm.h> 108 #include <netinet/in.h> 109 #include <netinet/ip.h> 110 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #ifdef TI_SF_BUF_JUMBO 117 #include <vm/vm.h> 118 #include <vm/vm_page.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 124 #include <sys/tiio.h> 125 #include <dev/ti/if_tireg.h> 126 #include <dev/ti/ti_fw.h> 127 #include <dev/ti/ti_fw2.h> 128 129 #include <sys/sysctl.h> 130 131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 /* 133 * We can only turn on header splitting if we're using extended receive 134 * BDs. 135 */ 136 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 137 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 138 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 139 140 typedef enum { 141 TI_SWAP_HTON, 142 TI_SWAP_NTOH 143 } ti_swap_type; 144 145 /* 146 * Various supported device vendors/types and their names. 147 */ 148 149 static const struct ti_type ti_devs[] = { 150 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 151 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 152 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 153 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 154 { TC_VENDORID, TC_DEVICEID_3C985, 155 "3Com 3c985-SX Gigabit Ethernet" }, 156 { NG_VENDORID, NG_DEVICEID_GA620, 157 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 158 { NG_VENDORID, NG_DEVICEID_GA620T, 159 "Netgear GA620 1000baseT Gigabit Ethernet" }, 160 { SGI_VENDORID, SGI_DEVICEID_TIGON, 161 "Silicon Graphics Gigabit Ethernet" }, 162 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 163 "Farallon PN9000SX Gigabit Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 168 static d_open_t ti_open; 169 static d_close_t ti_close; 170 static d_ioctl_t ti_ioctl2; 171 172 static struct cdevsw ti_cdevsw = { 173 .d_version = D_VERSION, 174 .d_flags = 0, 175 .d_open = ti_open, 176 .d_close = ti_close, 177 .d_ioctl = ti_ioctl2, 178 .d_name = "ti", 179 }; 180 181 static int ti_probe(device_t); 182 static int ti_attach(device_t); 183 static int ti_detach(device_t); 184 static void ti_txeof(struct ti_softc *); 185 static void ti_rxeof(struct ti_softc *); 186 187 static void ti_stats_update(struct ti_softc *); 188 static int ti_encap(struct ti_softc *, struct mbuf **); 189 190 static void ti_intr(void *); 191 static void ti_start(struct ifnet *); 192 static void ti_start_locked(struct ifnet *); 193 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 194 static void ti_init(void *); 195 static void ti_init_locked(void *); 196 static void ti_init2(struct ti_softc *); 197 static void ti_stop(struct ti_softc *); 198 static void ti_watchdog(void *); 199 static int ti_shutdown(device_t); 200 static int ti_ifmedia_upd(struct ifnet *); 201 static int ti_ifmedia_upd_locked(struct ti_softc *); 202 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203 204 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 205 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 206 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 207 208 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 209 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 210 static void ti_setmulti(struct ti_softc *); 211 212 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 213 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 214 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 215 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 216 int); 217 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 218 int, int, int); 219 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 220 static void ti_loadfw(struct ti_softc *); 221 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 222 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 223 static void ti_handle_events(struct ti_softc *); 224 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 225 static int ti_dma_alloc(struct ti_softc *); 226 static void ti_dma_free(struct ti_softc *); 227 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 228 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 229 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 230 bus_dmamap_t *); 231 static int ti_newbuf_std(struct ti_softc *, int); 232 static int ti_newbuf_mini(struct ti_softc *, int); 233 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 234 static int ti_init_rx_ring_std(struct ti_softc *); 235 static void ti_free_rx_ring_std(struct ti_softc *); 236 static int ti_init_rx_ring_jumbo(struct ti_softc *); 237 static void ti_free_rx_ring_jumbo(struct ti_softc *); 238 static int ti_init_rx_ring_mini(struct ti_softc *); 239 static void ti_free_rx_ring_mini(struct ti_softc *); 240 static void ti_free_tx_ring(struct ti_softc *); 241 static int ti_init_tx_ring(struct ti_softc *); 242 static void ti_discard_std(struct ti_softc *, int); 243 #ifndef TI_SF_BUF_JUMBO 244 static void ti_discard_jumbo(struct ti_softc *, int); 245 #endif 246 static void ti_discard_mini(struct ti_softc *, int); 247 248 static int ti_64bitslot_war(struct ti_softc *); 249 static int ti_chipinit(struct ti_softc *); 250 static int ti_gibinit(struct ti_softc *); 251 252 #ifdef TI_JUMBO_HDRSPLIT 253 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 254 int idx); 255 #endif /* TI_JUMBO_HDRSPLIT */ 256 257 static void ti_sysctl_node(struct ti_softc *); 258 259 static device_method_t ti_methods[] = { 260 /* Device interface */ 261 DEVMETHOD(device_probe, ti_probe), 262 DEVMETHOD(device_attach, ti_attach), 263 DEVMETHOD(device_detach, ti_detach), 264 DEVMETHOD(device_shutdown, ti_shutdown), 265 { 0, 0 } 266 }; 267 268 static driver_t ti_driver = { 269 "ti", 270 ti_methods, 271 sizeof(struct ti_softc) 272 }; 273 274 static devclass_t ti_devclass; 275 276 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 277 MODULE_DEPEND(ti, pci, 1, 1, 1); 278 MODULE_DEPEND(ti, ether, 1, 1, 1); 279 280 /* 281 * Send an instruction or address to the EEPROM, check for ACK. 282 */ 283 static uint32_t 284 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 285 { 286 int i, ack = 0; 287 288 /* 289 * Make sure we're in TX mode. 290 */ 291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 292 293 /* 294 * Feed in each bit and stobe the clock. 295 */ 296 for (i = 0x80; i; i >>= 1) { 297 if (byte & i) { 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 299 } else { 300 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 301 } 302 DELAY(1); 303 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 304 DELAY(1); 305 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 } 307 308 /* 309 * Turn off TX mode. 310 */ 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 312 313 /* 314 * Check for ack. 315 */ 316 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 317 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 319 320 return (ack); 321 } 322 323 /* 324 * Read a byte of data stored in the EEPROM at address 'addr.' 325 * We have to send two address bytes since the EEPROM can hold 326 * more than 256 bytes of data. 327 */ 328 static uint8_t 329 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 330 { 331 int i; 332 uint8_t byte = 0; 333 334 EEPROM_START; 335 336 /* 337 * Send write control code to EEPROM. 338 */ 339 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 340 device_printf(sc->ti_dev, 341 "failed to send write command, status: %x\n", 342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 343 return (1); 344 } 345 346 /* 347 * Send first byte of address of byte we want to read. 348 */ 349 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 350 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 351 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 352 return (1); 353 } 354 /* 355 * Send second byte address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 358 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return (1); 361 } 362 363 EEPROM_STOP; 364 EEPROM_START; 365 /* 366 * Send read control code to EEPROM. 367 */ 368 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 369 device_printf(sc->ti_dev, 370 "failed to send read command, status: %x\n", 371 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 372 return (1); 373 } 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 379 for (i = 0x80; i; i >>= 1) { 380 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 381 DELAY(1); 382 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 383 byte |= i; 384 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 385 DELAY(1); 386 } 387 388 EEPROM_STOP; 389 390 /* 391 * No ACK generated for read, so just return byte. 392 */ 393 394 *dest = byte; 395 396 return (0); 397 } 398 399 /* 400 * Read a sequence of bytes from the EEPROM. 401 */ 402 static int 403 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 404 { 405 int err = 0, i; 406 uint8_t byte = 0; 407 408 for (i = 0; i < cnt; i++) { 409 err = ti_eeprom_getbyte(sc, off + i, &byte); 410 if (err) 411 break; 412 *(dest + i) = byte; 413 } 414 415 return (err ? 1 : 0); 416 } 417 418 /* 419 * NIC memory read function. 420 * Can be used to copy data from NIC local memory. 421 */ 422 static void 423 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 424 { 425 int segptr, segsize, cnt; 426 char *ptr; 427 428 segptr = addr; 429 cnt = len; 430 ptr = buf; 431 432 while (cnt) { 433 if (cnt < TI_WINLEN) 434 segsize = cnt; 435 else 436 segsize = TI_WINLEN - (segptr % TI_WINLEN); 437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 440 segsize / 4); 441 ptr += segsize; 442 segptr += segsize; 443 cnt -= segsize; 444 } 445 } 446 447 448 /* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452 static void 453 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 454 { 455 int segptr, segsize, cnt; 456 char *ptr; 457 458 segptr = addr; 459 cnt = len; 460 ptr = buf; 461 462 while (cnt) { 463 if (cnt < TI_WINLEN) 464 segsize = cnt; 465 else 466 segsize = TI_WINLEN - (segptr % TI_WINLEN); 467 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 468 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 469 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 470 segsize / 4); 471 ptr += segsize; 472 segptr += segsize; 473 cnt -= segsize; 474 } 475 } 476 477 /* 478 * NIC memory read function. 479 * Can be used to clear a section of NIC local memory. 480 */ 481 static void 482 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 483 { 484 int segptr, segsize, cnt; 485 486 segptr = addr; 487 cnt = len; 488 489 while (cnt) { 490 if (cnt < TI_WINLEN) 491 segsize = cnt; 492 else 493 segsize = TI_WINLEN - (segptr % TI_WINLEN); 494 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 495 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 496 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 497 segptr += segsize; 498 cnt -= segsize; 499 } 500 } 501 502 static int 503 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 504 caddr_t buf, int useraddr, int readdata) 505 { 506 int segptr, segsize, cnt; 507 caddr_t ptr; 508 uint32_t origwin; 509 int resid, segresid; 510 int first_pass; 511 512 TI_LOCK_ASSERT(sc); 513 514 /* 515 * At the moment, we don't handle non-aligned cases, we just bail. 516 * If this proves to be a problem, it will be fixed. 517 */ 518 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 519 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 520 "word-aligned\n", __func__, tigon_addr); 521 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 522 "yet supported\n", __func__); 523 return (EINVAL); 524 } 525 526 segptr = tigon_addr & ~0x3; 527 segresid = tigon_addr - segptr; 528 529 /* 530 * This is the non-aligned amount left over that we'll need to 531 * copy. 532 */ 533 resid = len & 0x3; 534 535 /* Add in the left over amount at the front of the buffer */ 536 resid += segresid; 537 538 cnt = len & ~0x3; 539 /* 540 * If resid + segresid is >= 4, add multiples of 4 to the count and 541 * decrease the residual by that much. 542 */ 543 cnt += resid & ~0x3; 544 resid -= resid & ~0x3; 545 546 ptr = buf; 547 548 first_pass = 1; 549 550 /* 551 * Save the old window base value. 552 */ 553 origwin = CSR_READ_4(sc, TI_WINBASE); 554 555 while (cnt) { 556 bus_size_t ti_offset; 557 558 if (cnt < TI_WINLEN) 559 segsize = cnt; 560 else 561 segsize = TI_WINLEN - (segptr % TI_WINLEN); 562 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 563 564 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 565 566 if (readdata) { 567 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 568 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 569 if (useraddr) { 570 /* 571 * Yeah, this is a little on the kludgy 572 * side, but at least this code is only 573 * used for debugging. 574 */ 575 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 576 segsize, TI_SWAP_NTOH); 577 578 TI_UNLOCK(sc); 579 if (first_pass) { 580 copyout(&sc->ti_membuf2[segresid], ptr, 581 segsize - segresid); 582 first_pass = 0; 583 } else 584 copyout(sc->ti_membuf2, ptr, segsize); 585 TI_LOCK(sc); 586 } else { 587 if (first_pass) { 588 589 ti_bcopy_swap(sc->ti_membuf, 590 sc->ti_membuf2, segsize, 591 TI_SWAP_NTOH); 592 TI_UNLOCK(sc); 593 bcopy(&sc->ti_membuf2[segresid], ptr, 594 segsize - segresid); 595 TI_LOCK(sc); 596 first_pass = 0; 597 } else 598 ti_bcopy_swap(sc->ti_membuf, ptr, 599 segsize, TI_SWAP_NTOH); 600 } 601 602 } else { 603 if (useraddr) { 604 TI_UNLOCK(sc); 605 copyin(ptr, sc->ti_membuf2, segsize); 606 TI_LOCK(sc); 607 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 608 segsize, TI_SWAP_HTON); 609 } else 610 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 611 TI_SWAP_HTON); 612 613 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 614 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 615 } 616 segptr += segsize; 617 ptr += segsize; 618 cnt -= segsize; 619 } 620 621 /* 622 * Handle leftover, non-word-aligned bytes. 623 */ 624 if (resid != 0) { 625 uint32_t tmpval, tmpval2; 626 bus_size_t ti_offset; 627 628 /* 629 * Set the segment pointer. 630 */ 631 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 632 633 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 634 635 /* 636 * First, grab whatever is in our source/destination. 637 * We'll obviously need this for reads, but also for 638 * writes, since we'll be doing read/modify/write. 639 */ 640 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 641 ti_offset, &tmpval, 1); 642 643 /* 644 * Next, translate this from little-endian to big-endian 645 * (at least on i386 boxes). 646 */ 647 tmpval2 = ntohl(tmpval); 648 649 if (readdata) { 650 /* 651 * If we're reading, just copy the leftover number 652 * of bytes from the host byte order buffer to 653 * the user's buffer. 654 */ 655 if (useraddr) { 656 TI_UNLOCK(sc); 657 copyout(&tmpval2, ptr, resid); 658 TI_LOCK(sc); 659 } else 660 bcopy(&tmpval2, ptr, resid); 661 } else { 662 /* 663 * If we're writing, first copy the bytes to be 664 * written into the network byte order buffer, 665 * leaving the rest of the buffer with whatever was 666 * originally in there. Then, swap the bytes 667 * around into host order and write them out. 668 * 669 * XXX KDM the read side of this has been verified 670 * to work, but the write side of it has not been 671 * verified. So user beware. 672 */ 673 if (useraddr) { 674 TI_UNLOCK(sc); 675 copyin(ptr, &tmpval2, resid); 676 TI_LOCK(sc); 677 } else 678 bcopy(ptr, &tmpval2, resid); 679 680 tmpval = htonl(tmpval2); 681 682 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 683 ti_offset, &tmpval, 1); 684 } 685 } 686 687 CSR_WRITE_4(sc, TI_WINBASE, origwin); 688 689 return (0); 690 } 691 692 static int 693 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 694 caddr_t buf, int useraddr, int readdata, int cpu) 695 { 696 uint32_t segptr; 697 int cnt; 698 uint32_t tmpval, tmpval2; 699 caddr_t ptr; 700 701 TI_LOCK_ASSERT(sc); 702 703 /* 704 * At the moment, we don't handle non-aligned cases, we just bail. 705 * If this proves to be a problem, it will be fixed. 706 */ 707 if (tigon_addr & 0x3) { 708 device_printf(sc->ti_dev, "%s: tigon address %#x " 709 "isn't word-aligned\n", __func__, tigon_addr); 710 return (EINVAL); 711 } 712 713 if (len & 0x3) { 714 device_printf(sc->ti_dev, "%s: transfer length %d " 715 "isn't word-aligned\n", __func__, len); 716 return (EINVAL); 717 } 718 719 segptr = tigon_addr; 720 cnt = len; 721 ptr = buf; 722 723 while (cnt) { 724 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 725 726 if (readdata) { 727 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 728 729 tmpval = ntohl(tmpval2); 730 731 /* 732 * Note: I've used this debugging interface 733 * extensively with Alteon's 12.3.15 firmware, 734 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 735 * 736 * When you compile the firmware without 737 * optimization, which is necessary sometimes in 738 * order to properly step through it, you sometimes 739 * read out a bogus value of 0xc0017c instead of 740 * whatever was supposed to be in that scratchpad 741 * location. That value is on the stack somewhere, 742 * but I've never been able to figure out what was 743 * causing the problem. 744 * 745 * The address seems to pop up in random places, 746 * often not in the same place on two subsequent 747 * reads. 748 * 749 * In any case, the underlying data doesn't seem 750 * to be affected, just the value read out. 751 * 752 * KDM, 3/7/2000 753 */ 754 755 if (tmpval2 == 0xc0017c) 756 device_printf(sc->ti_dev, "found 0xc0017c at " 757 "%#x (tmpval2)\n", segptr); 758 759 if (tmpval == 0xc0017c) 760 device_printf(sc->ti_dev, "found 0xc0017c at " 761 "%#x (tmpval)\n", segptr); 762 763 if (useraddr) 764 copyout(&tmpval, ptr, 4); 765 else 766 bcopy(&tmpval, ptr, 4); 767 } else { 768 if (useraddr) 769 copyin(ptr, &tmpval2, 4); 770 else 771 bcopy(ptr, &tmpval2, 4); 772 773 tmpval = htonl(tmpval2); 774 775 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 776 } 777 778 cnt -= 4; 779 segptr += 4; 780 ptr += 4; 781 } 782 783 return (0); 784 } 785 786 static int 787 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 788 { 789 const uint8_t *tmpsrc; 790 uint8_t *tmpdst; 791 size_t tmplen; 792 793 if (len & 0x3) { 794 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 795 return (-1); 796 } 797 798 tmpsrc = src; 799 tmpdst = dst; 800 tmplen = len; 801 802 while (tmplen) { 803 if (swap_type == TI_SWAP_NTOH) 804 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 805 else 806 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 807 tmpsrc += 4; 808 tmpdst += 4; 809 tmplen -= 4; 810 } 811 812 return (0); 813 } 814 815 /* 816 * Load firmware image into the NIC. Check that the firmware revision 817 * is acceptable and see if we want the firmware for the Tigon 1 or 818 * Tigon 2. 819 */ 820 static void 821 ti_loadfw(struct ti_softc *sc) 822 { 823 824 TI_LOCK_ASSERT(sc); 825 826 switch (sc->ti_hwrev) { 827 case TI_HWREV_TIGON: 828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 830 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 831 device_printf(sc->ti_dev, "firmware revision mismatch; " 832 "want %d.%d.%d, got %d.%d.%d\n", 833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 834 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 835 tigonFwReleaseMinor, tigonFwReleaseFix); 836 return; 837 } 838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 841 tigonFwRodata); 842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 845 break; 846 case TI_HWREV_TIGON_II: 847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 850 device_printf(sc->ti_dev, "firmware revision mismatch; " 851 "want %d.%d.%d, got %d.%d.%d\n", 852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 854 tigon2FwReleaseMinor, tigon2FwReleaseFix); 855 return; 856 } 857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 858 tigon2FwText); 859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 860 tigon2FwData); 861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 862 tigon2FwRodata); 863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 866 break; 867 default: 868 device_printf(sc->ti_dev, 869 "can't load firmware: unknown hardware rev\n"); 870 break; 871 } 872 } 873 874 /* 875 * Send the NIC a command via the command ring. 876 */ 877 static void 878 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 879 { 880 int index; 881 882 index = sc->ti_cmd_saved_prodidx; 883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 884 TI_INC(index, TI_CMD_RING_CNT); 885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 886 sc->ti_cmd_saved_prodidx = index; 887 } 888 889 /* 890 * Send the NIC an extended command. The 'len' parameter specifies the 891 * number of command slots to include after the initial command. 892 */ 893 static void 894 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 895 { 896 int index; 897 int i; 898 899 index = sc->ti_cmd_saved_prodidx; 900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 901 TI_INC(index, TI_CMD_RING_CNT); 902 for (i = 0; i < len; i++) { 903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 904 *(uint32_t *)(&arg[i * 4])); 905 TI_INC(index, TI_CMD_RING_CNT); 906 } 907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 908 sc->ti_cmd_saved_prodidx = index; 909 } 910 911 /* 912 * Handle events that have triggered interrupts. 913 */ 914 static void 915 ti_handle_events(struct ti_softc *sc) 916 { 917 struct ti_event_desc *e; 918 919 if (sc->ti_rdata.ti_event_ring == NULL) 920 return; 921 922 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 923 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 924 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 925 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 926 switch (TI_EVENT_EVENT(e)) { 927 case TI_EV_LINKSTAT_CHANGED: 928 sc->ti_linkstat = TI_EVENT_CODE(e); 929 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 930 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 931 sc->ti_ifp->if_baudrate = IF_Mbps(100); 932 if (bootverbose) 933 device_printf(sc->ti_dev, 934 "10/100 link up\n"); 935 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 936 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 937 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 938 if (bootverbose) 939 device_printf(sc->ti_dev, 940 "gigabit link up\n"); 941 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 942 if_link_state_change(sc->ti_ifp, 943 LINK_STATE_DOWN); 944 sc->ti_ifp->if_baudrate = 0; 945 if (bootverbose) 946 device_printf(sc->ti_dev, 947 "link down\n"); 948 } 949 break; 950 case TI_EV_ERROR: 951 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 952 device_printf(sc->ti_dev, "invalid command\n"); 953 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 954 device_printf(sc->ti_dev, "unknown command\n"); 955 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 956 device_printf(sc->ti_dev, "bad config data\n"); 957 break; 958 case TI_EV_FIRMWARE_UP: 959 ti_init2(sc); 960 break; 961 case TI_EV_STATS_UPDATED: 962 ti_stats_update(sc); 963 break; 964 case TI_EV_RESET_JUMBO_RING: 965 case TI_EV_MCAST_UPDATED: 966 /* Who cares. */ 967 break; 968 default: 969 device_printf(sc->ti_dev, "unknown event: %d\n", 970 TI_EVENT_EVENT(e)); 971 break; 972 } 973 /* Advance the consumer index. */ 974 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 975 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 976 } 977 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 978 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 979 } 980 981 struct ti_dmamap_arg { 982 bus_addr_t ti_busaddr; 983 }; 984 985 static void 986 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 987 { 988 struct ti_dmamap_arg *ctx; 989 990 if (error) 991 return; 992 993 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 994 995 ctx = arg; 996 ctx->ti_busaddr = segs->ds_addr; 997 } 998 999 static int 1000 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1001 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1002 const char *msg) 1003 { 1004 struct ti_dmamap_arg ctx; 1005 int error; 1006 1007 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1008 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1009 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1010 if (error != 0) { 1011 device_printf(sc->ti_dev, 1012 "could not create %s dma tag\n", msg); 1013 return (error); 1014 } 1015 /* Allocate DMA'able memory for ring. */ 1016 error = bus_dmamem_alloc(*tag, (void **)ring, 1017 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1018 if (error != 0) { 1019 device_printf(sc->ti_dev, 1020 "could not allocate DMA'able memory for %s\n", msg); 1021 return (error); 1022 } 1023 /* Load the address of the ring. */ 1024 ctx.ti_busaddr = 0; 1025 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1026 &ctx, BUS_DMA_NOWAIT); 1027 if (error != 0) { 1028 device_printf(sc->ti_dev, 1029 "could not load DMA'able memory for %s\n", msg); 1030 return (error); 1031 } 1032 *paddr = ctx.ti_busaddr; 1033 return (0); 1034 } 1035 1036 static void 1037 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1038 bus_dmamap_t *map) 1039 { 1040 1041 if (*map != NULL) 1042 bus_dmamap_unload(*tag, *map); 1043 if (*map != NULL && *ring != NULL) { 1044 bus_dmamem_free(*tag, *ring, *map); 1045 *ring = NULL; 1046 *map = NULL; 1047 } 1048 if (*tag) { 1049 bus_dma_tag_destroy(*tag); 1050 *tag = NULL; 1051 } 1052 } 1053 1054 static int 1055 ti_dma_alloc(struct ti_softc *sc) 1056 { 1057 bus_addr_t lowaddr; 1058 int i, error; 1059 1060 lowaddr = BUS_SPACE_MAXADDR; 1061 if (sc->ti_dac == 0) 1062 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1063 1064 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1065 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1066 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1067 &sc->ti_cdata.ti_parent_tag); 1068 if (error != 0) { 1069 device_printf(sc->ti_dev, 1070 "could not allocate parent dma tag\n"); 1071 return (ENOMEM); 1072 } 1073 1074 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1075 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1076 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1077 if (error) 1078 return (error); 1079 1080 /* Producer/consumer status */ 1081 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1082 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1083 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1084 "event ring"); 1085 if (error) 1086 return (error); 1087 1088 /* Event ring */ 1089 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1090 &sc->ti_cdata.ti_event_ring_tag, 1091 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1092 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1093 "event ring"); 1094 if (error) 1095 return (error); 1096 1097 /* Command ring lives in shared memory so no need to create DMA area. */ 1098 1099 /* Standard RX ring */ 1100 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1101 &sc->ti_cdata.ti_rx_std_ring_tag, 1102 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1103 &sc->ti_cdata.ti_rx_std_ring_map, 1104 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1105 if (error) 1106 return (error); 1107 1108 /* Jumbo RX ring */ 1109 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1110 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1111 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1112 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1113 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1114 if (error) 1115 return (error); 1116 1117 /* RX return ring */ 1118 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1119 &sc->ti_cdata.ti_rx_return_ring_tag, 1120 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1121 &sc->ti_cdata.ti_rx_return_ring_map, 1122 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1123 if (error) 1124 return (error); 1125 1126 /* Create DMA tag for standard RX mbufs. */ 1127 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1128 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1129 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1130 if (error) { 1131 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1132 return (error); 1133 } 1134 1135 /* Create DMA tag for jumbo RX mbufs. */ 1136 #ifdef TI_SF_BUF_JUMBO 1137 /* 1138 * The VM system will take care of providing aligned pages. Alignment 1139 * is set to 1 here so that busdma resources won't be wasted. 1140 */ 1141 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1142 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1143 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1144 #else 1145 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1146 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1147 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1148 #endif 1149 if (error) { 1150 device_printf(sc->ti_dev, 1151 "could not allocate jumbo RX dma tag\n"); 1152 return (error); 1153 } 1154 1155 /* Create DMA tag for TX mbufs. */ 1156 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1157 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1158 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1159 &sc->ti_cdata.ti_tx_tag); 1160 if (error) { 1161 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1162 return (ENOMEM); 1163 } 1164 1165 /* Create DMA maps for RX buffers. */ 1166 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1167 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1168 &sc->ti_cdata.ti_rx_std_maps[i]); 1169 if (error) { 1170 device_printf(sc->ti_dev, 1171 "could not create DMA map for RX\n"); 1172 return (error); 1173 } 1174 } 1175 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1176 &sc->ti_cdata.ti_rx_std_sparemap); 1177 if (error) { 1178 device_printf(sc->ti_dev, 1179 "could not create spare DMA map for RX\n"); 1180 return (error); 1181 } 1182 1183 /* Create DMA maps for jumbo RX buffers. */ 1184 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1185 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1186 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1187 if (error) { 1188 device_printf(sc->ti_dev, 1189 "could not create DMA map for jumbo RX\n"); 1190 return (error); 1191 } 1192 } 1193 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1194 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1195 if (error) { 1196 device_printf(sc->ti_dev, 1197 "could not create spare DMA map for jumbo RX\n"); 1198 return (error); 1199 } 1200 1201 /* Create DMA maps for TX buffers. */ 1202 for (i = 0; i < TI_TX_RING_CNT; i++) { 1203 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1204 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1205 if (error) { 1206 device_printf(sc->ti_dev, 1207 "could not create DMA map for TX\n"); 1208 return (ENOMEM); 1209 } 1210 } 1211 1212 /* Mini ring and TX ring is not available on Tigon 1. */ 1213 if (sc->ti_hwrev == TI_HWREV_TIGON) 1214 return (0); 1215 1216 /* TX ring */ 1217 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1218 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1219 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1220 "TX ring"); 1221 if (error) 1222 return (error); 1223 1224 /* Mini RX ring */ 1225 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1226 &sc->ti_cdata.ti_rx_mini_ring_tag, 1227 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1228 &sc->ti_cdata.ti_rx_mini_ring_map, 1229 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1230 if (error) 1231 return (error); 1232 1233 /* Create DMA tag for mini RX mbufs. */ 1234 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1236 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1237 if (error) { 1238 device_printf(sc->ti_dev, 1239 "could not allocate mini RX dma tag\n"); 1240 return (error); 1241 } 1242 1243 /* Create DMA maps for mini RX buffers. */ 1244 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1245 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1246 &sc->ti_cdata.ti_rx_mini_maps[i]); 1247 if (error) { 1248 device_printf(sc->ti_dev, 1249 "could not create DMA map for mini RX\n"); 1250 return (error); 1251 } 1252 } 1253 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1254 &sc->ti_cdata.ti_rx_mini_sparemap); 1255 if (error) { 1256 device_printf(sc->ti_dev, 1257 "could not create spare DMA map for mini RX\n"); 1258 return (error); 1259 } 1260 1261 return (0); 1262 } 1263 1264 static void 1265 ti_dma_free(struct ti_softc *sc) 1266 { 1267 int i; 1268 1269 /* Destroy DMA maps for RX buffers. */ 1270 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1271 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1272 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1273 sc->ti_cdata.ti_rx_std_maps[i]); 1274 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1275 } 1276 } 1277 if (sc->ti_cdata.ti_rx_std_sparemap) { 1278 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1279 sc->ti_cdata.ti_rx_std_sparemap); 1280 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1281 } 1282 if (sc->ti_cdata.ti_rx_std_tag) { 1283 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1284 sc->ti_cdata.ti_rx_std_tag = NULL; 1285 } 1286 1287 /* Destroy DMA maps for jumbo RX buffers. */ 1288 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1289 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1290 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1291 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1292 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1293 } 1294 } 1295 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1296 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1297 sc->ti_cdata.ti_rx_jumbo_sparemap); 1298 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1299 } 1300 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1301 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1302 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1303 } 1304 1305 /* Destroy DMA maps for mini RX buffers. */ 1306 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1307 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1308 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1309 sc->ti_cdata.ti_rx_mini_maps[i]); 1310 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1311 } 1312 } 1313 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1314 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1315 sc->ti_cdata.ti_rx_mini_sparemap); 1316 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1317 } 1318 if (sc->ti_cdata.ti_rx_mini_tag) { 1319 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1320 sc->ti_cdata.ti_rx_mini_tag = NULL; 1321 } 1322 1323 /* Destroy DMA maps for TX buffers. */ 1324 for (i = 0; i < TI_TX_RING_CNT; i++) { 1325 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1326 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1328 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1329 } 1330 } 1331 if (sc->ti_cdata.ti_tx_tag) { 1332 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1333 sc->ti_cdata.ti_tx_tag = NULL; 1334 } 1335 1336 /* Destroy standard RX ring. */ 1337 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1338 (void *)&sc->ti_rdata.ti_rx_std_ring, 1339 &sc->ti_cdata.ti_rx_std_ring_map); 1340 /* Destroy jumbo RX ring. */ 1341 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1342 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1343 &sc->ti_cdata.ti_rx_jumbo_ring_map); 1344 /* Destroy mini RX ring. */ 1345 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1346 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1347 &sc->ti_cdata.ti_rx_mini_ring_map); 1348 /* Destroy RX return ring. */ 1349 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1350 (void *)&sc->ti_rdata.ti_rx_return_ring, 1351 &sc->ti_cdata.ti_rx_return_ring_map); 1352 /* Destroy TX ring. */ 1353 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1354 (void *)&sc->ti_rdata.ti_tx_ring, &sc->ti_cdata.ti_tx_ring_map); 1355 /* Destroy status block. */ 1356 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1357 (void *)&sc->ti_rdata.ti_status, &sc->ti_cdata.ti_status_map); 1358 /* Destroy event ring. */ 1359 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1360 (void *)&sc->ti_rdata.ti_event_ring, 1361 &sc->ti_cdata.ti_event_ring_map); 1362 /* Destroy GIB */ 1363 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1364 (void *)&sc->ti_rdata.ti_info, &sc->ti_cdata.ti_gib_map); 1365 1366 /* Destroy the parent tag. */ 1367 if (sc->ti_cdata.ti_parent_tag) { 1368 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1369 sc->ti_cdata.ti_parent_tag = NULL; 1370 } 1371 } 1372 1373 /* 1374 * Intialize a standard receive ring descriptor. 1375 */ 1376 static int 1377 ti_newbuf_std(struct ti_softc *sc, int i) 1378 { 1379 bus_dmamap_t map; 1380 bus_dma_segment_t segs[1]; 1381 struct mbuf *m; 1382 struct ti_rx_desc *r; 1383 int error, nsegs; 1384 1385 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1386 if (m == NULL) 1387 return (ENOBUFS); 1388 m->m_len = m->m_pkthdr.len = MCLBYTES; 1389 m_adj(m, ETHER_ALIGN); 1390 1391 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1392 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1393 if (error != 0) { 1394 m_freem(m); 1395 return (error); 1396 } 1397 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1398 1399 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1400 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1401 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1402 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1403 sc->ti_cdata.ti_rx_std_maps[i]); 1404 } 1405 1406 map = sc->ti_cdata.ti_rx_std_maps[i]; 1407 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1408 sc->ti_cdata.ti_rx_std_sparemap = map; 1409 sc->ti_cdata.ti_rx_std_chain[i] = m; 1410 1411 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1412 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1413 r->ti_len = segs[0].ds_len; 1414 r->ti_type = TI_BDTYPE_RECV_BD; 1415 r->ti_flags = 0; 1416 r->ti_vlan_tag = 0; 1417 r->ti_tcp_udp_cksum = 0; 1418 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1419 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1420 r->ti_idx = i; 1421 1422 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1423 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1424 return (0); 1425 } 1426 1427 /* 1428 * Intialize a mini receive ring descriptor. This only applies to 1429 * the Tigon 2. 1430 */ 1431 static int 1432 ti_newbuf_mini(struct ti_softc *sc, int i) 1433 { 1434 bus_dmamap_t map; 1435 bus_dma_segment_t segs[1]; 1436 struct mbuf *m; 1437 struct ti_rx_desc *r; 1438 int error, nsegs; 1439 1440 MGETHDR(m, M_NOWAIT, MT_DATA); 1441 if (m == NULL) 1442 return (ENOBUFS); 1443 m->m_len = m->m_pkthdr.len = MHLEN; 1444 m_adj(m, ETHER_ALIGN); 1445 1446 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1447 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1448 if (error != 0) { 1449 m_freem(m); 1450 return (error); 1451 } 1452 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1453 1454 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1455 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1456 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1457 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1458 sc->ti_cdata.ti_rx_mini_maps[i]); 1459 } 1460 1461 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1462 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1463 sc->ti_cdata.ti_rx_mini_sparemap = map; 1464 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1465 1466 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1467 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1468 r->ti_len = segs[0].ds_len; 1469 r->ti_type = TI_BDTYPE_RECV_BD; 1470 r->ti_flags = TI_BDFLAG_MINI_RING; 1471 r->ti_vlan_tag = 0; 1472 r->ti_tcp_udp_cksum = 0; 1473 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1474 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1475 r->ti_idx = i; 1476 1477 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1478 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1479 return (0); 1480 } 1481 1482 #ifndef TI_SF_BUF_JUMBO 1483 1484 /* 1485 * Initialize a jumbo receive ring descriptor. This allocates 1486 * a jumbo buffer from the pool managed internally by the driver. 1487 */ 1488 static int 1489 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1490 { 1491 bus_dmamap_t map; 1492 bus_dma_segment_t segs[1]; 1493 struct mbuf *m; 1494 struct ti_rx_desc *r; 1495 int error, nsegs; 1496 1497 (void)dummy; 1498 1499 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1500 if (m == NULL) 1501 return (ENOBUFS); 1502 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1503 m_adj(m, ETHER_ALIGN); 1504 1505 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1506 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1507 if (error != 0) { 1508 m_freem(m); 1509 return (error); 1510 } 1511 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1512 1513 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1514 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1515 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1516 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1517 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1518 } 1519 1520 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1521 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1522 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1523 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1524 1525 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1526 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1527 r->ti_len = segs[0].ds_len; 1528 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1529 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1530 r->ti_vlan_tag = 0; 1531 r->ti_tcp_udp_cksum = 0; 1532 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1533 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1534 r->ti_idx = i; 1535 1536 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1537 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1538 return (0); 1539 } 1540 1541 #else 1542 1543 #if (PAGE_SIZE == 4096) 1544 #define NPAYLOAD 2 1545 #else 1546 #define NPAYLOAD 1 1547 #endif 1548 1549 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1550 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1551 #define NFS_HDR_LEN (UDP_HDR_LEN) 1552 static int HDR_LEN = TCP_HDR_LEN; 1553 1554 /* 1555 * Initialize a jumbo receive ring descriptor. This allocates 1556 * a jumbo buffer from the pool managed internally by the driver. 1557 */ 1558 static int 1559 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1560 { 1561 bus_dmamap_t map; 1562 struct mbuf *cur, *m_new = NULL; 1563 struct mbuf *m[3] = {NULL, NULL, NULL}; 1564 struct ti_rx_desc_ext *r; 1565 vm_page_t frame; 1566 /* 1 extra buf to make nobufs easy*/ 1567 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1568 int i; 1569 bus_dma_segment_t segs[4]; 1570 int nsegs; 1571 1572 if (m_old != NULL) { 1573 m_new = m_old; 1574 cur = m_old->m_next; 1575 for (i = 0; i <= NPAYLOAD; i++){ 1576 m[i] = cur; 1577 cur = cur->m_next; 1578 } 1579 } else { 1580 /* Allocate the mbufs. */ 1581 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1582 if (m_new == NULL) { 1583 device_printf(sc->ti_dev, "mbuf allocation failed " 1584 "-- packet dropped!\n"); 1585 goto nobufs; 1586 } 1587 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA); 1588 if (m[NPAYLOAD] == NULL) { 1589 device_printf(sc->ti_dev, "cluster mbuf allocation " 1590 "failed -- packet dropped!\n"); 1591 goto nobufs; 1592 } 1593 MCLGET(m[NPAYLOAD], M_NOWAIT); 1594 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1595 device_printf(sc->ti_dev, "mbuf allocation failed " 1596 "-- packet dropped!\n"); 1597 goto nobufs; 1598 } 1599 m[NPAYLOAD]->m_len = MCLBYTES; 1600 1601 for (i = 0; i < NPAYLOAD; i++){ 1602 MGET(m[i], M_NOWAIT, MT_DATA); 1603 if (m[i] == NULL) { 1604 device_printf(sc->ti_dev, "mbuf allocation " 1605 "failed -- packet dropped!\n"); 1606 goto nobufs; 1607 } 1608 frame = vm_page_alloc(NULL, 0, 1609 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1610 VM_ALLOC_WIRED); 1611 if (frame == NULL) { 1612 device_printf(sc->ti_dev, "buffer allocation " 1613 "failed -- packet dropped!\n"); 1614 printf(" index %d page %d\n", idx, i); 1615 goto nobufs; 1616 } 1617 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1618 if (sf[i] == NULL) { 1619 vm_page_unwire(frame, 0); 1620 vm_page_free(frame); 1621 device_printf(sc->ti_dev, "buffer allocation " 1622 "failed -- packet dropped!\n"); 1623 printf(" index %d page %d\n", idx, i); 1624 goto nobufs; 1625 } 1626 } 1627 for (i = 0; i < NPAYLOAD; i++){ 1628 /* Attach the buffer to the mbuf. */ 1629 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1630 m[i]->m_len = PAGE_SIZE; 1631 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1632 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1633 0, EXT_DISPOSABLE); 1634 m[i]->m_next = m[i+1]; 1635 } 1636 /* link the buffers to the header */ 1637 m_new->m_next = m[0]; 1638 m_new->m_data += ETHER_ALIGN; 1639 if (sc->ti_hdrsplit) 1640 m_new->m_len = MHLEN - ETHER_ALIGN; 1641 else 1642 m_new->m_len = HDR_LEN; 1643 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1644 } 1645 1646 /* Set up the descriptor. */ 1647 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1648 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1649 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1650 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1651 segs, &nsegs, 0)) 1652 return (ENOBUFS); 1653 if ((nsegs < 1) || (nsegs > 4)) 1654 return (ENOBUFS); 1655 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1656 r->ti_len0 = m_new->m_len; 1657 1658 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1659 r->ti_len1 = PAGE_SIZE; 1660 1661 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1662 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1663 1664 if (PAGE_SIZE == 4096) { 1665 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1666 r->ti_len3 = MCLBYTES; 1667 } else { 1668 r->ti_len3 = 0; 1669 } 1670 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1671 1672 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1673 1674 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1675 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1676 1677 r->ti_idx = idx; 1678 1679 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1680 return (0); 1681 1682 nobufs: 1683 1684 /* 1685 * Warning! : 1686 * This can only be called before the mbufs are strung together. 1687 * If the mbufs are strung together, m_freem() will free the chain, 1688 * so that the later mbufs will be freed multiple times. 1689 */ 1690 if (m_new) 1691 m_freem(m_new); 1692 1693 for (i = 0; i < 3; i++) { 1694 if (m[i]) 1695 m_freem(m[i]); 1696 if (sf[i]) 1697 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1698 } 1699 return (ENOBUFS); 1700 } 1701 #endif 1702 1703 /* 1704 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1705 * that's 1MB or memory, which is a lot. For now, we fill only the first 1706 * 256 ring entries and hope that our CPU is fast enough to keep up with 1707 * the NIC. 1708 */ 1709 static int 1710 ti_init_rx_ring_std(struct ti_softc *sc) 1711 { 1712 int i; 1713 struct ti_cmd_desc cmd; 1714 1715 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1716 if (ti_newbuf_std(sc, i) != 0) 1717 return (ENOBUFS); 1718 }; 1719 1720 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1721 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1722 1723 return (0); 1724 } 1725 1726 static void 1727 ti_free_rx_ring_std(struct ti_softc *sc) 1728 { 1729 bus_dmamap_t map; 1730 int i; 1731 1732 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1733 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1734 map = sc->ti_cdata.ti_rx_std_maps[i]; 1735 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1736 BUS_DMASYNC_POSTREAD); 1737 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1738 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1739 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1740 } 1741 } 1742 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1743 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1744 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1745 } 1746 1747 static int 1748 ti_init_rx_ring_jumbo(struct ti_softc *sc) 1749 { 1750 struct ti_cmd_desc cmd; 1751 int i; 1752 1753 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1754 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1755 return (ENOBUFS); 1756 }; 1757 1758 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1759 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1760 1761 return (0); 1762 } 1763 1764 static void 1765 ti_free_rx_ring_jumbo(struct ti_softc *sc) 1766 { 1767 bus_dmamap_t map; 1768 int i; 1769 1770 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1771 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1772 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1773 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1774 BUS_DMASYNC_POSTREAD); 1775 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1776 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1777 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1778 } 1779 } 1780 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1781 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1782 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1783 } 1784 1785 static int 1786 ti_init_rx_ring_mini(struct ti_softc *sc) 1787 { 1788 int i; 1789 1790 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1791 if (ti_newbuf_mini(sc, i) != 0) 1792 return (ENOBUFS); 1793 }; 1794 1795 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1796 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1797 1798 return (0); 1799 } 1800 1801 static void 1802 ti_free_rx_ring_mini(struct ti_softc *sc) 1803 { 1804 bus_dmamap_t map; 1805 int i; 1806 1807 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1808 return; 1809 1810 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1811 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1812 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1813 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1814 BUS_DMASYNC_POSTREAD); 1815 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1816 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1817 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1818 } 1819 } 1820 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1821 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1822 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1823 } 1824 1825 static void 1826 ti_free_tx_ring(struct ti_softc *sc) 1827 { 1828 struct ti_txdesc *txd; 1829 int i; 1830 1831 if (sc->ti_rdata.ti_tx_ring == NULL) 1832 return; 1833 1834 for (i = 0; i < TI_TX_RING_CNT; i++) { 1835 txd = &sc->ti_cdata.ti_txdesc[i]; 1836 if (txd->tx_m != NULL) { 1837 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1838 BUS_DMASYNC_POSTWRITE); 1839 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1840 txd->tx_dmamap); 1841 m_freem(txd->tx_m); 1842 txd->tx_m = NULL; 1843 } 1844 } 1845 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1846 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1847 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1848 } 1849 1850 static int 1851 ti_init_tx_ring(struct ti_softc *sc) 1852 { 1853 struct ti_txdesc *txd; 1854 int i; 1855 1856 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1857 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1858 for (i = 0; i < TI_TX_RING_CNT; i++) { 1859 txd = &sc->ti_cdata.ti_txdesc[i]; 1860 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1861 } 1862 sc->ti_txcnt = 0; 1863 sc->ti_tx_saved_considx = 0; 1864 sc->ti_tx_saved_prodidx = 0; 1865 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1866 return (0); 1867 } 1868 1869 /* 1870 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1871 * but we have to support the old way too so that Tigon 1 cards will 1872 * work. 1873 */ 1874 static void 1875 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1876 { 1877 struct ti_cmd_desc cmd; 1878 uint16_t *m; 1879 uint32_t ext[2] = {0, 0}; 1880 1881 m = (uint16_t *)&addr->octet[0]; 1882 1883 switch (sc->ti_hwrev) { 1884 case TI_HWREV_TIGON: 1885 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1886 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1887 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1888 break; 1889 case TI_HWREV_TIGON_II: 1890 ext[0] = htons(m[0]); 1891 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1892 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1893 break; 1894 default: 1895 device_printf(sc->ti_dev, "unknown hwrev\n"); 1896 break; 1897 } 1898 } 1899 1900 static void 1901 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1902 { 1903 struct ti_cmd_desc cmd; 1904 uint16_t *m; 1905 uint32_t ext[2] = {0, 0}; 1906 1907 m = (uint16_t *)&addr->octet[0]; 1908 1909 switch (sc->ti_hwrev) { 1910 case TI_HWREV_TIGON: 1911 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1912 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1913 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1914 break; 1915 case TI_HWREV_TIGON_II: 1916 ext[0] = htons(m[0]); 1917 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1918 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1919 break; 1920 default: 1921 device_printf(sc->ti_dev, "unknown hwrev\n"); 1922 break; 1923 } 1924 } 1925 1926 /* 1927 * Configure the Tigon's multicast address filter. 1928 * 1929 * The actual multicast table management is a bit of a pain, thanks to 1930 * slight brain damage on the part of both Alteon and us. With our 1931 * multicast code, we are only alerted when the multicast address table 1932 * changes and at that point we only have the current list of addresses: 1933 * we only know the current state, not the previous state, so we don't 1934 * actually know what addresses were removed or added. The firmware has 1935 * state, but we can't get our grubby mits on it, and there is no 'delete 1936 * all multicast addresses' command. Hence, we have to maintain our own 1937 * state so we know what addresses have been programmed into the NIC at 1938 * any given time. 1939 */ 1940 static void 1941 ti_setmulti(struct ti_softc *sc) 1942 { 1943 struct ifnet *ifp; 1944 struct ifmultiaddr *ifma; 1945 struct ti_cmd_desc cmd; 1946 struct ti_mc_entry *mc; 1947 uint32_t intrs; 1948 1949 TI_LOCK_ASSERT(sc); 1950 1951 ifp = sc->ti_ifp; 1952 1953 if (ifp->if_flags & IFF_ALLMULTI) { 1954 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1955 return; 1956 } else { 1957 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1958 } 1959 1960 /* Disable interrupts. */ 1961 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1962 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1963 1964 /* First, zot all the existing filters. */ 1965 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1966 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1967 ti_del_mcast(sc, &mc->mc_addr); 1968 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1969 free(mc, M_DEVBUF); 1970 } 1971 1972 /* Now program new ones. */ 1973 if_maddr_rlock(ifp); 1974 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1975 if (ifma->ifma_addr->sa_family != AF_LINK) 1976 continue; 1977 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1978 if (mc == NULL) { 1979 device_printf(sc->ti_dev, 1980 "no memory for mcast filter entry\n"); 1981 continue; 1982 } 1983 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1984 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1985 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1986 ti_add_mcast(sc, &mc->mc_addr); 1987 } 1988 if_maddr_runlock(ifp); 1989 1990 /* Re-enable interrupts. */ 1991 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1992 } 1993 1994 /* 1995 * Check to see if the BIOS has configured us for a 64 bit slot when 1996 * we aren't actually in one. If we detect this condition, we can work 1997 * around it on the Tigon 2 by setting a bit in the PCI state register, 1998 * but for the Tigon 1 we must give up and abort the interface attach. 1999 */ 2000 static int 2001 ti_64bitslot_war(struct ti_softc *sc) 2002 { 2003 2004 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2005 CSR_WRITE_4(sc, 0x600, 0); 2006 CSR_WRITE_4(sc, 0x604, 0); 2007 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2008 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2009 if (sc->ti_hwrev == TI_HWREV_TIGON) 2010 return (EINVAL); 2011 else { 2012 TI_SETBIT(sc, TI_PCI_STATE, 2013 TI_PCISTATE_32BIT_BUS); 2014 return (0); 2015 } 2016 } 2017 } 2018 2019 return (0); 2020 } 2021 2022 /* 2023 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2024 * self-test results. 2025 */ 2026 static int 2027 ti_chipinit(struct ti_softc *sc) 2028 { 2029 uint32_t cacheline; 2030 uint32_t pci_writemax = 0; 2031 uint32_t hdrsplit; 2032 2033 /* Initialize link to down state. */ 2034 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2035 2036 /* Set endianness before we access any non-PCI registers. */ 2037 #if 0 && BYTE_ORDER == BIG_ENDIAN 2038 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2039 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2040 #else 2041 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2042 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2043 #endif 2044 2045 /* Check the ROM failed bit to see if self-tests passed. */ 2046 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2047 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2048 return (ENODEV); 2049 } 2050 2051 /* Halt the CPU. */ 2052 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2053 2054 /* Figure out the hardware revision. */ 2055 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2056 case TI_REV_TIGON_I: 2057 sc->ti_hwrev = TI_HWREV_TIGON; 2058 break; 2059 case TI_REV_TIGON_II: 2060 sc->ti_hwrev = TI_HWREV_TIGON_II; 2061 break; 2062 default: 2063 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2064 return (ENODEV); 2065 } 2066 2067 /* Do special setup for Tigon 2. */ 2068 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2069 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2070 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2071 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2072 } 2073 2074 /* 2075 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2076 * can't do header splitting. 2077 */ 2078 #ifdef TI_JUMBO_HDRSPLIT 2079 if (sc->ti_hwrev != TI_HWREV_TIGON) 2080 sc->ti_hdrsplit = 1; 2081 else 2082 device_printf(sc->ti_dev, 2083 "can't do header splitting on a Tigon I board\n"); 2084 #endif /* TI_JUMBO_HDRSPLIT */ 2085 2086 /* Set up the PCI state register. */ 2087 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2088 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2089 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2090 } 2091 2092 /* Clear the read/write max DMA parameters. */ 2093 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2094 TI_PCISTATE_READ_MAXDMA)); 2095 2096 /* Get cache line size. */ 2097 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2098 2099 /* 2100 * If the system has set enabled the PCI memory write 2101 * and invalidate command in the command register, set 2102 * the write max parameter accordingly. This is necessary 2103 * to use MWI with the Tigon 2. 2104 */ 2105 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2106 switch (cacheline) { 2107 case 1: 2108 case 4: 2109 case 8: 2110 case 16: 2111 case 32: 2112 case 64: 2113 break; 2114 default: 2115 /* Disable PCI memory write and invalidate. */ 2116 if (bootverbose) 2117 device_printf(sc->ti_dev, "cache line size %d" 2118 " not supported; disabling PCI MWI\n", 2119 cacheline); 2120 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2121 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2122 break; 2123 } 2124 } 2125 2126 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2127 2128 /* This sets the min dma param all the way up (0xff). */ 2129 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2130 2131 if (sc->ti_hdrsplit) 2132 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2133 else 2134 hdrsplit = 0; 2135 2136 /* Configure DMA variables. */ 2137 #if BYTE_ORDER == BIG_ENDIAN 2138 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2139 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2140 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2141 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2142 #else /* BYTE_ORDER */ 2143 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2144 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2145 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2146 #endif /* BYTE_ORDER */ 2147 2148 /* 2149 * Only allow 1 DMA channel to be active at a time. 2150 * I don't think this is a good idea, but without it 2151 * the firmware racks up lots of nicDmaReadRingFull 2152 * errors. This is not compatible with hardware checksums. 2153 */ 2154 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2155 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2156 2157 /* Recommended settings from Tigon manual. */ 2158 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2159 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2160 2161 if (ti_64bitslot_war(sc)) { 2162 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2163 "but we aren't"); 2164 return (EINVAL); 2165 } 2166 2167 return (0); 2168 } 2169 2170 /* 2171 * Initialize the general information block and firmware, and 2172 * start the CPU(s) running. 2173 */ 2174 static int 2175 ti_gibinit(struct ti_softc *sc) 2176 { 2177 struct ifnet *ifp; 2178 struct ti_rcb *rcb; 2179 int i; 2180 2181 TI_LOCK_ASSERT(sc); 2182 2183 ifp = sc->ti_ifp; 2184 2185 /* Disable interrupts for now. */ 2186 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2187 2188 /* Tell the chip where to find the general information block. */ 2189 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2190 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2191 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2192 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2193 2194 /* Load the firmware into SRAM. */ 2195 ti_loadfw(sc); 2196 2197 /* Set up the contents of the general info and ring control blocks. */ 2198 2199 /* Set up the event ring and producer pointer. */ 2200 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2201 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2202 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2203 rcb->ti_flags = 0; 2204 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2205 sc->ti_rdata.ti_status_paddr + 2206 offsetof(struct ti_status, ti_ev_prodidx_r)); 2207 sc->ti_ev_prodidx.ti_idx = 0; 2208 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2209 sc->ti_ev_saved_considx = 0; 2210 2211 /* Set up the command ring and producer mailbox. */ 2212 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2213 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2214 rcb->ti_flags = 0; 2215 rcb->ti_max_len = 0; 2216 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2217 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2218 } 2219 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2220 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2221 sc->ti_cmd_saved_prodidx = 0; 2222 2223 /* 2224 * Assign the address of the stats refresh buffer. 2225 * We re-use the current stats buffer for this to 2226 * conserve memory. 2227 */ 2228 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2229 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2230 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2231 2232 /* Set up the standard receive ring. */ 2233 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2234 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2235 rcb->ti_max_len = TI_FRAMELEN; 2236 rcb->ti_flags = 0; 2237 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2238 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2239 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2240 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2241 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2242 2243 /* Set up the jumbo receive ring. */ 2244 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2245 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2246 2247 #ifndef TI_SF_BUF_JUMBO 2248 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2249 rcb->ti_flags = 0; 2250 #else 2251 rcb->ti_max_len = PAGE_SIZE; 2252 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2253 #endif 2254 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2255 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2256 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2257 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2258 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2259 2260 /* 2261 * Set up the mini ring. Only activated on the 2262 * Tigon 2 but the slot in the config block is 2263 * still there on the Tigon 1. 2264 */ 2265 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2266 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2267 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2268 if (sc->ti_hwrev == TI_HWREV_TIGON) 2269 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2270 else 2271 rcb->ti_flags = 0; 2272 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2273 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2274 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2275 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2276 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2277 2278 /* 2279 * Set up the receive return ring. 2280 */ 2281 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2282 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2283 rcb->ti_flags = 0; 2284 rcb->ti_max_len = TI_RETURN_RING_CNT; 2285 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2286 sc->ti_rdata.ti_status_paddr + 2287 offsetof(struct ti_status, ti_return_prodidx_r)); 2288 2289 /* 2290 * Set up the tx ring. Note: for the Tigon 2, we have the option 2291 * of putting the transmit ring in the host's address space and 2292 * letting the chip DMA it instead of leaving the ring in the NIC's 2293 * memory and accessing it through the shared memory region. We 2294 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2295 * so we have to revert to the shared memory scheme if we detect 2296 * a Tigon 1 chip. 2297 */ 2298 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2299 if (sc->ti_rdata.ti_tx_ring != NULL) 2300 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2301 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2302 if (sc->ti_hwrev == TI_HWREV_TIGON) 2303 rcb->ti_flags = 0; 2304 else 2305 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2306 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2307 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2308 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2309 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2310 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2311 rcb->ti_max_len = TI_TX_RING_CNT; 2312 if (sc->ti_hwrev == TI_HWREV_TIGON) 2313 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2314 else 2315 ti_hostaddr64(&rcb->ti_hostaddr, 2316 sc->ti_rdata.ti_tx_ring_paddr); 2317 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2318 sc->ti_rdata.ti_status_paddr + 2319 offsetof(struct ti_status, ti_tx_considx_r)); 2320 2321 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2323 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2325 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2326 sc->ti_cdata.ti_event_ring_map, 2327 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2328 if (sc->ti_rdata.ti_tx_ring != NULL) 2329 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2330 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2331 2332 /* Set up tunables */ 2333 #if 0 2334 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2335 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2336 (sc->ti_rx_coal_ticks / 10)); 2337 else 2338 #endif 2339 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2340 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2341 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2342 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2343 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2344 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2345 2346 /* Turn interrupts on. */ 2347 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2348 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2349 2350 /* Start CPU. */ 2351 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2352 2353 return (0); 2354 } 2355 2356 /* 2357 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2358 * against our list and return its name if we find a match. 2359 */ 2360 static int 2361 ti_probe(device_t dev) 2362 { 2363 const struct ti_type *t; 2364 2365 t = ti_devs; 2366 2367 while (t->ti_name != NULL) { 2368 if ((pci_get_vendor(dev) == t->ti_vid) && 2369 (pci_get_device(dev) == t->ti_did)) { 2370 device_set_desc(dev, t->ti_name); 2371 return (BUS_PROBE_DEFAULT); 2372 } 2373 t++; 2374 } 2375 2376 return (ENXIO); 2377 } 2378 2379 static int 2380 ti_attach(device_t dev) 2381 { 2382 struct ifnet *ifp; 2383 struct ti_softc *sc; 2384 int error = 0, rid; 2385 u_char eaddr[6]; 2386 2387 sc = device_get_softc(dev); 2388 sc->ti_dev = dev; 2389 2390 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2391 MTX_DEF); 2392 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2393 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2394 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2395 if (ifp == NULL) { 2396 device_printf(dev, "can not if_alloc()\n"); 2397 error = ENOSPC; 2398 goto fail; 2399 } 2400 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2401 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2402 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2403 2404 /* 2405 * Map control/status registers. 2406 */ 2407 pci_enable_busmaster(dev); 2408 2409 rid = PCIR_BAR(0); 2410 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2411 RF_ACTIVE); 2412 2413 if (sc->ti_res == NULL) { 2414 device_printf(dev, "couldn't map memory\n"); 2415 error = ENXIO; 2416 goto fail; 2417 } 2418 2419 sc->ti_btag = rman_get_bustag(sc->ti_res); 2420 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2421 2422 /* Allocate interrupt */ 2423 rid = 0; 2424 2425 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2426 RF_SHAREABLE | RF_ACTIVE); 2427 2428 if (sc->ti_irq == NULL) { 2429 device_printf(dev, "couldn't map interrupt\n"); 2430 error = ENXIO; 2431 goto fail; 2432 } 2433 2434 if (ti_chipinit(sc)) { 2435 device_printf(dev, "chip initialization failed\n"); 2436 error = ENXIO; 2437 goto fail; 2438 } 2439 2440 /* Zero out the NIC's on-board SRAM. */ 2441 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2442 2443 /* Init again -- zeroing memory may have clobbered some registers. */ 2444 if (ti_chipinit(sc)) { 2445 device_printf(dev, "chip initialization failed\n"); 2446 error = ENXIO; 2447 goto fail; 2448 } 2449 2450 /* 2451 * Get station address from the EEPROM. Note: the manual states 2452 * that the MAC address is at offset 0x8c, however the data is 2453 * stored as two longwords (since that's how it's loaded into 2454 * the NIC). This means the MAC address is actually preceded 2455 * by two zero bytes. We need to skip over those. 2456 */ 2457 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2458 device_printf(dev, "failed to read station address\n"); 2459 error = ENXIO; 2460 goto fail; 2461 } 2462 2463 /* Allocate working area for memory dump. */ 2464 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2465 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2466 M_NOWAIT); 2467 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2468 device_printf(dev, "cannot allocate memory buffer\n"); 2469 error = ENOMEM; 2470 goto fail; 2471 } 2472 if ((error = ti_dma_alloc(sc)) != 0) 2473 goto fail; 2474 2475 /* 2476 * We really need a better way to tell a 1000baseTX card 2477 * from a 1000baseSX one, since in theory there could be 2478 * OEMed 1000baseTX cards from lame vendors who aren't 2479 * clever enough to change the PCI ID. For the moment 2480 * though, the AceNIC is the only copper card available. 2481 */ 2482 if (pci_get_vendor(dev) == ALT_VENDORID && 2483 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2484 sc->ti_copper = 1; 2485 /* Ok, it's not the only copper card available. */ 2486 if (pci_get_vendor(dev) == NG_VENDORID && 2487 pci_get_device(dev) == NG_DEVICEID_GA620T) 2488 sc->ti_copper = 1; 2489 2490 /* Set default tunable values. */ 2491 ti_sysctl_node(sc); 2492 2493 /* Set up ifnet structure */ 2494 ifp->if_softc = sc; 2495 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2496 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2497 ifp->if_ioctl = ti_ioctl; 2498 ifp->if_start = ti_start; 2499 ifp->if_init = ti_init; 2500 ifp->if_baudrate = IF_Gbps(1UL); 2501 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2502 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2503 IFQ_SET_READY(&ifp->if_snd); 2504 2505 /* Set up ifmedia support. */ 2506 if (sc->ti_copper) { 2507 /* 2508 * Copper cards allow manual 10/100 mode selection, 2509 * but not manual 1000baseTX mode selection. Why? 2510 * Becuase currently there's no way to specify the 2511 * master/slave setting through the firmware interface, 2512 * so Alteon decided to just bag it and handle it 2513 * via autonegotiation. 2514 */ 2515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2516 ifmedia_add(&sc->ifmedia, 2517 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2519 ifmedia_add(&sc->ifmedia, 2520 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2522 ifmedia_add(&sc->ifmedia, 2523 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2524 } else { 2525 /* Fiber cards don't support 10/100 modes. */ 2526 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2527 ifmedia_add(&sc->ifmedia, 2528 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2529 } 2530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2531 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2532 2533 /* 2534 * We're assuming here that card initialization is a sequential 2535 * thing. If it isn't, multiple cards probing at the same time 2536 * could stomp on the list of softcs here. 2537 */ 2538 2539 /* Register the device */ 2540 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2541 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2542 sc->dev->si_drv1 = sc; 2543 2544 /* 2545 * Call MI attach routine. 2546 */ 2547 ether_ifattach(ifp, eaddr); 2548 2549 /* VLAN capability setup. */ 2550 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2551 IFCAP_VLAN_HWTAGGING; 2552 ifp->if_capenable = ifp->if_capabilities; 2553 /* Tell the upper layer we support VLAN over-sized frames. */ 2554 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2555 2556 /* Driver supports link state tracking. */ 2557 ifp->if_capabilities |= IFCAP_LINKSTATE; 2558 ifp->if_capenable |= IFCAP_LINKSTATE; 2559 2560 /* Hook interrupt last to avoid having to lock softc */ 2561 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2562 NULL, ti_intr, sc, &sc->ti_intrhand); 2563 2564 if (error) { 2565 device_printf(dev, "couldn't set up irq\n"); 2566 goto fail; 2567 } 2568 2569 fail: 2570 if (error) 2571 ti_detach(dev); 2572 2573 return (error); 2574 } 2575 2576 /* 2577 * Shutdown hardware and free up resources. This can be called any 2578 * time after the mutex has been initialized. It is called in both 2579 * the error case in attach and the normal detach case so it needs 2580 * to be careful about only freeing resources that have actually been 2581 * allocated. 2582 */ 2583 static int 2584 ti_detach(device_t dev) 2585 { 2586 struct ti_softc *sc; 2587 struct ifnet *ifp; 2588 2589 sc = device_get_softc(dev); 2590 if (sc->dev) 2591 destroy_dev(sc->dev); 2592 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2593 ifp = sc->ti_ifp; 2594 if (device_is_attached(dev)) { 2595 ether_ifdetach(ifp); 2596 TI_LOCK(sc); 2597 ti_stop(sc); 2598 TI_UNLOCK(sc); 2599 } 2600 2601 /* These should only be active if attach succeeded */ 2602 callout_drain(&sc->ti_watchdog); 2603 bus_generic_detach(dev); 2604 ti_dma_free(sc); 2605 ifmedia_removeall(&sc->ifmedia); 2606 2607 if (sc->ti_intrhand) 2608 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2609 if (sc->ti_irq) 2610 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2611 if (sc->ti_res) { 2612 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2613 sc->ti_res); 2614 } 2615 if (ifp) 2616 if_free(ifp); 2617 if (sc->ti_membuf) 2618 free(sc->ti_membuf, M_DEVBUF); 2619 if (sc->ti_membuf2) 2620 free(sc->ti_membuf2, M_DEVBUF); 2621 2622 mtx_destroy(&sc->ti_mtx); 2623 2624 return (0); 2625 } 2626 2627 #ifdef TI_JUMBO_HDRSPLIT 2628 /* 2629 * If hdr_len is 0, that means that header splitting wasn't done on 2630 * this packet for some reason. The two most likely reasons are that 2631 * the protocol isn't a supported protocol for splitting, or this 2632 * packet had a fragment offset that wasn't 0. 2633 * 2634 * The header length, if it is non-zero, will always be the length of 2635 * the headers on the packet, but that length could be longer than the 2636 * first mbuf. So we take the minimum of the two as the actual 2637 * length. 2638 */ 2639 static __inline void 2640 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2641 { 2642 int i = 0; 2643 int lengths[4] = {0, 0, 0, 0}; 2644 struct mbuf *m, *mp; 2645 2646 if (hdr_len != 0) 2647 top->m_len = min(hdr_len, top->m_len); 2648 pkt_len -= top->m_len; 2649 lengths[i++] = top->m_len; 2650 2651 mp = top; 2652 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2653 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2654 pkt_len -= m->m_len; 2655 lengths[i++] = m->m_len; 2656 mp = m; 2657 } 2658 2659 #if 0 2660 if (hdr_len != 0) 2661 printf("got split packet: "); 2662 else 2663 printf("got non-split packet: "); 2664 2665 printf("%d,%d,%d,%d = %d\n", lengths[0], 2666 lengths[1], lengths[2], lengths[3], 2667 lengths[0] + lengths[1] + lengths[2] + 2668 lengths[3]); 2669 #endif 2670 2671 if (pkt_len) 2672 panic("header splitting didn't"); 2673 2674 if (m) { 2675 m_freem(m); 2676 mp->m_next = NULL; 2677 2678 } 2679 if (mp->m_next != NULL) 2680 panic("ti_hdr_split: last mbuf in chain should be null"); 2681 } 2682 #endif /* TI_JUMBO_HDRSPLIT */ 2683 2684 static void 2685 ti_discard_std(struct ti_softc *sc, int i) 2686 { 2687 2688 struct ti_rx_desc *r; 2689 2690 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2691 r->ti_len = MCLBYTES - ETHER_ALIGN; 2692 r->ti_type = TI_BDTYPE_RECV_BD; 2693 r->ti_flags = 0; 2694 r->ti_vlan_tag = 0; 2695 r->ti_tcp_udp_cksum = 0; 2696 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2697 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2698 r->ti_idx = i; 2699 } 2700 2701 static void 2702 ti_discard_mini(struct ti_softc *sc, int i) 2703 { 2704 2705 struct ti_rx_desc *r; 2706 2707 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2708 r->ti_len = MHLEN - ETHER_ALIGN; 2709 r->ti_type = TI_BDTYPE_RECV_BD; 2710 r->ti_flags = TI_BDFLAG_MINI_RING; 2711 r->ti_vlan_tag = 0; 2712 r->ti_tcp_udp_cksum = 0; 2713 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2714 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2715 r->ti_idx = i; 2716 } 2717 2718 #ifndef TI_SF_BUF_JUMBO 2719 static void 2720 ti_discard_jumbo(struct ti_softc *sc, int i) 2721 { 2722 2723 struct ti_rx_desc *r; 2724 2725 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2726 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2727 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2728 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2729 r->ti_vlan_tag = 0; 2730 r->ti_tcp_udp_cksum = 0; 2731 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2732 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2733 r->ti_idx = i; 2734 } 2735 #endif 2736 2737 /* 2738 * Frame reception handling. This is called if there's a frame 2739 * on the receive return list. 2740 * 2741 * Note: we have to be able to handle three possibilities here: 2742 * 1) the frame is from the mini receive ring (can only happen) 2743 * on Tigon 2 boards) 2744 * 2) the frame is from the jumbo recieve ring 2745 * 3) the frame is from the standard receive ring 2746 */ 2747 2748 static void 2749 ti_rxeof(struct ti_softc *sc) 2750 { 2751 struct ifnet *ifp; 2752 #ifdef TI_SF_BUF_JUMBO 2753 bus_dmamap_t map; 2754 #endif 2755 struct ti_cmd_desc cmd; 2756 int jumbocnt, minicnt, stdcnt, ti_len; 2757 2758 TI_LOCK_ASSERT(sc); 2759 2760 ifp = sc->ti_ifp; 2761 2762 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2763 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2764 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2765 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2766 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2767 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2768 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2769 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2770 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2771 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2772 2773 jumbocnt = minicnt = stdcnt = 0; 2774 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2775 struct ti_rx_desc *cur_rx; 2776 uint32_t rxidx; 2777 struct mbuf *m = NULL; 2778 uint16_t vlan_tag = 0; 2779 int have_tag = 0; 2780 2781 cur_rx = 2782 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2783 rxidx = cur_rx->ti_idx; 2784 ti_len = cur_rx->ti_len; 2785 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2786 2787 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2788 have_tag = 1; 2789 vlan_tag = cur_rx->ti_vlan_tag; 2790 } 2791 2792 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2793 jumbocnt++; 2794 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2795 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2796 #ifndef TI_SF_BUF_JUMBO 2797 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2798 ifp->if_ierrors++; 2799 ti_discard_jumbo(sc, rxidx); 2800 continue; 2801 } 2802 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2803 ifp->if_iqdrops++; 2804 ti_discard_jumbo(sc, rxidx); 2805 continue; 2806 } 2807 m->m_len = ti_len; 2808 #else /* !TI_SF_BUF_JUMBO */ 2809 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2810 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2811 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2812 BUS_DMASYNC_POSTREAD); 2813 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2814 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2815 ifp->if_ierrors++; 2816 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2817 continue; 2818 } 2819 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2820 ifp->if_iqdrops++; 2821 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2822 continue; 2823 } 2824 #ifdef TI_JUMBO_HDRSPLIT 2825 if (sc->ti_hdrsplit) 2826 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2827 ti_len, rxidx); 2828 else 2829 #endif /* TI_JUMBO_HDRSPLIT */ 2830 m_adj(m, ti_len - m->m_pkthdr.len); 2831 #endif /* TI_SF_BUF_JUMBO */ 2832 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2833 minicnt++; 2834 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2835 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2836 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2837 ifp->if_ierrors++; 2838 ti_discard_mini(sc, rxidx); 2839 continue; 2840 } 2841 if (ti_newbuf_mini(sc, rxidx) != 0) { 2842 ifp->if_iqdrops++; 2843 ti_discard_mini(sc, rxidx); 2844 continue; 2845 } 2846 m->m_len = ti_len; 2847 } else { 2848 stdcnt++; 2849 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2850 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2851 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2852 ifp->if_ierrors++; 2853 ti_discard_std(sc, rxidx); 2854 continue; 2855 } 2856 if (ti_newbuf_std(sc, rxidx) != 0) { 2857 ifp->if_iqdrops++; 2858 ti_discard_std(sc, rxidx); 2859 continue; 2860 } 2861 m->m_len = ti_len; 2862 } 2863 2864 m->m_pkthdr.len = ti_len; 2865 ifp->if_ipackets++; 2866 m->m_pkthdr.rcvif = ifp; 2867 2868 if (ifp->if_capenable & IFCAP_RXCSUM) { 2869 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2870 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2871 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2872 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2873 } 2874 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2875 m->m_pkthdr.csum_data = 2876 cur_rx->ti_tcp_udp_cksum; 2877 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2878 } 2879 } 2880 2881 /* 2882 * If we received a packet with a vlan tag, 2883 * tag it before passing the packet upward. 2884 */ 2885 if (have_tag) { 2886 m->m_pkthdr.ether_vtag = vlan_tag; 2887 m->m_flags |= M_VLANTAG; 2888 } 2889 TI_UNLOCK(sc); 2890 (*ifp->if_input)(ifp, m); 2891 TI_LOCK(sc); 2892 } 2893 2894 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2895 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2896 /* Only necessary on the Tigon 1. */ 2897 if (sc->ti_hwrev == TI_HWREV_TIGON) 2898 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2899 sc->ti_rx_saved_considx); 2900 2901 if (stdcnt > 0) { 2902 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2903 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2904 TI_UPDATE_STDPROD(sc, sc->ti_std); 2905 } 2906 if (minicnt > 0) { 2907 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2908 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2909 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2910 } 2911 if (jumbocnt > 0) { 2912 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2913 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2914 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2915 } 2916 } 2917 2918 static void 2919 ti_txeof(struct ti_softc *sc) 2920 { 2921 struct ti_txdesc *txd; 2922 struct ti_tx_desc txdesc; 2923 struct ti_tx_desc *cur_tx = NULL; 2924 struct ifnet *ifp; 2925 int idx; 2926 2927 ifp = sc->ti_ifp; 2928 2929 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2930 if (txd == NULL) 2931 return; 2932 2933 if (sc->ti_rdata.ti_tx_ring != NULL) 2934 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2935 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2936 /* 2937 * Go through our tx ring and free mbufs for those 2938 * frames that have been sent. 2939 */ 2940 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2941 TI_INC(idx, TI_TX_RING_CNT)) { 2942 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2943 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2944 sizeof(txdesc), &txdesc); 2945 cur_tx = &txdesc; 2946 } else 2947 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2948 sc->ti_txcnt--; 2949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2950 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2951 continue; 2952 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2953 BUS_DMASYNC_POSTWRITE); 2954 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2955 2956 ifp->if_opackets++; 2957 m_freem(txd->tx_m); 2958 txd->tx_m = NULL; 2959 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2960 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2961 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2962 } 2963 sc->ti_tx_saved_considx = idx; 2964 if (sc->ti_txcnt == 0) 2965 sc->ti_timer = 0; 2966 } 2967 2968 static void 2969 ti_intr(void *xsc) 2970 { 2971 struct ti_softc *sc; 2972 struct ifnet *ifp; 2973 2974 sc = xsc; 2975 TI_LOCK(sc); 2976 ifp = sc->ti_ifp; 2977 2978 /* Make sure this is really our interrupt. */ 2979 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2980 TI_UNLOCK(sc); 2981 return; 2982 } 2983 2984 /* Ack interrupt and stop others from occuring. */ 2985 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2986 2987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2988 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2989 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2990 /* Check RX return ring producer/consumer */ 2991 ti_rxeof(sc); 2992 2993 /* Check TX ring producer/consumer */ 2994 ti_txeof(sc); 2995 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2996 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2997 } 2998 2999 ti_handle_events(sc); 3000 3001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3002 /* Re-enable interrupts. */ 3003 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3004 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3005 ti_start_locked(ifp); 3006 } 3007 3008 TI_UNLOCK(sc); 3009 } 3010 3011 static void 3012 ti_stats_update(struct ti_softc *sc) 3013 { 3014 struct ifnet *ifp; 3015 struct ti_stats *s; 3016 3017 ifp = sc->ti_ifp; 3018 3019 if (sc->ti_stat_ticks == 0) 3020 return; 3021 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3022 BUS_DMASYNC_POSTREAD); 3023 3024 s = &sc->ti_rdata.ti_info->ti_stats; 3025 ifp->if_collisions += (s->dot3StatsSingleCollisionFrames + 3026 s->dot3StatsMultipleCollisionFrames + 3027 s->dot3StatsExcessiveCollisions + s->dot3StatsLateCollisions) - 3028 ifp->if_collisions; 3029 3030 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 3031 BUS_DMASYNC_PREREAD); 3032 } 3033 3034 /* 3035 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3036 * pointers to descriptors. 3037 */ 3038 static int 3039 ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3040 { 3041 struct ti_txdesc *txd; 3042 struct ti_tx_desc *f; 3043 struct ti_tx_desc txdesc; 3044 struct mbuf *m; 3045 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3046 uint16_t csum_flags; 3047 int error, frag, i, nseg; 3048 3049 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3050 return (ENOBUFS); 3051 3052 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3053 *m_head, txsegs, &nseg, 0); 3054 if (error == EFBIG) { 3055 m = m_defrag(*m_head, M_NOWAIT); 3056 if (m == NULL) { 3057 m_freem(*m_head); 3058 *m_head = NULL; 3059 return (ENOMEM); 3060 } 3061 *m_head = m; 3062 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3063 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3064 if (error) { 3065 m_freem(*m_head); 3066 *m_head = NULL; 3067 return (error); 3068 } 3069 } else if (error != 0) 3070 return (error); 3071 if (nseg == 0) { 3072 m_freem(*m_head); 3073 *m_head = NULL; 3074 return (EIO); 3075 } 3076 3077 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3078 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3079 return (ENOBUFS); 3080 } 3081 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3082 BUS_DMASYNC_PREWRITE); 3083 3084 m = *m_head; 3085 csum_flags = 0; 3086 if (m->m_pkthdr.csum_flags & CSUM_IP) 3087 csum_flags |= TI_BDFLAG_IP_CKSUM; 3088 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3089 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3090 3091 frag = sc->ti_tx_saved_prodidx; 3092 for (i = 0; i < nseg; i++) { 3093 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3094 bzero(&txdesc, sizeof(txdesc)); 3095 f = &txdesc; 3096 } else 3097 f = &sc->ti_rdata.ti_tx_ring[frag]; 3098 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3099 f->ti_len = txsegs[i].ds_len; 3100 f->ti_flags = csum_flags; 3101 if (m->m_flags & M_VLANTAG) { 3102 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3103 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3104 } else { 3105 f->ti_vlan_tag = 0; 3106 } 3107 3108 if (sc->ti_hwrev == TI_HWREV_TIGON) 3109 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3110 sizeof(txdesc), sizeof(txdesc), &txdesc); 3111 TI_INC(frag, TI_TX_RING_CNT); 3112 } 3113 3114 sc->ti_tx_saved_prodidx = frag; 3115 /* set TI_BDFLAG_END on the last descriptor */ 3116 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3117 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3118 txdesc.ti_flags |= TI_BDFLAG_END; 3119 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3120 sizeof(txdesc), &txdesc); 3121 } else 3122 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3123 3124 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3125 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3126 txd->tx_m = m; 3127 sc->ti_txcnt += nseg; 3128 3129 return (0); 3130 } 3131 3132 static void 3133 ti_start(struct ifnet *ifp) 3134 { 3135 struct ti_softc *sc; 3136 3137 sc = ifp->if_softc; 3138 TI_LOCK(sc); 3139 ti_start_locked(ifp); 3140 TI_UNLOCK(sc); 3141 } 3142 3143 /* 3144 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3145 * to the mbuf data regions directly in the transmit descriptors. 3146 */ 3147 static void 3148 ti_start_locked(struct ifnet *ifp) 3149 { 3150 struct ti_softc *sc; 3151 struct mbuf *m_head = NULL; 3152 int enq = 0; 3153 3154 sc = ifp->if_softc; 3155 3156 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3157 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3158 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3159 if (m_head == NULL) 3160 break; 3161 3162 /* 3163 * Pack the data into the transmit ring. If we 3164 * don't have room, set the OACTIVE flag and wait 3165 * for the NIC to drain the ring. 3166 */ 3167 if (ti_encap(sc, &m_head)) { 3168 if (m_head == NULL) 3169 break; 3170 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3171 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3172 break; 3173 } 3174 3175 enq++; 3176 /* 3177 * If there's a BPF listener, bounce a copy of this frame 3178 * to him. 3179 */ 3180 ETHER_BPF_MTAP(ifp, m_head); 3181 } 3182 3183 if (enq > 0) { 3184 if (sc->ti_rdata.ti_tx_ring != NULL) 3185 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3186 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3187 /* Transmit */ 3188 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3189 3190 /* 3191 * Set a timeout in case the chip goes out to lunch. 3192 */ 3193 sc->ti_timer = 5; 3194 } 3195 } 3196 3197 static void 3198 ti_init(void *xsc) 3199 { 3200 struct ti_softc *sc; 3201 3202 sc = xsc; 3203 TI_LOCK(sc); 3204 ti_init_locked(sc); 3205 TI_UNLOCK(sc); 3206 } 3207 3208 static void 3209 ti_init_locked(void *xsc) 3210 { 3211 struct ti_softc *sc = xsc; 3212 3213 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3214 return; 3215 3216 /* Cancel pending I/O and flush buffers. */ 3217 ti_stop(sc); 3218 3219 /* Init the gen info block, ring control blocks and firmware. */ 3220 if (ti_gibinit(sc)) { 3221 device_printf(sc->ti_dev, "initialization failure\n"); 3222 return; 3223 } 3224 } 3225 3226 static void ti_init2(struct ti_softc *sc) 3227 { 3228 struct ti_cmd_desc cmd; 3229 struct ifnet *ifp; 3230 uint8_t *ea; 3231 struct ifmedia *ifm; 3232 int tmp; 3233 3234 TI_LOCK_ASSERT(sc); 3235 3236 ifp = sc->ti_ifp; 3237 3238 /* Specify MTU and interface index. */ 3239 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3240 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3241 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3242 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3243 3244 /* Load our MAC address. */ 3245 ea = IF_LLADDR(sc->ti_ifp); 3246 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3247 CSR_WRITE_4(sc, TI_GCR_PAR1, 3248 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3249 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3250 3251 /* Enable or disable promiscuous mode as needed. */ 3252 if (ifp->if_flags & IFF_PROMISC) { 3253 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3254 } else { 3255 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3256 } 3257 3258 /* Program multicast filter. */ 3259 ti_setmulti(sc); 3260 3261 /* 3262 * If this is a Tigon 1, we should tell the 3263 * firmware to use software packet filtering. 3264 */ 3265 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3266 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3267 } 3268 3269 /* Init RX ring. */ 3270 if (ti_init_rx_ring_std(sc) != 0) { 3271 /* XXX */ 3272 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3273 return; 3274 } 3275 3276 /* Init jumbo RX ring. */ 3277 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3278 if (ti_init_rx_ring_jumbo(sc) != 0) { 3279 /* XXX */ 3280 device_printf(sc->ti_dev, 3281 "no memory for jumbo Rx buffers.\n"); 3282 return; 3283 } 3284 } 3285 3286 /* 3287 * If this is a Tigon 2, we can also configure the 3288 * mini ring. 3289 */ 3290 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3291 if (ti_init_rx_ring_mini(sc) != 0) { 3292 /* XXX */ 3293 device_printf(sc->ti_dev, 3294 "no memory for mini Rx buffers.\n"); 3295 return; 3296 } 3297 } 3298 3299 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3300 sc->ti_rx_saved_considx = 0; 3301 3302 /* Init TX ring. */ 3303 ti_init_tx_ring(sc); 3304 3305 /* Tell firmware we're alive. */ 3306 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3307 3308 /* Enable host interrupts. */ 3309 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3310 3311 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3312 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3313 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3314 3315 /* 3316 * Make sure to set media properly. We have to do this 3317 * here since we have to issue commands in order to set 3318 * the link negotiation and we can't issue commands until 3319 * the firmware is running. 3320 */ 3321 ifm = &sc->ifmedia; 3322 tmp = ifm->ifm_media; 3323 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3324 ti_ifmedia_upd_locked(sc); 3325 ifm->ifm_media = tmp; 3326 } 3327 3328 /* 3329 * Set media options. 3330 */ 3331 static int 3332 ti_ifmedia_upd(struct ifnet *ifp) 3333 { 3334 struct ti_softc *sc; 3335 int error; 3336 3337 sc = ifp->if_softc; 3338 TI_LOCK(sc); 3339 error = ti_ifmedia_upd(ifp); 3340 TI_UNLOCK(sc); 3341 3342 return (error); 3343 } 3344 3345 static int 3346 ti_ifmedia_upd_locked(struct ti_softc *sc) 3347 { 3348 struct ifmedia *ifm; 3349 struct ti_cmd_desc cmd; 3350 uint32_t flowctl; 3351 3352 ifm = &sc->ifmedia; 3353 3354 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3355 return (EINVAL); 3356 3357 flowctl = 0; 3358 3359 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3360 case IFM_AUTO: 3361 /* 3362 * Transmit flow control doesn't work on the Tigon 1. 3363 */ 3364 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3365 3366 /* 3367 * Transmit flow control can also cause problems on the 3368 * Tigon 2, apparantly with both the copper and fiber 3369 * boards. The symptom is that the interface will just 3370 * hang. This was reproduced with Alteon 180 switches. 3371 */ 3372 #if 0 3373 if (sc->ti_hwrev != TI_HWREV_TIGON) 3374 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3375 #endif 3376 3377 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3378 TI_GLNK_FULL_DUPLEX| flowctl | 3379 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3380 3381 flowctl = TI_LNK_RX_FLOWCTL_Y; 3382 #if 0 3383 if (sc->ti_hwrev != TI_HWREV_TIGON) 3384 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3385 #endif 3386 3387 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3388 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3389 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3390 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3391 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3392 break; 3393 case IFM_1000_SX: 3394 case IFM_1000_T: 3395 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3396 #if 0 3397 if (sc->ti_hwrev != TI_HWREV_TIGON) 3398 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3399 #endif 3400 3401 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3402 flowctl |TI_GLNK_ENB); 3403 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3404 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3405 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3406 } 3407 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3408 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3409 break; 3410 case IFM_100_FX: 3411 case IFM_10_FL: 3412 case IFM_100_TX: 3413 case IFM_10_T: 3414 flowctl = TI_LNK_RX_FLOWCTL_Y; 3415 #if 0 3416 if (sc->ti_hwrev != TI_HWREV_TIGON) 3417 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3418 #endif 3419 3420 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3421 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3422 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3423 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3424 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3425 } else { 3426 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3427 } 3428 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3429 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3430 } else { 3431 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3432 } 3433 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3434 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3435 break; 3436 } 3437 3438 return (0); 3439 } 3440 3441 /* 3442 * Report current media status. 3443 */ 3444 static void 3445 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3446 { 3447 struct ti_softc *sc; 3448 uint32_t media = 0; 3449 3450 sc = ifp->if_softc; 3451 3452 TI_LOCK(sc); 3453 3454 ifmr->ifm_status = IFM_AVALID; 3455 ifmr->ifm_active = IFM_ETHER; 3456 3457 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3458 TI_UNLOCK(sc); 3459 return; 3460 } 3461 3462 ifmr->ifm_status |= IFM_ACTIVE; 3463 3464 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3465 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3466 if (sc->ti_copper) 3467 ifmr->ifm_active |= IFM_1000_T; 3468 else 3469 ifmr->ifm_active |= IFM_1000_SX; 3470 if (media & TI_GLNK_FULL_DUPLEX) 3471 ifmr->ifm_active |= IFM_FDX; 3472 else 3473 ifmr->ifm_active |= IFM_HDX; 3474 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3475 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3476 if (sc->ti_copper) { 3477 if (media & TI_LNK_100MB) 3478 ifmr->ifm_active |= IFM_100_TX; 3479 if (media & TI_LNK_10MB) 3480 ifmr->ifm_active |= IFM_10_T; 3481 } else { 3482 if (media & TI_LNK_100MB) 3483 ifmr->ifm_active |= IFM_100_FX; 3484 if (media & TI_LNK_10MB) 3485 ifmr->ifm_active |= IFM_10_FL; 3486 } 3487 if (media & TI_LNK_FULL_DUPLEX) 3488 ifmr->ifm_active |= IFM_FDX; 3489 if (media & TI_LNK_HALF_DUPLEX) 3490 ifmr->ifm_active |= IFM_HDX; 3491 } 3492 TI_UNLOCK(sc); 3493 } 3494 3495 static int 3496 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3497 { 3498 struct ti_softc *sc = ifp->if_softc; 3499 struct ifreq *ifr = (struct ifreq *) data; 3500 struct ti_cmd_desc cmd; 3501 int mask, error = 0; 3502 3503 switch (command) { 3504 case SIOCSIFMTU: 3505 TI_LOCK(sc); 3506 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3507 error = EINVAL; 3508 else { 3509 ifp->if_mtu = ifr->ifr_mtu; 3510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3511 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3512 ti_init_locked(sc); 3513 } 3514 } 3515 TI_UNLOCK(sc); 3516 break; 3517 case SIOCSIFFLAGS: 3518 TI_LOCK(sc); 3519 if (ifp->if_flags & IFF_UP) { 3520 /* 3521 * If only the state of the PROMISC flag changed, 3522 * then just use the 'set promisc mode' command 3523 * instead of reinitializing the entire NIC. Doing 3524 * a full re-init means reloading the firmware and 3525 * waiting for it to start up, which may take a 3526 * second or two. 3527 */ 3528 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3529 ifp->if_flags & IFF_PROMISC && 3530 !(sc->ti_if_flags & IFF_PROMISC)) { 3531 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3532 TI_CMD_CODE_PROMISC_ENB, 0); 3533 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3534 !(ifp->if_flags & IFF_PROMISC) && 3535 sc->ti_if_flags & IFF_PROMISC) { 3536 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3537 TI_CMD_CODE_PROMISC_DIS, 0); 3538 } else 3539 ti_init_locked(sc); 3540 } else { 3541 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3542 ti_stop(sc); 3543 } 3544 } 3545 sc->ti_if_flags = ifp->if_flags; 3546 TI_UNLOCK(sc); 3547 break; 3548 case SIOCADDMULTI: 3549 case SIOCDELMULTI: 3550 TI_LOCK(sc); 3551 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3552 ti_setmulti(sc); 3553 TI_UNLOCK(sc); 3554 break; 3555 case SIOCSIFMEDIA: 3556 case SIOCGIFMEDIA: 3557 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3558 break; 3559 case SIOCSIFCAP: 3560 TI_LOCK(sc); 3561 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3562 if ((mask & IFCAP_TXCSUM) != 0 && 3563 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3564 ifp->if_capenable ^= IFCAP_TXCSUM; 3565 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3566 ifp->if_hwassist |= TI_CSUM_FEATURES; 3567 else 3568 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3569 } 3570 if ((mask & IFCAP_RXCSUM) != 0 && 3571 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3572 ifp->if_capenable ^= IFCAP_RXCSUM; 3573 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3574 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3575 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3576 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3577 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3578 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3579 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3580 IFCAP_VLAN_HWTAGGING)) != 0) { 3581 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3582 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3583 ti_init_locked(sc); 3584 } 3585 } 3586 TI_UNLOCK(sc); 3587 VLAN_CAPABILITIES(ifp); 3588 break; 3589 default: 3590 error = ether_ioctl(ifp, command, data); 3591 break; 3592 } 3593 3594 return (error); 3595 } 3596 3597 static int 3598 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3599 { 3600 struct ti_softc *sc; 3601 3602 sc = dev->si_drv1; 3603 if (sc == NULL) 3604 return (ENODEV); 3605 3606 TI_LOCK(sc); 3607 sc->ti_flags |= TI_FLAG_DEBUGING; 3608 TI_UNLOCK(sc); 3609 3610 return (0); 3611 } 3612 3613 static int 3614 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3615 { 3616 struct ti_softc *sc; 3617 3618 sc = dev->si_drv1; 3619 if (sc == NULL) 3620 return (ENODEV); 3621 3622 TI_LOCK(sc); 3623 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3624 TI_UNLOCK(sc); 3625 3626 return (0); 3627 } 3628 3629 /* 3630 * This ioctl routine goes along with the Tigon character device. 3631 */ 3632 static int 3633 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3634 struct thread *td) 3635 { 3636 struct ti_softc *sc; 3637 int error; 3638 3639 sc = dev->si_drv1; 3640 if (sc == NULL) 3641 return (ENODEV); 3642 3643 error = 0; 3644 3645 switch (cmd) { 3646 case TIIOCGETSTATS: 3647 { 3648 struct ti_stats *outstats; 3649 3650 outstats = (struct ti_stats *)addr; 3651 3652 TI_LOCK(sc); 3653 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3654 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3655 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3656 sizeof(struct ti_stats)); 3657 TI_UNLOCK(sc); 3658 break; 3659 } 3660 case TIIOCGETPARAMS: 3661 { 3662 struct ti_params *params; 3663 3664 params = (struct ti_params *)addr; 3665 3666 TI_LOCK(sc); 3667 params->ti_stat_ticks = sc->ti_stat_ticks; 3668 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3669 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3670 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3671 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3672 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3673 params->param_mask = TI_PARAM_ALL; 3674 TI_UNLOCK(sc); 3675 break; 3676 } 3677 case TIIOCSETPARAMS: 3678 { 3679 struct ti_params *params; 3680 3681 params = (struct ti_params *)addr; 3682 3683 TI_LOCK(sc); 3684 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3685 sc->ti_stat_ticks = params->ti_stat_ticks; 3686 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3687 } 3688 3689 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3690 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3691 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3692 sc->ti_rx_coal_ticks); 3693 } 3694 3695 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3696 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3697 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3698 sc->ti_tx_coal_ticks); 3699 } 3700 3701 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3702 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3703 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3704 sc->ti_rx_max_coal_bds); 3705 } 3706 3707 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3708 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3709 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3710 sc->ti_tx_max_coal_bds); 3711 } 3712 3713 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3714 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3715 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3716 sc->ti_tx_buf_ratio); 3717 } 3718 TI_UNLOCK(sc); 3719 break; 3720 } 3721 case TIIOCSETTRACE: { 3722 ti_trace_type trace_type; 3723 3724 trace_type = *(ti_trace_type *)addr; 3725 3726 /* 3727 * Set tracing to whatever the user asked for. Setting 3728 * this register to 0 should have the effect of disabling 3729 * tracing. 3730 */ 3731 TI_LOCK(sc); 3732 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3733 TI_UNLOCK(sc); 3734 break; 3735 } 3736 case TIIOCGETTRACE: { 3737 struct ti_trace_buf *trace_buf; 3738 uint32_t trace_start, cur_trace_ptr, trace_len; 3739 3740 trace_buf = (struct ti_trace_buf *)addr; 3741 3742 TI_LOCK(sc); 3743 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3744 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3745 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3746 #if 0 3747 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3748 "trace_len = %d\n", trace_start, 3749 cur_trace_ptr, trace_len); 3750 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3751 trace_buf->buf_len); 3752 #endif 3753 error = ti_copy_mem(sc, trace_start, min(trace_len, 3754 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3755 if (error == 0) { 3756 trace_buf->fill_len = min(trace_len, 3757 trace_buf->buf_len); 3758 if (cur_trace_ptr < trace_start) 3759 trace_buf->cur_trace_ptr = 3760 trace_start - cur_trace_ptr; 3761 else 3762 trace_buf->cur_trace_ptr = 3763 cur_trace_ptr - trace_start; 3764 } else 3765 trace_buf->fill_len = 0; 3766 TI_UNLOCK(sc); 3767 break; 3768 } 3769 3770 /* 3771 * For debugging, five ioctls are needed: 3772 * ALT_ATTACH 3773 * ALT_READ_TG_REG 3774 * ALT_WRITE_TG_REG 3775 * ALT_READ_TG_MEM 3776 * ALT_WRITE_TG_MEM 3777 */ 3778 case ALT_ATTACH: 3779 /* 3780 * From what I can tell, Alteon's Solaris Tigon driver 3781 * only has one character device, so you have to attach 3782 * to the Tigon board you're interested in. This seems 3783 * like a not-so-good way to do things, since unless you 3784 * subsequently specify the unit number of the device 3785 * you're interested in every ioctl, you'll only be 3786 * able to debug one board at a time. 3787 */ 3788 break; 3789 case ALT_READ_TG_MEM: 3790 case ALT_WRITE_TG_MEM: 3791 { 3792 struct tg_mem *mem_param; 3793 uint32_t sram_end, scratch_end; 3794 3795 mem_param = (struct tg_mem *)addr; 3796 3797 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3798 sram_end = TI_END_SRAM_I; 3799 scratch_end = TI_END_SCRATCH_I; 3800 } else { 3801 sram_end = TI_END_SRAM_II; 3802 scratch_end = TI_END_SCRATCH_II; 3803 } 3804 3805 /* 3806 * For now, we'll only handle accessing regular SRAM, 3807 * nothing else. 3808 */ 3809 TI_LOCK(sc); 3810 if (mem_param->tgAddr >= TI_BEG_SRAM && 3811 mem_param->tgAddr + mem_param->len <= sram_end) { 3812 /* 3813 * In this instance, we always copy to/from user 3814 * space, so the user space argument is set to 1. 3815 */ 3816 error = ti_copy_mem(sc, mem_param->tgAddr, 3817 mem_param->len, mem_param->userAddr, 1, 3818 cmd == ALT_READ_TG_MEM ? 1 : 0); 3819 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3820 mem_param->tgAddr <= scratch_end) { 3821 error = ti_copy_scratch(sc, mem_param->tgAddr, 3822 mem_param->len, mem_param->userAddr, 1, 3823 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3824 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3825 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3826 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3827 if_printf(sc->ti_ifp, 3828 "invalid memory range for Tigon I\n"); 3829 error = EINVAL; 3830 break; 3831 } 3832 error = ti_copy_scratch(sc, mem_param->tgAddr - 3833 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3834 mem_param->userAddr, 1, 3835 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3836 } else { 3837 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3838 "out of supported range\n", 3839 mem_param->tgAddr, mem_param->len); 3840 error = EINVAL; 3841 } 3842 TI_UNLOCK(sc); 3843 break; 3844 } 3845 case ALT_READ_TG_REG: 3846 case ALT_WRITE_TG_REG: 3847 { 3848 struct tg_reg *regs; 3849 uint32_t tmpval; 3850 3851 regs = (struct tg_reg *)addr; 3852 3853 /* 3854 * Make sure the address in question isn't out of range. 3855 */ 3856 if (regs->addr > TI_REG_MAX) { 3857 error = EINVAL; 3858 break; 3859 } 3860 TI_LOCK(sc); 3861 if (cmd == ALT_READ_TG_REG) { 3862 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3863 regs->addr, &tmpval, 1); 3864 regs->data = ntohl(tmpval); 3865 #if 0 3866 if ((regs->addr == TI_CPU_STATE) 3867 || (regs->addr == TI_CPU_CTL_B)) { 3868 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3869 regs->addr, tmpval); 3870 } 3871 #endif 3872 } else { 3873 tmpval = htonl(regs->data); 3874 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3875 regs->addr, &tmpval, 1); 3876 } 3877 TI_UNLOCK(sc); 3878 break; 3879 } 3880 default: 3881 error = ENOTTY; 3882 break; 3883 } 3884 return (error); 3885 } 3886 3887 static void 3888 ti_watchdog(void *arg) 3889 { 3890 struct ti_softc *sc; 3891 struct ifnet *ifp; 3892 3893 sc = arg; 3894 TI_LOCK_ASSERT(sc); 3895 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3896 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3897 return; 3898 3899 /* 3900 * When we're debugging, the chip is often stopped for long periods 3901 * of time, and that would normally cause the watchdog timer to fire. 3902 * Since that impedes debugging, we don't want to do that. 3903 */ 3904 if (sc->ti_flags & TI_FLAG_DEBUGING) 3905 return; 3906 3907 ifp = sc->ti_ifp; 3908 if_printf(ifp, "watchdog timeout -- resetting\n"); 3909 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3910 ti_init_locked(sc); 3911 3912 ifp->if_oerrors++; 3913 } 3914 3915 /* 3916 * Stop the adapter and free any mbufs allocated to the 3917 * RX and TX lists. 3918 */ 3919 static void 3920 ti_stop(struct ti_softc *sc) 3921 { 3922 struct ifnet *ifp; 3923 struct ti_cmd_desc cmd; 3924 3925 TI_LOCK_ASSERT(sc); 3926 3927 ifp = sc->ti_ifp; 3928 3929 /* Disable host interrupts. */ 3930 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3931 /* 3932 * Tell firmware we're shutting down. 3933 */ 3934 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3935 3936 /* Halt and reinitialize. */ 3937 if (ti_chipinit(sc) == 0) { 3938 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3939 /* XXX ignore init errors. */ 3940 ti_chipinit(sc); 3941 } 3942 3943 /* Free the RX lists. */ 3944 ti_free_rx_ring_std(sc); 3945 3946 /* Free jumbo RX list. */ 3947 ti_free_rx_ring_jumbo(sc); 3948 3949 /* Free mini RX list. */ 3950 ti_free_rx_ring_mini(sc); 3951 3952 /* Free TX buffers. */ 3953 ti_free_tx_ring(sc); 3954 3955 sc->ti_ev_prodidx.ti_idx = 0; 3956 sc->ti_return_prodidx.ti_idx = 0; 3957 sc->ti_tx_considx.ti_idx = 0; 3958 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3959 3960 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3961 callout_stop(&sc->ti_watchdog); 3962 } 3963 3964 /* 3965 * Stop all chip I/O so that the kernel's probe routines don't 3966 * get confused by errant DMAs when rebooting. 3967 */ 3968 static int 3969 ti_shutdown(device_t dev) 3970 { 3971 struct ti_softc *sc; 3972 3973 sc = device_get_softc(dev); 3974 TI_LOCK(sc); 3975 ti_chipinit(sc); 3976 TI_UNLOCK(sc); 3977 3978 return (0); 3979 } 3980 3981 static void 3982 ti_sysctl_node(struct ti_softc *sc) 3983 { 3984 struct sysctl_ctx_list *ctx; 3985 struct sysctl_oid_list *child; 3986 char tname[32]; 3987 3988 ctx = device_get_sysctl_ctx(sc->ti_dev); 3989 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 3990 3991 /* Use DAC */ 3992 sc->ti_dac = 1; 3993 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 3994 device_get_unit(sc->ti_dev)); 3995 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 3996 3997 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 3998 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 3999 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4000 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4001 4002 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4003 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4004 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4005 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4006 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4007 &sc->ti_tx_buf_ratio, 0, 4008 "Ratio of NIC memory devoted to TX buffer"); 4009 4010 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4011 &sc->ti_stat_ticks, 0, 4012 "Number of clock ticks for statistics update interval"); 4013 4014 /* Pull in device tunables. */ 4015 sc->ti_rx_coal_ticks = 170; 4016 resource_int_value(device_get_name(sc->ti_dev), 4017 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4018 &sc->ti_rx_coal_ticks); 4019 sc->ti_rx_max_coal_bds = 64; 4020 resource_int_value(device_get_name(sc->ti_dev), 4021 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4022 &sc->ti_rx_max_coal_bds); 4023 4024 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4025 resource_int_value(device_get_name(sc->ti_dev), 4026 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4027 &sc->ti_tx_coal_ticks); 4028 sc->ti_tx_max_coal_bds = 32; 4029 resource_int_value(device_get_name(sc->ti_dev), 4030 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4031 &sc->ti_tx_max_coal_bds); 4032 sc->ti_tx_buf_ratio = 21; 4033 resource_int_value(device_get_name(sc->ti_dev), 4034 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4035 &sc->ti_tx_buf_ratio); 4036 4037 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4038 resource_int_value(device_get_name(sc->ti_dev), 4039 device_get_unit(sc->ti_dev), "stat_ticks", 4040 &sc->ti_stat_ticks); 4041 } 4042