1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 95 #include <net/if.h> 96 #include <net/if_arp.h> 97 #include <net/ethernet.h> 98 #include <net/if_dl.h> 99 #include <net/if_media.h> 100 #include <net/if_types.h> 101 #include <net/if_vlan_var.h> 102 103 #include <net/bpf.h> 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/bus_memio.h> 112 #include <machine/bus.h> 113 #include <machine/resource.h> 114 #include <sys/bus.h> 115 #include <sys/rman.h> 116 117 /* #define TI_PRIVATE_JUMBOS */ 118 119 #if !defined(TI_PRIVATE_JUMBOS) 120 #include <sys/sockio.h> 121 #include <sys/uio.h> 122 #include <sys/lock.h> 123 #include <sys/sf_buf.h> 124 #include <vm/vm_extern.h> 125 #include <vm/pmap.h> 126 #include <vm/vm_map.h> 127 #include <vm/vm_map.h> 128 #include <vm/vm_param.h> 129 #include <vm/vm_pageout.h> 130 #include <sys/vmmeter.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_object.h> 133 #include <vm/vm_kern.h> 134 #include <sys/proc.h> 135 #endif /* !TI_PRIVATE_JUMBOS */ 136 137 #include <dev/pci/pcireg.h> 138 #include <dev/pci/pcivar.h> 139 140 #include <sys/tiio.h> 141 #include <pci/if_tireg.h> 142 #include <pci/ti_fw.h> 143 #include <pci/ti_fw2.h> 144 145 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 146 /* 147 * We can only turn on header splitting if we're using extended receive 148 * BDs. 149 */ 150 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 151 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 152 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 153 154 struct ti_softc *tis[8]; 155 156 typedef enum { 157 TI_SWAP_HTON, 158 TI_SWAP_NTOH 159 } ti_swap_type; 160 161 162 /* 163 * Various supported device vendors/types and their names. 164 */ 165 166 static struct ti_type ti_devs[] = { 167 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 170 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 171 { TC_VENDORID, TC_DEVICEID_3C985, 172 "3Com 3c985-SX Gigabit Ethernet" }, 173 { NG_VENDORID, NG_DEVICEID_GA620, 174 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 175 { NG_VENDORID, NG_DEVICEID_GA620T, 176 "Netgear GA620 1000baseT Gigabit Ethernet" }, 177 { SGI_VENDORID, SGI_DEVICEID_TIGON, 178 "Silicon Graphics Gigabit Ethernet" }, 179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 180 "Farallon PN9000SX Gigabit Ethernet" }, 181 { 0, 0, NULL } 182 }; 183 184 185 static d_open_t ti_open; 186 static d_close_t ti_close; 187 static d_ioctl_t ti_ioctl2; 188 189 static struct cdevsw ti_cdevsw = { 190 .d_version = D_VERSION, 191 .d_flags = D_NEEDGIANT, 192 .d_open = ti_open, 193 .d_close = ti_close, 194 .d_ioctl = ti_ioctl2, 195 .d_name = "ti", 196 }; 197 198 static int ti_probe (device_t); 199 static int ti_attach (device_t); 200 static int ti_detach (device_t); 201 static void ti_txeof (struct ti_softc *); 202 static void ti_rxeof (struct ti_softc *); 203 204 static void ti_stats_update (struct ti_softc *); 205 static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 206 207 static void ti_intr (void *); 208 static void ti_start (struct ifnet *); 209 static int ti_ioctl (struct ifnet *, u_long, caddr_t); 210 static void ti_init (void *); 211 static void ti_init2 (struct ti_softc *); 212 static void ti_stop (struct ti_softc *); 213 static void ti_watchdog (struct ifnet *); 214 static void ti_shutdown (device_t); 215 static int ti_ifmedia_upd (struct ifnet *); 216 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 219 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 220 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 221 222 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 223 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 224 static void ti_setmulti (struct ti_softc *); 225 226 static void ti_mem (struct ti_softc *, u_int32_t, 227 u_int32_t, caddr_t); 228 static int ti_copy_mem (struct ti_softc *, u_int32_t, 229 u_int32_t, caddr_t, int, int); 230 static int ti_copy_scratch (struct ti_softc *, u_int32_t, 231 u_int32_t, caddr_t, int, int, int); 232 static int ti_bcopy_swap (const void *, void *, size_t, 233 ti_swap_type); 234 static void ti_loadfw (struct ti_softc *); 235 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 236 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 237 caddr_t, int); 238 static void ti_handle_events (struct ti_softc *); 239 #ifdef TI_PRIVATE_JUMBOS 240 static int ti_alloc_jumbo_mem (struct ti_softc *); 241 static void *ti_jalloc (struct ti_softc *); 242 static void ti_jfree (void *, void *); 243 #endif /* TI_PRIVATE_JUMBOS */ 244 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 245 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 246 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 247 static int ti_init_rx_ring_std (struct ti_softc *); 248 static void ti_free_rx_ring_std (struct ti_softc *); 249 static int ti_init_rx_ring_jumbo (struct ti_softc *); 250 static void ti_free_rx_ring_jumbo (struct ti_softc *); 251 static int ti_init_rx_ring_mini (struct ti_softc *); 252 static void ti_free_rx_ring_mini (struct ti_softc *); 253 static void ti_free_tx_ring (struct ti_softc *); 254 static int ti_init_tx_ring (struct ti_softc *); 255 256 static int ti_64bitslot_war (struct ti_softc *); 257 static int ti_chipinit (struct ti_softc *); 258 static int ti_gibinit (struct ti_softc *); 259 260 #ifdef TI_JUMBO_HDRSPLIT 261 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 262 int pkt_len, int idx); 263 #endif /* TI_JUMBO_HDRSPLIT */ 264 265 static device_method_t ti_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, ti_probe), 268 DEVMETHOD(device_attach, ti_attach), 269 DEVMETHOD(device_detach, ti_detach), 270 DEVMETHOD(device_shutdown, ti_shutdown), 271 { 0, 0 } 272 }; 273 274 static driver_t ti_driver = { 275 "ti", 276 ti_methods, 277 sizeof(struct ti_softc) 278 }; 279 280 static devclass_t ti_devclass; 281 282 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 283 MODULE_DEPEND(ti, pci, 1, 1, 1); 284 MODULE_DEPEND(ti, ether, 1, 1, 1); 285 286 /* 287 * Send an instruction or address to the EEPROM, check for ACK. 288 */ 289 static u_int32_t ti_eeprom_putbyte(sc, byte) 290 struct ti_softc *sc; 291 int byte; 292 { 293 register int i, ack = 0; 294 295 /* 296 * Make sure we're in TX mode. 297 */ 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 299 300 /* 301 * Feed in each bit and stobe the clock. 302 */ 303 for (i = 0x80; i; i >>= 1) { 304 if (byte & i) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 306 } else { 307 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 308 } 309 DELAY(1); 310 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 311 DELAY(1); 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 } 314 315 /* 316 * Turn off TX mode. 317 */ 318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 319 320 /* 321 * Check for ack. 322 */ 323 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 324 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 327 return (ack); 328 } 329 330 /* 331 * Read a byte of data stored in the EEPROM at address 'addr.' 332 * We have to send two address bytes since the EEPROM can hold 333 * more than 256 bytes of data. 334 */ 335 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 336 struct ti_softc *sc; 337 int addr; 338 u_int8_t *dest; 339 { 340 register int i; 341 u_int8_t byte = 0; 342 343 EEPROM_START; 344 345 /* 346 * Send write control code to EEPROM. 347 */ 348 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 349 printf("ti%d: failed to send write command, status: %x\n", 350 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 351 return (1); 352 } 353 354 /* 355 * Send first byte of address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 358 printf("ti%d: failed to send address, status: %x\n", 359 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return (1); 361 } 362 /* 363 * Send second byte address of byte we want to read. 364 */ 365 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 366 printf("ti%d: failed to send address, status: %x\n", 367 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 368 return (1); 369 } 370 371 EEPROM_STOP; 372 EEPROM_START; 373 /* 374 * Send read control code to EEPROM. 375 */ 376 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 377 printf("ti%d: failed to send read command, status: %x\n", 378 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 379 return (1); 380 } 381 382 /* 383 * Start reading bits from EEPROM. 384 */ 385 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 386 for (i = 0x80; i; i >>= 1) { 387 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 388 DELAY(1); 389 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 390 byte |= i; 391 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 392 DELAY(1); 393 } 394 395 EEPROM_STOP; 396 397 /* 398 * No ACK generated for read, so just return byte. 399 */ 400 401 *dest = byte; 402 403 return (0); 404 } 405 406 /* 407 * Read a sequence of bytes from the EEPROM. 408 */ 409 static int 410 ti_read_eeprom(sc, dest, off, cnt) 411 struct ti_softc *sc; 412 caddr_t dest; 413 int off; 414 int cnt; 415 { 416 int err = 0, i; 417 u_int8_t byte = 0; 418 419 for (i = 0; i < cnt; i++) { 420 err = ti_eeprom_getbyte(sc, off + i, &byte); 421 if (err) 422 break; 423 *(dest + i) = byte; 424 } 425 426 return (err ? 1 : 0); 427 } 428 429 /* 430 * NIC memory access function. Can be used to either clear a section 431 * of NIC local memory or (if buf is non-NULL) copy data into it. 432 */ 433 static void 434 ti_mem(sc, addr, len, buf) 435 struct ti_softc *sc; 436 u_int32_t addr, len; 437 caddr_t buf; 438 { 439 int segptr, segsize, cnt; 440 caddr_t ti_winbase, ptr; 441 442 segptr = addr; 443 cnt = len; 444 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 445 ptr = buf; 446 447 while (cnt) { 448 if (cnt < TI_WINLEN) 449 segsize = cnt; 450 else 451 segsize = TI_WINLEN - (segptr % TI_WINLEN); 452 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 453 if (buf == NULL) 454 bzero((char *)ti_winbase + (segptr & 455 (TI_WINLEN - 1)), segsize); 456 else { 457 bcopy((char *)ptr, (char *)ti_winbase + 458 (segptr & (TI_WINLEN - 1)), segsize); 459 ptr += segsize; 460 } 461 segptr += segsize; 462 cnt -= segsize; 463 } 464 } 465 466 static int 467 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 468 struct ti_softc *sc; 469 u_int32_t tigon_addr, len; 470 caddr_t buf; 471 int useraddr, readdata; 472 { 473 int segptr, segsize, cnt; 474 caddr_t ptr; 475 u_int32_t origwin; 476 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 477 int resid, segresid; 478 int first_pass; 479 480 /* 481 * At the moment, we don't handle non-aligned cases, we just bail. 482 * If this proves to be a problem, it will be fixed. 483 */ 484 if ((readdata == 0) 485 && (tigon_addr & 0x3)) { 486 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 487 "word-aligned\n", sc->ti_unit, tigon_addr); 488 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 489 "supported\n", sc->ti_unit); 490 return (EINVAL); 491 } 492 493 segptr = tigon_addr & ~0x3; 494 segresid = tigon_addr - segptr; 495 496 /* 497 * This is the non-aligned amount left over that we'll need to 498 * copy. 499 */ 500 resid = len & 0x3; 501 502 /* Add in the left over amount at the front of the buffer */ 503 resid += segresid; 504 505 cnt = len & ~0x3; 506 /* 507 * If resid + segresid is >= 4, add multiples of 4 to the count and 508 * decrease the residual by that much. 509 */ 510 cnt += resid & ~0x3; 511 resid -= resid & ~0x3; 512 513 ptr = buf; 514 515 first_pass = 1; 516 517 /* 518 * Make sure we aren't interrupted while we're changing the window 519 * pointer. 520 */ 521 TI_LOCK(sc); 522 523 /* 524 * Save the old window base value. 525 */ 526 origwin = CSR_READ_4(sc, TI_WINBASE); 527 528 while (cnt) { 529 bus_size_t ti_offset; 530 531 if (cnt < TI_WINLEN) 532 segsize = cnt; 533 else 534 segsize = TI_WINLEN - (segptr % TI_WINLEN); 535 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 536 537 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 538 539 if (readdata) { 540 541 bus_space_read_region_4(sc->ti_btag, 542 sc->ti_bhandle, ti_offset, 543 (u_int32_t *)tmparray, 544 segsize >> 2); 545 if (useraddr) { 546 /* 547 * Yeah, this is a little on the kludgy 548 * side, but at least this code is only 549 * used for debugging. 550 */ 551 ti_bcopy_swap(tmparray, tmparray2, segsize, 552 TI_SWAP_NTOH); 553 554 if (first_pass) { 555 copyout(&tmparray2[segresid], ptr, 556 segsize - segresid); 557 first_pass = 0; 558 } else 559 copyout(tmparray2, ptr, segsize); 560 } else { 561 if (first_pass) { 562 563 ti_bcopy_swap(tmparray, tmparray2, 564 segsize, TI_SWAP_NTOH); 565 bcopy(&tmparray2[segresid], ptr, 566 segsize - segresid); 567 first_pass = 0; 568 } else 569 ti_bcopy_swap(tmparray, ptr, segsize, 570 TI_SWAP_NTOH); 571 } 572 573 } else { 574 if (useraddr) { 575 copyin(ptr, tmparray2, segsize); 576 ti_bcopy_swap(tmparray2, tmparray, segsize, 577 TI_SWAP_HTON); 578 } else 579 ti_bcopy_swap(ptr, tmparray, segsize, 580 TI_SWAP_HTON); 581 582 bus_space_write_region_4(sc->ti_btag, 583 sc->ti_bhandle, ti_offset, 584 (u_int32_t *)tmparray, 585 segsize >> 2); 586 } 587 segptr += segsize; 588 ptr += segsize; 589 cnt -= segsize; 590 } 591 592 /* 593 * Handle leftover, non-word-aligned bytes. 594 */ 595 if (resid != 0) { 596 u_int32_t tmpval, tmpval2; 597 bus_size_t ti_offset; 598 599 /* 600 * Set the segment pointer. 601 */ 602 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 603 604 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 605 606 /* 607 * First, grab whatever is in our source/destination. 608 * We'll obviously need this for reads, but also for 609 * writes, since we'll be doing read/modify/write. 610 */ 611 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 612 ti_offset, &tmpval, 1); 613 614 /* 615 * Next, translate this from little-endian to big-endian 616 * (at least on i386 boxes). 617 */ 618 tmpval2 = ntohl(tmpval); 619 620 if (readdata) { 621 /* 622 * If we're reading, just copy the leftover number 623 * of bytes from the host byte order buffer to 624 * the user's buffer. 625 */ 626 if (useraddr) 627 copyout(&tmpval2, ptr, resid); 628 else 629 bcopy(&tmpval2, ptr, resid); 630 } else { 631 /* 632 * If we're writing, first copy the bytes to be 633 * written into the network byte order buffer, 634 * leaving the rest of the buffer with whatever was 635 * originally in there. Then, swap the bytes 636 * around into host order and write them out. 637 * 638 * XXX KDM the read side of this has been verified 639 * to work, but the write side of it has not been 640 * verified. So user beware. 641 */ 642 if (useraddr) 643 copyin(ptr, &tmpval2, resid); 644 else 645 bcopy(ptr, &tmpval2, resid); 646 647 tmpval = htonl(tmpval2); 648 649 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 650 ti_offset, &tmpval, 1); 651 } 652 } 653 654 CSR_WRITE_4(sc, TI_WINBASE, origwin); 655 656 TI_UNLOCK(sc); 657 658 return (0); 659 } 660 661 static int 662 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 663 struct ti_softc *sc; 664 u_int32_t tigon_addr, len; 665 caddr_t buf; 666 int useraddr, readdata; 667 int cpu; 668 { 669 u_int32_t segptr; 670 int cnt; 671 u_int32_t tmpval, tmpval2; 672 caddr_t ptr; 673 674 /* 675 * At the moment, we don't handle non-aligned cases, we just bail. 676 * If this proves to be a problem, it will be fixed. 677 */ 678 if (tigon_addr & 0x3) { 679 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 680 "word-aligned\n", sc->ti_unit, tigon_addr); 681 return (EINVAL); 682 } 683 684 if (len & 0x3) { 685 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 686 "word-aligned\n", sc->ti_unit, len); 687 return (EINVAL); 688 } 689 690 segptr = tigon_addr; 691 cnt = len; 692 ptr = buf; 693 694 TI_LOCK(sc); 695 696 while (cnt) { 697 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 698 699 if (readdata) { 700 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 701 702 tmpval = ntohl(tmpval2); 703 704 /* 705 * Note: I've used this debugging interface 706 * extensively with Alteon's 12.3.15 firmware, 707 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 708 * 709 * When you compile the firmware without 710 * optimization, which is necessary sometimes in 711 * order to properly step through it, you sometimes 712 * read out a bogus value of 0xc0017c instead of 713 * whatever was supposed to be in that scratchpad 714 * location. That value is on the stack somewhere, 715 * but I've never been able to figure out what was 716 * causing the problem. 717 * 718 * The address seems to pop up in random places, 719 * often not in the same place on two subsequent 720 * reads. 721 * 722 * In any case, the underlying data doesn't seem 723 * to be affected, just the value read out. 724 * 725 * KDM, 3/7/2000 726 */ 727 728 if (tmpval2 == 0xc0017c) 729 printf("ti%d: found 0xc0017c at %#x " 730 "(tmpval2)\n", sc->ti_unit, segptr); 731 732 if (tmpval == 0xc0017c) 733 printf("ti%d: found 0xc0017c at %#x " 734 "(tmpval)\n", sc->ti_unit, segptr); 735 736 if (useraddr) 737 copyout(&tmpval, ptr, 4); 738 else 739 bcopy(&tmpval, ptr, 4); 740 } else { 741 if (useraddr) 742 copyin(ptr, &tmpval2, 4); 743 else 744 bcopy(ptr, &tmpval2, 4); 745 746 tmpval = htonl(tmpval2); 747 748 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 749 } 750 751 cnt -= 4; 752 segptr += 4; 753 ptr += 4; 754 } 755 756 TI_UNLOCK(sc); 757 758 return (0); 759 } 760 761 static int 762 ti_bcopy_swap(src, dst, len, swap_type) 763 const void *src; 764 void *dst; 765 size_t len; 766 ti_swap_type swap_type; 767 { 768 const u_int8_t *tmpsrc; 769 u_int8_t *tmpdst; 770 size_t tmplen; 771 772 if (len & 0x3) { 773 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 774 len); 775 return (-1); 776 } 777 778 tmpsrc = src; 779 tmpdst = dst; 780 tmplen = len; 781 782 while (tmplen) { 783 if (swap_type == TI_SWAP_NTOH) 784 *(u_int32_t *)tmpdst = 785 ntohl(*(const u_int32_t *)tmpsrc); 786 else 787 *(u_int32_t *)tmpdst = 788 htonl(*(const u_int32_t *)tmpsrc); 789 790 tmpsrc += 4; 791 tmpdst += 4; 792 tmplen -= 4; 793 } 794 795 return (0); 796 } 797 798 /* 799 * Load firmware image into the NIC. Check that the firmware revision 800 * is acceptable and see if we want the firmware for the Tigon 1 or 801 * Tigon 2. 802 */ 803 static void 804 ti_loadfw(sc) 805 struct ti_softc *sc; 806 { 807 switch (sc->ti_hwrev) { 808 case TI_HWREV_TIGON: 809 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 810 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 811 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 812 printf("ti%d: firmware revision mismatch; want " 813 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 814 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 815 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 816 tigonFwReleaseMinor, tigonFwReleaseFix); 817 return; 818 } 819 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 820 (caddr_t)tigonFwText); 821 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 822 (caddr_t)tigonFwData); 823 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 824 (caddr_t)tigonFwRodata); 825 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 826 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 827 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 828 break; 829 case TI_HWREV_TIGON_II: 830 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 831 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 832 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 833 printf("ti%d: firmware revision mismatch; want " 834 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 835 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 836 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 837 tigon2FwReleaseMinor, tigon2FwReleaseFix); 838 return; 839 } 840 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 841 (caddr_t)tigon2FwText); 842 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 843 (caddr_t)tigon2FwData); 844 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 845 (caddr_t)tigon2FwRodata); 846 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 847 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 848 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 849 break; 850 default: 851 printf("ti%d: can't load firmware: unknown hardware rev\n", 852 sc->ti_unit); 853 break; 854 } 855 } 856 857 /* 858 * Send the NIC a command via the command ring. 859 */ 860 static void 861 ti_cmd(sc, cmd) 862 struct ti_softc *sc; 863 struct ti_cmd_desc *cmd; 864 { 865 u_int32_t index; 866 867 if (sc->ti_rdata->ti_cmd_ring == NULL) 868 return; 869 870 index = sc->ti_cmd_saved_prodidx; 871 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 872 TI_INC(index, TI_CMD_RING_CNT); 873 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 874 sc->ti_cmd_saved_prodidx = index; 875 } 876 877 /* 878 * Send the NIC an extended command. The 'len' parameter specifies the 879 * number of command slots to include after the initial command. 880 */ 881 static void 882 ti_cmd_ext(sc, cmd, arg, len) 883 struct ti_softc *sc; 884 struct ti_cmd_desc *cmd; 885 caddr_t arg; 886 int len; 887 { 888 u_int32_t index; 889 register int i; 890 891 if (sc->ti_rdata->ti_cmd_ring == NULL) 892 return; 893 894 index = sc->ti_cmd_saved_prodidx; 895 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 896 TI_INC(index, TI_CMD_RING_CNT); 897 for (i = 0; i < len; i++) { 898 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 899 *(u_int32_t *)(&arg[i * 4])); 900 TI_INC(index, TI_CMD_RING_CNT); 901 } 902 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 903 sc->ti_cmd_saved_prodidx = index; 904 } 905 906 /* 907 * Handle events that have triggered interrupts. 908 */ 909 static void 910 ti_handle_events(sc) 911 struct ti_softc *sc; 912 { 913 struct ti_event_desc *e; 914 915 if (sc->ti_rdata->ti_event_ring == NULL) 916 return; 917 918 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 919 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 920 switch (e->ti_event) { 921 case TI_EV_LINKSTAT_CHANGED: 922 sc->ti_linkstat = e->ti_code; 923 if (e->ti_code == TI_EV_CODE_LINK_UP) 924 printf("ti%d: 10/100 link up\n", sc->ti_unit); 925 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 926 printf("ti%d: gigabit link up\n", sc->ti_unit); 927 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 928 printf("ti%d: link down\n", sc->ti_unit); 929 break; 930 case TI_EV_ERROR: 931 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 932 printf("ti%d: invalid command\n", sc->ti_unit); 933 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 934 printf("ti%d: unknown command\n", sc->ti_unit); 935 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 936 printf("ti%d: bad config data\n", sc->ti_unit); 937 break; 938 case TI_EV_FIRMWARE_UP: 939 ti_init2(sc); 940 break; 941 case TI_EV_STATS_UPDATED: 942 ti_stats_update(sc); 943 break; 944 case TI_EV_RESET_JUMBO_RING: 945 case TI_EV_MCAST_UPDATED: 946 /* Who cares. */ 947 break; 948 default: 949 printf("ti%d: unknown event: %d\n", 950 sc->ti_unit, e->ti_event); 951 break; 952 } 953 /* Advance the consumer index. */ 954 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 955 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 956 } 957 } 958 959 #ifdef TI_PRIVATE_JUMBOS 960 961 /* 962 * Memory management for the jumbo receive ring is a pain in the 963 * butt. We need to allocate at least 9018 bytes of space per frame, 964 * _and_ it has to be contiguous (unless you use the extended 965 * jumbo descriptor format). Using malloc() all the time won't 966 * work: malloc() allocates memory in powers of two, which means we 967 * would end up wasting a considerable amount of space by allocating 968 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 969 * to do our own memory management. 970 * 971 * The driver needs to allocate a contiguous chunk of memory at boot 972 * time. We then chop this up ourselves into 9K pieces and use them 973 * as external mbuf storage. 974 * 975 * One issue here is how much memory to allocate. The jumbo ring has 976 * 256 slots in it, but at 9K per slot than can consume over 2MB of 977 * RAM. This is a bit much, especially considering we also need 978 * RAM for the standard ring and mini ring (on the Tigon 2). To 979 * save space, we only actually allocate enough memory for 64 slots 980 * by default, which works out to between 500 and 600K. This can 981 * be tuned by changing a #define in if_tireg.h. 982 */ 983 984 static int 985 ti_alloc_jumbo_mem(sc) 986 struct ti_softc *sc; 987 { 988 caddr_t ptr; 989 register int i; 990 struct ti_jpool_entry *entry; 991 992 /* Grab a big chunk o' storage. */ 993 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 994 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 995 996 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 997 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 998 return (ENOBUFS); 999 } 1000 1001 SLIST_INIT(&sc->ti_jfree_listhead); 1002 SLIST_INIT(&sc->ti_jinuse_listhead); 1003 1004 /* 1005 * Now divide it up into 9K pieces and save the addresses 1006 * in an array. 1007 */ 1008 ptr = sc->ti_cdata.ti_jumbo_buf; 1009 for (i = 0; i < TI_JSLOTS; i++) { 1010 sc->ti_cdata.ti_jslots[i] = ptr; 1011 ptr += TI_JLEN; 1012 entry = malloc(sizeof(struct ti_jpool_entry), 1013 M_DEVBUF, M_NOWAIT); 1014 if (entry == NULL) { 1015 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1016 M_DEVBUF); 1017 sc->ti_cdata.ti_jumbo_buf = NULL; 1018 printf("ti%d: no memory for jumbo " 1019 "buffer queue!\n", sc->ti_unit); 1020 return (ENOBUFS); 1021 } 1022 entry->slot = i; 1023 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1024 } 1025 1026 return (0); 1027 } 1028 1029 /* 1030 * Allocate a jumbo buffer. 1031 */ 1032 static void *ti_jalloc(sc) 1033 struct ti_softc *sc; 1034 { 1035 struct ti_jpool_entry *entry; 1036 1037 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1038 1039 if (entry == NULL) { 1040 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1041 return (NULL); 1042 } 1043 1044 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1045 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1046 return (sc->ti_cdata.ti_jslots[entry->slot]); 1047 } 1048 1049 /* 1050 * Release a jumbo buffer. 1051 */ 1052 static void 1053 ti_jfree(buf, args) 1054 void *buf; 1055 void *args; 1056 { 1057 struct ti_softc *sc; 1058 int i; 1059 struct ti_jpool_entry *entry; 1060 1061 /* Extract the softc struct pointer. */ 1062 sc = (struct ti_softc *)args; 1063 1064 if (sc == NULL) 1065 panic("ti_jfree: didn't get softc pointer!"); 1066 1067 /* calculate the slot this buffer belongs to */ 1068 i = ((vm_offset_t)buf 1069 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1070 1071 if ((i < 0) || (i >= TI_JSLOTS)) 1072 panic("ti_jfree: asked to free buffer that we don't manage!"); 1073 1074 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1075 if (entry == NULL) 1076 panic("ti_jfree: buffer not in use!"); 1077 entry->slot = i; 1078 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1079 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1080 } 1081 1082 #endif /* TI_PRIVATE_JUMBOS */ 1083 1084 /* 1085 * Intialize a standard receive ring descriptor. 1086 */ 1087 static int 1088 ti_newbuf_std(sc, i, m) 1089 struct ti_softc *sc; 1090 int i; 1091 struct mbuf *m; 1092 { 1093 struct mbuf *m_new = NULL; 1094 struct ti_rx_desc *r; 1095 1096 if (m == NULL) { 1097 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1098 if (m_new == NULL) 1099 return (ENOBUFS); 1100 1101 MCLGET(m_new, M_DONTWAIT); 1102 if (!(m_new->m_flags & M_EXT)) { 1103 m_freem(m_new); 1104 return (ENOBUFS); 1105 } 1106 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1107 } else { 1108 m_new = m; 1109 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1110 m_new->m_data = m_new->m_ext.ext_buf; 1111 } 1112 1113 m_adj(m_new, ETHER_ALIGN); 1114 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1115 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1116 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1117 r->ti_type = TI_BDTYPE_RECV_BD; 1118 r->ti_flags = 0; 1119 if (sc->arpcom.ac_if.if_hwassist) 1120 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1121 r->ti_len = m_new->m_len; 1122 r->ti_idx = i; 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * Intialize a mini receive ring descriptor. This only applies to 1129 * the Tigon 2. 1130 */ 1131 static int 1132 ti_newbuf_mini(sc, i, m) 1133 struct ti_softc *sc; 1134 int i; 1135 struct mbuf *m; 1136 { 1137 struct mbuf *m_new = NULL; 1138 struct ti_rx_desc *r; 1139 1140 if (m == NULL) { 1141 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1142 if (m_new == NULL) { 1143 return (ENOBUFS); 1144 } 1145 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1146 } else { 1147 m_new = m; 1148 m_new->m_data = m_new->m_pktdat; 1149 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1150 } 1151 1152 m_adj(m_new, ETHER_ALIGN); 1153 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1154 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1155 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1156 r->ti_type = TI_BDTYPE_RECV_BD; 1157 r->ti_flags = TI_BDFLAG_MINI_RING; 1158 if (sc->arpcom.ac_if.if_hwassist) 1159 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1160 r->ti_len = m_new->m_len; 1161 r->ti_idx = i; 1162 1163 return (0); 1164 } 1165 1166 #ifdef TI_PRIVATE_JUMBOS 1167 1168 /* 1169 * Initialize a jumbo receive ring descriptor. This allocates 1170 * a jumbo buffer from the pool managed internally by the driver. 1171 */ 1172 static int 1173 ti_newbuf_jumbo(sc, i, m) 1174 struct ti_softc *sc; 1175 int i; 1176 struct mbuf *m; 1177 { 1178 struct mbuf *m_new = NULL; 1179 struct ti_rx_desc *r; 1180 1181 if (m == NULL) { 1182 caddr_t *buf = NULL; 1183 1184 /* Allocate the mbuf. */ 1185 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1186 if (m_new == NULL) { 1187 return (ENOBUFS); 1188 } 1189 1190 /* Allocate the jumbo buffer */ 1191 buf = ti_jalloc(sc); 1192 if (buf == NULL) { 1193 m_freem(m_new); 1194 printf("ti%d: jumbo allocation failed " 1195 "-- packet dropped!\n", sc->ti_unit); 1196 return (ENOBUFS); 1197 } 1198 1199 /* Attach the buffer to the mbuf. */ 1200 m_new->m_data = (void *) buf; 1201 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1202 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1203 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1204 } else { 1205 m_new = m; 1206 m_new->m_data = m_new->m_ext.ext_buf; 1207 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1208 } 1209 1210 m_adj(m_new, ETHER_ALIGN); 1211 /* Set up the descriptor. */ 1212 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1213 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1214 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1215 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1216 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1217 if (sc->arpcom.ac_if.if_hwassist) 1218 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1219 r->ti_len = m_new->m_len; 1220 r->ti_idx = i; 1221 1222 return (0); 1223 } 1224 1225 #else 1226 #include <vm/vm_page.h> 1227 1228 #if (PAGE_SIZE == 4096) 1229 #define NPAYLOAD 2 1230 #else 1231 #define NPAYLOAD 1 1232 #endif 1233 1234 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1235 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1236 #define NFS_HDR_LEN (UDP_HDR_LEN) 1237 static int HDR_LEN = TCP_HDR_LEN; 1238 1239 1240 /* 1241 * Initialize a jumbo receive ring descriptor. This allocates 1242 * a jumbo buffer from the pool managed internally by the driver. 1243 */ 1244 static int 1245 ti_newbuf_jumbo(sc, idx, m_old) 1246 struct ti_softc *sc; 1247 int idx; 1248 struct mbuf *m_old; 1249 { 1250 struct mbuf *cur, *m_new = NULL; 1251 struct mbuf *m[3] = {NULL, NULL, NULL}; 1252 struct ti_rx_desc_ext *r; 1253 vm_page_t frame; 1254 static int color; 1255 /* 1 extra buf to make nobufs easy*/ 1256 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1257 int i; 1258 1259 if (m_old != NULL) { 1260 m_new = m_old; 1261 cur = m_old->m_next; 1262 for (i = 0; i <= NPAYLOAD; i++){ 1263 m[i] = cur; 1264 cur = cur->m_next; 1265 } 1266 } else { 1267 /* Allocate the mbufs. */ 1268 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1269 if (m_new == NULL) { 1270 printf("ti%d: mbuf allocation failed " 1271 "-- packet dropped!\n", sc->ti_unit); 1272 goto nobufs; 1273 } 1274 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1275 if (m[NPAYLOAD] == NULL) { 1276 printf("ti%d: cluster mbuf allocation failed " 1277 "-- packet dropped!\n", sc->ti_unit); 1278 goto nobufs; 1279 } 1280 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1281 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1282 printf("ti%d: mbuf allocation failed " 1283 "-- packet dropped!\n", sc->ti_unit); 1284 goto nobufs; 1285 } 1286 m[NPAYLOAD]->m_len = MCLBYTES; 1287 1288 for (i = 0; i < NPAYLOAD; i++){ 1289 MGET(m[i], M_DONTWAIT, MT_DATA); 1290 if (m[i] == NULL) { 1291 printf("ti%d: mbuf allocation failed " 1292 "-- packet dropped!\n", sc->ti_unit); 1293 goto nobufs; 1294 } 1295 frame = vm_page_alloc(NULL, color++, 1296 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1297 VM_ALLOC_WIRED); 1298 if (frame == NULL) { 1299 printf("ti%d: buffer allocation failed " 1300 "-- packet dropped!\n", sc->ti_unit); 1301 printf(" index %d page %d\n", idx, i); 1302 goto nobufs; 1303 } 1304 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1305 if (sf[i] == NULL) { 1306 vm_page_lock_queues(); 1307 vm_page_unwire(frame, 0); 1308 vm_page_free(frame); 1309 vm_page_unlock_queues(); 1310 printf("ti%d: buffer allocation failed " 1311 "-- packet dropped!\n", sc->ti_unit); 1312 printf(" index %d page %d\n", idx, i); 1313 goto nobufs; 1314 } 1315 } 1316 for (i = 0; i < NPAYLOAD; i++){ 1317 /* Attach the buffer to the mbuf. */ 1318 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1319 m[i]->m_len = PAGE_SIZE; 1320 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1321 sf_buf_mext, sf[i], 0, EXT_DISPOSABLE); 1322 m[i]->m_next = m[i+1]; 1323 } 1324 /* link the buffers to the header */ 1325 m_new->m_next = m[0]; 1326 m_new->m_data += ETHER_ALIGN; 1327 if (sc->ti_hdrsplit) 1328 m_new->m_len = MHLEN - ETHER_ALIGN; 1329 else 1330 m_new->m_len = HDR_LEN; 1331 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1332 } 1333 1334 /* Set up the descriptor. */ 1335 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1336 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1337 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1338 r->ti_len0 = m_new->m_len; 1339 1340 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1341 r->ti_len1 = PAGE_SIZE; 1342 1343 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1344 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1345 1346 if (PAGE_SIZE == 4096) { 1347 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1348 r->ti_len3 = MCLBYTES; 1349 } else { 1350 r->ti_len3 = 0; 1351 } 1352 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1353 1354 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1355 1356 if (sc->arpcom.ac_if.if_hwassist) 1357 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1358 1359 r->ti_idx = idx; 1360 1361 return (0); 1362 1363 nobufs: 1364 1365 /* 1366 * Warning! : 1367 * This can only be called before the mbufs are strung together. 1368 * If the mbufs are strung together, m_freem() will free the chain, 1369 * so that the later mbufs will be freed multiple times. 1370 */ 1371 if (m_new) 1372 m_freem(m_new); 1373 1374 for (i = 0; i < 3; i++) { 1375 if (m[i]) 1376 m_freem(m[i]); 1377 if (sf[i]) 1378 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1379 } 1380 return (ENOBUFS); 1381 } 1382 #endif 1383 1384 1385 1386 /* 1387 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1388 * that's 1MB or memory, which is a lot. For now, we fill only the first 1389 * 256 ring entries and hope that our CPU is fast enough to keep up with 1390 * the NIC. 1391 */ 1392 static int 1393 ti_init_rx_ring_std(sc) 1394 struct ti_softc *sc; 1395 { 1396 register int i; 1397 struct ti_cmd_desc cmd; 1398 1399 for (i = 0; i < TI_SSLOTS; i++) { 1400 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1401 return (ENOBUFS); 1402 }; 1403 1404 TI_UPDATE_STDPROD(sc, i - 1); 1405 sc->ti_std = i - 1; 1406 1407 return (0); 1408 } 1409 1410 static void 1411 ti_free_rx_ring_std(sc) 1412 struct ti_softc *sc; 1413 { 1414 register int i; 1415 1416 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1417 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1418 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1419 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1420 } 1421 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1422 sizeof(struct ti_rx_desc)); 1423 } 1424 } 1425 1426 static int 1427 ti_init_rx_ring_jumbo(sc) 1428 struct ti_softc *sc; 1429 { 1430 register int i; 1431 struct ti_cmd_desc cmd; 1432 1433 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1434 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1435 return (ENOBUFS); 1436 }; 1437 1438 TI_UPDATE_JUMBOPROD(sc, i - 1); 1439 sc->ti_jumbo = i - 1; 1440 1441 return (0); 1442 } 1443 1444 static void 1445 ti_free_rx_ring_jumbo(sc) 1446 struct ti_softc *sc; 1447 { 1448 register int i; 1449 1450 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1451 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1452 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1453 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1454 } 1455 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1456 sizeof(struct ti_rx_desc)); 1457 } 1458 } 1459 1460 static int 1461 ti_init_rx_ring_mini(sc) 1462 struct ti_softc *sc; 1463 { 1464 register int i; 1465 1466 for (i = 0; i < TI_MSLOTS; i++) { 1467 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1468 return (ENOBUFS); 1469 }; 1470 1471 TI_UPDATE_MINIPROD(sc, i - 1); 1472 sc->ti_mini = i - 1; 1473 1474 return (0); 1475 } 1476 1477 static void 1478 ti_free_rx_ring_mini(sc) 1479 struct ti_softc *sc; 1480 { 1481 register int i; 1482 1483 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1484 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1485 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1486 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1487 } 1488 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1489 sizeof(struct ti_rx_desc)); 1490 } 1491 } 1492 1493 static void 1494 ti_free_tx_ring(sc) 1495 struct ti_softc *sc; 1496 { 1497 register int i; 1498 1499 if (sc->ti_rdata->ti_tx_ring == NULL) 1500 return; 1501 1502 for (i = 0; i < TI_TX_RING_CNT; i++) { 1503 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1504 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1505 sc->ti_cdata.ti_tx_chain[i] = NULL; 1506 } 1507 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1508 sizeof(struct ti_tx_desc)); 1509 } 1510 } 1511 1512 static int 1513 ti_init_tx_ring(sc) 1514 struct ti_softc *sc; 1515 { 1516 sc->ti_txcnt = 0; 1517 sc->ti_tx_saved_considx = 0; 1518 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1519 return (0); 1520 } 1521 1522 /* 1523 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1524 * but we have to support the old way too so that Tigon 1 cards will 1525 * work. 1526 */ 1527 static void 1528 ti_add_mcast(sc, addr) 1529 struct ti_softc *sc; 1530 struct ether_addr *addr; 1531 { 1532 struct ti_cmd_desc cmd; 1533 u_int16_t *m; 1534 u_int32_t ext[2] = {0, 0}; 1535 1536 m = (u_int16_t *)&addr->octet[0]; 1537 1538 switch (sc->ti_hwrev) { 1539 case TI_HWREV_TIGON: 1540 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1541 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1542 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1543 break; 1544 case TI_HWREV_TIGON_II: 1545 ext[0] = htons(m[0]); 1546 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1547 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1548 break; 1549 default: 1550 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1551 break; 1552 } 1553 } 1554 1555 static void 1556 ti_del_mcast(sc, addr) 1557 struct ti_softc *sc; 1558 struct ether_addr *addr; 1559 { 1560 struct ti_cmd_desc cmd; 1561 u_int16_t *m; 1562 u_int32_t ext[2] = {0, 0}; 1563 1564 m = (u_int16_t *)&addr->octet[0]; 1565 1566 switch (sc->ti_hwrev) { 1567 case TI_HWREV_TIGON: 1568 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1569 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1570 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1571 break; 1572 case TI_HWREV_TIGON_II: 1573 ext[0] = htons(m[0]); 1574 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1575 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1576 break; 1577 default: 1578 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1579 break; 1580 } 1581 } 1582 1583 /* 1584 * Configure the Tigon's multicast address filter. 1585 * 1586 * The actual multicast table management is a bit of a pain, thanks to 1587 * slight brain damage on the part of both Alteon and us. With our 1588 * multicast code, we are only alerted when the multicast address table 1589 * changes and at that point we only have the current list of addresses: 1590 * we only know the current state, not the previous state, so we don't 1591 * actually know what addresses were removed or added. The firmware has 1592 * state, but we can't get our grubby mits on it, and there is no 'delete 1593 * all multicast addresses' command. Hence, we have to maintain our own 1594 * state so we know what addresses have been programmed into the NIC at 1595 * any given time. 1596 */ 1597 static void 1598 ti_setmulti(sc) 1599 struct ti_softc *sc; 1600 { 1601 struct ifnet *ifp; 1602 struct ifmultiaddr *ifma; 1603 struct ti_cmd_desc cmd; 1604 struct ti_mc_entry *mc; 1605 u_int32_t intrs; 1606 1607 ifp = &sc->arpcom.ac_if; 1608 1609 if (ifp->if_flags & IFF_ALLMULTI) { 1610 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1611 return; 1612 } else { 1613 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1614 } 1615 1616 /* Disable interrupts. */ 1617 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1618 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1619 1620 /* First, zot all the existing filters. */ 1621 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1622 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1623 ti_del_mcast(sc, &mc->mc_addr); 1624 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1625 free(mc, M_DEVBUF); 1626 } 1627 1628 /* Now program new ones. */ 1629 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1630 if (ifma->ifma_addr->sa_family != AF_LINK) 1631 continue; 1632 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1633 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1634 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1635 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1636 ti_add_mcast(sc, &mc->mc_addr); 1637 } 1638 1639 /* Re-enable interrupts. */ 1640 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1641 } 1642 1643 /* 1644 * Check to see if the BIOS has configured us for a 64 bit slot when 1645 * we aren't actually in one. If we detect this condition, we can work 1646 * around it on the Tigon 2 by setting a bit in the PCI state register, 1647 * but for the Tigon 1 we must give up and abort the interface attach. 1648 */ 1649 static int ti_64bitslot_war(sc) 1650 struct ti_softc *sc; 1651 { 1652 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1653 CSR_WRITE_4(sc, 0x600, 0); 1654 CSR_WRITE_4(sc, 0x604, 0); 1655 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1656 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1657 if (sc->ti_hwrev == TI_HWREV_TIGON) 1658 return (EINVAL); 1659 else { 1660 TI_SETBIT(sc, TI_PCI_STATE, 1661 TI_PCISTATE_32BIT_BUS); 1662 return (0); 1663 } 1664 } 1665 } 1666 1667 return (0); 1668 } 1669 1670 /* 1671 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1672 * self-test results. 1673 */ 1674 static int 1675 ti_chipinit(sc) 1676 struct ti_softc *sc; 1677 { 1678 u_int32_t cacheline; 1679 u_int32_t pci_writemax = 0; 1680 u_int32_t hdrsplit; 1681 1682 /* Initialize link to down state. */ 1683 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1684 1685 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1686 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1687 else 1688 sc->arpcom.ac_if.if_hwassist = 0; 1689 1690 /* Set endianness before we access any non-PCI registers. */ 1691 #if BYTE_ORDER == BIG_ENDIAN 1692 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1693 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1694 #else 1695 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1696 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1697 #endif 1698 1699 /* Check the ROM failed bit to see if self-tests passed. */ 1700 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1701 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1702 return (ENODEV); 1703 } 1704 1705 /* Halt the CPU. */ 1706 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1707 1708 /* Figure out the hardware revision. */ 1709 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1710 case TI_REV_TIGON_I: 1711 sc->ti_hwrev = TI_HWREV_TIGON; 1712 break; 1713 case TI_REV_TIGON_II: 1714 sc->ti_hwrev = TI_HWREV_TIGON_II; 1715 break; 1716 default: 1717 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1718 return (ENODEV); 1719 } 1720 1721 /* Do special setup for Tigon 2. */ 1722 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1723 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1724 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1725 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1726 } 1727 1728 /* 1729 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1730 * can't do header splitting. 1731 */ 1732 #ifdef TI_JUMBO_HDRSPLIT 1733 if (sc->ti_hwrev != TI_HWREV_TIGON) 1734 sc->ti_hdrsplit = 1; 1735 else 1736 printf("ti%d: can't do header splitting on a Tigon I board\n", 1737 sc->ti_unit); 1738 #endif /* TI_JUMBO_HDRSPLIT */ 1739 1740 /* Set up the PCI state register. */ 1741 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1742 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1743 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1744 } 1745 1746 /* Clear the read/write max DMA parameters. */ 1747 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1748 TI_PCISTATE_READ_MAXDMA)); 1749 1750 /* Get cache line size. */ 1751 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1752 1753 /* 1754 * If the system has set enabled the PCI memory write 1755 * and invalidate command in the command register, set 1756 * the write max parameter accordingly. This is necessary 1757 * to use MWI with the Tigon 2. 1758 */ 1759 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1760 switch (cacheline) { 1761 case 1: 1762 case 4: 1763 case 8: 1764 case 16: 1765 case 32: 1766 case 64: 1767 break; 1768 default: 1769 /* Disable PCI memory write and invalidate. */ 1770 if (bootverbose) 1771 printf("ti%d: cache line size %d not " 1772 "supported; disabling PCI MWI\n", 1773 sc->ti_unit, cacheline); 1774 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1775 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1776 break; 1777 } 1778 } 1779 1780 #ifdef __brokenalpha__ 1781 /* 1782 * From the Alteon sample driver: 1783 * Must insure that we do not cross an 8K (bytes) boundary 1784 * for DMA reads. Our highest limit is 1K bytes. This is a 1785 * restriction on some ALPHA platforms with early revision 1786 * 21174 PCI chipsets, such as the AlphaPC 164lx 1787 */ 1788 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1789 #else 1790 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1791 #endif 1792 1793 /* This sets the min dma param all the way up (0xff). */ 1794 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1795 1796 if (sc->ti_hdrsplit) 1797 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1798 else 1799 hdrsplit = 0; 1800 1801 /* Configure DMA variables. */ 1802 #if BYTE_ORDER == BIG_ENDIAN 1803 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1804 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1805 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1806 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1807 #else /* BYTE_ORDER */ 1808 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1809 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1810 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1811 #endif /* BYTE_ORDER */ 1812 1813 /* 1814 * Only allow 1 DMA channel to be active at a time. 1815 * I don't think this is a good idea, but without it 1816 * the firmware racks up lots of nicDmaReadRingFull 1817 * errors. This is not compatible with hardware checksums. 1818 */ 1819 if (sc->arpcom.ac_if.if_hwassist == 0) 1820 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1821 1822 /* Recommended settings from Tigon manual. */ 1823 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1824 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1825 1826 if (ti_64bitslot_war(sc)) { 1827 printf("ti%d: bios thinks we're in a 64 bit slot, " 1828 "but we aren't", sc->ti_unit); 1829 return (EINVAL); 1830 } 1831 1832 return (0); 1833 } 1834 1835 /* 1836 * Initialize the general information block and firmware, and 1837 * start the CPU(s) running. 1838 */ 1839 static int 1840 ti_gibinit(sc) 1841 struct ti_softc *sc; 1842 { 1843 struct ti_rcb *rcb; 1844 int i; 1845 struct ifnet *ifp; 1846 1847 ifp = &sc->arpcom.ac_if; 1848 1849 /* Disable interrupts for now. */ 1850 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1851 1852 /* Tell the chip where to find the general information block. */ 1853 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1854 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1855 1856 /* Load the firmware into SRAM. */ 1857 ti_loadfw(sc); 1858 1859 /* Set up the contents of the general info and ring control blocks. */ 1860 1861 /* Set up the event ring and producer pointer. */ 1862 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1863 1864 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1865 rcb->ti_flags = 0; 1866 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1867 vtophys(&sc->ti_ev_prodidx); 1868 sc->ti_ev_prodidx.ti_idx = 0; 1869 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1870 sc->ti_ev_saved_considx = 0; 1871 1872 /* Set up the command ring and producer mailbox. */ 1873 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1874 1875 sc->ti_rdata->ti_cmd_ring = 1876 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1877 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1878 rcb->ti_flags = 0; 1879 rcb->ti_max_len = 0; 1880 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1881 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1882 } 1883 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1884 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1885 sc->ti_cmd_saved_prodidx = 0; 1886 1887 /* 1888 * Assign the address of the stats refresh buffer. 1889 * We re-use the current stats buffer for this to 1890 * conserve memory. 1891 */ 1892 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1893 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1894 1895 /* Set up the standard receive ring. */ 1896 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1897 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1898 rcb->ti_max_len = TI_FRAMELEN; 1899 rcb->ti_flags = 0; 1900 if (sc->arpcom.ac_if.if_hwassist) 1901 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1902 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1903 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1904 1905 /* Set up the jumbo receive ring. */ 1906 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1907 TI_HOSTADDR(rcb->ti_hostaddr) = 1908 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1909 1910 #ifdef TI_PRIVATE_JUMBOS 1911 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1912 rcb->ti_flags = 0; 1913 #else 1914 rcb->ti_max_len = PAGE_SIZE; 1915 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1916 #endif 1917 if (sc->arpcom.ac_if.if_hwassist) 1918 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1919 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1920 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1921 1922 /* 1923 * Set up the mini ring. Only activated on the 1924 * Tigon 2 but the slot in the config block is 1925 * still there on the Tigon 1. 1926 */ 1927 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1928 TI_HOSTADDR(rcb->ti_hostaddr) = 1929 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1930 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1931 if (sc->ti_hwrev == TI_HWREV_TIGON) 1932 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1933 else 1934 rcb->ti_flags = 0; 1935 if (sc->arpcom.ac_if.if_hwassist) 1936 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1937 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1938 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1939 1940 /* 1941 * Set up the receive return ring. 1942 */ 1943 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1944 TI_HOSTADDR(rcb->ti_hostaddr) = 1945 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1946 rcb->ti_flags = 0; 1947 rcb->ti_max_len = TI_RETURN_RING_CNT; 1948 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1949 vtophys(&sc->ti_return_prodidx); 1950 1951 /* 1952 * Set up the tx ring. Note: for the Tigon 2, we have the option 1953 * of putting the transmit ring in the host's address space and 1954 * letting the chip DMA it instead of leaving the ring in the NIC's 1955 * memory and accessing it through the shared memory region. We 1956 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1957 * so we have to revert to the shared memory scheme if we detect 1958 * a Tigon 1 chip. 1959 */ 1960 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1961 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1962 sc->ti_rdata->ti_tx_ring_nic = 1963 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1964 } 1965 bzero((char *)sc->ti_rdata->ti_tx_ring, 1966 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1967 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1968 if (sc->ti_hwrev == TI_HWREV_TIGON) 1969 rcb->ti_flags = 0; 1970 else 1971 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1972 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1973 if (sc->arpcom.ac_if.if_hwassist) 1974 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1975 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1976 rcb->ti_max_len = TI_TX_RING_CNT; 1977 if (sc->ti_hwrev == TI_HWREV_TIGON) 1978 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1979 else 1980 TI_HOSTADDR(rcb->ti_hostaddr) = 1981 vtophys(&sc->ti_rdata->ti_tx_ring); 1982 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1983 vtophys(&sc->ti_tx_considx); 1984 1985 /* Set up tuneables */ 1986 #if 0 1987 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1988 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1989 (sc->ti_rx_coal_ticks / 10)); 1990 else 1991 #endif 1992 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1993 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1994 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1995 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1996 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1997 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1998 1999 /* Turn interrupts on. */ 2000 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2001 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2002 2003 /* Start CPU. */ 2004 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2005 2006 return (0); 2007 } 2008 2009 /* 2010 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2011 * against our list and return its name if we find a match. 2012 */ 2013 static int 2014 ti_probe(dev) 2015 device_t dev; 2016 { 2017 struct ti_type *t; 2018 2019 t = ti_devs; 2020 2021 while (t->ti_name != NULL) { 2022 if ((pci_get_vendor(dev) == t->ti_vid) && 2023 (pci_get_device(dev) == t->ti_did)) { 2024 device_set_desc(dev, t->ti_name); 2025 return (0); 2026 } 2027 t++; 2028 } 2029 2030 return (ENXIO); 2031 } 2032 2033 static int 2034 ti_attach(dev) 2035 device_t dev; 2036 { 2037 struct ifnet *ifp; 2038 struct ti_softc *sc; 2039 int unit, error = 0, rid; 2040 2041 sc = device_get_softc(dev); 2042 unit = device_get_unit(dev); 2043 2044 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2045 MTX_DEF | MTX_RECURSE); 2046 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2047 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | 2048 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2049 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2050 2051 /* 2052 * Map control/status registers. 2053 */ 2054 pci_enable_busmaster(dev); 2055 2056 rid = TI_PCI_LOMEM; 2057 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2058 RF_ACTIVE|PCI_RF_DENSE); 2059 2060 if (sc->ti_res == NULL) { 2061 printf ("ti%d: couldn't map memory\n", unit); 2062 error = ENXIO; 2063 goto fail; 2064 } 2065 2066 sc->ti_btag = rman_get_bustag(sc->ti_res); 2067 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2068 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2069 2070 /* Allocate interrupt */ 2071 rid = 0; 2072 2073 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2074 RF_SHAREABLE | RF_ACTIVE); 2075 2076 if (sc->ti_irq == NULL) { 2077 printf("ti%d: couldn't map interrupt\n", unit); 2078 error = ENXIO; 2079 goto fail; 2080 } 2081 2082 sc->ti_unit = unit; 2083 2084 if (ti_chipinit(sc)) { 2085 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2086 error = ENXIO; 2087 goto fail; 2088 } 2089 2090 /* Zero out the NIC's on-board SRAM. */ 2091 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2092 2093 /* Init again -- zeroing memory may have clobbered some registers. */ 2094 if (ti_chipinit(sc)) { 2095 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2096 error = ENXIO; 2097 goto fail; 2098 } 2099 2100 /* 2101 * Get station address from the EEPROM. Note: the manual states 2102 * that the MAC address is at offset 0x8c, however the data is 2103 * stored as two longwords (since that's how it's loaded into 2104 * the NIC). This means the MAC address is actually preceded 2105 * by two zero bytes. We need to skip over those. 2106 */ 2107 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2108 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2109 printf("ti%d: failed to read station address\n", unit); 2110 error = ENXIO; 2111 goto fail; 2112 } 2113 2114 /* Allocate the general information block and ring buffers. */ 2115 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2116 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2117 2118 if (sc->ti_rdata == NULL) { 2119 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2120 error = ENXIO; 2121 goto fail; 2122 } 2123 2124 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2125 2126 /* Try to allocate memory for jumbo buffers. */ 2127 #ifdef TI_PRIVATE_JUMBOS 2128 if (ti_alloc_jumbo_mem(sc)) { 2129 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2130 error = ENXIO; 2131 goto fail; 2132 } 2133 #endif 2134 2135 /* 2136 * We really need a better way to tell a 1000baseTX card 2137 * from a 1000baseSX one, since in theory there could be 2138 * OEMed 1000baseTX cards from lame vendors who aren't 2139 * clever enough to change the PCI ID. For the moment 2140 * though, the AceNIC is the only copper card available. 2141 */ 2142 if (pci_get_vendor(dev) == ALT_VENDORID && 2143 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2144 sc->ti_copper = 1; 2145 /* Ok, it's not the only copper card available. */ 2146 if (pci_get_vendor(dev) == NG_VENDORID && 2147 pci_get_device(dev) == NG_DEVICEID_GA620T) 2148 sc->ti_copper = 1; 2149 2150 /* Set default tuneable values. */ 2151 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2152 #if 0 2153 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2154 #endif 2155 sc->ti_rx_coal_ticks = 170; 2156 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2157 sc->ti_rx_max_coal_bds = 64; 2158 #if 0 2159 sc->ti_tx_max_coal_bds = 128; 2160 #endif 2161 sc->ti_tx_max_coal_bds = 32; 2162 sc->ti_tx_buf_ratio = 21; 2163 2164 /* Set up ifnet structure */ 2165 ifp = &sc->arpcom.ac_if; 2166 ifp->if_softc = sc; 2167 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2168 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 2169 IFF_NEEDSGIANT; 2170 tis[unit] = sc; 2171 ifp->if_ioctl = ti_ioctl; 2172 ifp->if_start = ti_start; 2173 ifp->if_watchdog = ti_watchdog; 2174 ifp->if_init = ti_init; 2175 ifp->if_mtu = ETHERMTU; 2176 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2177 2178 /* Set up ifmedia support. */ 2179 if (sc->ti_copper) { 2180 /* 2181 * Copper cards allow manual 10/100 mode selection, 2182 * but not manual 1000baseTX mode selection. Why? 2183 * Becuase currently there's no way to specify the 2184 * master/slave setting through the firmware interface, 2185 * so Alteon decided to just bag it and handle it 2186 * via autonegotiation. 2187 */ 2188 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2189 ifmedia_add(&sc->ifmedia, 2190 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2191 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2192 ifmedia_add(&sc->ifmedia, 2193 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2194 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2195 ifmedia_add(&sc->ifmedia, 2196 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2197 } else { 2198 /* Fiber cards don't support 10/100 modes. */ 2199 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2200 ifmedia_add(&sc->ifmedia, 2201 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2202 } 2203 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2204 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2205 2206 /* 2207 * We're assuming here that card initialization is a sequential 2208 * thing. If it isn't, multiple cards probing at the same time 2209 * could stomp on the list of softcs here. 2210 */ 2211 2212 /* Register the device */ 2213 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2214 0600, "ti%d", sc->ti_unit); 2215 sc->dev->si_drv1 = sc; 2216 2217 /* 2218 * Call MI attach routine. 2219 */ 2220 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2221 2222 /* Hook interrupt last to avoid having to lock softc */ 2223 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2224 ti_intr, sc, &sc->ti_intrhand); 2225 2226 if (error) { 2227 printf("ti%d: couldn't set up irq\n", unit); 2228 ether_ifdetach(ifp); 2229 goto fail; 2230 } 2231 2232 fail: 2233 if (sc && error) 2234 ti_detach(dev); 2235 2236 return (error); 2237 } 2238 2239 /* 2240 * Shutdown hardware and free up resources. This can be called any 2241 * time after the mutex has been initialized. It is called in both 2242 * the error case in attach and the normal detach case so it needs 2243 * to be careful about only freeing resources that have actually been 2244 * allocated. 2245 */ 2246 static int 2247 ti_detach(dev) 2248 device_t dev; 2249 { 2250 struct ti_softc *sc; 2251 struct ifnet *ifp; 2252 2253 sc = device_get_softc(dev); 2254 destroy_dev(sc->dev); 2255 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2256 TI_LOCK(sc); 2257 ifp = &sc->arpcom.ac_if; 2258 2259 /* These should only be active if attach succeeded */ 2260 if (device_is_attached(dev)) { 2261 ti_stop(sc); 2262 ether_ifdetach(ifp); 2263 bus_generic_detach(dev); 2264 } 2265 ifmedia_removeall(&sc->ifmedia); 2266 2267 if (sc->ti_intrhand) 2268 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2269 if (sc->ti_irq) 2270 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2271 if (sc->ti_res) { 2272 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2273 sc->ti_res); 2274 } 2275 2276 #ifdef TI_PRIVATE_JUMBOS 2277 if (sc->ti_cdata.ti_jumbo_buf) 2278 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2279 #endif 2280 if (sc->ti_rdata) 2281 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2282 2283 TI_UNLOCK(sc); 2284 mtx_destroy(&sc->ti_mtx); 2285 2286 return (0); 2287 } 2288 2289 #ifdef TI_JUMBO_HDRSPLIT 2290 /* 2291 * If hdr_len is 0, that means that header splitting wasn't done on 2292 * this packet for some reason. The two most likely reasons are that 2293 * the protocol isn't a supported protocol for splitting, or this 2294 * packet had a fragment offset that wasn't 0. 2295 * 2296 * The header length, if it is non-zero, will always be the length of 2297 * the headers on the packet, but that length could be longer than the 2298 * first mbuf. So we take the minimum of the two as the actual 2299 * length. 2300 */ 2301 static __inline void 2302 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2303 { 2304 int i = 0; 2305 int lengths[4] = {0, 0, 0, 0}; 2306 struct mbuf *m, *mp; 2307 2308 if (hdr_len != 0) 2309 top->m_len = min(hdr_len, top->m_len); 2310 pkt_len -= top->m_len; 2311 lengths[i++] = top->m_len; 2312 2313 mp = top; 2314 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2315 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2316 pkt_len -= m->m_len; 2317 lengths[i++] = m->m_len; 2318 mp = m; 2319 } 2320 2321 #if 0 2322 if (hdr_len != 0) 2323 printf("got split packet: "); 2324 else 2325 printf("got non-split packet: "); 2326 2327 printf("%d,%d,%d,%d = %d\n", lengths[0], 2328 lengths[1], lengths[2], lengths[3], 2329 lengths[0] + lengths[1] + lengths[2] + 2330 lengths[3]); 2331 #endif 2332 2333 if (pkt_len) 2334 panic("header splitting didn't"); 2335 2336 if (m) { 2337 m_freem(m); 2338 mp->m_next = NULL; 2339 2340 } 2341 if (mp->m_next != NULL) 2342 panic("ti_hdr_split: last mbuf in chain should be null"); 2343 } 2344 #endif /* TI_JUMBO_HDRSPLIT */ 2345 2346 /* 2347 * Frame reception handling. This is called if there's a frame 2348 * on the receive return list. 2349 * 2350 * Note: we have to be able to handle three possibilities here: 2351 * 1) the frame is from the mini receive ring (can only happen) 2352 * on Tigon 2 boards) 2353 * 2) the frame is from the jumbo recieve ring 2354 * 3) the frame is from the standard receive ring 2355 */ 2356 2357 static void 2358 ti_rxeof(sc) 2359 struct ti_softc *sc; 2360 { 2361 struct ifnet *ifp; 2362 struct ti_cmd_desc cmd; 2363 2364 TI_LOCK_ASSERT(sc); 2365 2366 ifp = &sc->arpcom.ac_if; 2367 2368 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2369 struct ti_rx_desc *cur_rx; 2370 u_int32_t rxidx; 2371 struct mbuf *m = NULL; 2372 u_int16_t vlan_tag = 0; 2373 int have_tag = 0; 2374 2375 cur_rx = 2376 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2377 rxidx = cur_rx->ti_idx; 2378 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2379 2380 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2381 have_tag = 1; 2382 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2383 } 2384 2385 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2386 2387 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2388 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2389 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2390 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2391 ifp->if_ierrors++; 2392 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2393 continue; 2394 } 2395 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2396 ifp->if_ierrors++; 2397 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2398 continue; 2399 } 2400 #ifdef TI_PRIVATE_JUMBOS 2401 m->m_len = cur_rx->ti_len; 2402 #else /* TI_PRIVATE_JUMBOS */ 2403 #ifdef TI_JUMBO_HDRSPLIT 2404 if (sc->ti_hdrsplit) 2405 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2406 cur_rx->ti_len, rxidx); 2407 else 2408 #endif /* TI_JUMBO_HDRSPLIT */ 2409 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2410 #endif /* TI_PRIVATE_JUMBOS */ 2411 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2412 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2413 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2414 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2415 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2416 ifp->if_ierrors++; 2417 ti_newbuf_mini(sc, sc->ti_mini, m); 2418 continue; 2419 } 2420 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2421 ifp->if_ierrors++; 2422 ti_newbuf_mini(sc, sc->ti_mini, m); 2423 continue; 2424 } 2425 m->m_len = cur_rx->ti_len; 2426 } else { 2427 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2428 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2429 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2430 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2431 ifp->if_ierrors++; 2432 ti_newbuf_std(sc, sc->ti_std, m); 2433 continue; 2434 } 2435 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2436 ifp->if_ierrors++; 2437 ti_newbuf_std(sc, sc->ti_std, m); 2438 continue; 2439 } 2440 m->m_len = cur_rx->ti_len; 2441 } 2442 2443 m->m_pkthdr.len = cur_rx->ti_len; 2444 ifp->if_ipackets++; 2445 m->m_pkthdr.rcvif = ifp; 2446 2447 if (ifp->if_hwassist) { 2448 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2449 CSUM_DATA_VALID; 2450 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2451 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2452 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2453 } 2454 2455 /* 2456 * If we received a packet with a vlan tag, 2457 * tag it before passing the packet upward. 2458 */ 2459 if (have_tag) 2460 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2461 TI_UNLOCK(sc); 2462 (*ifp->if_input)(ifp, m); 2463 TI_LOCK(sc); 2464 } 2465 2466 /* Only necessary on the Tigon 1. */ 2467 if (sc->ti_hwrev == TI_HWREV_TIGON) 2468 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2469 sc->ti_rx_saved_considx); 2470 2471 TI_UPDATE_STDPROD(sc, sc->ti_std); 2472 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2473 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2474 } 2475 2476 static void 2477 ti_txeof(sc) 2478 struct ti_softc *sc; 2479 { 2480 struct ti_tx_desc *cur_tx = NULL; 2481 struct ifnet *ifp; 2482 2483 ifp = &sc->arpcom.ac_if; 2484 2485 /* 2486 * Go through our tx ring and free mbufs for those 2487 * frames that have been sent. 2488 */ 2489 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2490 u_int32_t idx = 0; 2491 2492 idx = sc->ti_tx_saved_considx; 2493 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2494 if (idx > 383) 2495 CSR_WRITE_4(sc, TI_WINBASE, 2496 TI_TX_RING_BASE + 6144); 2497 else if (idx > 255) 2498 CSR_WRITE_4(sc, TI_WINBASE, 2499 TI_TX_RING_BASE + 4096); 2500 else if (idx > 127) 2501 CSR_WRITE_4(sc, TI_WINBASE, 2502 TI_TX_RING_BASE + 2048); 2503 else 2504 CSR_WRITE_4(sc, TI_WINBASE, 2505 TI_TX_RING_BASE); 2506 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2507 } else 2508 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2509 if (cur_tx->ti_flags & TI_BDFLAG_END) 2510 ifp->if_opackets++; 2511 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2512 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2513 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2514 } 2515 sc->ti_txcnt--; 2516 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2517 ifp->if_timer = 0; 2518 } 2519 2520 if (cur_tx != NULL) 2521 ifp->if_flags &= ~IFF_OACTIVE; 2522 } 2523 2524 static void 2525 ti_intr(xsc) 2526 void *xsc; 2527 { 2528 struct ti_softc *sc; 2529 struct ifnet *ifp; 2530 2531 sc = xsc; 2532 TI_LOCK(sc); 2533 ifp = &sc->arpcom.ac_if; 2534 2535 /*#ifdef notdef*/ 2536 /* Avoid this for now -- checking this register is expensive. */ 2537 /* Make sure this is really our interrupt. */ 2538 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2539 TI_UNLOCK(sc); 2540 return; 2541 } 2542 /*#endif*/ 2543 2544 /* Ack interrupt and stop others from occuring. */ 2545 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2546 2547 if (ifp->if_flags & IFF_RUNNING) { 2548 /* Check RX return ring producer/consumer */ 2549 ti_rxeof(sc); 2550 2551 /* Check TX ring producer/consumer */ 2552 ti_txeof(sc); 2553 } 2554 2555 ti_handle_events(sc); 2556 2557 /* Re-enable interrupts. */ 2558 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2559 2560 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2561 ti_start(ifp); 2562 2563 TI_UNLOCK(sc); 2564 } 2565 2566 static void 2567 ti_stats_update(sc) 2568 struct ti_softc *sc; 2569 { 2570 struct ifnet *ifp; 2571 2572 ifp = &sc->arpcom.ac_if; 2573 2574 ifp->if_collisions += 2575 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2576 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2577 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2578 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2579 ifp->if_collisions; 2580 } 2581 2582 /* 2583 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2584 * pointers to descriptors. 2585 */ 2586 static int 2587 ti_encap(sc, m_head, txidx) 2588 struct ti_softc *sc; 2589 struct mbuf *m_head; 2590 u_int32_t *txidx; 2591 { 2592 struct ti_tx_desc *f = NULL; 2593 struct mbuf *m; 2594 u_int32_t frag, cur, cnt = 0; 2595 u_int16_t csum_flags = 0; 2596 struct m_tag *mtag; 2597 2598 m = m_head; 2599 cur = frag = *txidx; 2600 2601 if (m_head->m_pkthdr.csum_flags) { 2602 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2603 csum_flags |= TI_BDFLAG_IP_CKSUM; 2604 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2605 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2606 if (m_head->m_flags & M_LASTFRAG) 2607 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2608 else if (m_head->m_flags & M_FRAG) 2609 csum_flags |= TI_BDFLAG_IP_FRAG; 2610 } 2611 2612 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2613 2614 /* 2615 * Start packing the mbufs in this chain into 2616 * the fragment pointers. Stop when we run out 2617 * of fragments or hit the end of the mbuf chain. 2618 */ 2619 for (m = m_head; m != NULL; m = m->m_next) { 2620 if (m->m_len != 0) { 2621 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2622 if (frag > 383) 2623 CSR_WRITE_4(sc, TI_WINBASE, 2624 TI_TX_RING_BASE + 6144); 2625 else if (frag > 255) 2626 CSR_WRITE_4(sc, TI_WINBASE, 2627 TI_TX_RING_BASE + 4096); 2628 else if (frag > 127) 2629 CSR_WRITE_4(sc, TI_WINBASE, 2630 TI_TX_RING_BASE + 2048); 2631 else 2632 CSR_WRITE_4(sc, TI_WINBASE, 2633 TI_TX_RING_BASE); 2634 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2635 } else 2636 f = &sc->ti_rdata->ti_tx_ring[frag]; 2637 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2638 break; 2639 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2640 f->ti_len = m->m_len; 2641 f->ti_flags = csum_flags; 2642 2643 if (mtag != NULL) { 2644 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2645 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2646 } else { 2647 f->ti_vlan_tag = 0; 2648 } 2649 2650 /* 2651 * Sanity check: avoid coming within 16 descriptors 2652 * of the end of the ring. 2653 */ 2654 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2655 return (ENOBUFS); 2656 cur = frag; 2657 TI_INC(frag, TI_TX_RING_CNT); 2658 cnt++; 2659 } 2660 } 2661 2662 if (m != NULL) 2663 return (ENOBUFS); 2664 2665 if (frag == sc->ti_tx_saved_considx) 2666 return (ENOBUFS); 2667 2668 if (sc->ti_hwrev == TI_HWREV_TIGON) 2669 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2670 TI_BDFLAG_END; 2671 else 2672 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2673 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2674 sc->ti_txcnt += cnt; 2675 2676 *txidx = frag; 2677 2678 return (0); 2679 } 2680 2681 /* 2682 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2683 * to the mbuf data regions directly in the transmit descriptors. 2684 */ 2685 static void 2686 ti_start(ifp) 2687 struct ifnet *ifp; 2688 { 2689 struct ti_softc *sc; 2690 struct mbuf *m_head = NULL; 2691 u_int32_t prodidx = 0; 2692 2693 sc = ifp->if_softc; 2694 TI_LOCK(sc); 2695 2696 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2697 2698 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2699 IF_DEQUEUE(&ifp->if_snd, m_head); 2700 if (m_head == NULL) 2701 break; 2702 2703 /* 2704 * XXX 2705 * safety overkill. If this is a fragmented packet chain 2706 * with delayed TCP/UDP checksums, then only encapsulate 2707 * it if we have enough descriptors to handle the entire 2708 * chain at once. 2709 * (paranoia -- may not actually be needed) 2710 */ 2711 if (m_head->m_flags & M_FIRSTFRAG && 2712 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2713 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2714 m_head->m_pkthdr.csum_data + 16) { 2715 IF_PREPEND(&ifp->if_snd, m_head); 2716 ifp->if_flags |= IFF_OACTIVE; 2717 break; 2718 } 2719 } 2720 2721 /* 2722 * Pack the data into the transmit ring. If we 2723 * don't have room, set the OACTIVE flag and wait 2724 * for the NIC to drain the ring. 2725 */ 2726 if (ti_encap(sc, m_head, &prodidx)) { 2727 IF_PREPEND(&ifp->if_snd, m_head); 2728 ifp->if_flags |= IFF_OACTIVE; 2729 break; 2730 } 2731 2732 /* 2733 * If there's a BPF listener, bounce a copy of this frame 2734 * to him. 2735 */ 2736 BPF_MTAP(ifp, m_head); 2737 } 2738 2739 /* Transmit */ 2740 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2741 2742 /* 2743 * Set a timeout in case the chip goes out to lunch. 2744 */ 2745 ifp->if_timer = 5; 2746 TI_UNLOCK(sc); 2747 } 2748 2749 static void 2750 ti_init(xsc) 2751 void *xsc; 2752 { 2753 struct ti_softc *sc = xsc; 2754 2755 /* Cancel pending I/O and flush buffers. */ 2756 ti_stop(sc); 2757 2758 TI_LOCK(sc); 2759 /* Init the gen info block, ring control blocks and firmware. */ 2760 if (ti_gibinit(sc)) { 2761 printf("ti%d: initialization failure\n", sc->ti_unit); 2762 TI_UNLOCK(sc); 2763 return; 2764 } 2765 2766 TI_UNLOCK(sc); 2767 } 2768 2769 static void ti_init2(sc) 2770 struct ti_softc *sc; 2771 { 2772 struct ti_cmd_desc cmd; 2773 struct ifnet *ifp; 2774 u_int16_t *m; 2775 struct ifmedia *ifm; 2776 int tmp; 2777 2778 ifp = &sc->arpcom.ac_if; 2779 2780 /* Specify MTU and interface index. */ 2781 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 2782 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2783 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 2784 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2785 2786 /* Load our MAC address. */ 2787 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2788 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2789 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2790 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2791 2792 /* Enable or disable promiscuous mode as needed. */ 2793 if (ifp->if_flags & IFF_PROMISC) { 2794 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2795 } else { 2796 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2797 } 2798 2799 /* Program multicast filter. */ 2800 ti_setmulti(sc); 2801 2802 /* 2803 * If this is a Tigon 1, we should tell the 2804 * firmware to use software packet filtering. 2805 */ 2806 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2807 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2808 } 2809 2810 /* Init RX ring. */ 2811 ti_init_rx_ring_std(sc); 2812 2813 /* Init jumbo RX ring. */ 2814 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2815 ti_init_rx_ring_jumbo(sc); 2816 2817 /* 2818 * If this is a Tigon 2, we can also configure the 2819 * mini ring. 2820 */ 2821 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2822 ti_init_rx_ring_mini(sc); 2823 2824 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2825 sc->ti_rx_saved_considx = 0; 2826 2827 /* Init TX ring. */ 2828 ti_init_tx_ring(sc); 2829 2830 /* Tell firmware we're alive. */ 2831 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2832 2833 /* Enable host interrupts. */ 2834 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2835 2836 ifp->if_flags |= IFF_RUNNING; 2837 ifp->if_flags &= ~IFF_OACTIVE; 2838 2839 /* 2840 * Make sure to set media properly. We have to do this 2841 * here since we have to issue commands in order to set 2842 * the link negotiation and we can't issue commands until 2843 * the firmware is running. 2844 */ 2845 ifm = &sc->ifmedia; 2846 tmp = ifm->ifm_media; 2847 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2848 ti_ifmedia_upd(ifp); 2849 ifm->ifm_media = tmp; 2850 } 2851 2852 /* 2853 * Set media options. 2854 */ 2855 static int 2856 ti_ifmedia_upd(ifp) 2857 struct ifnet *ifp; 2858 { 2859 struct ti_softc *sc; 2860 struct ifmedia *ifm; 2861 struct ti_cmd_desc cmd; 2862 u_int32_t flowctl; 2863 2864 sc = ifp->if_softc; 2865 ifm = &sc->ifmedia; 2866 2867 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2868 return (EINVAL); 2869 2870 flowctl = 0; 2871 2872 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2873 case IFM_AUTO: 2874 /* 2875 * Transmit flow control doesn't work on the Tigon 1. 2876 */ 2877 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2878 2879 /* 2880 * Transmit flow control can also cause problems on the 2881 * Tigon 2, apparantly with both the copper and fiber 2882 * boards. The symptom is that the interface will just 2883 * hang. This was reproduced with Alteon 180 switches. 2884 */ 2885 #if 0 2886 if (sc->ti_hwrev != TI_HWREV_TIGON) 2887 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2888 #endif 2889 2890 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2891 TI_GLNK_FULL_DUPLEX| flowctl | 2892 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2893 2894 flowctl = TI_LNK_RX_FLOWCTL_Y; 2895 #if 0 2896 if (sc->ti_hwrev != TI_HWREV_TIGON) 2897 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2898 #endif 2899 2900 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2901 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 2902 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2903 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2904 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2905 break; 2906 case IFM_1000_SX: 2907 case IFM_1000_T: 2908 flowctl = TI_GLNK_RX_FLOWCTL_Y; 2909 #if 0 2910 if (sc->ti_hwrev != TI_HWREV_TIGON) 2911 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 2912 #endif 2913 2914 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2915 flowctl |TI_GLNK_ENB); 2916 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2917 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2918 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 2919 } 2920 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2921 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2922 break; 2923 case IFM_100_FX: 2924 case IFM_10_FL: 2925 case IFM_100_TX: 2926 case IFM_10_T: 2927 flowctl = TI_LNK_RX_FLOWCTL_Y; 2928 #if 0 2929 if (sc->ti_hwrev != TI_HWREV_TIGON) 2930 flowctl |= TI_LNK_TX_FLOWCTL_Y; 2931 #endif 2932 2933 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2934 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 2935 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2936 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2937 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2938 } else { 2939 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2940 } 2941 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2942 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2943 } else { 2944 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2945 } 2946 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2947 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2948 break; 2949 } 2950 2951 return (0); 2952 } 2953 2954 /* 2955 * Report current media status. 2956 */ 2957 static void 2958 ti_ifmedia_sts(ifp, ifmr) 2959 struct ifnet *ifp; 2960 struct ifmediareq *ifmr; 2961 { 2962 struct ti_softc *sc; 2963 u_int32_t media = 0; 2964 2965 sc = ifp->if_softc; 2966 2967 ifmr->ifm_status = IFM_AVALID; 2968 ifmr->ifm_active = IFM_ETHER; 2969 2970 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2971 return; 2972 2973 ifmr->ifm_status |= IFM_ACTIVE; 2974 2975 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2976 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2977 if (sc->ti_copper) 2978 ifmr->ifm_active |= IFM_1000_T; 2979 else 2980 ifmr->ifm_active |= IFM_1000_SX; 2981 if (media & TI_GLNK_FULL_DUPLEX) 2982 ifmr->ifm_active |= IFM_FDX; 2983 else 2984 ifmr->ifm_active |= IFM_HDX; 2985 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2986 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2987 if (sc->ti_copper) { 2988 if (media & TI_LNK_100MB) 2989 ifmr->ifm_active |= IFM_100_TX; 2990 if (media & TI_LNK_10MB) 2991 ifmr->ifm_active |= IFM_10_T; 2992 } else { 2993 if (media & TI_LNK_100MB) 2994 ifmr->ifm_active |= IFM_100_FX; 2995 if (media & TI_LNK_10MB) 2996 ifmr->ifm_active |= IFM_10_FL; 2997 } 2998 if (media & TI_LNK_FULL_DUPLEX) 2999 ifmr->ifm_active |= IFM_FDX; 3000 if (media & TI_LNK_HALF_DUPLEX) 3001 ifmr->ifm_active |= IFM_HDX; 3002 } 3003 } 3004 3005 static int 3006 ti_ioctl(ifp, command, data) 3007 struct ifnet *ifp; 3008 u_long command; 3009 caddr_t data; 3010 { 3011 struct ti_softc *sc = ifp->if_softc; 3012 struct ifreq *ifr = (struct ifreq *) data; 3013 int mask, error = 0; 3014 struct ti_cmd_desc cmd; 3015 3016 TI_LOCK(sc); 3017 3018 switch (command) { 3019 case SIOCSIFMTU: 3020 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3021 error = EINVAL; 3022 else { 3023 ifp->if_mtu = ifr->ifr_mtu; 3024 ti_init(sc); 3025 } 3026 break; 3027 case SIOCSIFFLAGS: 3028 if (ifp->if_flags & IFF_UP) { 3029 /* 3030 * If only the state of the PROMISC flag changed, 3031 * then just use the 'set promisc mode' command 3032 * instead of reinitializing the entire NIC. Doing 3033 * a full re-init means reloading the firmware and 3034 * waiting for it to start up, which may take a 3035 * second or two. 3036 */ 3037 if (ifp->if_flags & IFF_RUNNING && 3038 ifp->if_flags & IFF_PROMISC && 3039 !(sc->ti_if_flags & IFF_PROMISC)) { 3040 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3041 TI_CMD_CODE_PROMISC_ENB, 0); 3042 } else if (ifp->if_flags & IFF_RUNNING && 3043 !(ifp->if_flags & IFF_PROMISC) && 3044 sc->ti_if_flags & IFF_PROMISC) { 3045 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3046 TI_CMD_CODE_PROMISC_DIS, 0); 3047 } else 3048 ti_init(sc); 3049 } else { 3050 if (ifp->if_flags & IFF_RUNNING) { 3051 ti_stop(sc); 3052 } 3053 } 3054 sc->ti_if_flags = ifp->if_flags; 3055 error = 0; 3056 break; 3057 case SIOCADDMULTI: 3058 case SIOCDELMULTI: 3059 if (ifp->if_flags & IFF_RUNNING) { 3060 ti_setmulti(sc); 3061 error = 0; 3062 } 3063 break; 3064 case SIOCSIFMEDIA: 3065 case SIOCGIFMEDIA: 3066 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3067 break; 3068 case SIOCSIFCAP: 3069 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3070 if (mask & IFCAP_HWCSUM) { 3071 if (IFCAP_HWCSUM & ifp->if_capenable) 3072 ifp->if_capenable &= ~IFCAP_HWCSUM; 3073 else 3074 ifp->if_capenable |= IFCAP_HWCSUM; 3075 if (ifp->if_flags & IFF_RUNNING) 3076 ti_init(sc); 3077 } 3078 error = 0; 3079 break; 3080 default: 3081 error = ether_ioctl(ifp, command, data); 3082 break; 3083 } 3084 3085 TI_UNLOCK(sc); 3086 3087 return (error); 3088 } 3089 3090 static int 3091 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3092 { 3093 struct ti_softc *sc; 3094 3095 sc = dev->si_drv1; 3096 if (sc == NULL) 3097 return (ENODEV); 3098 3099 TI_LOCK(sc); 3100 sc->ti_flags |= TI_FLAG_DEBUGING; 3101 TI_UNLOCK(sc); 3102 3103 return (0); 3104 } 3105 3106 static int 3107 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3108 { 3109 struct ti_softc *sc; 3110 3111 sc = dev->si_drv1; 3112 if (sc == NULL) 3113 return (ENODEV); 3114 3115 TI_LOCK(sc); 3116 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3117 TI_UNLOCK(sc); 3118 3119 return (0); 3120 } 3121 3122 /* 3123 * This ioctl routine goes along with the Tigon character device. 3124 */ 3125 static int 3126 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3127 { 3128 int error; 3129 struct ti_softc *sc; 3130 3131 sc = dev->si_drv1; 3132 if (sc == NULL) 3133 return (ENODEV); 3134 3135 error = 0; 3136 3137 switch (cmd) { 3138 case TIIOCGETSTATS: 3139 { 3140 struct ti_stats *outstats; 3141 3142 outstats = (struct ti_stats *)addr; 3143 3144 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3145 sizeof(struct ti_stats)); 3146 break; 3147 } 3148 case TIIOCGETPARAMS: 3149 { 3150 struct ti_params *params; 3151 3152 params = (struct ti_params *)addr; 3153 3154 params->ti_stat_ticks = sc->ti_stat_ticks; 3155 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3156 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3157 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3158 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3159 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3160 params->param_mask = TI_PARAM_ALL; 3161 3162 error = 0; 3163 3164 break; 3165 } 3166 case TIIOCSETPARAMS: 3167 { 3168 struct ti_params *params; 3169 3170 params = (struct ti_params *)addr; 3171 3172 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3173 sc->ti_stat_ticks = params->ti_stat_ticks; 3174 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3175 } 3176 3177 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3178 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3179 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3180 sc->ti_rx_coal_ticks); 3181 } 3182 3183 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3184 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3185 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3186 sc->ti_tx_coal_ticks); 3187 } 3188 3189 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3190 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3191 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3192 sc->ti_rx_max_coal_bds); 3193 } 3194 3195 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3196 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3197 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3198 sc->ti_tx_max_coal_bds); 3199 } 3200 3201 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3202 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3203 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3204 sc->ti_tx_buf_ratio); 3205 } 3206 3207 error = 0; 3208 3209 break; 3210 } 3211 case TIIOCSETTRACE: { 3212 ti_trace_type trace_type; 3213 3214 trace_type = *(ti_trace_type *)addr; 3215 3216 /* 3217 * Set tracing to whatever the user asked for. Setting 3218 * this register to 0 should have the effect of disabling 3219 * tracing. 3220 */ 3221 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3222 3223 error = 0; 3224 3225 break; 3226 } 3227 case TIIOCGETTRACE: { 3228 struct ti_trace_buf *trace_buf; 3229 u_int32_t trace_start, cur_trace_ptr, trace_len; 3230 3231 trace_buf = (struct ti_trace_buf *)addr; 3232 3233 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3234 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3235 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3236 3237 #if 0 3238 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3239 "trace_len = %d\n", sc->ti_unit, trace_start, 3240 cur_trace_ptr, trace_len); 3241 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3242 trace_buf->buf_len); 3243 #endif 3244 3245 error = ti_copy_mem(sc, trace_start, min(trace_len, 3246 trace_buf->buf_len), 3247 (caddr_t)trace_buf->buf, 1, 1); 3248 3249 if (error == 0) { 3250 trace_buf->fill_len = min(trace_len, 3251 trace_buf->buf_len); 3252 if (cur_trace_ptr < trace_start) 3253 trace_buf->cur_trace_ptr = 3254 trace_start - cur_trace_ptr; 3255 else 3256 trace_buf->cur_trace_ptr = 3257 cur_trace_ptr - trace_start; 3258 } else 3259 trace_buf->fill_len = 0; 3260 3261 break; 3262 } 3263 3264 /* 3265 * For debugging, five ioctls are needed: 3266 * ALT_ATTACH 3267 * ALT_READ_TG_REG 3268 * ALT_WRITE_TG_REG 3269 * ALT_READ_TG_MEM 3270 * ALT_WRITE_TG_MEM 3271 */ 3272 case ALT_ATTACH: 3273 /* 3274 * From what I can tell, Alteon's Solaris Tigon driver 3275 * only has one character device, so you have to attach 3276 * to the Tigon board you're interested in. This seems 3277 * like a not-so-good way to do things, since unless you 3278 * subsequently specify the unit number of the device 3279 * you're interested in in every ioctl, you'll only be 3280 * able to debug one board at a time. 3281 */ 3282 error = 0; 3283 break; 3284 case ALT_READ_TG_MEM: 3285 case ALT_WRITE_TG_MEM: 3286 { 3287 struct tg_mem *mem_param; 3288 u_int32_t sram_end, scratch_end; 3289 3290 mem_param = (struct tg_mem *)addr; 3291 3292 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3293 sram_end = TI_END_SRAM_I; 3294 scratch_end = TI_END_SCRATCH_I; 3295 } else { 3296 sram_end = TI_END_SRAM_II; 3297 scratch_end = TI_END_SCRATCH_II; 3298 } 3299 3300 /* 3301 * For now, we'll only handle accessing regular SRAM, 3302 * nothing else. 3303 */ 3304 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3305 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3306 /* 3307 * In this instance, we always copy to/from user 3308 * space, so the user space argument is set to 1. 3309 */ 3310 error = ti_copy_mem(sc, mem_param->tgAddr, 3311 mem_param->len, 3312 mem_param->userAddr, 1, 3313 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3314 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3315 && (mem_param->tgAddr <= scratch_end)) { 3316 error = ti_copy_scratch(sc, mem_param->tgAddr, 3317 mem_param->len, 3318 mem_param->userAddr, 1, 3319 (cmd == ALT_READ_TG_MEM) ? 3320 1 : 0, TI_PROCESSOR_A); 3321 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3322 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3323 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3324 printf("ti%d: invalid memory range for " 3325 "Tigon I\n", sc->ti_unit); 3326 error = EINVAL; 3327 break; 3328 } 3329 error = ti_copy_scratch(sc, mem_param->tgAddr - 3330 TI_SCRATCH_DEBUG_OFF, 3331 mem_param->len, 3332 mem_param->userAddr, 1, 3333 (cmd == ALT_READ_TG_MEM) ? 3334 1 : 0, TI_PROCESSOR_B); 3335 } else { 3336 printf("ti%d: memory address %#x len %d is out of " 3337 "supported range\n", sc->ti_unit, 3338 mem_param->tgAddr, mem_param->len); 3339 error = EINVAL; 3340 } 3341 3342 break; 3343 } 3344 case ALT_READ_TG_REG: 3345 case ALT_WRITE_TG_REG: 3346 { 3347 struct tg_reg *regs; 3348 u_int32_t tmpval; 3349 3350 regs = (struct tg_reg *)addr; 3351 3352 /* 3353 * Make sure the address in question isn't out of range. 3354 */ 3355 if (regs->addr > TI_REG_MAX) { 3356 error = EINVAL; 3357 break; 3358 } 3359 if (cmd == ALT_READ_TG_REG) { 3360 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3361 regs->addr, &tmpval, 1); 3362 regs->data = ntohl(tmpval); 3363 #if 0 3364 if ((regs->addr == TI_CPU_STATE) 3365 || (regs->addr == TI_CPU_CTL_B)) { 3366 printf("ti%d: register %#x = %#x\n", 3367 sc->ti_unit, regs->addr, tmpval); 3368 } 3369 #endif 3370 } else { 3371 tmpval = htonl(regs->data); 3372 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3373 regs->addr, &tmpval, 1); 3374 } 3375 3376 break; 3377 } 3378 default: 3379 error = ENOTTY; 3380 break; 3381 } 3382 return (error); 3383 } 3384 3385 static void 3386 ti_watchdog(ifp) 3387 struct ifnet *ifp; 3388 { 3389 struct ti_softc *sc; 3390 3391 sc = ifp->if_softc; 3392 TI_LOCK(sc); 3393 3394 /* 3395 * When we're debugging, the chip is often stopped for long periods 3396 * of time, and that would normally cause the watchdog timer to fire. 3397 * Since that impedes debugging, we don't want to do that. 3398 */ 3399 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3400 TI_UNLOCK(sc); 3401 return; 3402 } 3403 3404 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3405 ti_stop(sc); 3406 ti_init(sc); 3407 3408 ifp->if_oerrors++; 3409 TI_UNLOCK(sc); 3410 } 3411 3412 /* 3413 * Stop the adapter and free any mbufs allocated to the 3414 * RX and TX lists. 3415 */ 3416 static void 3417 ti_stop(sc) 3418 struct ti_softc *sc; 3419 { 3420 struct ifnet *ifp; 3421 struct ti_cmd_desc cmd; 3422 3423 TI_LOCK(sc); 3424 3425 ifp = &sc->arpcom.ac_if; 3426 3427 /* Disable host interrupts. */ 3428 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3429 /* 3430 * Tell firmware we're shutting down. 3431 */ 3432 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3433 3434 /* Halt and reinitialize. */ 3435 ti_chipinit(sc); 3436 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3437 ti_chipinit(sc); 3438 3439 /* Free the RX lists. */ 3440 ti_free_rx_ring_std(sc); 3441 3442 /* Free jumbo RX list. */ 3443 ti_free_rx_ring_jumbo(sc); 3444 3445 /* Free mini RX list. */ 3446 ti_free_rx_ring_mini(sc); 3447 3448 /* Free TX buffers. */ 3449 ti_free_tx_ring(sc); 3450 3451 sc->ti_ev_prodidx.ti_idx = 0; 3452 sc->ti_return_prodidx.ti_idx = 0; 3453 sc->ti_tx_considx.ti_idx = 0; 3454 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3455 3456 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3457 TI_UNLOCK(sc); 3458 } 3459 3460 /* 3461 * Stop all chip I/O so that the kernel's probe routines don't 3462 * get confused by errant DMAs when rebooting. 3463 */ 3464 static void 3465 ti_shutdown(dev) 3466 device_t dev; 3467 { 3468 struct ti_softc *sc; 3469 3470 sc = device_get_softc(dev); 3471 TI_LOCK(sc); 3472 ti_chipinit(sc); 3473 TI_UNLOCK(sc); 3474 } 3475