1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/socket.h> 91 #include <sys/queue.h> 92 #include <sys/conf.h> 93 94 #include <net/if.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_types.h> 100 #include <net/if_vlan_var.h> 101 102 #include <net/bpf.h> 103 104 #include <netinet/in_systm.h> 105 #include <netinet/in.h> 106 #include <netinet/ip.h> 107 108 #include <vm/vm.h> /* for vtophys */ 109 #include <vm/pmap.h> /* for vtophys */ 110 #include <machine/bus_memio.h> 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 /* #define TI_PRIVATE_JUMBOS */ 117 118 #if !defined(TI_PRIVATE_JUMBOS) 119 #include <sys/sockio.h> 120 #include <sys/uio.h> 121 #include <sys/lock.h> 122 #include <vm/vm_extern.h> 123 #include <vm/pmap.h> 124 #include <vm/vm_map.h> 125 #include <vm/vm_map.h> 126 #include <vm/vm_param.h> 127 #include <vm/vm_pageout.h> 128 #include <sys/vmmeter.h> 129 #include <vm/vm_page.h> 130 #include <vm/vm_object.h> 131 #include <vm/vm_kern.h> 132 #include <sys/proc.h> 133 #include <sys/jumbo.h> 134 #endif /* !TI_PRIVATE_JUMBOS */ 135 #include <sys/vnode.h> /* for vfindev, vgone */ 136 137 #include <pci/pcireg.h> 138 #include <pci/pcivar.h> 139 140 #include <sys/tiio.h> 141 #include <pci/if_tireg.h> 142 #include <pci/ti_fw.h> 143 #include <pci/ti_fw2.h> 144 145 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 146 /* 147 * We can only turn on header splitting if we're using extended receive 148 * BDs. 149 */ 150 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 151 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 152 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 153 154 struct ti_softc *tis[8]; 155 156 typedef enum { 157 TI_SWAP_HTON, 158 TI_SWAP_NTOH 159 } ti_swap_type; 160 161 162 /* 163 * Various supported device vendors/types and their names. 164 */ 165 166 static struct ti_type ti_devs[] = { 167 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 168 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 169 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 170 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 171 { TC_VENDORID, TC_DEVICEID_3C985, 172 "3Com 3c985-SX Gigabit Ethernet" }, 173 { NG_VENDORID, NG_DEVICEID_GA620, 174 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 175 { NG_VENDORID, NG_DEVICEID_GA620T, 176 "Netgear GA620 1000baseT Gigabit Ethernet" }, 177 { SGI_VENDORID, SGI_DEVICEID_TIGON, 178 "Silicon Graphics Gigabit Ethernet" }, 179 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 180 "Farallon PN9000SX Gigabit Ethernet" }, 181 { 0, 0, NULL } 182 }; 183 184 #define TI_CDEV_MAJOR 153 185 186 static d_open_t ti_open; 187 static d_close_t ti_close; 188 static d_ioctl_t ti_ioctl2; 189 190 static struct cdevsw ti_cdevsw = { 191 .d_open = ti_open, 192 .d_close = ti_close, 193 .d_ioctl = ti_ioctl2, 194 .d_name = "ti", 195 .d_maj = TI_CDEV_MAJOR, 196 }; 197 198 static int ti_probe (device_t); 199 static int ti_attach (device_t); 200 static int ti_detach (device_t); 201 static void ti_txeof (struct ti_softc *); 202 static void ti_rxeof (struct ti_softc *); 203 204 static void ti_stats_update (struct ti_softc *); 205 static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *); 206 207 static void ti_intr (void *); 208 static void ti_start (struct ifnet *); 209 static int ti_ioctl (struct ifnet *, u_long, caddr_t); 210 static void ti_init (void *); 211 static void ti_init2 (struct ti_softc *); 212 static void ti_stop (struct ti_softc *); 213 static void ti_watchdog (struct ifnet *); 214 static void ti_shutdown (device_t); 215 static int ti_ifmedia_upd (struct ifnet *); 216 static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218 static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int); 219 static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *); 220 static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int); 221 222 static void ti_add_mcast (struct ti_softc *, struct ether_addr *); 223 static void ti_del_mcast (struct ti_softc *, struct ether_addr *); 224 static void ti_setmulti (struct ti_softc *); 225 226 static void ti_mem (struct ti_softc *, u_int32_t, 227 u_int32_t, caddr_t); 228 static int ti_copy_mem (struct ti_softc *, u_int32_t, 229 u_int32_t, caddr_t, int, int); 230 static int ti_copy_scratch (struct ti_softc *, u_int32_t, 231 u_int32_t, caddr_t, int, int, int); 232 static int ti_bcopy_swap (const void *, void *, size_t, 233 ti_swap_type); 234 static void ti_loadfw (struct ti_softc *); 235 static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *); 236 static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *, 237 caddr_t, int); 238 static void ti_handle_events (struct ti_softc *); 239 #ifdef TI_PRIVATE_JUMBOS 240 static int ti_alloc_jumbo_mem (struct ti_softc *); 241 static void *ti_jalloc (struct ti_softc *); 242 static void ti_jfree (void *, void *); 243 #endif /* TI_PRIVATE_JUMBOS */ 244 static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *); 245 static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *); 246 static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *); 247 static int ti_init_rx_ring_std (struct ti_softc *); 248 static void ti_free_rx_ring_std (struct ti_softc *); 249 static int ti_init_rx_ring_jumbo (struct ti_softc *); 250 static void ti_free_rx_ring_jumbo (struct ti_softc *); 251 static int ti_init_rx_ring_mini (struct ti_softc *); 252 static void ti_free_rx_ring_mini (struct ti_softc *); 253 static void ti_free_tx_ring (struct ti_softc *); 254 static int ti_init_tx_ring (struct ti_softc *); 255 256 static int ti_64bitslot_war (struct ti_softc *); 257 static int ti_chipinit (struct ti_softc *); 258 static int ti_gibinit (struct ti_softc *); 259 260 #ifdef TI_JUMBO_HDRSPLIT 261 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 262 int pkt_len, int idx); 263 #endif /* TI_JUMBO_HDRSPLIT */ 264 265 static device_method_t ti_methods[] = { 266 /* Device interface */ 267 DEVMETHOD(device_probe, ti_probe), 268 DEVMETHOD(device_attach, ti_attach), 269 DEVMETHOD(device_detach, ti_detach), 270 DEVMETHOD(device_shutdown, ti_shutdown), 271 { 0, 0 } 272 }; 273 274 static driver_t ti_driver = { 275 "ti", 276 ti_methods, 277 sizeof(struct ti_softc) 278 }; 279 280 static devclass_t ti_devclass; 281 282 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 283 284 /* List of Tigon softcs */ 285 static STAILQ_HEAD(ti_softc_list, ti_softc) ti_sc_list; 286 287 static struct ti_softc * 288 ti_lookup_softc(int unit) 289 { 290 struct ti_softc *sc; 291 for (sc = STAILQ_FIRST(&ti_sc_list); sc != NULL; 292 sc = STAILQ_NEXT(sc, ti_links)) 293 if (sc->ti_unit == unit) 294 return(sc); 295 return(NULL); 296 } 297 298 /* 299 * Send an instruction or address to the EEPROM, check for ACK. 300 */ 301 static u_int32_t ti_eeprom_putbyte(sc, byte) 302 struct ti_softc *sc; 303 int byte; 304 { 305 register int i, ack = 0; 306 307 /* 308 * Make sure we're in TX mode. 309 */ 310 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 311 312 /* 313 * Feed in each bit and stobe the clock. 314 */ 315 for (i = 0x80; i; i >>= 1) { 316 if (byte & i) { 317 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 318 } else { 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 320 } 321 DELAY(1); 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 DELAY(1); 324 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 325 } 326 327 /* 328 * Turn off TX mode. 329 */ 330 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 331 332 /* 333 * Check for ack. 334 */ 335 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 336 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 337 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 338 339 return(ack); 340 } 341 342 /* 343 * Read a byte of data stored in the EEPROM at address 'addr.' 344 * We have to send two address bytes since the EEPROM can hold 345 * more than 256 bytes of data. 346 */ 347 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 348 struct ti_softc *sc; 349 int addr; 350 u_int8_t *dest; 351 { 352 register int i; 353 u_int8_t byte = 0; 354 355 EEPROM_START; 356 357 /* 358 * Send write control code to EEPROM. 359 */ 360 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 361 printf("ti%d: failed to send write command, status: %x\n", 362 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 363 return(1); 364 } 365 366 /* 367 * Send first byte of address of byte we want to read. 368 */ 369 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 370 printf("ti%d: failed to send address, status: %x\n", 371 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 372 return(1); 373 } 374 /* 375 * Send second byte address of byte we want to read. 376 */ 377 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 378 printf("ti%d: failed to send address, status: %x\n", 379 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 380 return(1); 381 } 382 383 EEPROM_STOP; 384 EEPROM_START; 385 /* 386 * Send read control code to EEPROM. 387 */ 388 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 389 printf("ti%d: failed to send read command, status: %x\n", 390 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 391 return(1); 392 } 393 394 /* 395 * Start reading bits from EEPROM. 396 */ 397 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 398 for (i = 0x80; i; i >>= 1) { 399 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 400 DELAY(1); 401 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 402 byte |= i; 403 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 404 DELAY(1); 405 } 406 407 EEPROM_STOP; 408 409 /* 410 * No ACK generated for read, so just return byte. 411 */ 412 413 *dest = byte; 414 415 return(0); 416 } 417 418 /* 419 * Read a sequence of bytes from the EEPROM. 420 */ 421 static int 422 ti_read_eeprom(sc, dest, off, cnt) 423 struct ti_softc *sc; 424 caddr_t dest; 425 int off; 426 int cnt; 427 { 428 int err = 0, i; 429 u_int8_t byte = 0; 430 431 for (i = 0; i < cnt; i++) { 432 err = ti_eeprom_getbyte(sc, off + i, &byte); 433 if (err) 434 break; 435 *(dest + i) = byte; 436 } 437 438 return(err ? 1 : 0); 439 } 440 441 /* 442 * NIC memory access function. Can be used to either clear a section 443 * of NIC local memory or (if buf is non-NULL) copy data into it. 444 */ 445 static void 446 ti_mem(sc, addr, len, buf) 447 struct ti_softc *sc; 448 u_int32_t addr, len; 449 caddr_t buf; 450 { 451 int segptr, segsize, cnt; 452 caddr_t ti_winbase, ptr; 453 454 segptr = addr; 455 cnt = len; 456 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 457 ptr = buf; 458 459 while(cnt) { 460 if (cnt < TI_WINLEN) 461 segsize = cnt; 462 else 463 segsize = TI_WINLEN - (segptr % TI_WINLEN); 464 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 465 if (buf == NULL) 466 bzero((char *)ti_winbase + (segptr & 467 (TI_WINLEN - 1)), segsize); 468 else { 469 bcopy((char *)ptr, (char *)ti_winbase + 470 (segptr & (TI_WINLEN - 1)), segsize); 471 ptr += segsize; 472 } 473 segptr += segsize; 474 cnt -= segsize; 475 } 476 477 return; 478 } 479 480 static int 481 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 482 struct ti_softc *sc; 483 u_int32_t tigon_addr, len; 484 caddr_t buf; 485 int useraddr, readdata; 486 { 487 int segptr, segsize, cnt; 488 caddr_t ptr; 489 u_int32_t origwin; 490 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 491 int resid, segresid; 492 int first_pass; 493 494 /* 495 * At the moment, we don't handle non-aligned cases, we just bail. 496 * If this proves to be a problem, it will be fixed. 497 */ 498 if ((readdata == 0) 499 && (tigon_addr & 0x3)) { 500 printf("ti%d: ti_copy_mem: tigon address %#x isn't " 501 "word-aligned\n", sc->ti_unit, tigon_addr); 502 printf("ti%d: ti_copy_mem: unaligned writes aren't yet " 503 "supported\n", sc->ti_unit); 504 return(EINVAL); 505 } 506 507 segptr = tigon_addr & ~0x3; 508 segresid = tigon_addr - segptr; 509 510 /* 511 * This is the non-aligned amount left over that we'll need to 512 * copy. 513 */ 514 resid = len & 0x3; 515 516 /* Add in the left over amount at the front of the buffer */ 517 resid += segresid; 518 519 cnt = len & ~0x3; 520 /* 521 * If resid + segresid is >= 4, add multiples of 4 to the count and 522 * decrease the residual by that much. 523 */ 524 cnt += resid & ~0x3; 525 resid -= resid & ~0x3; 526 527 ptr = buf; 528 529 first_pass = 1; 530 531 /* 532 * Make sure we aren't interrupted while we're changing the window 533 * pointer. 534 */ 535 TI_LOCK(sc); 536 537 /* 538 * Save the old window base value. 539 */ 540 origwin = CSR_READ_4(sc, TI_WINBASE); 541 542 while(cnt) { 543 bus_size_t ti_offset; 544 545 if (cnt < TI_WINLEN) 546 segsize = cnt; 547 else 548 segsize = TI_WINLEN - (segptr % TI_WINLEN); 549 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 550 551 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 552 553 if (readdata) { 554 555 bus_space_read_region_4(sc->ti_btag, 556 sc->ti_bhandle, ti_offset, 557 (u_int32_t *)tmparray, 558 segsize >> 2); 559 if (useraddr) { 560 /* 561 * Yeah, this is a little on the kludgy 562 * side, but at least this code is only 563 * used for debugging. 564 */ 565 ti_bcopy_swap(tmparray, tmparray2, segsize, 566 TI_SWAP_NTOH); 567 568 if (first_pass) { 569 copyout(&tmparray2[segresid], ptr, 570 segsize - segresid); 571 first_pass = 0; 572 } else 573 copyout(tmparray2, ptr, segsize); 574 } else { 575 if (first_pass) { 576 577 ti_bcopy_swap(tmparray, tmparray2, 578 segsize, TI_SWAP_NTOH); 579 bcopy(&tmparray2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 ti_bcopy_swap(tmparray, ptr, segsize, 584 TI_SWAP_NTOH); 585 } 586 587 } else { 588 if (useraddr) { 589 copyin(ptr, tmparray2, segsize); 590 ti_bcopy_swap(tmparray2, tmparray, segsize, 591 TI_SWAP_HTON); 592 } else 593 ti_bcopy_swap(ptr, tmparray, segsize, 594 TI_SWAP_HTON); 595 596 bus_space_write_region_4(sc->ti_btag, 597 sc->ti_bhandle, ti_offset, 598 (u_int32_t *)tmparray, 599 segsize >> 2); 600 } 601 segptr += segsize; 602 ptr += segsize; 603 cnt -= segsize; 604 } 605 606 /* 607 * Handle leftover, non-word-aligned bytes. 608 */ 609 if (resid != 0) { 610 u_int32_t tmpval, tmpval2; 611 bus_size_t ti_offset; 612 613 /* 614 * Set the segment pointer. 615 */ 616 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 617 618 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 619 620 /* 621 * First, grab whatever is in our source/destination. 622 * We'll obviously need this for reads, but also for 623 * writes, since we'll be doing read/modify/write. 624 */ 625 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 626 ti_offset, &tmpval, 1); 627 628 /* 629 * Next, translate this from little-endian to big-endian 630 * (at least on i386 boxes). 631 */ 632 tmpval2 = ntohl(tmpval); 633 634 if (readdata) { 635 /* 636 * If we're reading, just copy the leftover number 637 * of bytes from the host byte order buffer to 638 * the user's buffer. 639 */ 640 if (useraddr) 641 copyout(&tmpval2, ptr, resid); 642 else 643 bcopy(&tmpval2, ptr, resid); 644 } else { 645 /* 646 * If we're writing, first copy the bytes to be 647 * written into the network byte order buffer, 648 * leaving the rest of the buffer with whatever was 649 * originally in there. Then, swap the bytes 650 * around into host order and write them out. 651 * 652 * XXX KDM the read side of this has been verified 653 * to work, but the write side of it has not been 654 * verified. So user beware. 655 */ 656 if (useraddr) 657 copyin(ptr, &tmpval2, resid); 658 else 659 bcopy(ptr, &tmpval2, resid); 660 661 tmpval = htonl(tmpval2); 662 663 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 664 ti_offset, &tmpval, 1); 665 } 666 } 667 668 CSR_WRITE_4(sc, TI_WINBASE, origwin); 669 670 TI_UNLOCK(sc); 671 672 return(0); 673 } 674 675 static int 676 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 677 struct ti_softc *sc; 678 u_int32_t tigon_addr, len; 679 caddr_t buf; 680 int useraddr, readdata; 681 int cpu; 682 { 683 u_int32_t segptr; 684 int cnt; 685 u_int32_t tmpval, tmpval2; 686 caddr_t ptr; 687 688 /* 689 * At the moment, we don't handle non-aligned cases, we just bail. 690 * If this proves to be a problem, it will be fixed. 691 */ 692 if (tigon_addr & 0x3) { 693 printf("ti%d: ti_copy_scratch: tigon address %#x isn't " 694 "word-aligned\n", sc->ti_unit, tigon_addr); 695 return(EINVAL); 696 } 697 698 if (len & 0x3) { 699 printf("ti%d: ti_copy_scratch: transfer length %d isn't " 700 "word-aligned\n", sc->ti_unit, len); 701 return(EINVAL); 702 } 703 704 segptr = tigon_addr; 705 cnt = len; 706 ptr = buf; 707 708 TI_LOCK(sc); 709 710 while (cnt) { 711 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 712 713 if (readdata) { 714 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 715 716 tmpval = ntohl(tmpval2); 717 718 /* 719 * Note: I've used this debugging interface 720 * extensively with Alteon's 12.3.15 firmware, 721 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 722 * 723 * When you compile the firmware without 724 * optimization, which is necessary sometimes in 725 * order to properly step through it, you sometimes 726 * read out a bogus value of 0xc0017c instead of 727 * whatever was supposed to be in that scratchpad 728 * location. That value is on the stack somewhere, 729 * but I've never been able to figure out what was 730 * causing the problem. 731 * 732 * The address seems to pop up in random places, 733 * often not in the same place on two subsequent 734 * reads. 735 * 736 * In any case, the underlying data doesn't seem 737 * to be affected, just the value read out. 738 * 739 * KDM, 3/7/2000 740 */ 741 742 if (tmpval2 == 0xc0017c) 743 printf("ti%d: found 0xc0017c at %#x " 744 "(tmpval2)\n", sc->ti_unit, segptr); 745 746 if (tmpval == 0xc0017c) 747 printf("ti%d: found 0xc0017c at %#x " 748 "(tmpval)\n", sc->ti_unit, segptr); 749 750 if (useraddr) 751 copyout(&tmpval, ptr, 4); 752 else 753 bcopy(&tmpval, ptr, 4); 754 } else { 755 if (useraddr) 756 copyin(ptr, &tmpval2, 4); 757 else 758 bcopy(ptr, &tmpval2, 4); 759 760 tmpval = htonl(tmpval2); 761 762 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 763 } 764 765 cnt -= 4; 766 segptr += 4; 767 ptr += 4; 768 } 769 770 TI_UNLOCK(sc); 771 772 return(0); 773 } 774 775 static int 776 ti_bcopy_swap(src, dst, len, swap_type) 777 const void *src; 778 void *dst; 779 size_t len; 780 ti_swap_type swap_type; 781 { 782 const u_int8_t *tmpsrc; 783 u_int8_t *tmpdst; 784 size_t tmplen; 785 786 if (len & 0x3) { 787 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 788 len); 789 return(-1); 790 } 791 792 tmpsrc = src; 793 tmpdst = dst; 794 tmplen = len; 795 796 while (tmplen) { 797 if (swap_type == TI_SWAP_NTOH) 798 *(u_int32_t *)tmpdst = 799 ntohl(*(const u_int32_t *)tmpsrc); 800 else 801 *(u_int32_t *)tmpdst = 802 htonl(*(const u_int32_t *)tmpsrc); 803 804 tmpsrc += 4; 805 tmpdst += 4; 806 tmplen -= 4; 807 } 808 809 return(0); 810 } 811 812 /* 813 * Load firmware image into the NIC. Check that the firmware revision 814 * is acceptable and see if we want the firmware for the Tigon 1 or 815 * Tigon 2. 816 */ 817 static void 818 ti_loadfw(sc) 819 struct ti_softc *sc; 820 { 821 switch(sc->ti_hwrev) { 822 case TI_HWREV_TIGON: 823 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 824 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 825 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 826 printf("ti%d: firmware revision mismatch; want " 827 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 828 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 829 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 830 tigonFwReleaseMinor, tigonFwReleaseFix); 831 return; 832 } 833 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 834 (caddr_t)tigonFwText); 835 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 836 (caddr_t)tigonFwData); 837 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 838 (caddr_t)tigonFwRodata); 839 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 840 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 841 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 842 break; 843 case TI_HWREV_TIGON_II: 844 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 845 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 846 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 847 printf("ti%d: firmware revision mismatch; want " 848 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 849 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 850 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 851 tigon2FwReleaseMinor, tigon2FwReleaseFix); 852 return; 853 } 854 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 855 (caddr_t)tigon2FwText); 856 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 857 (caddr_t)tigon2FwData); 858 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 859 (caddr_t)tigon2FwRodata); 860 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 861 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 862 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 863 break; 864 default: 865 printf("ti%d: can't load firmware: unknown hardware rev\n", 866 sc->ti_unit); 867 break; 868 } 869 870 return; 871 } 872 873 /* 874 * Send the NIC a command via the command ring. 875 */ 876 static void 877 ti_cmd(sc, cmd) 878 struct ti_softc *sc; 879 struct ti_cmd_desc *cmd; 880 { 881 u_int32_t index; 882 883 if (sc->ti_rdata->ti_cmd_ring == NULL) 884 return; 885 886 index = sc->ti_cmd_saved_prodidx; 887 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 888 TI_INC(index, TI_CMD_RING_CNT); 889 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 890 sc->ti_cmd_saved_prodidx = index; 891 892 return; 893 } 894 895 /* 896 * Send the NIC an extended command. The 'len' parameter specifies the 897 * number of command slots to include after the initial command. 898 */ 899 static void 900 ti_cmd_ext(sc, cmd, arg, len) 901 struct ti_softc *sc; 902 struct ti_cmd_desc *cmd; 903 caddr_t arg; 904 int len; 905 { 906 u_int32_t index; 907 register int i; 908 909 if (sc->ti_rdata->ti_cmd_ring == NULL) 910 return; 911 912 index = sc->ti_cmd_saved_prodidx; 913 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 914 TI_INC(index, TI_CMD_RING_CNT); 915 for (i = 0; i < len; i++) { 916 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 917 *(u_int32_t *)(&arg[i * 4])); 918 TI_INC(index, TI_CMD_RING_CNT); 919 } 920 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 921 sc->ti_cmd_saved_prodidx = index; 922 923 return; 924 } 925 926 /* 927 * Handle events that have triggered interrupts. 928 */ 929 static void 930 ti_handle_events(sc) 931 struct ti_softc *sc; 932 { 933 struct ti_event_desc *e; 934 935 if (sc->ti_rdata->ti_event_ring == NULL) 936 return; 937 938 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 939 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 940 switch(e->ti_event) { 941 case TI_EV_LINKSTAT_CHANGED: 942 sc->ti_linkstat = e->ti_code; 943 if (e->ti_code == TI_EV_CODE_LINK_UP) 944 printf("ti%d: 10/100 link up\n", sc->ti_unit); 945 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 946 printf("ti%d: gigabit link up\n", sc->ti_unit); 947 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 948 printf("ti%d: link down\n", sc->ti_unit); 949 break; 950 case TI_EV_ERROR: 951 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 952 printf("ti%d: invalid command\n", sc->ti_unit); 953 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 954 printf("ti%d: unknown command\n", sc->ti_unit); 955 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 956 printf("ti%d: bad config data\n", sc->ti_unit); 957 break; 958 case TI_EV_FIRMWARE_UP: 959 ti_init2(sc); 960 break; 961 case TI_EV_STATS_UPDATED: 962 ti_stats_update(sc); 963 break; 964 case TI_EV_RESET_JUMBO_RING: 965 case TI_EV_MCAST_UPDATED: 966 /* Who cares. */ 967 break; 968 default: 969 printf("ti%d: unknown event: %d\n", 970 sc->ti_unit, e->ti_event); 971 break; 972 } 973 /* Advance the consumer index. */ 974 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 975 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 976 } 977 978 return; 979 } 980 981 #ifdef TI_PRIVATE_JUMBOS 982 983 /* 984 * Memory management for the jumbo receive ring is a pain in the 985 * butt. We need to allocate at least 9018 bytes of space per frame, 986 * _and_ it has to be contiguous (unless you use the extended 987 * jumbo descriptor format). Using malloc() all the time won't 988 * work: malloc() allocates memory in powers of two, which means we 989 * would end up wasting a considerable amount of space by allocating 990 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 991 * to do our own memory management. 992 * 993 * The driver needs to allocate a contiguous chunk of memory at boot 994 * time. We then chop this up ourselves into 9K pieces and use them 995 * as external mbuf storage. 996 * 997 * One issue here is how much memory to allocate. The jumbo ring has 998 * 256 slots in it, but at 9K per slot than can consume over 2MB of 999 * RAM. This is a bit much, especially considering we also need 1000 * RAM for the standard ring and mini ring (on the Tigon 2). To 1001 * save space, we only actually allocate enough memory for 64 slots 1002 * by default, which works out to between 500 and 600K. This can 1003 * be tuned by changing a #define in if_tireg.h. 1004 */ 1005 1006 static int 1007 ti_alloc_jumbo_mem(sc) 1008 struct ti_softc *sc; 1009 { 1010 caddr_t ptr; 1011 register int i; 1012 struct ti_jpool_entry *entry; 1013 1014 /* Grab a big chunk o' storage. */ 1015 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 1016 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1017 1018 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 1019 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 1020 return(ENOBUFS); 1021 } 1022 1023 SLIST_INIT(&sc->ti_jfree_listhead); 1024 SLIST_INIT(&sc->ti_jinuse_listhead); 1025 1026 /* 1027 * Now divide it up into 9K pieces and save the addresses 1028 * in an array. 1029 */ 1030 ptr = sc->ti_cdata.ti_jumbo_buf; 1031 for (i = 0; i < TI_JSLOTS; i++) { 1032 sc->ti_cdata.ti_jslots[i] = ptr; 1033 ptr += TI_JLEN; 1034 entry = malloc(sizeof(struct ti_jpool_entry), 1035 M_DEVBUF, M_NOWAIT); 1036 if (entry == NULL) { 1037 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, 1038 M_DEVBUF); 1039 sc->ti_cdata.ti_jumbo_buf = NULL; 1040 printf("ti%d: no memory for jumbo " 1041 "buffer queue!\n", sc->ti_unit); 1042 return(ENOBUFS); 1043 } 1044 entry->slot = i; 1045 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1046 } 1047 1048 return(0); 1049 } 1050 1051 /* 1052 * Allocate a jumbo buffer. 1053 */ 1054 static void *ti_jalloc(sc) 1055 struct ti_softc *sc; 1056 { 1057 struct ti_jpool_entry *entry; 1058 1059 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1060 1061 if (entry == NULL) { 1062 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 1063 return(NULL); 1064 } 1065 1066 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1067 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1068 return(sc->ti_cdata.ti_jslots[entry->slot]); 1069 } 1070 1071 /* 1072 * Release a jumbo buffer. 1073 */ 1074 static void 1075 ti_jfree(buf, args) 1076 void *buf; 1077 void *args; 1078 { 1079 struct ti_softc *sc; 1080 int i; 1081 struct ti_jpool_entry *entry; 1082 1083 /* Extract the softc struct pointer. */ 1084 sc = (struct ti_softc *)args; 1085 1086 if (sc == NULL) 1087 panic("ti_jfree: didn't get softc pointer!"); 1088 1089 /* calculate the slot this buffer belongs to */ 1090 i = ((vm_offset_t)buf 1091 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1092 1093 if ((i < 0) || (i >= TI_JSLOTS)) 1094 panic("ti_jfree: asked to free buffer that we don't manage!"); 1095 1096 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1097 if (entry == NULL) 1098 panic("ti_jfree: buffer not in use!"); 1099 entry->slot = i; 1100 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1101 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1102 1103 return; 1104 } 1105 1106 #endif /* TI_PRIVATE_JUMBOS */ 1107 1108 /* 1109 * Intialize a standard receive ring descriptor. 1110 */ 1111 static int 1112 ti_newbuf_std(sc, i, m) 1113 struct ti_softc *sc; 1114 int i; 1115 struct mbuf *m; 1116 { 1117 struct mbuf *m_new = NULL; 1118 struct ti_rx_desc *r; 1119 1120 if (m == NULL) { 1121 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1122 if (m_new == NULL) 1123 return(ENOBUFS); 1124 1125 MCLGET(m_new, M_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 m_freem(m_new); 1128 return(ENOBUFS); 1129 } 1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1131 } else { 1132 m_new = m; 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 m_new->m_data = m_new->m_ext.ext_buf; 1135 } 1136 1137 m_adj(m_new, ETHER_ALIGN); 1138 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1139 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1140 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1141 r->ti_type = TI_BDTYPE_RECV_BD; 1142 r->ti_flags = 0; 1143 if (sc->arpcom.ac_if.if_hwassist) 1144 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1145 r->ti_len = m_new->m_len; 1146 r->ti_idx = i; 1147 1148 return(0); 1149 } 1150 1151 /* 1152 * Intialize a mini receive ring descriptor. This only applies to 1153 * the Tigon 2. 1154 */ 1155 static int 1156 ti_newbuf_mini(sc, i, m) 1157 struct ti_softc *sc; 1158 int i; 1159 struct mbuf *m; 1160 { 1161 struct mbuf *m_new = NULL; 1162 struct ti_rx_desc *r; 1163 1164 if (m == NULL) { 1165 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1166 if (m_new == NULL) { 1167 return(ENOBUFS); 1168 } 1169 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1170 } else { 1171 m_new = m; 1172 m_new->m_data = m_new->m_pktdat; 1173 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1174 } 1175 1176 m_adj(m_new, ETHER_ALIGN); 1177 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1178 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1179 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1180 r->ti_type = TI_BDTYPE_RECV_BD; 1181 r->ti_flags = TI_BDFLAG_MINI_RING; 1182 if (sc->arpcom.ac_if.if_hwassist) 1183 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1184 r->ti_len = m_new->m_len; 1185 r->ti_idx = i; 1186 1187 return(0); 1188 } 1189 1190 #ifdef TI_PRIVATE_JUMBOS 1191 1192 /* 1193 * Initialize a jumbo receive ring descriptor. This allocates 1194 * a jumbo buffer from the pool managed internally by the driver. 1195 */ 1196 static int 1197 ti_newbuf_jumbo(sc, i, m) 1198 struct ti_softc *sc; 1199 int i; 1200 struct mbuf *m; 1201 { 1202 struct mbuf *m_new = NULL; 1203 struct ti_rx_desc *r; 1204 1205 if (m == NULL) { 1206 caddr_t *buf = NULL; 1207 1208 /* Allocate the mbuf. */ 1209 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1210 if (m_new == NULL) { 1211 return(ENOBUFS); 1212 } 1213 1214 /* Allocate the jumbo buffer */ 1215 buf = ti_jalloc(sc); 1216 if (buf == NULL) { 1217 m_freem(m_new); 1218 printf("ti%d: jumbo allocation failed " 1219 "-- packet dropped!\n", sc->ti_unit); 1220 return(ENOBUFS); 1221 } 1222 1223 /* Attach the buffer to the mbuf. */ 1224 m_new->m_data = (void *) buf; 1225 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1226 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1227 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1228 } else { 1229 m_new = m; 1230 m_new->m_data = m_new->m_ext.ext_buf; 1231 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1232 } 1233 1234 m_adj(m_new, ETHER_ALIGN); 1235 /* Set up the descriptor. */ 1236 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1237 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1238 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 1239 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1240 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1241 if (sc->arpcom.ac_if.if_hwassist) 1242 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1243 r->ti_len = m_new->m_len; 1244 r->ti_idx = i; 1245 1246 return(0); 1247 } 1248 1249 #else 1250 #include <vm/vm_page.h> 1251 1252 #if (PAGE_SIZE == 4096) 1253 #define NPAYLOAD 2 1254 #else 1255 #define NPAYLOAD 1 1256 #endif 1257 1258 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1259 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1260 #define NFS_HDR_LEN (UDP_HDR_LEN) 1261 static int HDR_LEN = TCP_HDR_LEN; 1262 1263 1264 /* 1265 * Initialize a jumbo receive ring descriptor. This allocates 1266 * a jumbo buffer from the pool managed internally by the driver. 1267 */ 1268 static int 1269 ti_newbuf_jumbo(sc, idx, m_old) 1270 struct ti_softc *sc; 1271 int idx; 1272 struct mbuf *m_old; 1273 { 1274 struct mbuf *cur, *m_new = NULL; 1275 struct mbuf *m[3] = {NULL, NULL, NULL}; 1276 struct ti_rx_desc_ext *r; 1277 vm_page_t frame; 1278 /* 1 extra buf to make nobufs easy*/ 1279 caddr_t buf[3] = {NULL, NULL, NULL}; 1280 int i; 1281 1282 if (m_old != NULL) { 1283 m_new = m_old; 1284 cur = m_old->m_next; 1285 for (i = 0; i <= NPAYLOAD; i++){ 1286 m[i] = cur; 1287 cur = cur->m_next; 1288 } 1289 } else { 1290 /* Allocate the mbufs. */ 1291 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1292 if (m_new == NULL) { 1293 printf("ti%d: mbuf allocation failed " 1294 "-- packet dropped!\n", sc->ti_unit); 1295 goto nobufs; 1296 } 1297 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1298 if (m[NPAYLOAD] == NULL) { 1299 printf("ti%d: cluster mbuf allocation failed " 1300 "-- packet dropped!\n", sc->ti_unit); 1301 goto nobufs; 1302 } 1303 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1304 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1305 printf("ti%d: mbuf allocation failed " 1306 "-- packet dropped!\n", sc->ti_unit); 1307 goto nobufs; 1308 } 1309 m[NPAYLOAD]->m_len = MCLBYTES; 1310 1311 for (i = 0; i < NPAYLOAD; i++){ 1312 MGET(m[i], M_DONTWAIT, MT_DATA); 1313 if (m[i] == NULL) { 1314 printf("ti%d: mbuf allocation failed " 1315 "-- packet dropped!\n", sc->ti_unit); 1316 goto nobufs; 1317 } 1318 if (!(frame = jumbo_pg_alloc())){ 1319 printf("ti%d: buffer allocation failed " 1320 "-- packet dropped!\n", sc->ti_unit); 1321 printf(" index %d page %d\n", idx, i); 1322 goto nobufs; 1323 } 1324 buf[i] = jumbo_phys_to_kva(VM_PAGE_TO_PHYS(frame)); 1325 } 1326 for (i = 0; i < NPAYLOAD; i++){ 1327 /* Attach the buffer to the mbuf. */ 1328 m[i]->m_data = (void *)buf[i]; 1329 m[i]->m_len = PAGE_SIZE; 1330 MEXTADD(m[i], (void *)buf[i], PAGE_SIZE, 1331 jumbo_freem, NULL, 0, EXT_DISPOSABLE); 1332 m[i]->m_next = m[i+1]; 1333 } 1334 /* link the buffers to the header */ 1335 m_new->m_next = m[0]; 1336 m_new->m_data += ETHER_ALIGN; 1337 if (sc->ti_hdrsplit) 1338 m_new->m_len = MHLEN - ETHER_ALIGN; 1339 else 1340 m_new->m_len = HDR_LEN; 1341 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1342 } 1343 1344 /* Set up the descriptor. */ 1345 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1346 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1347 TI_HOSTADDR(r->ti_addr0) = vtophys(mtod(m_new, caddr_t)); 1348 r->ti_len0 = m_new->m_len; 1349 1350 TI_HOSTADDR(r->ti_addr1) = vtophys(mtod(m[0], caddr_t)); 1351 r->ti_len1 = PAGE_SIZE; 1352 1353 TI_HOSTADDR(r->ti_addr2) = vtophys(mtod(m[1], caddr_t)); 1354 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1355 1356 if (PAGE_SIZE == 4096) { 1357 TI_HOSTADDR(r->ti_addr3) = vtophys(mtod(m[2], caddr_t)); 1358 r->ti_len3 = MCLBYTES; 1359 } else { 1360 r->ti_len3 = 0; 1361 } 1362 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1363 1364 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1365 1366 if (sc->arpcom.ac_if.if_hwassist) 1367 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1368 1369 r->ti_idx = idx; 1370 1371 return(0); 1372 1373 nobufs: 1374 1375 /* 1376 * Warning! : 1377 * This can only be called before the mbufs are strung together. 1378 * If the mbufs are strung together, m_freem() will free the chain, 1379 * so that the later mbufs will be freed multiple times. 1380 */ 1381 if (m_new) 1382 m_freem(m_new); 1383 1384 for(i = 0; i < 3; i++){ 1385 if (m[i]) 1386 m_freem(m[i]); 1387 if (buf[i]) 1388 jumbo_pg_free((vm_offset_t)buf[i]); 1389 } 1390 return ENOBUFS; 1391 } 1392 #endif 1393 1394 1395 1396 /* 1397 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1398 * that's 1MB or memory, which is a lot. For now, we fill only the first 1399 * 256 ring entries and hope that our CPU is fast enough to keep up with 1400 * the NIC. 1401 */ 1402 static int 1403 ti_init_rx_ring_std(sc) 1404 struct ti_softc *sc; 1405 { 1406 register int i; 1407 struct ti_cmd_desc cmd; 1408 1409 for (i = 0; i < TI_SSLOTS; i++) { 1410 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1411 return(ENOBUFS); 1412 }; 1413 1414 TI_UPDATE_STDPROD(sc, i - 1); 1415 sc->ti_std = i - 1; 1416 1417 return(0); 1418 } 1419 1420 static void 1421 ti_free_rx_ring_std(sc) 1422 struct ti_softc *sc; 1423 { 1424 register int i; 1425 1426 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1427 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1428 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1429 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1430 } 1431 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1432 sizeof(struct ti_rx_desc)); 1433 } 1434 1435 return; 1436 } 1437 1438 static int 1439 ti_init_rx_ring_jumbo(sc) 1440 struct ti_softc *sc; 1441 { 1442 register int i; 1443 struct ti_cmd_desc cmd; 1444 1445 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1446 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1447 return(ENOBUFS); 1448 }; 1449 1450 TI_UPDATE_JUMBOPROD(sc, i - 1); 1451 sc->ti_jumbo = i - 1; 1452 1453 return(0); 1454 } 1455 1456 static void 1457 ti_free_rx_ring_jumbo(sc) 1458 struct ti_softc *sc; 1459 { 1460 register int i; 1461 1462 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1463 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1464 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1465 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1466 } 1467 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1468 sizeof(struct ti_rx_desc)); 1469 } 1470 1471 return; 1472 } 1473 1474 static int 1475 ti_init_rx_ring_mini(sc) 1476 struct ti_softc *sc; 1477 { 1478 register int i; 1479 1480 for (i = 0; i < TI_MSLOTS; i++) { 1481 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1482 return(ENOBUFS); 1483 }; 1484 1485 TI_UPDATE_MINIPROD(sc, i - 1); 1486 sc->ti_mini = i - 1; 1487 1488 return(0); 1489 } 1490 1491 static void 1492 ti_free_rx_ring_mini(sc) 1493 struct ti_softc *sc; 1494 { 1495 register int i; 1496 1497 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1498 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1499 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1500 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1501 } 1502 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1503 sizeof(struct ti_rx_desc)); 1504 } 1505 1506 return; 1507 } 1508 1509 static void 1510 ti_free_tx_ring(sc) 1511 struct ti_softc *sc; 1512 { 1513 register int i; 1514 1515 if (sc->ti_rdata->ti_tx_ring == NULL) 1516 return; 1517 1518 for (i = 0; i < TI_TX_RING_CNT; i++) { 1519 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1520 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1521 sc->ti_cdata.ti_tx_chain[i] = NULL; 1522 } 1523 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1524 sizeof(struct ti_tx_desc)); 1525 } 1526 1527 return; 1528 } 1529 1530 static int 1531 ti_init_tx_ring(sc) 1532 struct ti_softc *sc; 1533 { 1534 sc->ti_txcnt = 0; 1535 sc->ti_tx_saved_considx = 0; 1536 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1537 return(0); 1538 } 1539 1540 /* 1541 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1542 * but we have to support the old way too so that Tigon 1 cards will 1543 * work. 1544 */ 1545 static void 1546 ti_add_mcast(sc, addr) 1547 struct ti_softc *sc; 1548 struct ether_addr *addr; 1549 { 1550 struct ti_cmd_desc cmd; 1551 u_int16_t *m; 1552 u_int32_t ext[2] = {0, 0}; 1553 1554 m = (u_int16_t *)&addr->octet[0]; 1555 1556 switch(sc->ti_hwrev) { 1557 case TI_HWREV_TIGON: 1558 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1559 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1560 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1561 break; 1562 case TI_HWREV_TIGON_II: 1563 ext[0] = htons(m[0]); 1564 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1565 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1566 break; 1567 default: 1568 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1569 break; 1570 } 1571 1572 return; 1573 } 1574 1575 static void 1576 ti_del_mcast(sc, addr) 1577 struct ti_softc *sc; 1578 struct ether_addr *addr; 1579 { 1580 struct ti_cmd_desc cmd; 1581 u_int16_t *m; 1582 u_int32_t ext[2] = {0, 0}; 1583 1584 m = (u_int16_t *)&addr->octet[0]; 1585 1586 switch(sc->ti_hwrev) { 1587 case TI_HWREV_TIGON: 1588 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1589 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1590 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1591 break; 1592 case TI_HWREV_TIGON_II: 1593 ext[0] = htons(m[0]); 1594 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1595 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1596 break; 1597 default: 1598 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1599 break; 1600 } 1601 1602 return; 1603 } 1604 1605 /* 1606 * Configure the Tigon's multicast address filter. 1607 * 1608 * The actual multicast table management is a bit of a pain, thanks to 1609 * slight brain damage on the part of both Alteon and us. With our 1610 * multicast code, we are only alerted when the multicast address table 1611 * changes and at that point we only have the current list of addresses: 1612 * we only know the current state, not the previous state, so we don't 1613 * actually know what addresses were removed or added. The firmware has 1614 * state, but we can't get our grubby mits on it, and there is no 'delete 1615 * all multicast addresses' command. Hence, we have to maintain our own 1616 * state so we know what addresses have been programmed into the NIC at 1617 * any given time. 1618 */ 1619 static void 1620 ti_setmulti(sc) 1621 struct ti_softc *sc; 1622 { 1623 struct ifnet *ifp; 1624 struct ifmultiaddr *ifma; 1625 struct ti_cmd_desc cmd; 1626 struct ti_mc_entry *mc; 1627 u_int32_t intrs; 1628 1629 ifp = &sc->arpcom.ac_if; 1630 1631 if (ifp->if_flags & IFF_ALLMULTI) { 1632 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1633 return; 1634 } else { 1635 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1636 } 1637 1638 /* Disable interrupts. */ 1639 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1640 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1641 1642 /* First, zot all the existing filters. */ 1643 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1644 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1645 ti_del_mcast(sc, &mc->mc_addr); 1646 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1647 free(mc, M_DEVBUF); 1648 } 1649 1650 /* Now program new ones. */ 1651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1652 if (ifma->ifma_addr->sa_family != AF_LINK) 1653 continue; 1654 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1655 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1656 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1657 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1658 ti_add_mcast(sc, &mc->mc_addr); 1659 } 1660 1661 /* Re-enable interrupts. */ 1662 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1663 1664 return; 1665 } 1666 1667 /* 1668 * Check to see if the BIOS has configured us for a 64 bit slot when 1669 * we aren't actually in one. If we detect this condition, we can work 1670 * around it on the Tigon 2 by setting a bit in the PCI state register, 1671 * but for the Tigon 1 we must give up and abort the interface attach. 1672 */ 1673 static int ti_64bitslot_war(sc) 1674 struct ti_softc *sc; 1675 { 1676 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1677 CSR_WRITE_4(sc, 0x600, 0); 1678 CSR_WRITE_4(sc, 0x604, 0); 1679 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1680 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1681 if (sc->ti_hwrev == TI_HWREV_TIGON) 1682 return(EINVAL); 1683 else { 1684 TI_SETBIT(sc, TI_PCI_STATE, 1685 TI_PCISTATE_32BIT_BUS); 1686 return(0); 1687 } 1688 } 1689 } 1690 1691 return(0); 1692 } 1693 1694 /* 1695 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1696 * self-test results. 1697 */ 1698 static int 1699 ti_chipinit(sc) 1700 struct ti_softc *sc; 1701 { 1702 u_int32_t cacheline; 1703 u_int32_t pci_writemax = 0; 1704 u_int32_t hdrsplit; 1705 1706 /* Initialize link to down state. */ 1707 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1708 1709 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM) 1710 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1711 else 1712 sc->arpcom.ac_if.if_hwassist = 0; 1713 1714 /* Set endianness before we access any non-PCI registers. */ 1715 #if BYTE_ORDER == BIG_ENDIAN 1716 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1717 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1718 #else 1719 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1720 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1721 #endif 1722 1723 /* Check the ROM failed bit to see if self-tests passed. */ 1724 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1725 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1726 return(ENODEV); 1727 } 1728 1729 /* Halt the CPU. */ 1730 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1731 1732 /* Figure out the hardware revision. */ 1733 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1734 case TI_REV_TIGON_I: 1735 sc->ti_hwrev = TI_HWREV_TIGON; 1736 break; 1737 case TI_REV_TIGON_II: 1738 sc->ti_hwrev = TI_HWREV_TIGON_II; 1739 break; 1740 default: 1741 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1742 return(ENODEV); 1743 } 1744 1745 /* Do special setup for Tigon 2. */ 1746 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1747 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1748 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1749 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1750 } 1751 1752 /* 1753 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1754 * can't do header splitting. 1755 */ 1756 #ifdef TI_JUMBO_HDRSPLIT 1757 if (sc->ti_hwrev != TI_HWREV_TIGON) 1758 sc->ti_hdrsplit = 1; 1759 else 1760 printf("ti%d: can't do header splitting on a Tigon I board\n", 1761 sc->ti_unit); 1762 #endif /* TI_JUMBO_HDRSPLIT */ 1763 1764 /* Set up the PCI state register. */ 1765 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1766 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1767 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1768 } 1769 1770 /* Clear the read/write max DMA parameters. */ 1771 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1772 TI_PCISTATE_READ_MAXDMA)); 1773 1774 /* Get cache line size. */ 1775 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1776 1777 /* 1778 * If the system has set enabled the PCI memory write 1779 * and invalidate command in the command register, set 1780 * the write max parameter accordingly. This is necessary 1781 * to use MWI with the Tigon 2. 1782 */ 1783 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1784 switch(cacheline) { 1785 case 1: 1786 case 4: 1787 case 8: 1788 case 16: 1789 case 32: 1790 case 64: 1791 break; 1792 default: 1793 /* Disable PCI memory write and invalidate. */ 1794 if (bootverbose) 1795 printf("ti%d: cache line size %d not " 1796 "supported; disabling PCI MWI\n", 1797 sc->ti_unit, cacheline); 1798 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1799 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1800 break; 1801 } 1802 } 1803 1804 #ifdef __brokenalpha__ 1805 /* 1806 * From the Alteon sample driver: 1807 * Must insure that we do not cross an 8K (bytes) boundary 1808 * for DMA reads. Our highest limit is 1K bytes. This is a 1809 * restriction on some ALPHA platforms with early revision 1810 * 21174 PCI chipsets, such as the AlphaPC 164lx 1811 */ 1812 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1813 #else 1814 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1815 #endif 1816 1817 /* This sets the min dma param all the way up (0xff). */ 1818 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1819 1820 if (sc->ti_hdrsplit) 1821 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 1822 else 1823 hdrsplit = 0; 1824 1825 /* Configure DMA variables. */ 1826 #if BYTE_ORDER == BIG_ENDIAN 1827 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1828 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1829 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1830 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 1831 #else /* BYTE_ORDER */ 1832 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1833 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1834 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 1835 #endif /* BYTE_ORDER */ 1836 1837 /* 1838 * Only allow 1 DMA channel to be active at a time. 1839 * I don't think this is a good idea, but without it 1840 * the firmware racks up lots of nicDmaReadRingFull 1841 * errors. This is not compatible with hardware checksums. 1842 */ 1843 if (sc->arpcom.ac_if.if_hwassist == 0) 1844 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1845 1846 /* Recommended settings from Tigon manual. */ 1847 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1848 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1849 1850 if (ti_64bitslot_war(sc)) { 1851 printf("ti%d: bios thinks we're in a 64 bit slot, " 1852 "but we aren't", sc->ti_unit); 1853 return(EINVAL); 1854 } 1855 1856 return(0); 1857 } 1858 1859 /* 1860 * Initialize the general information block and firmware, and 1861 * start the CPU(s) running. 1862 */ 1863 static int 1864 ti_gibinit(sc) 1865 struct ti_softc *sc; 1866 { 1867 struct ti_rcb *rcb; 1868 int i; 1869 struct ifnet *ifp; 1870 1871 ifp = &sc->arpcom.ac_if; 1872 1873 /* Disable interrupts for now. */ 1874 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1875 1876 /* Tell the chip where to find the general information block. */ 1877 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1878 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1879 1880 /* Load the firmware into SRAM. */ 1881 ti_loadfw(sc); 1882 1883 /* Set up the contents of the general info and ring control blocks. */ 1884 1885 /* Set up the event ring and producer pointer. */ 1886 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1887 1888 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1889 rcb->ti_flags = 0; 1890 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1891 vtophys(&sc->ti_ev_prodidx); 1892 sc->ti_ev_prodidx.ti_idx = 0; 1893 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1894 sc->ti_ev_saved_considx = 0; 1895 1896 /* Set up the command ring and producer mailbox. */ 1897 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1898 1899 sc->ti_rdata->ti_cmd_ring = 1900 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1901 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1902 rcb->ti_flags = 0; 1903 rcb->ti_max_len = 0; 1904 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1905 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1906 } 1907 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1908 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1909 sc->ti_cmd_saved_prodidx = 0; 1910 1911 /* 1912 * Assign the address of the stats refresh buffer. 1913 * We re-use the current stats buffer for this to 1914 * conserve memory. 1915 */ 1916 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1917 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1918 1919 /* Set up the standard receive ring. */ 1920 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1921 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1922 rcb->ti_max_len = TI_FRAMELEN; 1923 rcb->ti_flags = 0; 1924 if (sc->arpcom.ac_if.if_hwassist) 1925 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1926 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1927 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1928 1929 /* Set up the jumbo receive ring. */ 1930 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1931 TI_HOSTADDR(rcb->ti_hostaddr) = 1932 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1933 1934 #ifdef TI_PRIVATE_JUMBOS 1935 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1936 rcb->ti_flags = 0; 1937 #else 1938 rcb->ti_max_len = PAGE_SIZE; 1939 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 1940 #endif 1941 if (sc->arpcom.ac_if.if_hwassist) 1942 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1943 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1944 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1945 1946 /* 1947 * Set up the mini ring. Only activated on the 1948 * Tigon 2 but the slot in the config block is 1949 * still there on the Tigon 1. 1950 */ 1951 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1952 TI_HOSTADDR(rcb->ti_hostaddr) = 1953 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1954 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1955 if (sc->ti_hwrev == TI_HWREV_TIGON) 1956 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1957 else 1958 rcb->ti_flags = 0; 1959 if (sc->arpcom.ac_if.if_hwassist) 1960 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1961 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1962 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1963 1964 /* 1965 * Set up the receive return ring. 1966 */ 1967 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1968 TI_HOSTADDR(rcb->ti_hostaddr) = 1969 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1970 rcb->ti_flags = 0; 1971 rcb->ti_max_len = TI_RETURN_RING_CNT; 1972 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1973 vtophys(&sc->ti_return_prodidx); 1974 1975 /* 1976 * Set up the tx ring. Note: for the Tigon 2, we have the option 1977 * of putting the transmit ring in the host's address space and 1978 * letting the chip DMA it instead of leaving the ring in the NIC's 1979 * memory and accessing it through the shared memory region. We 1980 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1981 * so we have to revert to the shared memory scheme if we detect 1982 * a Tigon 1 chip. 1983 */ 1984 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1985 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1986 sc->ti_rdata->ti_tx_ring_nic = 1987 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1988 } 1989 bzero((char *)sc->ti_rdata->ti_tx_ring, 1990 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1991 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1992 if (sc->ti_hwrev == TI_HWREV_TIGON) 1993 rcb->ti_flags = 0; 1994 else 1995 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1996 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1997 if (sc->arpcom.ac_if.if_hwassist) 1998 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1999 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2000 rcb->ti_max_len = TI_TX_RING_CNT; 2001 if (sc->ti_hwrev == TI_HWREV_TIGON) 2002 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2003 else 2004 TI_HOSTADDR(rcb->ti_hostaddr) = 2005 vtophys(&sc->ti_rdata->ti_tx_ring); 2006 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2007 vtophys(&sc->ti_tx_considx); 2008 2009 /* Set up tuneables */ 2010 #if 0 2011 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2012 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2013 (sc->ti_rx_coal_ticks / 10)); 2014 else 2015 #endif 2016 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2017 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2018 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2019 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2020 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2021 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2022 2023 /* Turn interrupts on. */ 2024 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2025 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2026 2027 /* Start CPU. */ 2028 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2029 2030 return(0); 2031 } 2032 2033 /* 2034 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2035 * against our list and return its name if we find a match. 2036 */ 2037 static int 2038 ti_probe(dev) 2039 device_t dev; 2040 { 2041 struct ti_type *t; 2042 2043 t = ti_devs; 2044 2045 while(t->ti_name != NULL) { 2046 if ((pci_get_vendor(dev) == t->ti_vid) && 2047 (pci_get_device(dev) == t->ti_did)) { 2048 device_set_desc(dev, t->ti_name); 2049 return(0); 2050 } 2051 t++; 2052 } 2053 2054 return(ENXIO); 2055 } 2056 2057 #ifdef KLD_MODULE 2058 static int 2059 log2rndup(int len) 2060 { 2061 int log2size = 0, t = len; 2062 while (t > 1) { 2063 log2size++; 2064 t >>= 1; 2065 } 2066 if (len != (1 << log2size)) 2067 log2size++; 2068 return log2size; 2069 } 2070 2071 static int 2072 ti_mbuf_sanity(device_t dev) 2073 { 2074 if ((mbstat.m_msize != MSIZE) || mbstat.m_mclbytes != MCLBYTES){ 2075 device_printf(dev, "\n"); 2076 device_printf(dev, "This module was compiled with " 2077 "-DMCLSHIFT=%d -DMSIZE=%d\n", MCLSHIFT, 2078 MSIZE); 2079 device_printf(dev, "The kernel was compiled with MCLSHIFT=%d," 2080 " MSIZE=%d\n", log2rndup(mbstat.m_mclbytes), 2081 (int)mbstat.m_msize); 2082 return(EINVAL); 2083 } 2084 return(0); 2085 } 2086 #endif 2087 2088 2089 static int 2090 ti_attach(dev) 2091 device_t dev; 2092 { 2093 u_int32_t command; 2094 struct ifnet *ifp; 2095 struct ti_softc *sc; 2096 int unit, error = 0, rid; 2097 2098 sc = NULL; 2099 2100 #ifdef KLD_MODULE 2101 if (ti_mbuf_sanity(dev)){ 2102 device_printf(dev, "Module mbuf constants do not match " 2103 "kernel constants!\n"); 2104 device_printf(dev, "Rebuild the module or the kernel so " 2105 "they match\n"); 2106 device_printf(dev, "\n"); 2107 error = EINVAL; 2108 goto fail; 2109 } 2110 #endif 2111 2112 sc = device_get_softc(dev); 2113 unit = device_get_unit(dev); 2114 2115 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2116 MTX_DEF | MTX_RECURSE); 2117 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 2118 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities; 2119 2120 /* 2121 * Map control/status registers. 2122 */ 2123 pci_enable_busmaster(dev); 2124 pci_enable_io(dev, SYS_RES_MEMORY); 2125 command = pci_read_config(dev, PCIR_COMMAND, 4); 2126 2127 if (!(command & PCIM_CMD_MEMEN)) { 2128 printf("ti%d: failed to enable memory mapping!\n", unit); 2129 error = ENXIO; 2130 goto fail; 2131 } 2132 2133 rid = TI_PCI_LOMEM; 2134 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2135 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2136 2137 if (sc->ti_res == NULL) { 2138 printf ("ti%d: couldn't map memory\n", unit); 2139 error = ENXIO; 2140 goto fail; 2141 } 2142 2143 sc->ti_btag = rman_get_bustag(sc->ti_res); 2144 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2145 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 2146 2147 /* Allocate interrupt */ 2148 rid = 0; 2149 2150 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2151 RF_SHAREABLE | RF_ACTIVE); 2152 2153 if (sc->ti_irq == NULL) { 2154 printf("ti%d: couldn't map interrupt\n", unit); 2155 error = ENXIO; 2156 goto fail; 2157 } 2158 2159 sc->ti_unit = unit; 2160 2161 if (ti_chipinit(sc)) { 2162 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2163 error = ENXIO; 2164 goto fail; 2165 } 2166 2167 /* Zero out the NIC's on-board SRAM. */ 2168 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2169 2170 /* Init again -- zeroing memory may have clobbered some registers. */ 2171 if (ti_chipinit(sc)) { 2172 printf("ti%d: chip initialization failed\n", sc->ti_unit); 2173 error = ENXIO; 2174 goto fail; 2175 } 2176 2177 /* 2178 * Get station address from the EEPROM. Note: the manual states 2179 * that the MAC address is at offset 0x8c, however the data is 2180 * stored as two longwords (since that's how it's loaded into 2181 * the NIC). This means the MAC address is actually preceded 2182 * by two zero bytes. We need to skip over those. 2183 */ 2184 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2185 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2186 printf("ti%d: failed to read station address\n", unit); 2187 error = ENXIO; 2188 goto fail; 2189 } 2190 2191 /* 2192 * A Tigon chip was detected. Inform the world. 2193 */ 2194 printf("ti%d: Ethernet address: %6D\n", unit, 2195 sc->arpcom.ac_enaddr, ":"); 2196 2197 /* Allocate the general information block and ring buffers. */ 2198 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 2199 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2200 2201 if (sc->ti_rdata == NULL) { 2202 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 2203 error = ENXIO; 2204 goto fail; 2205 } 2206 2207 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2208 2209 /* Try to allocate memory for jumbo buffers. */ 2210 #ifdef TI_PRIVATE_JUMBOS 2211 if (ti_alloc_jumbo_mem(sc)) { 2212 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 2213 error = ENXIO; 2214 goto fail; 2215 } 2216 #else 2217 if (!jumbo_vm_init()) { 2218 printf("ti%d: VM initialization failed!\n", sc->ti_unit); 2219 error = ENOMEM; 2220 goto fail; 2221 } 2222 #endif 2223 2224 /* 2225 * We really need a better way to tell a 1000baseTX card 2226 * from a 1000baseSX one, since in theory there could be 2227 * OEMed 1000baseTX cards from lame vendors who aren't 2228 * clever enough to change the PCI ID. For the moment 2229 * though, the AceNIC is the only copper card available. 2230 */ 2231 if (pci_get_vendor(dev) == ALT_VENDORID && 2232 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2233 sc->ti_copper = 1; 2234 /* Ok, it's not the only copper card available. */ 2235 if (pci_get_vendor(dev) == NG_VENDORID && 2236 pci_get_device(dev) == NG_DEVICEID_GA620T) 2237 sc->ti_copper = 1; 2238 2239 /* Set default tuneable values. */ 2240 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2241 #if 0 2242 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2243 #endif 2244 sc->ti_rx_coal_ticks = 170; 2245 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2246 sc->ti_rx_max_coal_bds = 64; 2247 #if 0 2248 sc->ti_tx_max_coal_bds = 128; 2249 #endif 2250 sc->ti_tx_max_coal_bds = 32; 2251 sc->ti_tx_buf_ratio = 21; 2252 2253 /* Set up ifnet structure */ 2254 ifp = &sc->arpcom.ac_if; 2255 ifp->if_softc = sc; 2256 ifp->if_unit = sc->ti_unit; 2257 ifp->if_name = "ti"; 2258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2259 tis[unit] = sc; 2260 ifp->if_ioctl = ti_ioctl; 2261 ifp->if_output = ether_output; 2262 ifp->if_start = ti_start; 2263 ifp->if_watchdog = ti_watchdog; 2264 ifp->if_init = ti_init; 2265 ifp->if_mtu = ETHERMTU; 2266 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2267 2268 /* Set up ifmedia support. */ 2269 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2270 if (sc->ti_copper) { 2271 /* 2272 * Copper cards allow manual 10/100 mode selection, 2273 * but not manual 1000baseTX mode selection. Why? 2274 * Becuase currently there's no way to specify the 2275 * master/slave setting through the firmware interface, 2276 * so Alteon decided to just bag it and handle it 2277 * via autonegotiation. 2278 */ 2279 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2280 ifmedia_add(&sc->ifmedia, 2281 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2282 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2283 ifmedia_add(&sc->ifmedia, 2284 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2285 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2286 ifmedia_add(&sc->ifmedia, 2287 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2288 } else { 2289 /* Fiber cards don't support 10/100 modes. */ 2290 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2291 ifmedia_add(&sc->ifmedia, 2292 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2293 } 2294 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2295 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2296 2297 /* 2298 * We're assuming here that card initialization is a sequential 2299 * thing. If it isn't, multiple cards probing at the same time 2300 * could stomp on the list of softcs here. 2301 */ 2302 /* 2303 * If this is the first card to be initialized, initialize the 2304 * softc queue. 2305 */ 2306 if (unit == 0) 2307 STAILQ_INIT(&ti_sc_list); 2308 2309 STAILQ_INSERT_TAIL(&ti_sc_list, sc, ti_links); 2310 2311 /* Register the device */ 2312 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2313 0600, "ti%d", sc->ti_unit); 2314 2315 /* 2316 * Call MI attach routine. 2317 */ 2318 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2319 2320 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 2321 ti_intr, sc, &sc->ti_intrhand); 2322 2323 if (error) { 2324 printf("ti%d: couldn't set up irq\n", unit); 2325 goto fail; 2326 } 2327 2328 fail: 2329 if (sc && error) 2330 ti_detach(dev); 2331 2332 return(error); 2333 } 2334 2335 /* 2336 * Verify that our character special device is not currently 2337 * open. Also track down any cached vnodes & kill them before 2338 * the module is unloaded 2339 */ 2340 static int 2341 ti_unref_special(device_t dev) 2342 { 2343 struct vnode *ti_vn; 2344 int count; 2345 struct ti_softc *sc = sc = device_get_softc(dev); 2346 2347 if (!vfinddev(sc->dev, VCHR, &ti_vn)) { 2348 return 0; 2349 } 2350 2351 if ((count = vcount(ti_vn))) { 2352 device_printf(dev, "%d refs to special device, " 2353 "denying unload\n", count); 2354 return count; 2355 } 2356 /* now we know that there's a vnode in the cache. We hunt it 2357 down and kill it now, before unloading */ 2358 vgone(ti_vn); 2359 return(0); 2360 } 2361 2362 2363 static int 2364 ti_detach(dev) 2365 device_t dev; 2366 { 2367 struct ti_softc *sc; 2368 struct ifnet *ifp; 2369 2370 if (ti_unref_special(dev)) 2371 return EBUSY; 2372 2373 sc = device_get_softc(dev); 2374 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2375 TI_LOCK(sc); 2376 ifp = &sc->arpcom.ac_if; 2377 2378 if (device_is_alive(dev)) { 2379 if (bus_child_present(dev)) 2380 ti_stop(sc); 2381 ether_ifdetach(ifp); 2382 bus_generic_detach(dev); 2383 ifmedia_removeall(&sc->ifmedia); 2384 } 2385 2386 if (sc->ti_intrhand) 2387 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2388 if (sc->ti_irq) 2389 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2390 if (sc->ti_res) { 2391 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2392 sc->ti_res); 2393 } 2394 2395 #ifdef TI_PRIVATE_JUMBOS 2396 if (sc->ti_cdata.ti_jumbo_buf) 2397 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF); 2398 #endif 2399 if (sc->ti_rdata) 2400 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF); 2401 2402 TI_UNLOCK(sc); 2403 mtx_destroy(&sc->ti_mtx); 2404 2405 return(0); 2406 } 2407 2408 #ifdef TI_JUMBO_HDRSPLIT 2409 /* 2410 * If hdr_len is 0, that means that header splitting wasn't done on 2411 * this packet for some reason. The two most likely reasons are that 2412 * the protocol isn't a supported protocol for splitting, or this 2413 * packet had a fragment offset that wasn't 0. 2414 * 2415 * The header length, if it is non-zero, will always be the length of 2416 * the headers on the packet, but that length could be longer than the 2417 * first mbuf. So we take the minimum of the two as the actual 2418 * length. 2419 */ 2420 static __inline void 2421 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2422 { 2423 int i = 0; 2424 int lengths[4] = {0, 0, 0, 0}; 2425 struct mbuf *m, *mp; 2426 2427 if (hdr_len != 0) 2428 top->m_len = min(hdr_len, top->m_len); 2429 pkt_len -= top->m_len; 2430 lengths[i++] = top->m_len; 2431 2432 mp = top; 2433 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2434 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2435 pkt_len -= m->m_len; 2436 lengths[i++] = m->m_len; 2437 mp = m; 2438 } 2439 2440 #if 0 2441 if (hdr_len != 0) 2442 printf("got split packet: "); 2443 else 2444 printf("got non-split packet: "); 2445 2446 printf("%d,%d,%d,%d = %d\n", lengths[0], 2447 lengths[1], lengths[2], lengths[3], 2448 lengths[0] + lengths[1] + lengths[2] + 2449 lengths[3]); 2450 #endif 2451 2452 if (pkt_len) 2453 panic("header splitting didn't"); 2454 2455 if (m) { 2456 m_freem(m); 2457 mp->m_next = NULL; 2458 2459 } 2460 if (mp->m_next != NULL) 2461 panic("ti_hdr_split: last mbuf in chain should be null"); 2462 } 2463 #endif /* TI_JUMBO_HDRSPLIT */ 2464 2465 /* 2466 * Frame reception handling. This is called if there's a frame 2467 * on the receive return list. 2468 * 2469 * Note: we have to be able to handle three possibilities here: 2470 * 1) the frame is from the mini receive ring (can only happen) 2471 * on Tigon 2 boards) 2472 * 2) the frame is from the jumbo recieve ring 2473 * 3) the frame is from the standard receive ring 2474 */ 2475 2476 static void 2477 ti_rxeof(sc) 2478 struct ti_softc *sc; 2479 { 2480 struct ifnet *ifp; 2481 struct ti_cmd_desc cmd; 2482 2483 ifp = &sc->arpcom.ac_if; 2484 2485 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2486 struct ti_rx_desc *cur_rx; 2487 u_int32_t rxidx; 2488 struct ether_header *eh; 2489 struct mbuf *m = NULL; 2490 u_int16_t vlan_tag = 0; 2491 int have_tag = 0; 2492 2493 cur_rx = 2494 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2495 rxidx = cur_rx->ti_idx; 2496 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2497 2498 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2499 have_tag = 1; 2500 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2501 } 2502 2503 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2504 2505 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2506 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2507 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2508 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2509 ifp->if_ierrors++; 2510 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2511 continue; 2512 } 2513 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2514 ifp->if_ierrors++; 2515 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2516 continue; 2517 } 2518 #ifdef TI_PRIVATE_JUMBOS 2519 m->m_len = cur_rx->ti_len; 2520 #else /* TI_PRIVATE_JUMBOS */ 2521 #ifdef TI_JUMBO_HDRSPLIT 2522 if (sc->ti_hdrsplit) 2523 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2524 cur_rx->ti_len, rxidx); 2525 else 2526 #endif /* TI_JUMBO_HDRSPLIT */ 2527 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2528 #endif /* TI_PRIVATE_JUMBOS */ 2529 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2530 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2531 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2532 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2533 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2534 ifp->if_ierrors++; 2535 ti_newbuf_mini(sc, sc->ti_mini, m); 2536 continue; 2537 } 2538 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2539 ifp->if_ierrors++; 2540 ti_newbuf_mini(sc, sc->ti_mini, m); 2541 continue; 2542 } 2543 m->m_len = cur_rx->ti_len; 2544 } else { 2545 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2546 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2547 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2548 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2549 ifp->if_ierrors++; 2550 ti_newbuf_std(sc, sc->ti_std, m); 2551 continue; 2552 } 2553 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2554 ifp->if_ierrors++; 2555 ti_newbuf_std(sc, sc->ti_std, m); 2556 continue; 2557 } 2558 m->m_len = cur_rx->ti_len; 2559 } 2560 2561 m->m_pkthdr.len = cur_rx->ti_len; 2562 ifp->if_ipackets++; 2563 eh = mtod(m, struct ether_header *); 2564 m->m_pkthdr.rcvif = ifp; 2565 2566 if (ifp->if_hwassist) { 2567 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2568 CSUM_DATA_VALID; 2569 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2570 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2571 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2572 } 2573 2574 /* 2575 * If we received a packet with a vlan tag, 2576 * tag it before passing the packet upward. 2577 */ 2578 if (have_tag) 2579 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2580 (*ifp->if_input)(ifp, m); 2581 } 2582 2583 /* Only necessary on the Tigon 1. */ 2584 if (sc->ti_hwrev == TI_HWREV_TIGON) 2585 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2586 sc->ti_rx_saved_considx); 2587 2588 TI_UPDATE_STDPROD(sc, sc->ti_std); 2589 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2590 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2591 2592 return; 2593 } 2594 2595 static void 2596 ti_txeof(sc) 2597 struct ti_softc *sc; 2598 { 2599 struct ti_tx_desc *cur_tx = NULL; 2600 struct ifnet *ifp; 2601 2602 ifp = &sc->arpcom.ac_if; 2603 2604 /* 2605 * Go through our tx ring and free mbufs for those 2606 * frames that have been sent. 2607 */ 2608 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2609 u_int32_t idx = 0; 2610 2611 idx = sc->ti_tx_saved_considx; 2612 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2613 if (idx > 383) 2614 CSR_WRITE_4(sc, TI_WINBASE, 2615 TI_TX_RING_BASE + 6144); 2616 else if (idx > 255) 2617 CSR_WRITE_4(sc, TI_WINBASE, 2618 TI_TX_RING_BASE + 4096); 2619 else if (idx > 127) 2620 CSR_WRITE_4(sc, TI_WINBASE, 2621 TI_TX_RING_BASE + 2048); 2622 else 2623 CSR_WRITE_4(sc, TI_WINBASE, 2624 TI_TX_RING_BASE); 2625 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2626 } else 2627 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2628 if (cur_tx->ti_flags & TI_BDFLAG_END) 2629 ifp->if_opackets++; 2630 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2631 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2632 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2633 } 2634 sc->ti_txcnt--; 2635 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2636 ifp->if_timer = 0; 2637 } 2638 2639 if (cur_tx != NULL) 2640 ifp->if_flags &= ~IFF_OACTIVE; 2641 2642 return; 2643 } 2644 2645 static void 2646 ti_intr(xsc) 2647 void *xsc; 2648 { 2649 struct ti_softc *sc; 2650 struct ifnet *ifp; 2651 2652 sc = xsc; 2653 TI_LOCK(sc); 2654 ifp = &sc->arpcom.ac_if; 2655 2656 /*#ifdef notdef*/ 2657 /* Avoid this for now -- checking this register is expensive. */ 2658 /* Make sure this is really our interrupt. */ 2659 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2660 TI_UNLOCK(sc); 2661 return; 2662 } 2663 /*#endif*/ 2664 2665 /* Ack interrupt and stop others from occuring. */ 2666 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2667 2668 if (ifp->if_flags & IFF_RUNNING) { 2669 /* Check RX return ring producer/consumer */ 2670 ti_rxeof(sc); 2671 2672 /* Check TX ring producer/consumer */ 2673 ti_txeof(sc); 2674 } 2675 2676 ti_handle_events(sc); 2677 2678 /* Re-enable interrupts. */ 2679 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2680 2681 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2682 ti_start(ifp); 2683 2684 TI_UNLOCK(sc); 2685 2686 return; 2687 } 2688 2689 static void 2690 ti_stats_update(sc) 2691 struct ti_softc *sc; 2692 { 2693 struct ifnet *ifp; 2694 2695 ifp = &sc->arpcom.ac_if; 2696 2697 ifp->if_collisions += 2698 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2699 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2700 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2701 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2702 ifp->if_collisions; 2703 2704 return; 2705 } 2706 2707 /* 2708 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2709 * pointers to descriptors. 2710 */ 2711 static int 2712 ti_encap(sc, m_head, txidx) 2713 struct ti_softc *sc; 2714 struct mbuf *m_head; 2715 u_int32_t *txidx; 2716 { 2717 struct ti_tx_desc *f = NULL; 2718 struct mbuf *m; 2719 u_int32_t frag, cur, cnt = 0; 2720 u_int16_t csum_flags = 0; 2721 struct m_tag *mtag; 2722 2723 m = m_head; 2724 cur = frag = *txidx; 2725 2726 if (m_head->m_pkthdr.csum_flags) { 2727 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2728 csum_flags |= TI_BDFLAG_IP_CKSUM; 2729 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2730 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2731 if (m_head->m_flags & M_LASTFRAG) 2732 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2733 else if (m_head->m_flags & M_FRAG) 2734 csum_flags |= TI_BDFLAG_IP_FRAG; 2735 } 2736 2737 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2738 2739 /* 2740 * Start packing the mbufs in this chain into 2741 * the fragment pointers. Stop when we run out 2742 * of fragments or hit the end of the mbuf chain. 2743 */ 2744 for (m = m_head; m != NULL; m = m->m_next) { 2745 if (m->m_len != 0) { 2746 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2747 if (frag > 383) 2748 CSR_WRITE_4(sc, TI_WINBASE, 2749 TI_TX_RING_BASE + 6144); 2750 else if (frag > 255) 2751 CSR_WRITE_4(sc, TI_WINBASE, 2752 TI_TX_RING_BASE + 4096); 2753 else if (frag > 127) 2754 CSR_WRITE_4(sc, TI_WINBASE, 2755 TI_TX_RING_BASE + 2048); 2756 else 2757 CSR_WRITE_4(sc, TI_WINBASE, 2758 TI_TX_RING_BASE); 2759 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2760 } else 2761 f = &sc->ti_rdata->ti_tx_ring[frag]; 2762 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2763 break; 2764 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2765 f->ti_len = m->m_len; 2766 f->ti_flags = csum_flags; 2767 2768 if (mtag != NULL) { 2769 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2770 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag) & 0xfff; 2771 } else { 2772 f->ti_vlan_tag = 0; 2773 } 2774 2775 /* 2776 * Sanity check: avoid coming within 16 descriptors 2777 * of the end of the ring. 2778 */ 2779 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2780 return(ENOBUFS); 2781 cur = frag; 2782 TI_INC(frag, TI_TX_RING_CNT); 2783 cnt++; 2784 } 2785 } 2786 2787 if (m != NULL) 2788 return(ENOBUFS); 2789 2790 if (frag == sc->ti_tx_saved_considx) 2791 return(ENOBUFS); 2792 2793 if (sc->ti_hwrev == TI_HWREV_TIGON) 2794 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2795 TI_BDFLAG_END; 2796 else 2797 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2798 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2799 sc->ti_txcnt += cnt; 2800 2801 *txidx = frag; 2802 2803 return(0); 2804 } 2805 2806 /* 2807 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2808 * to the mbuf data regions directly in the transmit descriptors. 2809 */ 2810 static void 2811 ti_start(ifp) 2812 struct ifnet *ifp; 2813 { 2814 struct ti_softc *sc; 2815 struct mbuf *m_head = NULL; 2816 u_int32_t prodidx = 0; 2817 2818 sc = ifp->if_softc; 2819 TI_LOCK(sc); 2820 2821 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2822 2823 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2824 IF_DEQUEUE(&ifp->if_snd, m_head); 2825 if (m_head == NULL) 2826 break; 2827 2828 /* 2829 * XXX 2830 * safety overkill. If this is a fragmented packet chain 2831 * with delayed TCP/UDP checksums, then only encapsulate 2832 * it if we have enough descriptors to handle the entire 2833 * chain at once. 2834 * (paranoia -- may not actually be needed) 2835 */ 2836 if (m_head->m_flags & M_FIRSTFRAG && 2837 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2838 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2839 m_head->m_pkthdr.csum_data + 16) { 2840 IF_PREPEND(&ifp->if_snd, m_head); 2841 ifp->if_flags |= IFF_OACTIVE; 2842 break; 2843 } 2844 } 2845 2846 /* 2847 * Pack the data into the transmit ring. If we 2848 * don't have room, set the OACTIVE flag and wait 2849 * for the NIC to drain the ring. 2850 */ 2851 if (ti_encap(sc, m_head, &prodidx)) { 2852 IF_PREPEND(&ifp->if_snd, m_head); 2853 ifp->if_flags |= IFF_OACTIVE; 2854 break; 2855 } 2856 2857 /* 2858 * If there's a BPF listener, bounce a copy of this frame 2859 * to him. 2860 */ 2861 BPF_MTAP(ifp, m_head); 2862 } 2863 2864 /* Transmit */ 2865 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2866 2867 /* 2868 * Set a timeout in case the chip goes out to lunch. 2869 */ 2870 ifp->if_timer = 5; 2871 TI_UNLOCK(sc); 2872 2873 return; 2874 } 2875 2876 static void 2877 ti_init(xsc) 2878 void *xsc; 2879 { 2880 struct ti_softc *sc = xsc; 2881 2882 /* Cancel pending I/O and flush buffers. */ 2883 ti_stop(sc); 2884 2885 TI_LOCK(sc); 2886 /* Init the gen info block, ring control blocks and firmware. */ 2887 if (ti_gibinit(sc)) { 2888 printf("ti%d: initialization failure\n", sc->ti_unit); 2889 TI_UNLOCK(sc); 2890 return; 2891 } 2892 2893 TI_UNLOCK(sc); 2894 2895 return; 2896 } 2897 2898 static void ti_init2(sc) 2899 struct ti_softc *sc; 2900 { 2901 struct ti_cmd_desc cmd; 2902 struct ifnet *ifp; 2903 u_int16_t *m; 2904 struct ifmedia *ifm; 2905 int tmp; 2906 2907 ifp = &sc->arpcom.ac_if; 2908 2909 /* Specify MTU and interface index. */ 2910 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2911 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2912 ETHER_HDR_LEN + ETHER_CRC_LEN); 2913 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2914 2915 /* Load our MAC address. */ 2916 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2917 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2918 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2919 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2920 2921 /* Enable or disable promiscuous mode as needed. */ 2922 if (ifp->if_flags & IFF_PROMISC) { 2923 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2924 } else { 2925 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2926 } 2927 2928 /* Program multicast filter. */ 2929 ti_setmulti(sc); 2930 2931 /* 2932 * If this is a Tigon 1, we should tell the 2933 * firmware to use software packet filtering. 2934 */ 2935 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2936 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2937 } 2938 2939 /* Init RX ring. */ 2940 ti_init_rx_ring_std(sc); 2941 2942 /* Init jumbo RX ring. */ 2943 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2944 ti_init_rx_ring_jumbo(sc); 2945 2946 /* 2947 * If this is a Tigon 2, we can also configure the 2948 * mini ring. 2949 */ 2950 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2951 ti_init_rx_ring_mini(sc); 2952 2953 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2954 sc->ti_rx_saved_considx = 0; 2955 2956 /* Init TX ring. */ 2957 ti_init_tx_ring(sc); 2958 2959 /* Tell firmware we're alive. */ 2960 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2961 2962 /* Enable host interrupts. */ 2963 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2964 2965 ifp->if_flags |= IFF_RUNNING; 2966 ifp->if_flags &= ~IFF_OACTIVE; 2967 2968 /* 2969 * Make sure to set media properly. We have to do this 2970 * here since we have to issue commands in order to set 2971 * the link negotiation and we can't issue commands until 2972 * the firmware is running. 2973 */ 2974 ifm = &sc->ifmedia; 2975 tmp = ifm->ifm_media; 2976 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2977 ti_ifmedia_upd(ifp); 2978 ifm->ifm_media = tmp; 2979 2980 return; 2981 } 2982 2983 /* 2984 * Set media options. 2985 */ 2986 static int 2987 ti_ifmedia_upd(ifp) 2988 struct ifnet *ifp; 2989 { 2990 struct ti_softc *sc; 2991 struct ifmedia *ifm; 2992 struct ti_cmd_desc cmd; 2993 u_int32_t flowctl; 2994 2995 sc = ifp->if_softc; 2996 ifm = &sc->ifmedia; 2997 2998 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2999 return(EINVAL); 3000 3001 flowctl = 0; 3002 3003 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3004 case IFM_AUTO: 3005 /* 3006 * Transmit flow control doesn't work on the Tigon 1. 3007 */ 3008 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3009 3010 /* 3011 * Transmit flow control can also cause problems on the 3012 * Tigon 2, apparantly with both the copper and fiber 3013 * boards. The symptom is that the interface will just 3014 * hang. This was reproduced with Alteon 180 switches. 3015 */ 3016 #if 0 3017 if (sc->ti_hwrev != TI_HWREV_TIGON) 3018 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3019 #endif 3020 3021 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3022 TI_GLNK_FULL_DUPLEX| flowctl | 3023 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3024 3025 flowctl = TI_LNK_RX_FLOWCTL_Y; 3026 #if 0 3027 if (sc->ti_hwrev != TI_HWREV_TIGON) 3028 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3029 #endif 3030 3031 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3032 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3033 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3034 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3035 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3036 break; 3037 case IFM_1000_SX: 3038 case IFM_1000_T: 3039 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3040 #if 0 3041 if (sc->ti_hwrev != TI_HWREV_TIGON) 3042 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3043 #endif 3044 3045 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3046 flowctl |TI_GLNK_ENB); 3047 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3048 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3049 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3050 } 3051 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3052 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3053 break; 3054 case IFM_100_FX: 3055 case IFM_10_FL: 3056 case IFM_100_TX: 3057 case IFM_10_T: 3058 flowctl = TI_LNK_RX_FLOWCTL_Y; 3059 #if 0 3060 if (sc->ti_hwrev != TI_HWREV_TIGON) 3061 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3062 #endif 3063 3064 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3065 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3066 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3067 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3068 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3069 } else { 3070 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3071 } 3072 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3073 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3074 } else { 3075 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3076 } 3077 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3078 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3079 break; 3080 } 3081 3082 return(0); 3083 } 3084 3085 /* 3086 * Report current media status. 3087 */ 3088 static void 3089 ti_ifmedia_sts(ifp, ifmr) 3090 struct ifnet *ifp; 3091 struct ifmediareq *ifmr; 3092 { 3093 struct ti_softc *sc; 3094 u_int32_t media = 0; 3095 3096 sc = ifp->if_softc; 3097 3098 ifmr->ifm_status = IFM_AVALID; 3099 ifmr->ifm_active = IFM_ETHER; 3100 3101 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3102 return; 3103 3104 ifmr->ifm_status |= IFM_ACTIVE; 3105 3106 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3107 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3108 if (sc->ti_copper) 3109 ifmr->ifm_active |= IFM_1000_T; 3110 else 3111 ifmr->ifm_active |= IFM_1000_SX; 3112 if (media & TI_GLNK_FULL_DUPLEX) 3113 ifmr->ifm_active |= IFM_FDX; 3114 else 3115 ifmr->ifm_active |= IFM_HDX; 3116 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3117 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3118 if (sc->ti_copper) { 3119 if (media & TI_LNK_100MB) 3120 ifmr->ifm_active |= IFM_100_TX; 3121 if (media & TI_LNK_10MB) 3122 ifmr->ifm_active |= IFM_10_T; 3123 } else { 3124 if (media & TI_LNK_100MB) 3125 ifmr->ifm_active |= IFM_100_FX; 3126 if (media & TI_LNK_10MB) 3127 ifmr->ifm_active |= IFM_10_FL; 3128 } 3129 if (media & TI_LNK_FULL_DUPLEX) 3130 ifmr->ifm_active |= IFM_FDX; 3131 if (media & TI_LNK_HALF_DUPLEX) 3132 ifmr->ifm_active |= IFM_HDX; 3133 } 3134 3135 return; 3136 } 3137 3138 static int 3139 ti_ioctl(ifp, command, data) 3140 struct ifnet *ifp; 3141 u_long command; 3142 caddr_t data; 3143 { 3144 struct ti_softc *sc = ifp->if_softc; 3145 struct ifreq *ifr = (struct ifreq *) data; 3146 int mask, error = 0; 3147 struct ti_cmd_desc cmd; 3148 3149 TI_LOCK(sc); 3150 3151 switch(command) { 3152 case SIOCSIFMTU: 3153 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3154 error = EINVAL; 3155 else { 3156 ifp->if_mtu = ifr->ifr_mtu; 3157 ti_init(sc); 3158 } 3159 break; 3160 case SIOCSIFFLAGS: 3161 if (ifp->if_flags & IFF_UP) { 3162 /* 3163 * If only the state of the PROMISC flag changed, 3164 * then just use the 'set promisc mode' command 3165 * instead of reinitializing the entire NIC. Doing 3166 * a full re-init means reloading the firmware and 3167 * waiting for it to start up, which may take a 3168 * second or two. 3169 */ 3170 if (ifp->if_flags & IFF_RUNNING && 3171 ifp->if_flags & IFF_PROMISC && 3172 !(sc->ti_if_flags & IFF_PROMISC)) { 3173 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3174 TI_CMD_CODE_PROMISC_ENB, 0); 3175 } else if (ifp->if_flags & IFF_RUNNING && 3176 !(ifp->if_flags & IFF_PROMISC) && 3177 sc->ti_if_flags & IFF_PROMISC) { 3178 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3179 TI_CMD_CODE_PROMISC_DIS, 0); 3180 } else 3181 ti_init(sc); 3182 } else { 3183 if (ifp->if_flags & IFF_RUNNING) { 3184 ti_stop(sc); 3185 } 3186 } 3187 sc->ti_if_flags = ifp->if_flags; 3188 error = 0; 3189 break; 3190 case SIOCADDMULTI: 3191 case SIOCDELMULTI: 3192 if (ifp->if_flags & IFF_RUNNING) { 3193 ti_setmulti(sc); 3194 error = 0; 3195 } 3196 break; 3197 case SIOCSIFMEDIA: 3198 case SIOCGIFMEDIA: 3199 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3200 break; 3201 case SIOCSIFCAP: 3202 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3203 if (mask & IFCAP_HWCSUM) { 3204 if (IFCAP_HWCSUM & ifp->if_capenable) 3205 ifp->if_capenable &= ~IFCAP_HWCSUM; 3206 else 3207 ifp->if_capenable |= IFCAP_HWCSUM; 3208 if (ifp->if_flags & IFF_RUNNING) 3209 ti_init(sc); 3210 } 3211 error = 0; 3212 break; 3213 default: 3214 error = ether_ioctl(ifp, command, data); 3215 break; 3216 } 3217 3218 TI_UNLOCK(sc); 3219 3220 return(error); 3221 } 3222 3223 static int 3224 ti_open(dev_t dev, int flags, int fmt, struct thread *td) 3225 { 3226 int unit; 3227 struct ti_softc *sc; 3228 3229 unit = minor(dev) & 0xff; 3230 3231 sc = ti_lookup_softc(unit); 3232 3233 if (sc == NULL) 3234 return(ENODEV); 3235 3236 TI_LOCK(sc); 3237 sc->ti_flags |= TI_FLAG_DEBUGING; 3238 TI_UNLOCK(sc); 3239 3240 return(0); 3241 } 3242 3243 static int 3244 ti_close(dev_t dev, int flag, int fmt, struct thread *td) 3245 { 3246 int unit; 3247 struct ti_softc *sc; 3248 3249 unit = minor(dev) & 0xff; 3250 3251 sc = ti_lookup_softc(unit); 3252 3253 if (sc == NULL) 3254 return(ENODEV); 3255 3256 TI_LOCK(sc); 3257 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3258 TI_UNLOCK(sc); 3259 3260 return(0); 3261 } 3262 3263 /* 3264 * This ioctl routine goes along with the Tigon character device. 3265 */ 3266 static int 3267 ti_ioctl2(dev_t dev, u_long cmd, caddr_t addr, int flag, struct thread *td) 3268 { 3269 int unit, error; 3270 struct ti_softc *sc; 3271 3272 unit = minor(dev) & 0xff; 3273 3274 sc = ti_lookup_softc(unit); 3275 3276 if (sc == NULL) 3277 return(ENODEV); 3278 3279 error = 0; 3280 3281 switch(cmd) { 3282 case TIIOCGETSTATS: 3283 { 3284 struct ti_stats *outstats; 3285 3286 outstats = (struct ti_stats *)addr; 3287 3288 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3289 sizeof(struct ti_stats)); 3290 break; 3291 } 3292 case TIIOCGETPARAMS: 3293 { 3294 struct ti_params *params; 3295 3296 params = (struct ti_params *)addr; 3297 3298 params->ti_stat_ticks = sc->ti_stat_ticks; 3299 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3300 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3301 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3302 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3303 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3304 params->param_mask = TI_PARAM_ALL; 3305 3306 error = 0; 3307 3308 break; 3309 } 3310 case TIIOCSETPARAMS: 3311 { 3312 struct ti_params *params; 3313 3314 params = (struct ti_params *)addr; 3315 3316 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3317 sc->ti_stat_ticks = params->ti_stat_ticks; 3318 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3319 } 3320 3321 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3322 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3323 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3324 sc->ti_rx_coal_ticks); 3325 } 3326 3327 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3328 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3329 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3330 sc->ti_tx_coal_ticks); 3331 } 3332 3333 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3334 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3335 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3336 sc->ti_rx_max_coal_bds); 3337 } 3338 3339 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3340 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3341 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3342 sc->ti_tx_max_coal_bds); 3343 } 3344 3345 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3346 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3347 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3348 sc->ti_tx_buf_ratio); 3349 } 3350 3351 error = 0; 3352 3353 break; 3354 } 3355 case TIIOCSETTRACE: { 3356 ti_trace_type trace_type; 3357 3358 trace_type = *(ti_trace_type *)addr; 3359 3360 /* 3361 * Set tracing to whatever the user asked for. Setting 3362 * this register to 0 should have the effect of disabling 3363 * tracing. 3364 */ 3365 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3366 3367 error = 0; 3368 3369 break; 3370 } 3371 case TIIOCGETTRACE: { 3372 struct ti_trace_buf *trace_buf; 3373 u_int32_t trace_start, cur_trace_ptr, trace_len; 3374 3375 trace_buf = (struct ti_trace_buf *)addr; 3376 3377 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3378 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3379 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3380 3381 #if 0 3382 printf("ti%d: trace_start = %#x, cur_trace_ptr = %#x, " 3383 "trace_len = %d\n", sc->ti_unit, trace_start, 3384 cur_trace_ptr, trace_len); 3385 printf("ti%d: trace_buf->buf_len = %d\n", sc->ti_unit, 3386 trace_buf->buf_len); 3387 #endif 3388 3389 error = ti_copy_mem(sc, trace_start, min(trace_len, 3390 trace_buf->buf_len), 3391 (caddr_t)trace_buf->buf, 1, 1); 3392 3393 if (error == 0) { 3394 trace_buf->fill_len = min(trace_len, 3395 trace_buf->buf_len); 3396 if (cur_trace_ptr < trace_start) 3397 trace_buf->cur_trace_ptr = 3398 trace_start - cur_trace_ptr; 3399 else 3400 trace_buf->cur_trace_ptr = 3401 cur_trace_ptr - trace_start; 3402 } else 3403 trace_buf->fill_len = 0; 3404 3405 3406 break; 3407 } 3408 3409 /* 3410 * For debugging, five ioctls are needed: 3411 * ALT_ATTACH 3412 * ALT_READ_TG_REG 3413 * ALT_WRITE_TG_REG 3414 * ALT_READ_TG_MEM 3415 * ALT_WRITE_TG_MEM 3416 */ 3417 case ALT_ATTACH: 3418 /* 3419 * From what I can tell, Alteon's Solaris Tigon driver 3420 * only has one character device, so you have to attach 3421 * to the Tigon board you're interested in. This seems 3422 * like a not-so-good way to do things, since unless you 3423 * subsequently specify the unit number of the device 3424 * you're interested in in every ioctl, you'll only be 3425 * able to debug one board at a time. 3426 */ 3427 error = 0; 3428 break; 3429 case ALT_READ_TG_MEM: 3430 case ALT_WRITE_TG_MEM: 3431 { 3432 struct tg_mem *mem_param; 3433 u_int32_t sram_end, scratch_end; 3434 3435 mem_param = (struct tg_mem *)addr; 3436 3437 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3438 sram_end = TI_END_SRAM_I; 3439 scratch_end = TI_END_SCRATCH_I; 3440 } else { 3441 sram_end = TI_END_SRAM_II; 3442 scratch_end = TI_END_SCRATCH_II; 3443 } 3444 3445 /* 3446 * For now, we'll only handle accessing regular SRAM, 3447 * nothing else. 3448 */ 3449 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3450 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3451 /* 3452 * In this instance, we always copy to/from user 3453 * space, so the user space argument is set to 1. 3454 */ 3455 error = ti_copy_mem(sc, mem_param->tgAddr, 3456 mem_param->len, 3457 mem_param->userAddr, 1, 3458 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3459 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3460 && (mem_param->tgAddr <= scratch_end)) { 3461 error = ti_copy_scratch(sc, mem_param->tgAddr, 3462 mem_param->len, 3463 mem_param->userAddr, 1, 3464 (cmd == ALT_READ_TG_MEM) ? 3465 1 : 0, TI_PROCESSOR_A); 3466 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3467 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3468 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3469 printf("ti%d: invalid memory range for " 3470 "Tigon I\n", sc->ti_unit); 3471 error = EINVAL; 3472 break; 3473 } 3474 error = ti_copy_scratch(sc, mem_param->tgAddr - 3475 TI_SCRATCH_DEBUG_OFF, 3476 mem_param->len, 3477 mem_param->userAddr, 1, 3478 (cmd == ALT_READ_TG_MEM) ? 3479 1 : 0, TI_PROCESSOR_B); 3480 } else { 3481 printf("ti%d: memory address %#x len %d is out of " 3482 "supported range\n", sc->ti_unit, 3483 mem_param->tgAddr, mem_param->len); 3484 error = EINVAL; 3485 } 3486 3487 break; 3488 } 3489 case ALT_READ_TG_REG: 3490 case ALT_WRITE_TG_REG: 3491 { 3492 struct tg_reg *regs; 3493 u_int32_t tmpval; 3494 3495 regs = (struct tg_reg *)addr; 3496 3497 /* 3498 * Make sure the address in question isn't out of range. 3499 */ 3500 if (regs->addr > TI_REG_MAX) { 3501 error = EINVAL; 3502 break; 3503 } 3504 if (cmd == ALT_READ_TG_REG) { 3505 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3506 regs->addr, &tmpval, 1); 3507 regs->data = ntohl(tmpval); 3508 #if 0 3509 if ((regs->addr == TI_CPU_STATE) 3510 || (regs->addr == TI_CPU_CTL_B)) { 3511 printf("ti%d: register %#x = %#x\n", 3512 sc->ti_unit, regs->addr, tmpval); 3513 } 3514 #endif 3515 } else { 3516 tmpval = htonl(regs->data); 3517 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3518 regs->addr, &tmpval, 1); 3519 } 3520 3521 break; 3522 } 3523 default: 3524 error = ENOTTY; 3525 break; 3526 } 3527 return(error); 3528 } 3529 3530 static void 3531 ti_watchdog(ifp) 3532 struct ifnet *ifp; 3533 { 3534 struct ti_softc *sc; 3535 3536 sc = ifp->if_softc; 3537 TI_LOCK(sc); 3538 3539 /* 3540 * When we're debugging, the chip is often stopped for long periods 3541 * of time, and that would normally cause the watchdog timer to fire. 3542 * Since that impedes debugging, we don't want to do that. 3543 */ 3544 if (sc->ti_flags & TI_FLAG_DEBUGING) { 3545 TI_UNLOCK(sc); 3546 return; 3547 } 3548 3549 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 3550 ti_stop(sc); 3551 ti_init(sc); 3552 3553 ifp->if_oerrors++; 3554 TI_UNLOCK(sc); 3555 3556 return; 3557 } 3558 3559 /* 3560 * Stop the adapter and free any mbufs allocated to the 3561 * RX and TX lists. 3562 */ 3563 static void 3564 ti_stop(sc) 3565 struct ti_softc *sc; 3566 { 3567 struct ifnet *ifp; 3568 struct ti_cmd_desc cmd; 3569 3570 TI_LOCK(sc); 3571 3572 ifp = &sc->arpcom.ac_if; 3573 3574 /* Disable host interrupts. */ 3575 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3576 /* 3577 * Tell firmware we're shutting down. 3578 */ 3579 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3580 3581 /* Halt and reinitialize. */ 3582 ti_chipinit(sc); 3583 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 3584 ti_chipinit(sc); 3585 3586 /* Free the RX lists. */ 3587 ti_free_rx_ring_std(sc); 3588 3589 /* Free jumbo RX list. */ 3590 ti_free_rx_ring_jumbo(sc); 3591 3592 /* Free mini RX list. */ 3593 ti_free_rx_ring_mini(sc); 3594 3595 /* Free TX buffers. */ 3596 ti_free_tx_ring(sc); 3597 3598 sc->ti_ev_prodidx.ti_idx = 0; 3599 sc->ti_return_prodidx.ti_idx = 0; 3600 sc->ti_tx_considx.ti_idx = 0; 3601 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3602 3603 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3604 TI_UNLOCK(sc); 3605 3606 return; 3607 } 3608 3609 /* 3610 * Stop all chip I/O so that the kernel's probe routines don't 3611 * get confused by errant DMAs when rebooting. 3612 */ 3613 static void 3614 ti_shutdown(dev) 3615 device_t dev; 3616 { 3617 struct ti_softc *sc; 3618 3619 sc = device_get_softc(dev); 3620 TI_LOCK(sc); 3621 ti_chipinit(sc); 3622 TI_UNLOCK(sc); 3623 3624 return; 3625 } 3626