1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45 /* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring desciptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81 #include "vlan.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/sockio.h> 86 #include <sys/mbuf.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/socket.h> 90 #include <sys/queue.h> 91 92 #include <net/if.h> 93 #include <net/if_arp.h> 94 #include <net/ethernet.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 98 #include <net/bpf.h> 99 100 #if NVLAN > 0 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 #endif 104 105 #include <netinet/in_systm.h> 106 #include <netinet/in.h> 107 #include <netinet/ip.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_memio.h> 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <pci/pcireg.h> 119 #include <pci/pcivar.h> 120 121 #include <pci/if_tireg.h> 122 #include <pci/ti_fw.h> 123 #include <pci/ti_fw2.h> 124 125 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 126 127 #if !defined(lint) 128 static const char rcsid[] = 129 "$FreeBSD$"; 130 #endif 131 132 /* 133 * Various supported device vendors/types and their names. 134 */ 135 136 static struct ti_type ti_devs[] = { 137 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 138 "Alteon AceNIC Gigabit Ethernet" }, 139 { TC_VENDORID, TC_DEVICEID_3C985, 140 "3Com 3c985-SX Gigabit Ethernet" }, 141 { NG_VENDORID, NG_DEVICEID_GA620, 142 "Netgear GA620 Gigabit Ethernet" }, 143 { SGI_VENDORID, SGI_DEVICEID_TIGON, 144 "Silicon Graphics Gigabit Ethernet" }, 145 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 146 "Farallon PN9000SX Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int ti_probe __P((device_t)); 151 static int ti_attach __P((device_t)); 152 static int ti_detach __P((device_t)); 153 static void ti_txeof __P((struct ti_softc *)); 154 static void ti_rxeof __P((struct ti_softc *)); 155 156 static void ti_stats_update __P((struct ti_softc *)); 157 static int ti_encap __P((struct ti_softc *, struct mbuf *, 158 u_int32_t *)); 159 160 static void ti_intr __P((void *)); 161 static void ti_start __P((struct ifnet *)); 162 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 163 static void ti_init __P((void *)); 164 static void ti_init2 __P((struct ti_softc *)); 165 static void ti_stop __P((struct ti_softc *)); 166 static void ti_watchdog __P((struct ifnet *)); 167 static void ti_shutdown __P((device_t)); 168 static int ti_ifmedia_upd __P((struct ifnet *)); 169 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 172 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 173 int, u_int8_t *)); 174 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 175 176 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 177 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 178 static void ti_setmulti __P((struct ti_softc *)); 179 180 static void ti_mem __P((struct ti_softc *, u_int32_t, 181 u_int32_t, caddr_t)); 182 static void ti_loadfw __P((struct ti_softc *)); 183 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 184 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 185 caddr_t, int)); 186 static void ti_handle_events __P((struct ti_softc *)); 187 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 188 static void *ti_jalloc __P((struct ti_softc *)); 189 static void ti_jfree __P((caddr_t, u_int)); 190 static void ti_jref __P((caddr_t, u_int)); 191 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *)); 192 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *)); 193 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 194 static int ti_init_rx_ring_std __P((struct ti_softc *)); 195 static void ti_free_rx_ring_std __P((struct ti_softc *)); 196 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 197 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 198 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 199 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 200 static void ti_free_tx_ring __P((struct ti_softc *)); 201 static int ti_init_tx_ring __P((struct ti_softc *)); 202 203 static int ti_64bitslot_war __P((struct ti_softc *)); 204 static int ti_chipinit __P((struct ti_softc *)); 205 static int ti_gibinit __P((struct ti_softc *)); 206 207 static device_method_t ti_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, ti_probe), 210 DEVMETHOD(device_attach, ti_attach), 211 DEVMETHOD(device_detach, ti_detach), 212 DEVMETHOD(device_shutdown, ti_shutdown), 213 { 0, 0 } 214 }; 215 216 static driver_t ti_driver = { 217 "ti", 218 ti_methods, 219 sizeof(struct ti_softc) 220 }; 221 222 static devclass_t ti_devclass; 223 224 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0); 225 226 /* 227 * Send an instruction or address to the EEPROM, check for ACK. 228 */ 229 static u_int32_t ti_eeprom_putbyte(sc, byte) 230 struct ti_softc *sc; 231 int byte; 232 { 233 register int i, ack = 0; 234 235 /* 236 * Make sure we're in TX mode. 237 */ 238 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Feed in each bit and stobe the clock. 242 */ 243 for (i = 0x80; i; i >>= 1) { 244 if (byte & i) { 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 246 } else { 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 248 } 249 DELAY(1); 250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 DELAY(1); 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 } 254 255 /* 256 * Turn off TX mode. 257 */ 258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 259 260 /* 261 * Check for ack. 262 */ 263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 266 267 return(ack); 268 } 269 270 /* 271 * Read a byte of data stored in the EEPROM at address 'addr.' 272 * We have to send two address bytes since the EEPROM can hold 273 * more than 256 bytes of data. 274 */ 275 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 276 struct ti_softc *sc; 277 int addr; 278 u_int8_t *dest; 279 { 280 register int i; 281 u_int8_t byte = 0; 282 283 EEPROM_START; 284 285 /* 286 * Send write control code to EEPROM. 287 */ 288 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 289 printf("ti%d: failed to send write command, status: %x\n", 290 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 291 return(1); 292 } 293 294 /* 295 * Send first byte of address of byte we want to read. 296 */ 297 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 298 printf("ti%d: failed to send address, status: %x\n", 299 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return(1); 301 } 302 /* 303 * Send second byte address of byte we want to read. 304 */ 305 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 306 printf("ti%d: failed to send address, status: %x\n", 307 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 EEPROM_STOP; 312 EEPROM_START; 313 /* 314 * Send read control code to EEPROM. 315 */ 316 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 317 printf("ti%d: failed to send read command, status: %x\n", 318 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 319 return(1); 320 } 321 322 /* 323 * Start reading bits from EEPROM. 324 */ 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 326 for (i = 0x80; i; i >>= 1) { 327 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 328 DELAY(1); 329 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 330 byte |= i; 331 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 332 DELAY(1); 333 } 334 335 EEPROM_STOP; 336 337 /* 338 * No ACK generated for read, so just return byte. 339 */ 340 341 *dest = byte; 342 343 return(0); 344 } 345 346 /* 347 * Read a sequence of bytes from the EEPROM. 348 */ 349 static int ti_read_eeprom(sc, dest, off, cnt) 350 struct ti_softc *sc; 351 caddr_t dest; 352 int off; 353 int cnt; 354 { 355 int err = 0, i; 356 u_int8_t byte = 0; 357 358 for (i = 0; i < cnt; i++) { 359 err = ti_eeprom_getbyte(sc, off + i, &byte); 360 if (err) 361 break; 362 *(dest + i) = byte; 363 } 364 365 return(err ? 1 : 0); 366 } 367 368 /* 369 * NIC memory access function. Can be used to either clear a section 370 * of NIC local memory or (if buf is non-NULL) copy data into it. 371 */ 372 static void ti_mem(sc, addr, len, buf) 373 struct ti_softc *sc; 374 u_int32_t addr, len; 375 caddr_t buf; 376 { 377 int segptr, segsize, cnt; 378 caddr_t ti_winbase, ptr; 379 380 segptr = addr; 381 cnt = len; 382 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW); 383 ptr = buf; 384 385 while(cnt) { 386 if (cnt < TI_WINLEN) 387 segsize = cnt; 388 else 389 segsize = TI_WINLEN - (segptr % TI_WINLEN); 390 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 391 if (buf == NULL) 392 bzero((char *)ti_winbase + (segptr & 393 (TI_WINLEN - 1)), segsize); 394 else { 395 bcopy((char *)ptr, (char *)ti_winbase + 396 (segptr & (TI_WINLEN - 1)), segsize); 397 ptr += segsize; 398 } 399 segptr += segsize; 400 cnt -= segsize; 401 } 402 403 return; 404 } 405 406 /* 407 * Load firmware image into the NIC. Check that the firmware revision 408 * is acceptable and see if we want the firmware for the Tigon 1 or 409 * Tigon 2. 410 */ 411 static void ti_loadfw(sc) 412 struct ti_softc *sc; 413 { 414 switch(sc->ti_hwrev) { 415 case TI_HWREV_TIGON: 416 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("ti%d: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 423 tigonFwReleaseMinor, tigonFwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 427 (caddr_t)tigonFwText); 428 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 429 (caddr_t)tigonFwData); 430 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 431 (caddr_t)tigonFwRodata); 432 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 433 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 434 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 435 break; 436 case TI_HWREV_TIGON_II: 437 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 438 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 439 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 440 printf("ti%d: firmware revision mismatch; want " 441 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit, 442 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 443 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 444 tigon2FwReleaseMinor, tigon2FwReleaseFix); 445 return; 446 } 447 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 448 (caddr_t)tigon2FwText); 449 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 450 (caddr_t)tigon2FwData); 451 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 452 (caddr_t)tigon2FwRodata); 453 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 454 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 455 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 456 break; 457 default: 458 printf("ti%d: can't load firmware: unknown hardware rev\n", 459 sc->ti_unit); 460 break; 461 } 462 463 return; 464 } 465 466 /* 467 * Send the NIC a command via the command ring. 468 */ 469 static void ti_cmd(sc, cmd) 470 struct ti_softc *sc; 471 struct ti_cmd_desc *cmd; 472 { 473 u_int32_t index; 474 475 if (sc->ti_rdata->ti_cmd_ring == NULL) 476 return; 477 478 index = sc->ti_cmd_saved_prodidx; 479 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 480 TI_INC(index, TI_CMD_RING_CNT); 481 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 482 sc->ti_cmd_saved_prodidx = index; 483 484 return; 485 } 486 487 /* 488 * Send the NIC an extended command. The 'len' parameter specifies the 489 * number of command slots to include after the initial command. 490 */ 491 static void ti_cmd_ext(sc, cmd, arg, len) 492 struct ti_softc *sc; 493 struct ti_cmd_desc *cmd; 494 caddr_t arg; 495 int len; 496 { 497 u_int32_t index; 498 register int i; 499 500 if (sc->ti_rdata->ti_cmd_ring == NULL) 501 return; 502 503 index = sc->ti_cmd_saved_prodidx; 504 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 505 TI_INC(index, TI_CMD_RING_CNT); 506 for (i = 0; i < len; i++) { 507 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 508 *(u_int32_t *)(&arg[i * 4])); 509 TI_INC(index, TI_CMD_RING_CNT); 510 } 511 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 512 sc->ti_cmd_saved_prodidx = index; 513 514 return; 515 } 516 517 /* 518 * Handle events that have triggered interrupts. 519 */ 520 static void ti_handle_events(sc) 521 struct ti_softc *sc; 522 { 523 struct ti_event_desc *e; 524 525 if (sc->ti_rdata->ti_event_ring == NULL) 526 return; 527 528 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 529 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 530 switch(e->ti_event) { 531 case TI_EV_LINKSTAT_CHANGED: 532 sc->ti_linkstat = e->ti_code; 533 if (e->ti_code == TI_EV_CODE_LINK_UP) 534 printf("ti%d: 10/100 link up\n", sc->ti_unit); 535 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 536 printf("ti%d: gigabit link up\n", sc->ti_unit); 537 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 538 printf("ti%d: link down\n", sc->ti_unit); 539 break; 540 case TI_EV_ERROR: 541 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 542 printf("ti%d: invalid command\n", sc->ti_unit); 543 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 544 printf("ti%d: unknown command\n", sc->ti_unit); 545 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 546 printf("ti%d: bad config data\n", sc->ti_unit); 547 break; 548 case TI_EV_FIRMWARE_UP: 549 ti_init2(sc); 550 break; 551 case TI_EV_STATS_UPDATED: 552 ti_stats_update(sc); 553 break; 554 case TI_EV_RESET_JUMBO_RING: 555 case TI_EV_MCAST_UPDATED: 556 /* Who cares. */ 557 break; 558 default: 559 printf("ti%d: unknown event: %d\n", 560 sc->ti_unit, e->ti_event); 561 break; 562 } 563 /* Advance the consumer index. */ 564 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 565 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 566 } 567 568 return; 569 } 570 571 /* 572 * Memory management for the jumbo receive ring is a pain in the 573 * butt. We need to allocate at least 9018 bytes of space per frame, 574 * _and_ it has to be contiguous (unless you use the extended 575 * jumbo descriptor format). Using malloc() all the time won't 576 * work: malloc() allocates memory in powers of two, which means we 577 * would end up wasting a considerable amount of space by allocating 578 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 579 * to do our own memory management. 580 * 581 * The driver needs to allocate a contiguous chunk of memory at boot 582 * time. We then chop this up ourselves into 9K pieces and use them 583 * as external mbuf storage. 584 * 585 * One issue here is how much memory to allocate. The jumbo ring has 586 * 256 slots in it, but at 9K per slot than can consume over 2MB of 587 * RAM. This is a bit much, especially considering we also need 588 * RAM for the standard ring and mini ring (on the Tigon 2). To 589 * save space, we only actually allocate enough memory for 64 slots 590 * by default, which works out to between 500 and 600K. This can 591 * be tuned by changing a #define in if_tireg.h. 592 */ 593 594 static int ti_alloc_jumbo_mem(sc) 595 struct ti_softc *sc; 596 { 597 caddr_t ptr; 598 register int i; 599 struct ti_jpool_entry *entry; 600 601 /* Grab a big chunk o' storage. */ 602 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF, 603 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 604 605 if (sc->ti_cdata.ti_jumbo_buf == NULL) { 606 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit); 607 return(ENOBUFS); 608 } 609 610 SLIST_INIT(&sc->ti_jfree_listhead); 611 SLIST_INIT(&sc->ti_jinuse_listhead); 612 613 /* 614 * Now divide it up into 9K pieces and save the addresses 615 * in an array. Note that we play an evil trick here by using 616 * the first few bytes in the buffer to hold the the address 617 * of the softc structure for this interface. This is because 618 * ti_jfree() needs it, but it is called by the mbuf management 619 * code which will not pass it to us explicitly. 620 */ 621 ptr = sc->ti_cdata.ti_jumbo_buf; 622 for (i = 0; i < TI_JSLOTS; i++) { 623 u_int64_t **aptr; 624 aptr = (u_int64_t **)ptr; 625 aptr[0] = (u_int64_t *)sc; 626 ptr += sizeof(u_int64_t); 627 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 628 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 629 ptr += (TI_JLEN - sizeof(u_int64_t)); 630 entry = malloc(sizeof(struct ti_jpool_entry), 631 M_DEVBUF, M_NOWAIT); 632 if (entry == NULL) { 633 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 634 sc->ti_cdata.ti_jumbo_buf = NULL; 635 printf("ti%d: no memory for jumbo " 636 "buffer queue!\n", sc->ti_unit); 637 return(ENOBUFS); 638 } 639 entry->slot = i; 640 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 641 } 642 643 return(0); 644 } 645 646 /* 647 * Allocate a jumbo buffer. 648 */ 649 static void *ti_jalloc(sc) 650 struct ti_softc *sc; 651 { 652 struct ti_jpool_entry *entry; 653 654 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 655 656 if (entry == NULL) { 657 printf("ti%d: no free jumbo buffers\n", sc->ti_unit); 658 return(NULL); 659 } 660 661 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 662 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 663 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 664 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 665 } 666 667 /* 668 * Adjust usage count on a jumbo buffer. In general this doesn't 669 * get used much because our jumbo buffers don't get passed around 670 * too much, but it's implemented for correctness. 671 */ 672 static void ti_jref(buf, size) 673 caddr_t buf; 674 u_int size; 675 { 676 struct ti_softc *sc; 677 u_int64_t **aptr; 678 register int i; 679 680 /* Extract the softc struct pointer. */ 681 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 682 sc = (struct ti_softc *)(aptr[0]); 683 684 if (sc == NULL) 685 panic("ti_jref: can't find softc pointer!"); 686 687 if (size != TI_JUMBO_FRAMELEN) 688 panic("ti_jref: adjusting refcount of buf of wrong size!"); 689 690 /* calculate the slot this buffer belongs to */ 691 692 i = ((vm_offset_t)aptr 693 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 694 695 if ((i < 0) || (i >= TI_JSLOTS)) 696 panic("ti_jref: asked to reference buffer " 697 "that we don't manage!"); 698 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 699 panic("ti_jref: buffer already free!"); 700 else 701 sc->ti_cdata.ti_jslots[i].ti_inuse++; 702 703 return; 704 } 705 706 /* 707 * Release a jumbo buffer. 708 */ 709 static void ti_jfree(buf, size) 710 caddr_t buf; 711 u_int size; 712 { 713 struct ti_softc *sc; 714 u_int64_t **aptr; 715 int i; 716 struct ti_jpool_entry *entry; 717 718 /* Extract the softc struct pointer. */ 719 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 720 sc = (struct ti_softc *)(aptr[0]); 721 722 if (sc == NULL) 723 panic("ti_jfree: can't find softc pointer!"); 724 725 if (size != TI_JUMBO_FRAMELEN) 726 panic("ti_jfree: freeing buffer of wrong size!"); 727 728 /* calculate the slot this buffer belongs to */ 729 730 i = ((vm_offset_t)aptr 731 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 732 733 if ((i < 0) || (i >= TI_JSLOTS)) 734 panic("ti_jfree: asked to free buffer that we don't manage!"); 735 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 736 panic("ti_jfree: buffer already free!"); 737 else { 738 sc->ti_cdata.ti_jslots[i].ti_inuse--; 739 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 740 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 741 if (entry == NULL) 742 panic("ti_jfree: buffer not in use!"); 743 entry->slot = i; 744 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, 745 jpool_entries); 746 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, 747 entry, jpool_entries); 748 } 749 } 750 751 return; 752 } 753 754 755 /* 756 * Intialize a standard receive ring descriptor. 757 */ 758 static int ti_newbuf_std(sc, i, m) 759 struct ti_softc *sc; 760 int i; 761 struct mbuf *m; 762 { 763 struct mbuf *m_new = NULL; 764 struct ti_rx_desc *r; 765 766 if (m == NULL) { 767 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 768 if (m_new == NULL) { 769 printf("ti%d: mbuf allocation failed " 770 "-- packet dropped!\n", sc->ti_unit); 771 return(ENOBUFS); 772 } 773 774 MCLGET(m_new, M_DONTWAIT); 775 if (!(m_new->m_flags & M_EXT)) { 776 printf("ti%d: cluster allocation failed " 777 "-- packet dropped!\n", sc->ti_unit); 778 m_freem(m_new); 779 return(ENOBUFS); 780 } 781 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 782 } else { 783 m_new = m; 784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 785 m_new->m_data = m_new->m_ext.ext_buf; 786 } 787 788 m_adj(m_new, ETHER_ALIGN); 789 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 790 r = &sc->ti_rdata->ti_rx_std_ring[i]; 791 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 792 r->ti_type = TI_BDTYPE_RECV_BD; 793 r->ti_flags = 0; 794 if (sc->arpcom.ac_if.if_hwassist) 795 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 796 r->ti_len = m_new->m_len; 797 r->ti_idx = i; 798 799 return(0); 800 } 801 802 /* 803 * Intialize a mini receive ring descriptor. This only applies to 804 * the Tigon 2. 805 */ 806 static int ti_newbuf_mini(sc, i, m) 807 struct ti_softc *sc; 808 int i; 809 struct mbuf *m; 810 { 811 struct mbuf *m_new = NULL; 812 struct ti_rx_desc *r; 813 814 if (m == NULL) { 815 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 816 if (m_new == NULL) { 817 printf("ti%d: mbuf allocation failed " 818 "-- packet dropped!\n", sc->ti_unit); 819 return(ENOBUFS); 820 } 821 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 822 } else { 823 m_new = m; 824 m_new->m_data = m_new->m_pktdat; 825 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 826 } 827 828 m_adj(m_new, ETHER_ALIGN); 829 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 830 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 831 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 832 r->ti_type = TI_BDTYPE_RECV_BD; 833 r->ti_flags = TI_BDFLAG_MINI_RING; 834 if (sc->arpcom.ac_if.if_hwassist) 835 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 836 r->ti_len = m_new->m_len; 837 r->ti_idx = i; 838 839 return(0); 840 } 841 842 /* 843 * Initialize a jumbo receive ring descriptor. This allocates 844 * a jumbo buffer from the pool managed internally by the driver. 845 */ 846 static int ti_newbuf_jumbo(sc, i, m) 847 struct ti_softc *sc; 848 int i; 849 struct mbuf *m; 850 { 851 struct mbuf *m_new = NULL; 852 struct ti_rx_desc *r; 853 854 if (m == NULL) { 855 caddr_t *buf = NULL; 856 857 /* Allocate the mbuf. */ 858 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 859 if (m_new == NULL) { 860 printf("ti%d: mbuf allocation failed " 861 "-- packet dropped!\n", sc->ti_unit); 862 return(ENOBUFS); 863 } 864 865 /* Allocate the jumbo buffer */ 866 buf = ti_jalloc(sc); 867 if (buf == NULL) { 868 m_freem(m_new); 869 printf("ti%d: jumbo allocation failed " 870 "-- packet dropped!\n", sc->ti_unit); 871 return(ENOBUFS); 872 } 873 874 /* Attach the buffer to the mbuf. */ 875 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 876 m_new->m_flags |= M_EXT; 877 m_new->m_len = m_new->m_pkthdr.len = 878 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 879 m_new->m_ext.ext_free = ti_jfree; 880 m_new->m_ext.ext_ref = ti_jref; 881 } else { 882 m_new = m; 883 m_new->m_data = m_new->m_ext.ext_buf; 884 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 885 } 886 887 m_adj(m_new, ETHER_ALIGN); 888 /* Set up the descriptor. */ 889 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 890 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 891 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t)); 892 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 893 r->ti_flags = TI_BDFLAG_JUMBO_RING; 894 if (sc->arpcom.ac_if.if_hwassist) 895 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 896 r->ti_len = m_new->m_len; 897 r->ti_idx = i; 898 899 return(0); 900 } 901 902 /* 903 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 904 * that's 1MB or memory, which is a lot. For now, we fill only the first 905 * 256 ring entries and hope that our CPU is fast enough to keep up with 906 * the NIC. 907 */ 908 static int ti_init_rx_ring_std(sc) 909 struct ti_softc *sc; 910 { 911 register int i; 912 struct ti_cmd_desc cmd; 913 914 for (i = 0; i < TI_SSLOTS; i++) { 915 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 916 return(ENOBUFS); 917 }; 918 919 TI_UPDATE_STDPROD(sc, i - 1); 920 sc->ti_std = i - 1; 921 922 return(0); 923 } 924 925 static void ti_free_rx_ring_std(sc) 926 struct ti_softc *sc; 927 { 928 register int i; 929 930 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 931 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 932 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 933 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 934 } 935 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 936 sizeof(struct ti_rx_desc)); 937 } 938 939 return; 940 } 941 942 static int ti_init_rx_ring_jumbo(sc) 943 struct ti_softc *sc; 944 { 945 register int i; 946 struct ti_cmd_desc cmd; 947 948 for (i = 0; i < (TI_JSLOTS - 20); i++) { 949 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 950 return(ENOBUFS); 951 }; 952 953 TI_UPDATE_JUMBOPROD(sc, i - 1); 954 sc->ti_jumbo = i - 1; 955 956 return(0); 957 } 958 959 static void ti_free_rx_ring_jumbo(sc) 960 struct ti_softc *sc; 961 { 962 register int i; 963 964 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 965 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 966 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 967 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 968 } 969 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 970 sizeof(struct ti_rx_desc)); 971 } 972 973 return; 974 } 975 976 static int ti_init_rx_ring_mini(sc) 977 struct ti_softc *sc; 978 { 979 register int i; 980 981 for (i = 0; i < TI_MSLOTS; i++) { 982 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 983 return(ENOBUFS); 984 }; 985 986 TI_UPDATE_MINIPROD(sc, i - 1); 987 sc->ti_mini = i - 1; 988 989 return(0); 990 } 991 992 static void ti_free_rx_ring_mini(sc) 993 struct ti_softc *sc; 994 { 995 register int i; 996 997 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 998 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 999 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1000 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1001 } 1002 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1003 sizeof(struct ti_rx_desc)); 1004 } 1005 1006 return; 1007 } 1008 1009 static void ti_free_tx_ring(sc) 1010 struct ti_softc *sc; 1011 { 1012 register int i; 1013 1014 if (sc->ti_rdata->ti_tx_ring == NULL) 1015 return; 1016 1017 for (i = 0; i < TI_TX_RING_CNT; i++) { 1018 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1019 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1020 sc->ti_cdata.ti_tx_chain[i] = NULL; 1021 } 1022 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1023 sizeof(struct ti_tx_desc)); 1024 } 1025 1026 return; 1027 } 1028 1029 static int ti_init_tx_ring(sc) 1030 struct ti_softc *sc; 1031 { 1032 sc->ti_txcnt = 0; 1033 sc->ti_tx_saved_considx = 0; 1034 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1035 return(0); 1036 } 1037 1038 /* 1039 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1040 * but we have to support the old way too so that Tigon 1 cards will 1041 * work. 1042 */ 1043 void ti_add_mcast(sc, addr) 1044 struct ti_softc *sc; 1045 struct ether_addr *addr; 1046 { 1047 struct ti_cmd_desc cmd; 1048 u_int16_t *m; 1049 u_int32_t ext[2] = {0, 0}; 1050 1051 m = (u_int16_t *)&addr->octet[0]; 1052 1053 switch(sc->ti_hwrev) { 1054 case TI_HWREV_TIGON: 1055 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1056 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1057 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1058 break; 1059 case TI_HWREV_TIGON_II: 1060 ext[0] = htons(m[0]); 1061 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1062 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1063 break; 1064 default: 1065 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1066 break; 1067 } 1068 1069 return; 1070 } 1071 1072 void ti_del_mcast(sc, addr) 1073 struct ti_softc *sc; 1074 struct ether_addr *addr; 1075 { 1076 struct ti_cmd_desc cmd; 1077 u_int16_t *m; 1078 u_int32_t ext[2] = {0, 0}; 1079 1080 m = (u_int16_t *)&addr->octet[0]; 1081 1082 switch(sc->ti_hwrev) { 1083 case TI_HWREV_TIGON: 1084 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1085 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1086 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1087 break; 1088 case TI_HWREV_TIGON_II: 1089 ext[0] = htons(m[0]); 1090 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1091 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1092 break; 1093 default: 1094 printf("ti%d: unknown hwrev\n", sc->ti_unit); 1095 break; 1096 } 1097 1098 return; 1099 } 1100 1101 /* 1102 * Configure the Tigon's multicast address filter. 1103 * 1104 * The actual multicast table management is a bit of a pain, thanks to 1105 * slight brain damage on the part of both Alteon and us. With our 1106 * multicast code, we are only alerted when the multicast address table 1107 * changes and at that point we only have the current list of addresses: 1108 * we only know the current state, not the previous state, so we don't 1109 * actually know what addresses were removed or added. The firmware has 1110 * state, but we can't get our grubby mits on it, and there is no 'delete 1111 * all multicast addresses' command. Hence, we have to maintain our own 1112 * state so we know what addresses have been programmed into the NIC at 1113 * any given time. 1114 */ 1115 static void ti_setmulti(sc) 1116 struct ti_softc *sc; 1117 { 1118 struct ifnet *ifp; 1119 struct ifmultiaddr *ifma; 1120 struct ti_cmd_desc cmd; 1121 struct ti_mc_entry *mc; 1122 u_int32_t intrs; 1123 1124 ifp = &sc->arpcom.ac_if; 1125 1126 if (ifp->if_flags & IFF_ALLMULTI) { 1127 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1128 return; 1129 } else { 1130 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1131 } 1132 1133 /* Disable interrupts. */ 1134 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1135 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1136 1137 /* First, zot all the existing filters. */ 1138 while (sc->ti_mc_listhead.slh_first != NULL) { 1139 mc = sc->ti_mc_listhead.slh_first; 1140 ti_del_mcast(sc, &mc->mc_addr); 1141 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1142 free(mc, M_DEVBUF); 1143 } 1144 1145 /* Now program new ones. */ 1146 for (ifma = ifp->if_multiaddrs.lh_first; 1147 ifma != NULL; ifma = ifma->ifma_link.le_next) { 1148 if (ifma->ifma_addr->sa_family != AF_LINK) 1149 continue; 1150 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1151 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1152 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1153 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1154 ti_add_mcast(sc, &mc->mc_addr); 1155 } 1156 1157 /* Re-enable interrupts. */ 1158 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1159 1160 return; 1161 } 1162 1163 /* 1164 * Check to see if the BIOS has configured us for a 64 bit slot when 1165 * we aren't actually in one. If we detect this condition, we can work 1166 * around it on the Tigon 2 by setting a bit in the PCI state register, 1167 * but for the Tigon 1 we must give up and abort the interface attach. 1168 */ 1169 static int ti_64bitslot_war(sc) 1170 struct ti_softc *sc; 1171 { 1172 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1173 CSR_WRITE_4(sc, 0x600, 0); 1174 CSR_WRITE_4(sc, 0x604, 0); 1175 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1176 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1177 if (sc->ti_hwrev == TI_HWREV_TIGON) 1178 return(EINVAL); 1179 else { 1180 TI_SETBIT(sc, TI_PCI_STATE, 1181 TI_PCISTATE_32BIT_BUS); 1182 return(0); 1183 } 1184 } 1185 } 1186 1187 return(0); 1188 } 1189 1190 /* 1191 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1192 * self-test results. 1193 */ 1194 static int ti_chipinit(sc) 1195 struct ti_softc *sc; 1196 { 1197 u_int32_t cacheline; 1198 u_int32_t pci_writemax = 0; 1199 1200 /* Initialize link to down state. */ 1201 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1202 1203 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES; 1204 1205 /* Set endianness before we access any non-PCI registers. */ 1206 #if BYTE_ORDER == BIG_ENDIAN 1207 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1208 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1209 #else 1210 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1211 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1212 #endif 1213 1214 /* Check the ROM failed bit to see if self-tests passed. */ 1215 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1216 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit); 1217 return(ENODEV); 1218 } 1219 1220 /* Halt the CPU. */ 1221 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1222 1223 /* Figure out the hardware revision. */ 1224 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1225 case TI_REV_TIGON_I: 1226 sc->ti_hwrev = TI_HWREV_TIGON; 1227 break; 1228 case TI_REV_TIGON_II: 1229 sc->ti_hwrev = TI_HWREV_TIGON_II; 1230 break; 1231 default: 1232 printf("ti%d: unsupported chip revision\n", sc->ti_unit); 1233 return(ENODEV); 1234 } 1235 1236 /* Do special setup for Tigon 2. */ 1237 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1238 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1240 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1241 } 1242 1243 /* Set up the PCI state register. */ 1244 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1245 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1246 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1247 } 1248 1249 /* Clear the read/write max DMA parameters. */ 1250 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1251 TI_PCISTATE_READ_MAXDMA)); 1252 1253 /* Get cache line size. */ 1254 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1255 1256 /* 1257 * If the system has set enabled the PCI memory write 1258 * and invalidate command in the command register, set 1259 * the write max parameter accordingly. This is necessary 1260 * to use MWI with the Tigon 2. 1261 */ 1262 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1263 switch(cacheline) { 1264 case 1: 1265 case 4: 1266 case 8: 1267 case 16: 1268 case 32: 1269 case 64: 1270 break; 1271 default: 1272 /* Disable PCI memory write and invalidate. */ 1273 if (bootverbose) 1274 printf("ti%d: cache line size %d not " 1275 "supported; disabling PCI MWI\n", 1276 sc->ti_unit, cacheline); 1277 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 1278 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 1279 break; 1280 } 1281 } 1282 1283 #ifdef __brokenalpha__ 1284 /* 1285 * From the Alteon sample driver: 1286 * Must insure that we do not cross an 8K (bytes) boundary 1287 * for DMA reads. Our highest limit is 1K bytes. This is a 1288 * restriction on some ALPHA platforms with early revision 1289 * 21174 PCI chipsets, such as the AlphaPC 164lx 1290 */ 1291 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1292 #else 1293 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1294 #endif 1295 1296 /* This sets the min dma param all the way up (0xff). */ 1297 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1298 1299 /* Configure DMA variables. */ 1300 #if BYTE_ORDER == BIG_ENDIAN 1301 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1302 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1303 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1304 TI_OPMODE_DONT_FRAG_JUMBO); 1305 #else 1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1307 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1308 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1309 #endif 1310 1311 /* 1312 * Only allow 1 DMA channel to be active at a time. 1313 * I don't think this is a good idea, but without it 1314 * the firmware racks up lots of nicDmaReadRingFull 1315 * errors. This is not compatible with hardware checksums. 1316 */ 1317 if (sc->arpcom.ac_if.if_hwassist == 0) 1318 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1319 1320 /* Recommended settings from Tigon manual. */ 1321 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1322 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1323 1324 if (ti_64bitslot_war(sc)) { 1325 printf("ti%d: bios thinks we're in a 64 bit slot, " 1326 "but we aren't", sc->ti_unit); 1327 return(EINVAL); 1328 } 1329 1330 return(0); 1331 } 1332 1333 /* 1334 * Initialize the general information block and firmware, and 1335 * start the CPU(s) running. 1336 */ 1337 static int ti_gibinit(sc) 1338 struct ti_softc *sc; 1339 { 1340 struct ti_rcb *rcb; 1341 int i; 1342 struct ifnet *ifp; 1343 1344 ifp = &sc->arpcom.ac_if; 1345 1346 /* Disable interrupts for now. */ 1347 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1348 1349 /* Tell the chip where to find the general information block. */ 1350 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1351 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info)); 1352 1353 /* Load the firmware into SRAM. */ 1354 ti_loadfw(sc); 1355 1356 /* Set up the contents of the general info and ring control blocks. */ 1357 1358 /* Set up the event ring and producer pointer. */ 1359 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1360 1361 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring); 1362 rcb->ti_flags = 0; 1363 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1364 vtophys(&sc->ti_ev_prodidx); 1365 sc->ti_ev_prodidx.ti_idx = 0; 1366 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1367 sc->ti_ev_saved_considx = 0; 1368 1369 /* Set up the command ring and producer mailbox. */ 1370 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1371 1372 sc->ti_rdata->ti_cmd_ring = 1373 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING); 1374 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1375 rcb->ti_flags = 0; 1376 rcb->ti_max_len = 0; 1377 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1378 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1379 } 1380 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1381 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1382 sc->ti_cmd_saved_prodidx = 0; 1383 1384 /* 1385 * Assign the address of the stats refresh buffer. 1386 * We re-use the current stats buffer for this to 1387 * conserve memory. 1388 */ 1389 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1390 vtophys(&sc->ti_rdata->ti_info.ti_stats); 1391 1392 /* Set up the standard receive ring. */ 1393 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1394 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring); 1395 rcb->ti_max_len = TI_FRAMELEN; 1396 rcb->ti_flags = 0; 1397 if (sc->arpcom.ac_if.if_hwassist) 1398 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1399 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1400 #if NVLAN > 0 1401 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1402 #endif 1403 1404 /* Set up the jumbo receive ring. */ 1405 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1406 TI_HOSTADDR(rcb->ti_hostaddr) = 1407 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring); 1408 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1409 rcb->ti_flags = 0; 1410 if (sc->arpcom.ac_if.if_hwassist) 1411 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1412 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1413 #if NVLAN > 0 1414 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1415 #endif 1416 1417 /* 1418 * Set up the mini ring. Only activated on the 1419 * Tigon 2 but the slot in the config block is 1420 * still there on the Tigon 1. 1421 */ 1422 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1423 TI_HOSTADDR(rcb->ti_hostaddr) = 1424 vtophys(&sc->ti_rdata->ti_rx_mini_ring); 1425 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1426 if (sc->ti_hwrev == TI_HWREV_TIGON) 1427 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1428 else 1429 rcb->ti_flags = 0; 1430 if (sc->arpcom.ac_if.if_hwassist) 1431 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1432 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1433 #if NVLAN > 0 1434 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1435 #endif 1436 1437 /* 1438 * Set up the receive return ring. 1439 */ 1440 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1441 TI_HOSTADDR(rcb->ti_hostaddr) = 1442 vtophys(&sc->ti_rdata->ti_rx_return_ring); 1443 rcb->ti_flags = 0; 1444 rcb->ti_max_len = TI_RETURN_RING_CNT; 1445 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1446 vtophys(&sc->ti_return_prodidx); 1447 1448 /* 1449 * Set up the tx ring. Note: for the Tigon 2, we have the option 1450 * of putting the transmit ring in the host's address space and 1451 * letting the chip DMA it instead of leaving the ring in the NIC's 1452 * memory and accessing it through the shared memory region. We 1453 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1454 * so we have to revert to the shared memory scheme if we detect 1455 * a Tigon 1 chip. 1456 */ 1457 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1458 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1459 sc->ti_rdata->ti_tx_ring_nic = 1460 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1461 } 1462 bzero((char *)sc->ti_rdata->ti_tx_ring, 1463 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1464 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1465 if (sc->ti_hwrev == TI_HWREV_TIGON) 1466 rcb->ti_flags = 0; 1467 else 1468 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1469 #if NVLAN > 0 1470 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1471 #endif 1472 if (sc->arpcom.ac_if.if_hwassist) 1473 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1474 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 1475 rcb->ti_max_len = TI_TX_RING_CNT; 1476 if (sc->ti_hwrev == TI_HWREV_TIGON) 1477 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1478 else 1479 TI_HOSTADDR(rcb->ti_hostaddr) = 1480 vtophys(&sc->ti_rdata->ti_tx_ring); 1481 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1482 vtophys(&sc->ti_tx_considx); 1483 1484 /* Set up tuneables */ 1485 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1486 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1487 (sc->ti_rx_coal_ticks / 10)); 1488 else 1489 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1490 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1491 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1492 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1493 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1494 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1495 1496 /* Turn interrupts on. */ 1497 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1498 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1499 1500 /* Start CPU. */ 1501 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1502 1503 return(0); 1504 } 1505 1506 /* 1507 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1508 * against our list and return its name if we find a match. 1509 */ 1510 static int ti_probe(dev) 1511 device_t dev; 1512 { 1513 struct ti_type *t; 1514 1515 t = ti_devs; 1516 1517 while(t->ti_name != NULL) { 1518 if ((pci_get_vendor(dev) == t->ti_vid) && 1519 (pci_get_device(dev) == t->ti_did)) { 1520 device_set_desc(dev, t->ti_name); 1521 return(0); 1522 } 1523 t++; 1524 } 1525 1526 return(ENXIO); 1527 } 1528 1529 static int ti_attach(dev) 1530 device_t dev; 1531 { 1532 int s; 1533 u_int32_t command; 1534 struct ifnet *ifp; 1535 struct ti_softc *sc; 1536 int unit, error = 0, rid; 1537 1538 s = splimp(); 1539 1540 sc = device_get_softc(dev); 1541 unit = device_get_unit(dev); 1542 bzero(sc, sizeof(struct ti_softc)); 1543 1544 /* 1545 * Map control/status registers. 1546 */ 1547 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1548 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1549 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1550 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1551 1552 if (!(command & PCIM_CMD_MEMEN)) { 1553 printf("ti%d: failed to enable memory mapping!\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 rid = TI_PCI_LOMEM; 1559 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1560 0, ~0, 1, RF_ACTIVE); 1561 1562 if (sc->ti_res == NULL) { 1563 printf ("ti%d: couldn't map memory\n", unit); 1564 error = ENXIO; 1565 goto fail; 1566 } 1567 1568 sc->ti_btag = rman_get_bustag(sc->ti_res); 1569 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 1570 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res); 1571 1572 /* 1573 * XXX FIXME: rman_get_virtual() on the alpha is currently 1574 * broken and returns a physical address instead of a kernel 1575 * virtual address. Consequently, we need to do a little 1576 * extra mangling of the vhandle on the alpha. This should 1577 * eventually be fixed! The whole idea here is to get rid 1578 * of platform dependencies. 1579 */ 1580 #ifdef __alpha__ 1581 if (pci_cvt_to_bwx(sc->ti_vhandle)) 1582 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle); 1583 else 1584 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle); 1585 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle); 1586 #endif 1587 1588 /* Allocate interrupt */ 1589 rid = 0; 1590 1591 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1592 RF_SHAREABLE | RF_ACTIVE); 1593 1594 if (sc->ti_irq == NULL) { 1595 printf("ti%d: couldn't map interrupt\n", unit); 1596 error = ENXIO; 1597 goto fail; 1598 } 1599 1600 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET, 1601 ti_intr, sc, &sc->ti_intrhand); 1602 1603 if (error) { 1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1605 bus_release_resource(dev, SYS_RES_MEMORY, 1606 TI_PCI_LOMEM, sc->ti_res); 1607 printf("ti%d: couldn't set up irq\n", unit); 1608 goto fail; 1609 } 1610 1611 sc->ti_unit = unit; 1612 1613 if (ti_chipinit(sc)) { 1614 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1615 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1617 bus_release_resource(dev, SYS_RES_MEMORY, 1618 TI_PCI_LOMEM, sc->ti_res); 1619 error = ENXIO; 1620 goto fail; 1621 } 1622 1623 /* Zero out the NIC's on-board SRAM. */ 1624 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1625 1626 /* Init again -- zeroing memory may have clobbered some registers. */ 1627 if (ti_chipinit(sc)) { 1628 printf("ti%d: chip initialization failed\n", sc->ti_unit); 1629 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1630 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1631 bus_release_resource(dev, SYS_RES_MEMORY, 1632 TI_PCI_LOMEM, sc->ti_res); 1633 error = ENXIO; 1634 goto fail; 1635 } 1636 1637 /* 1638 * Get station address from the EEPROM. Note: the manual states 1639 * that the MAC address is at offset 0x8c, however the data is 1640 * stored as two longwords (since that's how it's loaded into 1641 * the NIC). This means the MAC address is actually preceeded 1642 * by two zero bytes. We need to skip over those. 1643 */ 1644 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1645 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1646 printf("ti%d: failed to read station address\n", unit); 1647 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1648 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1649 bus_release_resource(dev, SYS_RES_MEMORY, 1650 TI_PCI_LOMEM, sc->ti_res); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 1655 /* 1656 * A Tigon chip was detected. Inform the world. 1657 */ 1658 printf("ti%d: Ethernet address: %6D\n", unit, 1659 sc->arpcom.ac_enaddr, ":"); 1660 1661 /* Allocate the general information block and ring buffers. */ 1662 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF, 1663 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1664 1665 if (sc->ti_rdata == NULL) { 1666 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1668 bus_release_resource(dev, SYS_RES_MEMORY, 1669 TI_PCI_LOMEM, sc->ti_res); 1670 error = ENXIO; 1671 printf("ti%d: no memory for list buffers!\n", sc->ti_unit); 1672 goto fail; 1673 } 1674 1675 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1676 1677 /* Try to allocate memory for jumbo buffers. */ 1678 if (ti_alloc_jumbo_mem(sc)) { 1679 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit); 1680 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1681 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1682 bus_release_resource(dev, SYS_RES_MEMORY, 1683 TI_PCI_LOMEM, sc->ti_res); 1684 free(sc->ti_rdata, M_DEVBUF); 1685 error = ENXIO; 1686 goto fail; 1687 } 1688 1689 /* Set default tuneable values. */ 1690 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1691 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1692 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1693 sc->ti_rx_max_coal_bds = 64; 1694 sc->ti_tx_max_coal_bds = 128; 1695 sc->ti_tx_buf_ratio = 21; 1696 1697 /* Set up ifnet structure */ 1698 ifp = &sc->arpcom.ac_if; 1699 ifp->if_softc = sc; 1700 ifp->if_unit = sc->ti_unit; 1701 ifp->if_name = "ti"; 1702 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1703 ifp->if_ioctl = ti_ioctl; 1704 ifp->if_output = ether_output; 1705 ifp->if_start = ti_start; 1706 ifp->if_watchdog = ti_watchdog; 1707 ifp->if_init = ti_init; 1708 ifp->if_mtu = ETHERMTU; 1709 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1710 1711 /* Set up ifmedia support. */ 1712 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1713 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1714 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1715 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1716 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1717 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1718 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1719 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1720 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1721 1722 /* 1723 * Call MI attach routines. 1724 */ 1725 if_attach(ifp); 1726 ether_ifattach(ifp); 1727 1728 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1729 1730 fail: 1731 splx(s); 1732 1733 return(error); 1734 } 1735 1736 static int ti_detach(dev) 1737 device_t dev; 1738 { 1739 struct ti_softc *sc; 1740 struct ifnet *ifp; 1741 int s; 1742 1743 s = splimp(); 1744 1745 sc = device_get_softc(dev); 1746 ifp = &sc->arpcom.ac_if; 1747 1748 if_detach(ifp); 1749 ti_stop(sc); 1750 1751 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 1752 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 1753 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res); 1754 1755 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 1756 free(sc->ti_rdata, M_DEVBUF); 1757 ifmedia_removeall(&sc->ifmedia); 1758 1759 splx(s); 1760 1761 return(0); 1762 } 1763 1764 /* 1765 * Frame reception handling. This is called if there's a frame 1766 * on the receive return list. 1767 * 1768 * Note: we have to be able to handle three possibilities here: 1769 * 1) the frame is from the mini receive ring (can only happen) 1770 * on Tigon 2 boards) 1771 * 2) the frame is from the jumbo recieve ring 1772 * 3) the frame is from the standard receive ring 1773 */ 1774 1775 static void ti_rxeof(sc) 1776 struct ti_softc *sc; 1777 { 1778 struct ifnet *ifp; 1779 struct ti_cmd_desc cmd; 1780 1781 ifp = &sc->arpcom.ac_if; 1782 1783 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1784 struct ti_rx_desc *cur_rx; 1785 u_int32_t rxidx; 1786 struct ether_header *eh; 1787 struct mbuf *m = NULL; 1788 #if NVLAN > 0 1789 u_int16_t vlan_tag = 0; 1790 int have_tag = 0; 1791 #endif 1792 1793 cur_rx = 1794 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1795 rxidx = cur_rx->ti_idx; 1796 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1797 1798 #if NVLAN > 0 1799 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1800 have_tag = 1; 1801 vlan_tag = cur_rx->ti_vlan_tag; 1802 } 1803 #endif 1804 1805 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1806 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1807 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1808 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1809 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1810 ifp->if_ierrors++; 1811 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1812 continue; 1813 } 1814 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 1815 ifp->if_ierrors++; 1816 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1817 continue; 1818 } 1819 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1820 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1821 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1822 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1823 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1824 ifp->if_ierrors++; 1825 ti_newbuf_mini(sc, sc->ti_mini, m); 1826 continue; 1827 } 1828 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 1829 ifp->if_ierrors++; 1830 ti_newbuf_mini(sc, sc->ti_mini, m); 1831 continue; 1832 } 1833 } else { 1834 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1835 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1836 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1837 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1838 ifp->if_ierrors++; 1839 ti_newbuf_std(sc, sc->ti_std, m); 1840 continue; 1841 } 1842 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 1843 ifp->if_ierrors++; 1844 ti_newbuf_std(sc, sc->ti_std, m); 1845 continue; 1846 } 1847 } 1848 1849 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1850 ifp->if_ipackets++; 1851 eh = mtod(m, struct ether_header *); 1852 m->m_pkthdr.rcvif = ifp; 1853 1854 /* 1855 * Handle BPF listeners. Let the BPF user see the packet, but 1856 * don't pass it up to the ether_input() layer unless it's 1857 * a broadcast packet, multicast packet, matches our ethernet 1858 * address or the interface is in promiscuous mode. 1859 */ 1860 if (ifp->if_bpf) { 1861 bpf_mtap(ifp, m); 1862 if (ifp->if_flags & IFF_PROMISC && 1863 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1864 ETHER_ADDR_LEN) && 1865 (eh->ether_dhost[0] & 1) == 0)) { 1866 m_freem(m); 1867 continue; 1868 } 1869 } 1870 1871 /* Remove header from mbuf and pass it on. */ 1872 m_adj(m, sizeof(struct ether_header)); 1873 1874 if (ifp->if_hwassist) { 1875 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1876 CSUM_DATA_VALID; 1877 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 1878 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1879 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 1880 } 1881 1882 #if NVLAN > 0 1883 /* 1884 * If we received a packet with a vlan tag, pass it 1885 * to vlan_input() instead of ether_input(). 1886 */ 1887 if (have_tag) { 1888 vlan_input_tag(eh, m, vlan_tag); 1889 have_tag = vlan_tag = 0; 1890 continue; 1891 } 1892 #endif 1893 ether_input(ifp, eh, m); 1894 } 1895 1896 /* Only necessary on the Tigon 1. */ 1897 if (sc->ti_hwrev == TI_HWREV_TIGON) 1898 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1899 sc->ti_rx_saved_considx); 1900 1901 TI_UPDATE_STDPROD(sc, sc->ti_std); 1902 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1903 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1904 1905 return; 1906 } 1907 1908 static void ti_txeof(sc) 1909 struct ti_softc *sc; 1910 { 1911 struct ti_tx_desc *cur_tx = NULL; 1912 struct ifnet *ifp; 1913 1914 ifp = &sc->arpcom.ac_if; 1915 1916 /* 1917 * Go through our tx ring and free mbufs for those 1918 * frames that have been sent. 1919 */ 1920 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 1921 u_int32_t idx = 0; 1922 1923 idx = sc->ti_tx_saved_considx; 1924 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1925 if (idx > 383) 1926 CSR_WRITE_4(sc, TI_WINBASE, 1927 TI_TX_RING_BASE + 6144); 1928 else if (idx > 255) 1929 CSR_WRITE_4(sc, TI_WINBASE, 1930 TI_TX_RING_BASE + 4096); 1931 else if (idx > 127) 1932 CSR_WRITE_4(sc, TI_WINBASE, 1933 TI_TX_RING_BASE + 2048); 1934 else 1935 CSR_WRITE_4(sc, TI_WINBASE, 1936 TI_TX_RING_BASE); 1937 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 1938 } else 1939 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 1940 if (cur_tx->ti_flags & TI_BDFLAG_END) 1941 ifp->if_opackets++; 1942 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 1943 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 1944 sc->ti_cdata.ti_tx_chain[idx] = NULL; 1945 } 1946 sc->ti_txcnt--; 1947 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 1948 ifp->if_timer = 0; 1949 } 1950 1951 if (cur_tx != NULL) 1952 ifp->if_flags &= ~IFF_OACTIVE; 1953 1954 return; 1955 } 1956 1957 static void ti_intr(xsc) 1958 void *xsc; 1959 { 1960 struct ti_softc *sc; 1961 struct ifnet *ifp; 1962 1963 sc = xsc; 1964 ifp = &sc->arpcom.ac_if; 1965 1966 #ifdef notdef 1967 /* Avoid this for now -- checking this register is expensive. */ 1968 /* Make sure this is really our interrupt. */ 1969 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 1970 return; 1971 #endif 1972 1973 /* Ack interrupt and stop others from occuring. */ 1974 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1975 1976 if (ifp->if_flags & IFF_RUNNING) { 1977 /* Check RX return ring producer/consumer */ 1978 ti_rxeof(sc); 1979 1980 /* Check TX ring producer/consumer */ 1981 ti_txeof(sc); 1982 } 1983 1984 ti_handle_events(sc); 1985 1986 /* Re-enable interrupts. */ 1987 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1988 1989 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1990 ti_start(ifp); 1991 1992 return; 1993 } 1994 1995 static void ti_stats_update(sc) 1996 struct ti_softc *sc; 1997 { 1998 struct ifnet *ifp; 1999 2000 ifp = &sc->arpcom.ac_if; 2001 2002 ifp->if_collisions += 2003 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2004 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2005 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2006 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2007 ifp->if_collisions; 2008 2009 return; 2010 } 2011 2012 /* 2013 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2014 * pointers to descriptors. 2015 */ 2016 static int ti_encap(sc, m_head, txidx) 2017 struct ti_softc *sc; 2018 struct mbuf *m_head; 2019 u_int32_t *txidx; 2020 { 2021 struct ti_tx_desc *f = NULL; 2022 struct mbuf *m; 2023 u_int32_t frag, cur, cnt = 0; 2024 u_int16_t csum_flags = 0; 2025 #if NVLAN > 0 2026 struct ifvlan *ifv = NULL; 2027 2028 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2029 m_head->m_pkthdr.rcvif != NULL && 2030 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2031 ifv = m_head->m_pkthdr.rcvif->if_softc; 2032 #endif 2033 2034 m = m_head; 2035 cur = frag = *txidx; 2036 2037 if (m_head->m_pkthdr.csum_flags) { 2038 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2039 csum_flags |= TI_BDFLAG_IP_CKSUM; 2040 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2041 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2042 if (m_head->m_flags & M_LASTFRAG) 2043 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2044 else if (m_head->m_flags & M_FRAG) 2045 csum_flags |= TI_BDFLAG_IP_FRAG; 2046 } 2047 /* 2048 * Start packing the mbufs in this chain into 2049 * the fragment pointers. Stop when we run out 2050 * of fragments or hit the end of the mbuf chain. 2051 */ 2052 for (m = m_head; m != NULL; m = m->m_next) { 2053 if (m->m_len != 0) { 2054 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2055 if (frag > 383) 2056 CSR_WRITE_4(sc, TI_WINBASE, 2057 TI_TX_RING_BASE + 6144); 2058 else if (frag > 255) 2059 CSR_WRITE_4(sc, TI_WINBASE, 2060 TI_TX_RING_BASE + 4096); 2061 else if (frag > 127) 2062 CSR_WRITE_4(sc, TI_WINBASE, 2063 TI_TX_RING_BASE + 2048); 2064 else 2065 CSR_WRITE_4(sc, TI_WINBASE, 2066 TI_TX_RING_BASE); 2067 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2068 } else 2069 f = &sc->ti_rdata->ti_tx_ring[frag]; 2070 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2071 break; 2072 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t)); 2073 f->ti_len = m->m_len; 2074 f->ti_flags = csum_flags; 2075 #if NVLAN > 0 2076 if (ifv != NULL) { 2077 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2078 f->ti_vlan_tag = ifv->ifv_tag; 2079 } else { 2080 f->ti_vlan_tag = 0; 2081 } 2082 #endif 2083 /* 2084 * Sanity check: avoid coming within 16 descriptors 2085 * of the end of the ring. 2086 */ 2087 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2088 return(ENOBUFS); 2089 cur = frag; 2090 TI_INC(frag, TI_TX_RING_CNT); 2091 cnt++; 2092 } 2093 } 2094 2095 if (m != NULL) 2096 return(ENOBUFS); 2097 2098 if (frag == sc->ti_tx_saved_considx) 2099 return(ENOBUFS); 2100 2101 if (sc->ti_hwrev == TI_HWREV_TIGON) 2102 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2103 TI_BDFLAG_END; 2104 else 2105 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2106 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2107 sc->ti_txcnt += cnt; 2108 2109 *txidx = frag; 2110 2111 return(0); 2112 } 2113 2114 /* 2115 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2116 * to the mbuf data regions directly in the transmit descriptors. 2117 */ 2118 static void ti_start(ifp) 2119 struct ifnet *ifp; 2120 { 2121 struct ti_softc *sc; 2122 struct mbuf *m_head = NULL; 2123 u_int32_t prodidx = 0; 2124 2125 sc = ifp->if_softc; 2126 2127 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2128 2129 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2130 IF_DEQUEUE(&ifp->if_snd, m_head); 2131 if (m_head == NULL) 2132 break; 2133 2134 /* 2135 * XXX 2136 * safety overkill. If this is a fragmented packet chain 2137 * with delayed TCP/UDP checksums, then only encapsulate 2138 * it if we have enough descriptors to handle the entire 2139 * chain at once. 2140 * (paranoia -- may not actually be needed) 2141 */ 2142 if (m_head->m_flags & M_FIRSTFRAG && 2143 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2144 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 2145 m_head->m_pkthdr.csum_data + 16) { 2146 IF_PREPEND(&ifp->if_snd, m_head); 2147 ifp->if_flags |= IFF_OACTIVE; 2148 break; 2149 } 2150 } 2151 2152 /* 2153 * Pack the data into the transmit ring. If we 2154 * don't have room, set the OACTIVE flag and wait 2155 * for the NIC to drain the ring. 2156 */ 2157 if (ti_encap(sc, m_head, &prodidx)) { 2158 IF_PREPEND(&ifp->if_snd, m_head); 2159 ifp->if_flags |= IFF_OACTIVE; 2160 break; 2161 } 2162 2163 /* 2164 * If there's a BPF listener, bounce a copy of this frame 2165 * to him. 2166 */ 2167 if (ifp->if_bpf) 2168 bpf_mtap(ifp, m_head); 2169 } 2170 2171 /* Transmit */ 2172 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2173 2174 /* 2175 * Set a timeout in case the chip goes out to lunch. 2176 */ 2177 ifp->if_timer = 5; 2178 2179 return; 2180 } 2181 2182 static void ti_init(xsc) 2183 void *xsc; 2184 { 2185 struct ti_softc *sc = xsc; 2186 int s; 2187 2188 s = splimp(); 2189 2190 /* Cancel pending I/O and flush buffers. */ 2191 ti_stop(sc); 2192 2193 /* Init the gen info block, ring control blocks and firmware. */ 2194 if (ti_gibinit(sc)) { 2195 printf("ti%d: initialization failure\n", sc->ti_unit); 2196 splx(s); 2197 return; 2198 } 2199 2200 splx(s); 2201 2202 return; 2203 } 2204 2205 static void ti_init2(sc) 2206 struct ti_softc *sc; 2207 { 2208 struct ti_cmd_desc cmd; 2209 struct ifnet *ifp; 2210 u_int16_t *m; 2211 struct ifmedia *ifm; 2212 int tmp; 2213 2214 ifp = &sc->arpcom.ac_if; 2215 2216 /* Specify MTU and interface index. */ 2217 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit); 2218 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2219 ETHER_HDR_LEN + ETHER_CRC_LEN); 2220 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2221 2222 /* Load our MAC address. */ 2223 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2224 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0])); 2225 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2])); 2226 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2227 2228 /* Enable or disable promiscuous mode as needed. */ 2229 if (ifp->if_flags & IFF_PROMISC) { 2230 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2231 } else { 2232 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2233 } 2234 2235 /* Program multicast filter. */ 2236 ti_setmulti(sc); 2237 2238 /* 2239 * If this is a Tigon 1, we should tell the 2240 * firmware to use software packet filtering. 2241 */ 2242 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2243 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2244 } 2245 2246 /* Init RX ring. */ 2247 ti_init_rx_ring_std(sc); 2248 2249 /* Init jumbo RX ring. */ 2250 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2251 ti_init_rx_ring_jumbo(sc); 2252 2253 /* 2254 * If this is a Tigon 2, we can also configure the 2255 * mini ring. 2256 */ 2257 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2258 ti_init_rx_ring_mini(sc); 2259 2260 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2261 sc->ti_rx_saved_considx = 0; 2262 2263 /* Init TX ring. */ 2264 ti_init_tx_ring(sc); 2265 2266 /* Tell firmware we're alive. */ 2267 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2268 2269 /* Enable host interrupts. */ 2270 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2271 2272 ifp->if_flags |= IFF_RUNNING; 2273 ifp->if_flags &= ~IFF_OACTIVE; 2274 2275 /* 2276 * Make sure to set media properly. We have to do this 2277 * here since we have to issue commands in order to set 2278 * the link negotiation and we can't issue commands until 2279 * the firmware is running. 2280 */ 2281 ifm = &sc->ifmedia; 2282 tmp = ifm->ifm_media; 2283 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2284 ti_ifmedia_upd(ifp); 2285 ifm->ifm_media = tmp; 2286 2287 return; 2288 } 2289 2290 /* 2291 * Set media options. 2292 */ 2293 static int ti_ifmedia_upd(ifp) 2294 struct ifnet *ifp; 2295 { 2296 struct ti_softc *sc; 2297 struct ifmedia *ifm; 2298 struct ti_cmd_desc cmd; 2299 2300 sc = ifp->if_softc; 2301 ifm = &sc->ifmedia; 2302 2303 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2304 return(EINVAL); 2305 2306 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2307 case IFM_AUTO: 2308 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2309 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2310 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2311 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2312 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2313 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2314 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2315 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2316 break; 2317 case IFM_1000_SX: 2318 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2319 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2320 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2321 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2322 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2323 break; 2324 case IFM_100_FX: 2325 case IFM_10_FL: 2326 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2327 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2328 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2329 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2330 } else { 2331 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2332 } 2333 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2334 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2335 } else { 2336 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2337 } 2338 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2339 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2340 break; 2341 } 2342 2343 return(0); 2344 } 2345 2346 /* 2347 * Report current media status. 2348 */ 2349 static void ti_ifmedia_sts(ifp, ifmr) 2350 struct ifnet *ifp; 2351 struct ifmediareq *ifmr; 2352 { 2353 struct ti_softc *sc; 2354 2355 sc = ifp->if_softc; 2356 2357 ifmr->ifm_status = IFM_AVALID; 2358 ifmr->ifm_active = IFM_ETHER; 2359 2360 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2361 return; 2362 2363 ifmr->ifm_status |= IFM_ACTIVE; 2364 2365 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2366 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2367 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2368 u_int32_t media; 2369 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2370 if (media & TI_LNK_100MB) 2371 ifmr->ifm_active |= IFM_100_FX; 2372 if (media & TI_LNK_10MB) 2373 ifmr->ifm_active |= IFM_10_FL; 2374 if (media & TI_LNK_FULL_DUPLEX) 2375 ifmr->ifm_active |= IFM_FDX; 2376 if (media & TI_LNK_HALF_DUPLEX) 2377 ifmr->ifm_active |= IFM_HDX; 2378 } 2379 2380 return; 2381 } 2382 2383 static int ti_ioctl(ifp, command, data) 2384 struct ifnet *ifp; 2385 u_long command; 2386 caddr_t data; 2387 { 2388 struct ti_softc *sc = ifp->if_softc; 2389 struct ifreq *ifr = (struct ifreq *) data; 2390 int s, error = 0; 2391 struct ti_cmd_desc cmd; 2392 2393 s = splimp(); 2394 2395 switch(command) { 2396 case SIOCSIFADDR: 2397 case SIOCGIFADDR: 2398 error = ether_ioctl(ifp, command, data); 2399 break; 2400 case SIOCSIFMTU: 2401 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2402 error = EINVAL; 2403 else { 2404 ifp->if_mtu = ifr->ifr_mtu; 2405 ti_init(sc); 2406 } 2407 break; 2408 case SIOCSIFFLAGS: 2409 if (ifp->if_flags & IFF_UP) { 2410 /* 2411 * If only the state of the PROMISC flag changed, 2412 * then just use the 'set promisc mode' command 2413 * instead of reinitializing the entire NIC. Doing 2414 * a full re-init means reloading the firmware and 2415 * waiting for it to start up, which may take a 2416 * second or two. 2417 */ 2418 if (ifp->if_flags & IFF_RUNNING && 2419 ifp->if_flags & IFF_PROMISC && 2420 !(sc->ti_if_flags & IFF_PROMISC)) { 2421 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2422 TI_CMD_CODE_PROMISC_ENB, 0); 2423 } else if (ifp->if_flags & IFF_RUNNING && 2424 !(ifp->if_flags & IFF_PROMISC) && 2425 sc->ti_if_flags & IFF_PROMISC) { 2426 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2427 TI_CMD_CODE_PROMISC_DIS, 0); 2428 } else 2429 ti_init(sc); 2430 } else { 2431 if (ifp->if_flags & IFF_RUNNING) { 2432 ti_stop(sc); 2433 } 2434 } 2435 sc->ti_if_flags = ifp->if_flags; 2436 error = 0; 2437 break; 2438 case SIOCADDMULTI: 2439 case SIOCDELMULTI: 2440 if (ifp->if_flags & IFF_RUNNING) { 2441 ti_setmulti(sc); 2442 error = 0; 2443 } 2444 break; 2445 case SIOCSIFMEDIA: 2446 case SIOCGIFMEDIA: 2447 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2448 break; 2449 default: 2450 error = EINVAL; 2451 break; 2452 } 2453 2454 (void)splx(s); 2455 2456 return(error); 2457 } 2458 2459 static void ti_watchdog(ifp) 2460 struct ifnet *ifp; 2461 { 2462 struct ti_softc *sc; 2463 2464 sc = ifp->if_softc; 2465 2466 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit); 2467 ti_stop(sc); 2468 ti_init(sc); 2469 2470 ifp->if_oerrors++; 2471 2472 return; 2473 } 2474 2475 /* 2476 * Stop the adapter and free any mbufs allocated to the 2477 * RX and TX lists. 2478 */ 2479 static void ti_stop(sc) 2480 struct ti_softc *sc; 2481 { 2482 struct ifnet *ifp; 2483 struct ti_cmd_desc cmd; 2484 2485 ifp = &sc->arpcom.ac_if; 2486 2487 /* Disable host interrupts. */ 2488 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2489 /* 2490 * Tell firmware we're shutting down. 2491 */ 2492 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2493 2494 /* Halt and reinitialize. */ 2495 ti_chipinit(sc); 2496 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2497 ti_chipinit(sc); 2498 2499 /* Free the RX lists. */ 2500 ti_free_rx_ring_std(sc); 2501 2502 /* Free jumbo RX list. */ 2503 ti_free_rx_ring_jumbo(sc); 2504 2505 /* Free mini RX list. */ 2506 ti_free_rx_ring_mini(sc); 2507 2508 /* Free TX buffers. */ 2509 ti_free_tx_ring(sc); 2510 2511 sc->ti_ev_prodidx.ti_idx = 0; 2512 sc->ti_return_prodidx.ti_idx = 0; 2513 sc->ti_tx_considx.ti_idx = 0; 2514 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2515 2516 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2517 2518 return; 2519 } 2520 2521 /* 2522 * Stop all chip I/O so that the kernel's probe routines don't 2523 * get confused by errant DMAs when rebooting. 2524 */ 2525 static void ti_shutdown(dev) 2526 device_t dev; 2527 { 2528 struct ti_softc *sc; 2529 2530 sc = device_get_softc(dev); 2531 2532 ti_chipinit(sc); 2533 2534 return; 2535 } 2536