xref: /freebsd/sys/dev/ti/if_ti.c (revision 0e97acdf58fe27b09c4824a474b0344daf997c5f)
1 /*-
2  * Copyright (c) 1997, 1998, 1999
3  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 /*
34  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
35  * Manuals, sample driver and firmware source kits are available
36  * from http://www.alteon.com/support/openkits.
37  *
38  * Written by Bill Paul <wpaul@ctr.columbia.edu>
39  * Electrical Engineering Department
40  * Columbia University, New York City
41  */
42 
43 /*
44  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
45  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
46  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
47  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
48  * filtering and jumbo (9014 byte) frames. The hardware is largely
49  * controlled by firmware, which must be loaded into the NIC during
50  * initialization.
51  *
52  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
53  * revision, which supports new features such as extended commands,
54  * extended jumbo receive ring desciptors and a mini receive ring.
55  *
56  * Alteon Networks is to be commended for releasing such a vast amount
57  * of development material for the Tigon NIC without requiring an NDA
58  * (although they really should have done it a long time ago). With
59  * any luck, the other vendors will finally wise up and follow Alteon's
60  * stellar example.
61  *
62  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
63  * this driver by #including it as a C header file. This bloats the
64  * driver somewhat, but it's the easiest method considering that the
65  * driver code and firmware code need to be kept in sync. The source
66  * for the firmware is not provided with the FreeBSD distribution since
67  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
68  *
69  * The following people deserve special thanks:
70  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
71  *   for testing
72  * - Raymond Lee of Netgear, for providing a pair of Netgear
73  *   GA620 Tigon 2 boards for testing
74  * - Ulf Zimmermann, for bringing the GA260 to my attention and
75  *   convincing me to write this driver.
76  * - Andrew Gallatin for providing FreeBSD/Alpha support.
77  */
78 
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
81 
82 #include "opt_ti.h"
83 
84 #include <sys/param.h>
85 #include <sys/systm.h>
86 #include <sys/sockio.h>
87 #include <sys/mbuf.h>
88 #include <sys/malloc.h>
89 #include <sys/kernel.h>
90 #include <sys/module.h>
91 #include <sys/socket.h>
92 #include <sys/queue.h>
93 #include <sys/conf.h>
94 #include <sys/sf_buf.h>
95 
96 #include <net/if.h>
97 #include <net/if_var.h>
98 #include <net/if_arp.h>
99 #include <net/ethernet.h>
100 #include <net/if_dl.h>
101 #include <net/if_media.h>
102 #include <net/if_types.h>
103 #include <net/if_vlan_var.h>
104 
105 #include <net/bpf.h>
106 
107 #include <netinet/in_systm.h>
108 #include <netinet/in.h>
109 #include <netinet/ip.h>
110 
111 #include <machine/bus.h>
112 #include <machine/resource.h>
113 #include <sys/bus.h>
114 #include <sys/rman.h>
115 
116 #ifdef TI_SF_BUF_JUMBO
117 #include <vm/vm.h>
118 #include <vm/vm_page.h>
119 #endif
120 
121 #include <dev/pci/pcireg.h>
122 #include <dev/pci/pcivar.h>
123 
124 #include <sys/tiio.h>
125 #include <dev/ti/if_tireg.h>
126 #include <dev/ti/ti_fw.h>
127 #include <dev/ti/ti_fw2.h>
128 
129 #include <sys/sysctl.h>
130 
131 #define TI_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
132 /*
133  * We can only turn on header splitting if we're using extended receive
134  * BDs.
135  */
136 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO)
137 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO"
138 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */
139 
140 typedef enum {
141 	TI_SWAP_HTON,
142 	TI_SWAP_NTOH
143 } ti_swap_type;
144 
145 /*
146  * Various supported device vendors/types and their names.
147  */
148 
149 static const struct ti_type ti_devs[] = {
150 	{ ALT_VENDORID,	ALT_DEVICEID_ACENIC,
151 		"Alteon AceNIC 1000baseSX Gigabit Ethernet" },
152 	{ ALT_VENDORID,	ALT_DEVICEID_ACENIC_COPPER,
153 		"Alteon AceNIC 1000baseT Gigabit Ethernet" },
154 	{ TC_VENDORID,	TC_DEVICEID_3C985,
155 		"3Com 3c985-SX Gigabit Ethernet" },
156 	{ NG_VENDORID, NG_DEVICEID_GA620,
157 		"Netgear GA620 1000baseSX Gigabit Ethernet" },
158 	{ NG_VENDORID, NG_DEVICEID_GA620T,
159 		"Netgear GA620 1000baseT Gigabit Ethernet" },
160 	{ SGI_VENDORID, SGI_DEVICEID_TIGON,
161 		"Silicon Graphics Gigabit Ethernet" },
162 	{ DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
163 		"Farallon PN9000SX Gigabit Ethernet" },
164 	{ 0, 0, NULL }
165 };
166 
167 
168 static	d_open_t	ti_open;
169 static	d_close_t	ti_close;
170 static	d_ioctl_t	ti_ioctl2;
171 
172 static struct cdevsw ti_cdevsw = {
173 	.d_version =	D_VERSION,
174 	.d_flags =	0,
175 	.d_open =	ti_open,
176 	.d_close =	ti_close,
177 	.d_ioctl =	ti_ioctl2,
178 	.d_name =	"ti",
179 };
180 
181 static int ti_probe(device_t);
182 static int ti_attach(device_t);
183 static int ti_detach(device_t);
184 static void ti_txeof(struct ti_softc *);
185 static void ti_rxeof(struct ti_softc *);
186 
187 static int ti_encap(struct ti_softc *, struct mbuf **);
188 
189 static void ti_intr(void *);
190 static void ti_start(struct ifnet *);
191 static void ti_start_locked(struct ifnet *);
192 static int ti_ioctl(struct ifnet *, u_long, caddr_t);
193 static uint64_t ti_get_counter(struct ifnet *, ift_counter);
194 static void ti_init(void *);
195 static void ti_init_locked(void *);
196 static void ti_init2(struct ti_softc *);
197 static void ti_stop(struct ti_softc *);
198 static void ti_watchdog(void *);
199 static int ti_shutdown(device_t);
200 static int ti_ifmedia_upd(struct ifnet *);
201 static int ti_ifmedia_upd_locked(struct ti_softc *);
202 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
203 
204 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
205 static uint8_t	ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
206 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
207 
208 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
209 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
210 static void ti_setmulti(struct ti_softc *);
211 
212 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *);
213 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *);
214 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t);
215 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int,
216     int);
217 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t,
218     int, int, int);
219 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type);
220 static void ti_loadfw(struct ti_softc *);
221 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
222 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int);
223 static void ti_handle_events(struct ti_softc *);
224 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int);
225 static int ti_dma_alloc(struct ti_softc *);
226 static void ti_dma_free(struct ti_softc *);
227 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t,
228     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
229 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **,
230     bus_dmamap_t, bus_addr_t *);
231 static int ti_newbuf_std(struct ti_softc *, int);
232 static int ti_newbuf_mini(struct ti_softc *, int);
233 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
234 static int ti_init_rx_ring_std(struct ti_softc *);
235 static void ti_free_rx_ring_std(struct ti_softc *);
236 static int ti_init_rx_ring_jumbo(struct ti_softc *);
237 static void ti_free_rx_ring_jumbo(struct ti_softc *);
238 static int ti_init_rx_ring_mini(struct ti_softc *);
239 static void ti_free_rx_ring_mini(struct ti_softc *);
240 static void ti_free_tx_ring(struct ti_softc *);
241 static int ti_init_tx_ring(struct ti_softc *);
242 static void ti_discard_std(struct ti_softc *, int);
243 #ifndef TI_SF_BUF_JUMBO
244 static void ti_discard_jumbo(struct ti_softc *, int);
245 #endif
246 static void ti_discard_mini(struct ti_softc *, int);
247 
248 static int ti_64bitslot_war(struct ti_softc *);
249 static int ti_chipinit(struct ti_softc *);
250 static int ti_gibinit(struct ti_softc *);
251 
252 #ifdef TI_JUMBO_HDRSPLIT
253 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len,
254     int idx);
255 #endif /* TI_JUMBO_HDRSPLIT */
256 
257 static void ti_sysctl_node(struct ti_softc *);
258 
259 static device_method_t ti_methods[] = {
260 	/* Device interface */
261 	DEVMETHOD(device_probe,		ti_probe),
262 	DEVMETHOD(device_attach,	ti_attach),
263 	DEVMETHOD(device_detach,	ti_detach),
264 	DEVMETHOD(device_shutdown,	ti_shutdown),
265 	{ 0, 0 }
266 };
267 
268 static driver_t ti_driver = {
269 	"ti",
270 	ti_methods,
271 	sizeof(struct ti_softc)
272 };
273 
274 static devclass_t ti_devclass;
275 
276 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0);
277 MODULE_DEPEND(ti, pci, 1, 1, 1);
278 MODULE_DEPEND(ti, ether, 1, 1, 1);
279 
280 /*
281  * Send an instruction or address to the EEPROM, check for ACK.
282  */
283 static uint32_t
284 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
285 {
286 	int i, ack = 0;
287 
288 	/*
289 	 * Make sure we're in TX mode.
290 	 */
291 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
292 
293 	/*
294 	 * Feed in each bit and stobe the clock.
295 	 */
296 	for (i = 0x80; i; i >>= 1) {
297 		if (byte & i) {
298 			TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
299 		} else {
300 			TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
301 		}
302 		DELAY(1);
303 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
304 		DELAY(1);
305 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
306 	}
307 
308 	/*
309 	 * Turn off TX mode.
310 	 */
311 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
312 
313 	/*
314 	 * Check for ack.
315 	 */
316 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
317 	ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
318 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
319 
320 	return (ack);
321 }
322 
323 /*
324  * Read a byte of data stored in the EEPROM at address 'addr.'
325  * We have to send two address bytes since the EEPROM can hold
326  * more than 256 bytes of data.
327  */
328 static uint8_t
329 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
330 {
331 	int i;
332 	uint8_t byte = 0;
333 
334 	EEPROM_START;
335 
336 	/*
337 	 * Send write control code to EEPROM.
338 	 */
339 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
340 		device_printf(sc->ti_dev,
341 		    "failed to send write command, status: %x\n",
342 		    CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
343 		return (1);
344 	}
345 
346 	/*
347 	 * Send first byte of address of byte we want to read.
348 	 */
349 	if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
350 		device_printf(sc->ti_dev, "failed to send address, status: %x\n",
351 		    CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
352 		return (1);
353 	}
354 	/*
355 	 * Send second byte address of byte we want to read.
356 	 */
357 	if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
358 		device_printf(sc->ti_dev, "failed to send address, status: %x\n",
359 		    CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
360 		return (1);
361 	}
362 
363 	EEPROM_STOP;
364 	EEPROM_START;
365 	/*
366 	 * Send read control code to EEPROM.
367 	 */
368 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
369 		device_printf(sc->ti_dev,
370 		    "failed to send read command, status: %x\n",
371 		    CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
372 		return (1);
373 	}
374 
375 	/*
376 	 * Start reading bits from EEPROM.
377 	 */
378 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
379 	for (i = 0x80; i; i >>= 1) {
380 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
381 		DELAY(1);
382 		if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
383 			byte |= i;
384 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
385 		DELAY(1);
386 	}
387 
388 	EEPROM_STOP;
389 
390 	/*
391 	 * No ACK generated for read, so just return byte.
392 	 */
393 
394 	*dest = byte;
395 
396 	return (0);
397 }
398 
399 /*
400  * Read a sequence of bytes from the EEPROM.
401  */
402 static int
403 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
404 {
405 	int err = 0, i;
406 	uint8_t byte = 0;
407 
408 	for (i = 0; i < cnt; i++) {
409 		err = ti_eeprom_getbyte(sc, off + i, &byte);
410 		if (err)
411 			break;
412 		*(dest + i) = byte;
413 	}
414 
415 	return (err ? 1 : 0);
416 }
417 
418 /*
419  * NIC memory read function.
420  * Can be used to copy data from NIC local memory.
421  */
422 static void
423 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
424 {
425 	int segptr, segsize, cnt;
426 	char *ptr;
427 
428 	segptr = addr;
429 	cnt = len;
430 	ptr = buf;
431 
432 	while (cnt) {
433 		if (cnt < TI_WINLEN)
434 			segsize = cnt;
435 		else
436 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
437 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
438 		bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
439 		    TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
440 		    segsize / 4);
441 		ptr += segsize;
442 		segptr += segsize;
443 		cnt -= segsize;
444 	}
445 }
446 
447 
448 /*
449  * NIC memory write function.
450  * Can be used to copy data into NIC local memory.
451  */
452 static void
453 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf)
454 {
455 	int segptr, segsize, cnt;
456 	char *ptr;
457 
458 	segptr = addr;
459 	cnt = len;
460 	ptr = buf;
461 
462 	while (cnt) {
463 		if (cnt < TI_WINLEN)
464 			segsize = cnt;
465 		else
466 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
467 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
468 		bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
469 		    TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr,
470 		    segsize / 4);
471 		ptr += segsize;
472 		segptr += segsize;
473 		cnt -= segsize;
474 	}
475 }
476 
477 /*
478  * NIC memory read function.
479  * Can be used to clear a section of NIC local memory.
480  */
481 static void
482 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len)
483 {
484 	int segptr, segsize, cnt;
485 
486 	segptr = addr;
487 	cnt = len;
488 
489 	while (cnt) {
490 		if (cnt < TI_WINLEN)
491 			segsize = cnt;
492 		else
493 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
494 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
495 		bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
496 		    TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4);
497 		segptr += segsize;
498 		cnt -= segsize;
499 	}
500 }
501 
502 static int
503 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
504     caddr_t buf, int useraddr, int readdata)
505 {
506 	int segptr, segsize, cnt;
507 	caddr_t ptr;
508 	uint32_t origwin;
509 	int resid, segresid;
510 	int first_pass;
511 
512 	TI_LOCK_ASSERT(sc);
513 
514 	/*
515 	 * At the moment, we don't handle non-aligned cases, we just bail.
516 	 * If this proves to be a problem, it will be fixed.
517 	 */
518 	if (readdata == 0 && (tigon_addr & 0x3) != 0) {
519 		device_printf(sc->ti_dev, "%s: tigon address %#x isn't "
520 		    "word-aligned\n", __func__, tigon_addr);
521 		device_printf(sc->ti_dev, "%s: unaligned writes aren't "
522 		    "yet supported\n", __func__);
523 		return (EINVAL);
524 	}
525 
526 	segptr = tigon_addr & ~0x3;
527 	segresid = tigon_addr - segptr;
528 
529 	/*
530 	 * This is the non-aligned amount left over that we'll need to
531 	 * copy.
532 	 */
533 	resid = len & 0x3;
534 
535 	/* Add in the left over amount at the front of the buffer */
536 	resid += segresid;
537 
538 	cnt = len & ~0x3;
539 	/*
540 	 * If resid + segresid is >= 4, add multiples of 4 to the count and
541 	 * decrease the residual by that much.
542 	 */
543 	cnt += resid & ~0x3;
544 	resid -= resid & ~0x3;
545 
546 	ptr = buf;
547 
548 	first_pass = 1;
549 
550 	/*
551 	 * Save the old window base value.
552 	 */
553 	origwin = CSR_READ_4(sc, TI_WINBASE);
554 
555 	while (cnt) {
556 		bus_size_t ti_offset;
557 
558 		if (cnt < TI_WINLEN)
559 			segsize = cnt;
560 		else
561 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
562 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
563 
564 		ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1));
565 
566 		if (readdata) {
567 			bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
568 			    ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
569 			if (useraddr) {
570 				/*
571 				 * Yeah, this is a little on the kludgy
572 				 * side, but at least this code is only
573 				 * used for debugging.
574 				 */
575 				ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2,
576 				    segsize, TI_SWAP_NTOH);
577 
578 				TI_UNLOCK(sc);
579 				if (first_pass) {
580 					copyout(&sc->ti_membuf2[segresid], ptr,
581 					    segsize - segresid);
582 					first_pass = 0;
583 				} else
584 					copyout(sc->ti_membuf2, ptr, segsize);
585 				TI_LOCK(sc);
586 			} else {
587 				if (first_pass) {
588 
589 					ti_bcopy_swap(sc->ti_membuf,
590 					    sc->ti_membuf2, segsize,
591 					    TI_SWAP_NTOH);
592 					TI_UNLOCK(sc);
593 					bcopy(&sc->ti_membuf2[segresid], ptr,
594 					    segsize - segresid);
595 					TI_LOCK(sc);
596 					first_pass = 0;
597 				} else
598 					ti_bcopy_swap(sc->ti_membuf, ptr,
599 					    segsize, TI_SWAP_NTOH);
600 			}
601 
602 		} else {
603 			if (useraddr) {
604 				TI_UNLOCK(sc);
605 				copyin(ptr, sc->ti_membuf2, segsize);
606 				TI_LOCK(sc);
607 				ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf,
608 				    segsize, TI_SWAP_HTON);
609 			} else
610 				ti_bcopy_swap(ptr, sc->ti_membuf, segsize,
611 				    TI_SWAP_HTON);
612 
613 			bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
614 			    ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2);
615 		}
616 		segptr += segsize;
617 		ptr += segsize;
618 		cnt -= segsize;
619 	}
620 
621 	/*
622 	 * Handle leftover, non-word-aligned bytes.
623 	 */
624 	if (resid != 0) {
625 		uint32_t tmpval, tmpval2;
626 		bus_size_t ti_offset;
627 
628 		/*
629 		 * Set the segment pointer.
630 		 */
631 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
632 
633 		ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1));
634 
635 		/*
636 		 * First, grab whatever is in our source/destination.
637 		 * We'll obviously need this for reads, but also for
638 		 * writes, since we'll be doing read/modify/write.
639 		 */
640 		bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
641 		    ti_offset, &tmpval, 1);
642 
643 		/*
644 		 * Next, translate this from little-endian to big-endian
645 		 * (at least on i386 boxes).
646 		 */
647 		tmpval2 = ntohl(tmpval);
648 
649 		if (readdata) {
650 			/*
651 			 * If we're reading, just copy the leftover number
652 			 * of bytes from the host byte order buffer to
653 			 * the user's buffer.
654 			 */
655 			if (useraddr) {
656 				TI_UNLOCK(sc);
657 				copyout(&tmpval2, ptr, resid);
658 				TI_LOCK(sc);
659 			} else
660 				bcopy(&tmpval2, ptr, resid);
661 		} else {
662 			/*
663 			 * If we're writing, first copy the bytes to be
664 			 * written into the network byte order buffer,
665 			 * leaving the rest of the buffer with whatever was
666 			 * originally in there.  Then, swap the bytes
667 			 * around into host order and write them out.
668 			 *
669 			 * XXX KDM the read side of this has been verified
670 			 * to work, but the write side of it has not been
671 			 * verified.  So user beware.
672 			 */
673 			if (useraddr) {
674 				TI_UNLOCK(sc);
675 				copyin(ptr, &tmpval2, resid);
676 				TI_LOCK(sc);
677 			} else
678 				bcopy(ptr, &tmpval2, resid);
679 
680 			tmpval = htonl(tmpval2);
681 
682 			bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
683 			    ti_offset, &tmpval, 1);
684 		}
685 	}
686 
687 	CSR_WRITE_4(sc, TI_WINBASE, origwin);
688 
689 	return (0);
690 }
691 
692 static int
693 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len,
694     caddr_t buf, int useraddr, int readdata, int cpu)
695 {
696 	uint32_t segptr;
697 	int cnt;
698 	uint32_t tmpval, tmpval2;
699 	caddr_t ptr;
700 
701 	TI_LOCK_ASSERT(sc);
702 
703 	/*
704 	 * At the moment, we don't handle non-aligned cases, we just bail.
705 	 * If this proves to be a problem, it will be fixed.
706 	 */
707 	if (tigon_addr & 0x3) {
708 		device_printf(sc->ti_dev, "%s: tigon address %#x "
709 		    "isn't word-aligned\n", __func__, tigon_addr);
710 		return (EINVAL);
711 	}
712 
713 	if (len & 0x3) {
714 		device_printf(sc->ti_dev, "%s: transfer length %d "
715 		    "isn't word-aligned\n", __func__, len);
716 		return (EINVAL);
717 	}
718 
719 	segptr = tigon_addr;
720 	cnt = len;
721 	ptr = buf;
722 
723 	while (cnt) {
724 		CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr);
725 
726 		if (readdata) {
727 			tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
728 
729 			tmpval = ntohl(tmpval2);
730 
731 			/*
732 			 * Note:  I've used this debugging interface
733 			 * extensively with Alteon's 12.3.15 firmware,
734 			 * compiled with GCC 2.7.2.1 and binutils 2.9.1.
735 			 *
736 			 * When you compile the firmware without
737 			 * optimization, which is necessary sometimes in
738 			 * order to properly step through it, you sometimes
739 			 * read out a bogus value of 0xc0017c instead of
740 			 * whatever was supposed to be in that scratchpad
741 			 * location.  That value is on the stack somewhere,
742 			 * but I've never been able to figure out what was
743 			 * causing the problem.
744 			 *
745 			 * The address seems to pop up in random places,
746 			 * often not in the same place on two subsequent
747 			 * reads.
748 			 *
749 			 * In any case, the underlying data doesn't seem
750 			 * to be affected, just the value read out.
751 			 *
752 			 * KDM, 3/7/2000
753 			 */
754 
755 			if (tmpval2 == 0xc0017c)
756 				device_printf(sc->ti_dev, "found 0xc0017c at "
757 				    "%#x (tmpval2)\n", segptr);
758 
759 			if (tmpval == 0xc0017c)
760 				device_printf(sc->ti_dev, "found 0xc0017c at "
761 				    "%#x (tmpval)\n", segptr);
762 
763 			if (useraddr)
764 				copyout(&tmpval, ptr, 4);
765 			else
766 				bcopy(&tmpval, ptr, 4);
767 		} else {
768 			if (useraddr)
769 				copyin(ptr, &tmpval2, 4);
770 			else
771 				bcopy(ptr, &tmpval2, 4);
772 
773 			tmpval = htonl(tmpval2);
774 
775 			CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval);
776 		}
777 
778 		cnt -= 4;
779 		segptr += 4;
780 		ptr += 4;
781 	}
782 
783 	return (0);
784 }
785 
786 static int
787 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type)
788 {
789 	const uint8_t *tmpsrc;
790 	uint8_t *tmpdst;
791 	size_t tmplen;
792 
793 	if (len & 0x3) {
794 		printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len);
795 		return (-1);
796 	}
797 
798 	tmpsrc = src;
799 	tmpdst = dst;
800 	tmplen = len;
801 
802 	while (tmplen) {
803 		if (swap_type == TI_SWAP_NTOH)
804 			*(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc);
805 		else
806 			*(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc);
807 		tmpsrc += 4;
808 		tmpdst += 4;
809 		tmplen -= 4;
810 	}
811 
812 	return (0);
813 }
814 
815 /*
816  * Load firmware image into the NIC. Check that the firmware revision
817  * is acceptable and see if we want the firmware for the Tigon 1 or
818  * Tigon 2.
819  */
820 static void
821 ti_loadfw(struct ti_softc *sc)
822 {
823 
824 	TI_LOCK_ASSERT(sc);
825 
826 	switch (sc->ti_hwrev) {
827 	case TI_HWREV_TIGON:
828 		if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
829 		    tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
830 		    tigonFwReleaseFix != TI_FIRMWARE_FIX) {
831 			device_printf(sc->ti_dev, "firmware revision mismatch; "
832 			    "want %d.%d.%d, got %d.%d.%d\n",
833 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
834 			    TI_FIRMWARE_FIX, tigonFwReleaseMajor,
835 			    tigonFwReleaseMinor, tigonFwReleaseFix);
836 			return;
837 		}
838 		ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
839 		ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
840 		ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen,
841 		    tigonFwRodata);
842 		ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen);
843 		ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen);
844 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
845 		break;
846 	case TI_HWREV_TIGON_II:
847 		if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
848 		    tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
849 		    tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
850 			device_printf(sc->ti_dev, "firmware revision mismatch; "
851 			    "want %d.%d.%d, got %d.%d.%d\n",
852 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
853 			    TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
854 			    tigon2FwReleaseMinor, tigon2FwReleaseFix);
855 			return;
856 		}
857 		ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen,
858 		    tigon2FwText);
859 		ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen,
860 		    tigon2FwData);
861 		ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
862 		    tigon2FwRodata);
863 		ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen);
864 		ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen);
865 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
866 		break;
867 	default:
868 		device_printf(sc->ti_dev,
869 		    "can't load firmware: unknown hardware rev\n");
870 		break;
871 	}
872 }
873 
874 /*
875  * Send the NIC a command via the command ring.
876  */
877 static void
878 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
879 {
880 	int index;
881 
882 	index = sc->ti_cmd_saved_prodidx;
883 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
884 	TI_INC(index, TI_CMD_RING_CNT);
885 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
886 	sc->ti_cmd_saved_prodidx = index;
887 }
888 
889 /*
890  * Send the NIC an extended command. The 'len' parameter specifies the
891  * number of command slots to include after the initial command.
892  */
893 static void
894 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
895 {
896 	int index;
897 	int i;
898 
899 	index = sc->ti_cmd_saved_prodidx;
900 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
901 	TI_INC(index, TI_CMD_RING_CNT);
902 	for (i = 0; i < len; i++) {
903 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
904 		    *(uint32_t *)(&arg[i * 4]));
905 		TI_INC(index, TI_CMD_RING_CNT);
906 	}
907 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
908 	sc->ti_cmd_saved_prodidx = index;
909 }
910 
911 /*
912  * Handle events that have triggered interrupts.
913  */
914 static void
915 ti_handle_events(struct ti_softc *sc)
916 {
917 	struct ti_event_desc *e;
918 
919 	if (sc->ti_rdata.ti_event_ring == NULL)
920 		return;
921 
922 	bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
923 	    sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD);
924 	while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
925 		e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx];
926 		switch (TI_EVENT_EVENT(e)) {
927 		case TI_EV_LINKSTAT_CHANGED:
928 			sc->ti_linkstat = TI_EVENT_CODE(e);
929 			if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
930 				if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
931 				sc->ti_ifp->if_baudrate = IF_Mbps(100);
932 				if (bootverbose)
933 					device_printf(sc->ti_dev,
934 					    "10/100 link up\n");
935 			} else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
936 				if_link_state_change(sc->ti_ifp, LINK_STATE_UP);
937 				sc->ti_ifp->if_baudrate = IF_Gbps(1UL);
938 				if (bootverbose)
939 					device_printf(sc->ti_dev,
940 					    "gigabit link up\n");
941 			} else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
942 				if_link_state_change(sc->ti_ifp,
943 				    LINK_STATE_DOWN);
944 				sc->ti_ifp->if_baudrate = 0;
945 				if (bootverbose)
946 					device_printf(sc->ti_dev,
947 					    "link down\n");
948 			}
949 			break;
950 		case TI_EV_ERROR:
951 			if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
952 				device_printf(sc->ti_dev, "invalid command\n");
953 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
954 				device_printf(sc->ti_dev, "unknown command\n");
955 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
956 				device_printf(sc->ti_dev, "bad config data\n");
957 			break;
958 		case TI_EV_FIRMWARE_UP:
959 			ti_init2(sc);
960 			break;
961 		case TI_EV_STATS_UPDATED:
962 		case TI_EV_RESET_JUMBO_RING:
963 		case TI_EV_MCAST_UPDATED:
964 			/* Who cares. */
965 			break;
966 		default:
967 			device_printf(sc->ti_dev, "unknown event: %d\n",
968 			    TI_EVENT_EVENT(e));
969 			break;
970 		}
971 		/* Advance the consumer index. */
972 		TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
973 		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
974 	}
975 	bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
976 	    sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD);
977 }
978 
979 struct ti_dmamap_arg {
980 	bus_addr_t	ti_busaddr;
981 };
982 
983 static void
984 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
985 {
986 	struct ti_dmamap_arg *ctx;
987 
988 	if (error)
989 		return;
990 
991 	KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
992 
993 	ctx = arg;
994 	ctx->ti_busaddr = segs->ds_addr;
995 }
996 
997 static int
998 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize,
999     bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr,
1000     const char *msg)
1001 {
1002 	struct ti_dmamap_arg ctx;
1003 	int error;
1004 
1005 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag,
1006 	    alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1007 	    NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
1008 	if (error != 0) {
1009 		device_printf(sc->ti_dev,
1010 		    "could not create %s dma tag\n", msg);
1011 		return (error);
1012 	}
1013 	/* Allocate DMA'able memory for ring. */
1014 	error = bus_dmamem_alloc(*tag, (void **)ring,
1015 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1016 	if (error != 0) {
1017 		device_printf(sc->ti_dev,
1018 		    "could not allocate DMA'able memory for %s\n", msg);
1019 		return (error);
1020 	}
1021 	/* Load the address of the ring. */
1022 	ctx.ti_busaddr = 0;
1023 	error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr,
1024 	    &ctx, BUS_DMA_NOWAIT);
1025 	if (error != 0) {
1026 		device_printf(sc->ti_dev,
1027 		    "could not load DMA'able memory for %s\n", msg);
1028 		return (error);
1029 	}
1030 	*paddr = ctx.ti_busaddr;
1031 	return (0);
1032 }
1033 
1034 static void
1035 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring,
1036     bus_dmamap_t map, bus_addr_t *paddr)
1037 {
1038 
1039 	if (*paddr != 0) {
1040 		bus_dmamap_unload(*tag, map);
1041 		*paddr = 0;
1042 	}
1043 	if (*ring != NULL) {
1044 		bus_dmamem_free(*tag, *ring, map);
1045 		*ring = NULL;
1046 	}
1047 	if (*tag) {
1048 		bus_dma_tag_destroy(*tag);
1049 		*tag = NULL;
1050 	}
1051 }
1052 
1053 static int
1054 ti_dma_alloc(struct ti_softc *sc)
1055 {
1056 	bus_addr_t lowaddr;
1057 	int i, error;
1058 
1059 	lowaddr = BUS_SPACE_MAXADDR;
1060 	if (sc->ti_dac == 0)
1061 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1062 
1063 	error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr,
1064 	    BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1065 	    BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1066 	    &sc->ti_cdata.ti_parent_tag);
1067 	if (error != 0) {
1068 		device_printf(sc->ti_dev,
1069 		    "could not allocate parent dma tag\n");
1070 		return (ENOMEM);
1071 	}
1072 
1073 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib),
1074 	    &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info,
1075 	    &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB");
1076 	if (error)
1077 		return (error);
1078 
1079 	/* Producer/consumer status */
1080 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status),
1081 	    &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status,
1082 	    &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr,
1083 	    "event ring");
1084 	if (error)
1085 		return (error);
1086 
1087 	/* Event ring */
1088 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ,
1089 	    &sc->ti_cdata.ti_event_ring_tag,
1090 	    (uint8_t **)&sc->ti_rdata.ti_event_ring,
1091 	    &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr,
1092 	    "event ring");
1093 	if (error)
1094 		return (error);
1095 
1096 	/* Command ring lives in shared memory so no need to create DMA area. */
1097 
1098 	/* Standard RX ring */
1099 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ,
1100 	    &sc->ti_cdata.ti_rx_std_ring_tag,
1101 	    (uint8_t **)&sc->ti_rdata.ti_rx_std_ring,
1102 	    &sc->ti_cdata.ti_rx_std_ring_map,
1103 	    &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring");
1104 	if (error)
1105 		return (error);
1106 
1107 	/* Jumbo RX ring */
1108 	error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ,
1109 	    &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1110 	    (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring,
1111 	    &sc->ti_cdata.ti_rx_jumbo_ring_map,
1112 	    &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring");
1113 	if (error)
1114 		return (error);
1115 
1116 	/* RX return ring */
1117 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ,
1118 	    &sc->ti_cdata.ti_rx_return_ring_tag,
1119 	    (uint8_t **)&sc->ti_rdata.ti_rx_return_ring,
1120 	    &sc->ti_cdata.ti_rx_return_ring_map,
1121 	    &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring");
1122 	if (error)
1123 		return (error);
1124 
1125 	/* Create DMA tag for standard RX mbufs. */
1126 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1127 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1128 	    MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag);
1129 	if (error) {
1130 		device_printf(sc->ti_dev, "could not allocate RX dma tag\n");
1131 		return (error);
1132 	}
1133 
1134 	/* Create DMA tag for jumbo RX mbufs. */
1135 #ifdef TI_SF_BUF_JUMBO
1136 	/*
1137 	 * The VM system will take care of providing aligned pages.  Alignment
1138 	 * is set to 1 here so that busdma resources won't be wasted.
1139 	 */
1140 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1141 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4,
1142 	    PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1143 #else
1144 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1145 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1,
1146 	    MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag);
1147 #endif
1148 	if (error) {
1149 		device_printf(sc->ti_dev,
1150 		    "could not allocate jumbo RX dma tag\n");
1151 		return (error);
1152 	}
1153 
1154 	/* Create DMA tag for TX mbufs. */
1155 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1,
1156 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1157 	    MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1158 	    &sc->ti_cdata.ti_tx_tag);
1159 	if (error) {
1160 		device_printf(sc->ti_dev, "could not allocate TX dma tag\n");
1161 		return (ENOMEM);
1162 	}
1163 
1164 	/* Create DMA maps for RX buffers. */
1165 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1166 		error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1167 		    &sc->ti_cdata.ti_rx_std_maps[i]);
1168 		if (error) {
1169 			device_printf(sc->ti_dev,
1170 			    "could not create DMA map for RX\n");
1171 			return (error);
1172 		}
1173 	}
1174 	error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0,
1175 	    &sc->ti_cdata.ti_rx_std_sparemap);
1176 	if (error) {
1177 		device_printf(sc->ti_dev,
1178 		    "could not create spare DMA map for RX\n");
1179 		return (error);
1180 	}
1181 
1182 	/* Create DMA maps for jumbo RX buffers. */
1183 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1184 		error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1185 		    &sc->ti_cdata.ti_rx_jumbo_maps[i]);
1186 		if (error) {
1187 			device_printf(sc->ti_dev,
1188 			    "could not create DMA map for jumbo RX\n");
1189 			return (error);
1190 		}
1191 	}
1192 	error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0,
1193 	    &sc->ti_cdata.ti_rx_jumbo_sparemap);
1194 	if (error) {
1195 		device_printf(sc->ti_dev,
1196 		    "could not create spare DMA map for jumbo RX\n");
1197 		return (error);
1198 	}
1199 
1200 	/* Create DMA maps for TX buffers. */
1201 	for (i = 0; i < TI_TX_RING_CNT; i++) {
1202 		error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0,
1203 		    &sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1204 		if (error) {
1205 			device_printf(sc->ti_dev,
1206 			    "could not create DMA map for TX\n");
1207 			return (ENOMEM);
1208 		}
1209 	}
1210 
1211 	/* Mini ring and TX ring is not available on Tigon 1. */
1212 	if (sc->ti_hwrev == TI_HWREV_TIGON)
1213 		return (0);
1214 
1215 	/* TX ring */
1216 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ,
1217 	    &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring,
1218 	    &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr,
1219 	    "TX ring");
1220 	if (error)
1221 		return (error);
1222 
1223 	/* Mini RX ring */
1224 	error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ,
1225 	    &sc->ti_cdata.ti_rx_mini_ring_tag,
1226 	    (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring,
1227 	    &sc->ti_cdata.ti_rx_mini_ring_map,
1228 	    &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring");
1229 	if (error)
1230 		return (error);
1231 
1232 	/* Create DMA tag for mini RX mbufs. */
1233 	error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0,
1234 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1,
1235 	    MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag);
1236 	if (error) {
1237 		device_printf(sc->ti_dev,
1238 		    "could not allocate mini RX dma tag\n");
1239 		return (error);
1240 	}
1241 
1242 	/* Create DMA maps for mini RX buffers. */
1243 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1244 		error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1245 		    &sc->ti_cdata.ti_rx_mini_maps[i]);
1246 		if (error) {
1247 			device_printf(sc->ti_dev,
1248 			    "could not create DMA map for mini RX\n");
1249 			return (error);
1250 		}
1251 	}
1252 	error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0,
1253 	    &sc->ti_cdata.ti_rx_mini_sparemap);
1254 	if (error) {
1255 		device_printf(sc->ti_dev,
1256 		    "could not create spare DMA map for mini RX\n");
1257 		return (error);
1258 	}
1259 
1260 	return (0);
1261 }
1262 
1263 static void
1264 ti_dma_free(struct ti_softc *sc)
1265 {
1266 	int i;
1267 
1268 	/* Destroy DMA maps for RX buffers. */
1269 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1270 		if (sc->ti_cdata.ti_rx_std_maps[i]) {
1271 			bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1272 			    sc->ti_cdata.ti_rx_std_maps[i]);
1273 			sc->ti_cdata.ti_rx_std_maps[i] = NULL;
1274 		}
1275 	}
1276 	if (sc->ti_cdata.ti_rx_std_sparemap) {
1277 		bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag,
1278 		    sc->ti_cdata.ti_rx_std_sparemap);
1279 		sc->ti_cdata.ti_rx_std_sparemap = NULL;
1280 	}
1281 	if (sc->ti_cdata.ti_rx_std_tag) {
1282 		bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag);
1283 		sc->ti_cdata.ti_rx_std_tag = NULL;
1284 	}
1285 
1286 	/* Destroy DMA maps for jumbo RX buffers. */
1287 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1288 		if (sc->ti_cdata.ti_rx_jumbo_maps[i]) {
1289 			bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1290 			    sc->ti_cdata.ti_rx_jumbo_maps[i]);
1291 			sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL;
1292 		}
1293 	}
1294 	if (sc->ti_cdata.ti_rx_jumbo_sparemap) {
1295 		bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag,
1296 		    sc->ti_cdata.ti_rx_jumbo_sparemap);
1297 		sc->ti_cdata.ti_rx_jumbo_sparemap = NULL;
1298 	}
1299 	if (sc->ti_cdata.ti_rx_jumbo_tag) {
1300 		bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag);
1301 		sc->ti_cdata.ti_rx_jumbo_tag = NULL;
1302 	}
1303 
1304 	/* Destroy DMA maps for mini RX buffers. */
1305 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1306 		if (sc->ti_cdata.ti_rx_mini_maps[i]) {
1307 			bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1308 			    sc->ti_cdata.ti_rx_mini_maps[i]);
1309 			sc->ti_cdata.ti_rx_mini_maps[i] = NULL;
1310 		}
1311 	}
1312 	if (sc->ti_cdata.ti_rx_mini_sparemap) {
1313 		bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag,
1314 		    sc->ti_cdata.ti_rx_mini_sparemap);
1315 		sc->ti_cdata.ti_rx_mini_sparemap = NULL;
1316 	}
1317 	if (sc->ti_cdata.ti_rx_mini_tag) {
1318 		bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag);
1319 		sc->ti_cdata.ti_rx_mini_tag = NULL;
1320 	}
1321 
1322 	/* Destroy DMA maps for TX buffers. */
1323 	for (i = 0; i < TI_TX_RING_CNT; i++) {
1324 		if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) {
1325 			bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag,
1326 			    sc->ti_cdata.ti_txdesc[i].tx_dmamap);
1327 			sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL;
1328 		}
1329 	}
1330 	if (sc->ti_cdata.ti_tx_tag) {
1331 		bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag);
1332 		sc->ti_cdata.ti_tx_tag = NULL;
1333 	}
1334 
1335 	/* Destroy standard RX ring. */
1336 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag,
1337 	    (void *)&sc->ti_rdata.ti_rx_std_ring,
1338 	    sc->ti_cdata.ti_rx_std_ring_map,
1339 	    &sc->ti_rdata.ti_rx_std_ring_paddr);
1340 	/* Destroy jumbo RX ring. */
1341 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag,
1342 	    (void *)&sc->ti_rdata.ti_rx_jumbo_ring,
1343 	    sc->ti_cdata.ti_rx_jumbo_ring_map,
1344 	    &sc->ti_rdata.ti_rx_jumbo_ring_paddr);
1345 	/* Destroy mini RX ring. */
1346 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag,
1347 	    (void *)&sc->ti_rdata.ti_rx_mini_ring,
1348 	    sc->ti_cdata.ti_rx_mini_ring_map,
1349 	    &sc->ti_rdata.ti_rx_mini_ring_paddr);
1350 	/* Destroy RX return ring. */
1351 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag,
1352 	    (void *)&sc->ti_rdata.ti_rx_return_ring,
1353 	    sc->ti_cdata.ti_rx_return_ring_map,
1354 	    &sc->ti_rdata.ti_rx_return_ring_paddr);
1355 	/* Destroy TX ring. */
1356 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag,
1357 	    (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map,
1358 	    &sc->ti_rdata.ti_tx_ring_paddr);
1359 	/* Destroy status block. */
1360 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag,
1361 	    (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map,
1362 	    &sc->ti_rdata.ti_status_paddr);
1363 	/* Destroy event ring. */
1364 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag,
1365 	    (void *)&sc->ti_rdata.ti_event_ring,
1366 	    sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr);
1367 	/* Destroy GIB */
1368 	ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag,
1369 	    (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map,
1370 	    &sc->ti_rdata.ti_info_paddr);
1371 
1372 	/* Destroy the parent tag. */
1373 	if (sc->ti_cdata.ti_parent_tag) {
1374 		bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag);
1375 		sc->ti_cdata.ti_parent_tag = NULL;
1376 	}
1377 }
1378 
1379 /*
1380  * Intialize a standard receive ring descriptor.
1381  */
1382 static int
1383 ti_newbuf_std(struct ti_softc *sc, int i)
1384 {
1385 	bus_dmamap_t map;
1386 	bus_dma_segment_t segs[1];
1387 	struct mbuf *m;
1388 	struct ti_rx_desc *r;
1389 	int error, nsegs;
1390 
1391 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1392 	if (m == NULL)
1393 		return (ENOBUFS);
1394 	m->m_len = m->m_pkthdr.len = MCLBYTES;
1395 	m_adj(m, ETHER_ALIGN);
1396 
1397 	error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag,
1398 	    sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0);
1399 	if (error != 0) {
1400 		m_freem(m);
1401 		return (error);
1402         }
1403 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1404 
1405 	if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1406 		bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1407 		    sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD);
1408 		bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag,
1409 		    sc->ti_cdata.ti_rx_std_maps[i]);
1410 	}
1411 
1412 	map = sc->ti_cdata.ti_rx_std_maps[i];
1413 	sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap;
1414 	sc->ti_cdata.ti_rx_std_sparemap = map;
1415 	sc->ti_cdata.ti_rx_std_chain[i] = m;
1416 
1417 	r = &sc->ti_rdata.ti_rx_std_ring[i];
1418 	ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1419 	r->ti_len = segs[0].ds_len;
1420 	r->ti_type = TI_BDTYPE_RECV_BD;
1421 	r->ti_flags = 0;
1422 	r->ti_vlan_tag = 0;
1423 	r->ti_tcp_udp_cksum = 0;
1424 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1425 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1426 	r->ti_idx = i;
1427 
1428 	bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag,
1429 	    sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD);
1430 	return (0);
1431 }
1432 
1433 /*
1434  * Intialize a mini receive ring descriptor. This only applies to
1435  * the Tigon 2.
1436  */
1437 static int
1438 ti_newbuf_mini(struct ti_softc *sc, int i)
1439 {
1440 	bus_dmamap_t map;
1441 	bus_dma_segment_t segs[1];
1442 	struct mbuf *m;
1443 	struct ti_rx_desc *r;
1444 	int error, nsegs;
1445 
1446 	MGETHDR(m, M_NOWAIT, MT_DATA);
1447 	if (m == NULL)
1448 		return (ENOBUFS);
1449 	m->m_len = m->m_pkthdr.len = MHLEN;
1450 	m_adj(m, ETHER_ALIGN);
1451 
1452 	error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag,
1453 	    sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0);
1454 	if (error != 0) {
1455 		m_freem(m);
1456 		return (error);
1457         }
1458 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1459 
1460 	if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1461 		bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1462 		    sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD);
1463 		bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag,
1464 		    sc->ti_cdata.ti_rx_mini_maps[i]);
1465 	}
1466 
1467 	map = sc->ti_cdata.ti_rx_mini_maps[i];
1468 	sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap;
1469 	sc->ti_cdata.ti_rx_mini_sparemap = map;
1470 	sc->ti_cdata.ti_rx_mini_chain[i] = m;
1471 
1472 	r = &sc->ti_rdata.ti_rx_mini_ring[i];
1473 	ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1474 	r->ti_len = segs[0].ds_len;
1475 	r->ti_type = TI_BDTYPE_RECV_BD;
1476 	r->ti_flags = TI_BDFLAG_MINI_RING;
1477 	r->ti_vlan_tag = 0;
1478 	r->ti_tcp_udp_cksum = 0;
1479 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1480 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1481 	r->ti_idx = i;
1482 
1483 	bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag,
1484 	    sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD);
1485 	return (0);
1486 }
1487 
1488 #ifndef TI_SF_BUF_JUMBO
1489 
1490 /*
1491  * Initialize a jumbo receive ring descriptor. This allocates
1492  * a jumbo buffer from the pool managed internally by the driver.
1493  */
1494 static int
1495 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy)
1496 {
1497 	bus_dmamap_t map;
1498 	bus_dma_segment_t segs[1];
1499 	struct mbuf *m;
1500 	struct ti_rx_desc *r;
1501 	int error, nsegs;
1502 
1503 	(void)dummy;
1504 
1505 	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1506 	if (m == NULL)
1507 		return (ENOBUFS);
1508 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1509 	m_adj(m, ETHER_ALIGN);
1510 
1511 	error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag,
1512 	    sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1513 	if (error != 0) {
1514 		m_freem(m);
1515 		return (error);
1516         }
1517 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1518 
1519 	if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1520 		bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1521 		    sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD);
1522 		bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag,
1523 		    sc->ti_cdata.ti_rx_jumbo_maps[i]);
1524 	}
1525 
1526 	map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1527 	sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap;
1528 	sc->ti_cdata.ti_rx_jumbo_sparemap = map;
1529 	sc->ti_cdata.ti_rx_jumbo_chain[i] = m;
1530 
1531 	r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
1532 	ti_hostaddr64(&r->ti_addr, segs[0].ds_addr);
1533 	r->ti_len = segs[0].ds_len;
1534 	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1535 	r->ti_flags = TI_BDFLAG_JUMBO_RING;
1536 	r->ti_vlan_tag = 0;
1537 	r->ti_tcp_udp_cksum = 0;
1538 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1539 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
1540 	r->ti_idx = i;
1541 
1542 	bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag,
1543 	    sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD);
1544 	return (0);
1545 }
1546 
1547 #else
1548 
1549 #if (PAGE_SIZE == 4096)
1550 #define NPAYLOAD 2
1551 #else
1552 #define NPAYLOAD 1
1553 #endif
1554 
1555 #define TCP_HDR_LEN (52 + sizeof(struct ether_header))
1556 #define UDP_HDR_LEN (28 + sizeof(struct ether_header))
1557 #define NFS_HDR_LEN (UDP_HDR_LEN)
1558 static int HDR_LEN = TCP_HDR_LEN;
1559 
1560 /*
1561  * Initialize a jumbo receive ring descriptor. This allocates
1562  * a jumbo buffer from the pool managed internally by the driver.
1563  */
1564 static int
1565 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old)
1566 {
1567 	bus_dmamap_t map;
1568 	struct mbuf *cur, *m_new = NULL;
1569 	struct mbuf *m[3] = {NULL, NULL, NULL};
1570 	struct ti_rx_desc_ext *r;
1571 	vm_page_t frame;
1572 	/* 1 extra buf to make nobufs easy*/
1573 	struct sf_buf *sf[3] = {NULL, NULL, NULL};
1574 	int i;
1575 	bus_dma_segment_t segs[4];
1576 	int nsegs;
1577 
1578 	if (m_old != NULL) {
1579 		m_new = m_old;
1580 		cur = m_old->m_next;
1581 		for (i = 0; i <= NPAYLOAD; i++){
1582 			m[i] = cur;
1583 			cur = cur->m_next;
1584 		}
1585 	} else {
1586 		/* Allocate the mbufs. */
1587 		MGETHDR(m_new, M_NOWAIT, MT_DATA);
1588 		if (m_new == NULL) {
1589 			device_printf(sc->ti_dev, "mbuf allocation failed "
1590 			    "-- packet dropped!\n");
1591 			goto nobufs;
1592 		}
1593 		MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA);
1594 		if (m[NPAYLOAD] == NULL) {
1595 			device_printf(sc->ti_dev, "cluster mbuf allocation "
1596 			    "failed -- packet dropped!\n");
1597 			goto nobufs;
1598 		}
1599 		MCLGET(m[NPAYLOAD], M_NOWAIT);
1600 		if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) {
1601 			device_printf(sc->ti_dev, "mbuf allocation failed "
1602 			    "-- packet dropped!\n");
1603 			goto nobufs;
1604 		}
1605 		m[NPAYLOAD]->m_len = MCLBYTES;
1606 
1607 		for (i = 0; i < NPAYLOAD; i++){
1608 			MGET(m[i], M_NOWAIT, MT_DATA);
1609 			if (m[i] == NULL) {
1610 				device_printf(sc->ti_dev, "mbuf allocation "
1611 				    "failed -- packet dropped!\n");
1612 				goto nobufs;
1613 			}
1614 			frame = vm_page_alloc(NULL, 0,
1615 			    VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
1616 			    VM_ALLOC_WIRED);
1617 			if (frame == NULL) {
1618 				device_printf(sc->ti_dev, "buffer allocation "
1619 				    "failed -- packet dropped!\n");
1620 				printf("      index %d page %d\n", idx, i);
1621 				goto nobufs;
1622 			}
1623 			sf[i] = sf_buf_alloc(frame, SFB_NOWAIT);
1624 			if (sf[i] == NULL) {
1625 				vm_page_unwire(frame, PQ_INACTIVE);
1626 				vm_page_free(frame);
1627 				device_printf(sc->ti_dev, "buffer allocation "
1628 				    "failed -- packet dropped!\n");
1629 				printf("      index %d page %d\n", idx, i);
1630 				goto nobufs;
1631 			}
1632 		}
1633 		for (i = 0; i < NPAYLOAD; i++){
1634 		/* Attach the buffer to the mbuf. */
1635 			m[i]->m_data = (void *)sf_buf_kva(sf[i]);
1636 			m[i]->m_len = PAGE_SIZE;
1637 			MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE,
1638 			    sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i],
1639 			    0, EXT_DISPOSABLE);
1640 			m[i]->m_next = m[i+1];
1641 		}
1642 		/* link the buffers to the header */
1643 		m_new->m_next = m[0];
1644 		m_new->m_data += ETHER_ALIGN;
1645 		if (sc->ti_hdrsplit)
1646 			m_new->m_len = MHLEN - ETHER_ALIGN;
1647 		else
1648 			m_new->m_len = HDR_LEN;
1649 		m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len;
1650 	}
1651 
1652 	/* Set up the descriptor. */
1653 	r = &sc->ti_rdata.ti_rx_jumbo_ring[idx];
1654 	sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new;
1655 	map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1656 	if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new,
1657 	    segs, &nsegs, 0))
1658 		return (ENOBUFS);
1659 	if ((nsegs < 1) || (nsegs > 4))
1660 		return (ENOBUFS);
1661 	ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr);
1662 	r->ti_len0 = m_new->m_len;
1663 
1664 	ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr);
1665 	r->ti_len1 = PAGE_SIZE;
1666 
1667 	ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr);
1668 	r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */
1669 
1670 	if (PAGE_SIZE == 4096) {
1671 		ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr);
1672 		r->ti_len3 = MCLBYTES;
1673 	} else {
1674 		r->ti_len3 = 0;
1675 	}
1676 	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
1677 
1678 	r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD;
1679 
1680 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
1681 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM;
1682 
1683 	r->ti_idx = idx;
1684 
1685 	bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD);
1686 	return (0);
1687 
1688 nobufs:
1689 
1690 	/*
1691 	 * Warning! :
1692 	 * This can only be called before the mbufs are strung together.
1693 	 * If the mbufs are strung together, m_freem() will free the chain,
1694 	 * so that the later mbufs will be freed multiple times.
1695 	 */
1696 	if (m_new)
1697 		m_freem(m_new);
1698 
1699 	for (i = 0; i < 3; i++) {
1700 		if (m[i])
1701 			m_freem(m[i]);
1702 		if (sf[i])
1703 			sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]);
1704 	}
1705 	return (ENOBUFS);
1706 }
1707 #endif
1708 
1709 /*
1710  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1711  * that's 1MB or memory, which is a lot. For now, we fill only the first
1712  * 256 ring entries and hope that our CPU is fast enough to keep up with
1713  * the NIC.
1714  */
1715 static int
1716 ti_init_rx_ring_std(struct ti_softc *sc)
1717 {
1718 	int i;
1719 	struct ti_cmd_desc cmd;
1720 
1721 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1722 		if (ti_newbuf_std(sc, i) != 0)
1723 			return (ENOBUFS);
1724 	};
1725 
1726 	sc->ti_std = TI_STD_RX_RING_CNT - 1;
1727 	TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1);
1728 
1729 	return (0);
1730 }
1731 
1732 static void
1733 ti_free_rx_ring_std(struct ti_softc *sc)
1734 {
1735 	bus_dmamap_t map;
1736 	int i;
1737 
1738 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
1739 		if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
1740 			map = sc->ti_cdata.ti_rx_std_maps[i];
1741 			bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map,
1742 			    BUS_DMASYNC_POSTREAD);
1743 			bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map);
1744 			m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
1745 			sc->ti_cdata.ti_rx_std_chain[i] = NULL;
1746 		}
1747 	}
1748 	bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ);
1749 	bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
1750 	    sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1751 }
1752 
1753 static int
1754 ti_init_rx_ring_jumbo(struct ti_softc *sc)
1755 {
1756 	struct ti_cmd_desc cmd;
1757 	int i;
1758 
1759 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1760 		if (ti_newbuf_jumbo(sc, i, NULL) != 0)
1761 			return (ENOBUFS);
1762 	};
1763 
1764 	sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1;
1765 	TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1);
1766 
1767 	return (0);
1768 }
1769 
1770 static void
1771 ti_free_rx_ring_jumbo(struct ti_softc *sc)
1772 {
1773 	bus_dmamap_t map;
1774 	int i;
1775 
1776 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
1777 		if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
1778 			map = sc->ti_cdata.ti_rx_jumbo_maps[i];
1779 			bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
1780 			    BUS_DMASYNC_POSTREAD);
1781 			bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
1782 			m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
1783 			sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
1784 		}
1785 	}
1786 	bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ);
1787 	bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
1788 	    sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1789 }
1790 
1791 static int
1792 ti_init_rx_ring_mini(struct ti_softc *sc)
1793 {
1794 	int i;
1795 
1796 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1797 		if (ti_newbuf_mini(sc, i) != 0)
1798 			return (ENOBUFS);
1799 	};
1800 
1801 	sc->ti_mini = TI_MINI_RX_RING_CNT - 1;
1802 	TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1);
1803 
1804 	return (0);
1805 }
1806 
1807 static void
1808 ti_free_rx_ring_mini(struct ti_softc *sc)
1809 {
1810 	bus_dmamap_t map;
1811 	int i;
1812 
1813 	if (sc->ti_rdata.ti_rx_mini_ring == NULL)
1814 		return;
1815 
1816 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1817 		if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1818 			map = sc->ti_cdata.ti_rx_mini_maps[i];
1819 			bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map,
1820 			    BUS_DMASYNC_POSTREAD);
1821 			bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map);
1822 			m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1823 			sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1824 		}
1825 	}
1826 	bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ);
1827 	bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
1828 	    sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
1829 }
1830 
1831 static void
1832 ti_free_tx_ring(struct ti_softc *sc)
1833 {
1834 	struct ti_txdesc *txd;
1835 	int i;
1836 
1837 	if (sc->ti_rdata.ti_tx_ring == NULL)
1838 		return;
1839 
1840 	for (i = 0; i < TI_TX_RING_CNT; i++) {
1841 		txd = &sc->ti_cdata.ti_txdesc[i];
1842 		if (txd->tx_m != NULL) {
1843 			bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
1844 			    BUS_DMASYNC_POSTWRITE);
1845 			bus_dmamap_unload(sc->ti_cdata.ti_tx_tag,
1846 			    txd->tx_dmamap);
1847 			m_freem(txd->tx_m);
1848 			txd->tx_m = NULL;
1849 		}
1850 	}
1851 	bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
1852 	bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
1853 	    sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
1854 }
1855 
1856 static int
1857 ti_init_tx_ring(struct ti_softc *sc)
1858 {
1859 	struct ti_txdesc *txd;
1860 	int i;
1861 
1862 	STAILQ_INIT(&sc->ti_cdata.ti_txfreeq);
1863 	STAILQ_INIT(&sc->ti_cdata.ti_txbusyq);
1864 	for (i = 0; i < TI_TX_RING_CNT; i++) {
1865 		txd = &sc->ti_cdata.ti_txdesc[i];
1866 		STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
1867 	}
1868 	sc->ti_txcnt = 0;
1869 	sc->ti_tx_saved_considx = 0;
1870 	sc->ti_tx_saved_prodidx = 0;
1871 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1872 	return (0);
1873 }
1874 
1875 /*
1876  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1877  * but we have to support the old way too so that Tigon 1 cards will
1878  * work.
1879  */
1880 static void
1881 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1882 {
1883 	struct ti_cmd_desc cmd;
1884 	uint16_t *m;
1885 	uint32_t ext[2] = {0, 0};
1886 
1887 	m = (uint16_t *)&addr->octet[0];
1888 
1889 	switch (sc->ti_hwrev) {
1890 	case TI_HWREV_TIGON:
1891 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1892 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1893 		TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1894 		break;
1895 	case TI_HWREV_TIGON_II:
1896 		ext[0] = htons(m[0]);
1897 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1898 		TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1899 		break;
1900 	default:
1901 		device_printf(sc->ti_dev, "unknown hwrev\n");
1902 		break;
1903 	}
1904 }
1905 
1906 static void
1907 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1908 {
1909 	struct ti_cmd_desc cmd;
1910 	uint16_t *m;
1911 	uint32_t ext[2] = {0, 0};
1912 
1913 	m = (uint16_t *)&addr->octet[0];
1914 
1915 	switch (sc->ti_hwrev) {
1916 	case TI_HWREV_TIGON:
1917 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1918 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1919 		TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1920 		break;
1921 	case TI_HWREV_TIGON_II:
1922 		ext[0] = htons(m[0]);
1923 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1924 		TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1925 		break;
1926 	default:
1927 		device_printf(sc->ti_dev, "unknown hwrev\n");
1928 		break;
1929 	}
1930 }
1931 
1932 /*
1933  * Configure the Tigon's multicast address filter.
1934  *
1935  * The actual multicast table management is a bit of a pain, thanks to
1936  * slight brain damage on the part of both Alteon and us. With our
1937  * multicast code, we are only alerted when the multicast address table
1938  * changes and at that point we only have the current list of addresses:
1939  * we only know the current state, not the previous state, so we don't
1940  * actually know what addresses were removed or added. The firmware has
1941  * state, but we can't get our grubby mits on it, and there is no 'delete
1942  * all multicast addresses' command. Hence, we have to maintain our own
1943  * state so we know what addresses have been programmed into the NIC at
1944  * any given time.
1945  */
1946 static void
1947 ti_setmulti(struct ti_softc *sc)
1948 {
1949 	struct ifnet *ifp;
1950 	struct ifmultiaddr *ifma;
1951 	struct ti_cmd_desc cmd;
1952 	struct ti_mc_entry *mc;
1953 	uint32_t intrs;
1954 
1955 	TI_LOCK_ASSERT(sc);
1956 
1957 	ifp = sc->ti_ifp;
1958 
1959 	if (ifp->if_flags & IFF_ALLMULTI) {
1960 		TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1961 		return;
1962 	} else {
1963 		TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1964 	}
1965 
1966 	/* Disable interrupts. */
1967 	intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1968 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1969 
1970 	/* First, zot all the existing filters. */
1971 	while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1972 		mc = SLIST_FIRST(&sc->ti_mc_listhead);
1973 		ti_del_mcast(sc, &mc->mc_addr);
1974 		SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1975 		free(mc, M_DEVBUF);
1976 	}
1977 
1978 	/* Now program new ones. */
1979 	if_maddr_rlock(ifp);
1980 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1981 		if (ifma->ifma_addr->sa_family != AF_LINK)
1982 			continue;
1983 		mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1984 		if (mc == NULL) {
1985 			device_printf(sc->ti_dev,
1986 			    "no memory for mcast filter entry\n");
1987 			continue;
1988 		}
1989 		bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1990 		    (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1991 		SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1992 		ti_add_mcast(sc, &mc->mc_addr);
1993 	}
1994 	if_maddr_runlock(ifp);
1995 
1996 	/* Re-enable interrupts. */
1997 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1998 }
1999 
2000 /*
2001  * Check to see if the BIOS has configured us for a 64 bit slot when
2002  * we aren't actually in one. If we detect this condition, we can work
2003  * around it on the Tigon 2 by setting a bit in the PCI state register,
2004  * but for the Tigon 1 we must give up and abort the interface attach.
2005  */
2006 static int
2007 ti_64bitslot_war(struct ti_softc *sc)
2008 {
2009 
2010 	if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
2011 		CSR_WRITE_4(sc, 0x600, 0);
2012 		CSR_WRITE_4(sc, 0x604, 0);
2013 		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
2014 		if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
2015 			if (sc->ti_hwrev == TI_HWREV_TIGON)
2016 				return (EINVAL);
2017 			else {
2018 				TI_SETBIT(sc, TI_PCI_STATE,
2019 				    TI_PCISTATE_32BIT_BUS);
2020 				return (0);
2021 			}
2022 		}
2023 	}
2024 
2025 	return (0);
2026 }
2027 
2028 /*
2029  * Do endian, PCI and DMA initialization. Also check the on-board ROM
2030  * self-test results.
2031  */
2032 static int
2033 ti_chipinit(struct ti_softc *sc)
2034 {
2035 	uint32_t cacheline;
2036 	uint32_t pci_writemax = 0;
2037 	uint32_t hdrsplit;
2038 
2039 	/* Initialize link to down state. */
2040 	sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
2041 
2042 	/* Set endianness before we access any non-PCI registers. */
2043 #if 0 && BYTE_ORDER == BIG_ENDIAN
2044 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2045 	    TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
2046 #else
2047 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
2048 	    TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
2049 #endif
2050 
2051 	/* Check the ROM failed bit to see if self-tests passed. */
2052 	if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2053 		device_printf(sc->ti_dev, "board self-diagnostics failed!\n");
2054 		return (ENODEV);
2055 	}
2056 
2057 	/* Halt the CPU. */
2058 	TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
2059 
2060 	/* Figure out the hardware revision. */
2061 	switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2062 	case TI_REV_TIGON_I:
2063 		sc->ti_hwrev = TI_HWREV_TIGON;
2064 		break;
2065 	case TI_REV_TIGON_II:
2066 		sc->ti_hwrev = TI_HWREV_TIGON_II;
2067 		break;
2068 	default:
2069 		device_printf(sc->ti_dev, "unsupported chip revision\n");
2070 		return (ENODEV);
2071 	}
2072 
2073 	/* Do special setup for Tigon 2. */
2074 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2075 		TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
2076 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
2077 		TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
2078 	}
2079 
2080 	/*
2081 	 * We don't have firmware source for the Tigon 1, so Tigon 1 boards
2082 	 * can't do header splitting.
2083 	 */
2084 #ifdef TI_JUMBO_HDRSPLIT
2085 	if (sc->ti_hwrev != TI_HWREV_TIGON)
2086 		sc->ti_hdrsplit = 1;
2087 	else
2088 		device_printf(sc->ti_dev,
2089 		    "can't do header splitting on a Tigon I board\n");
2090 #endif /* TI_JUMBO_HDRSPLIT */
2091 
2092 	/* Set up the PCI state register. */
2093 	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
2094 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
2095 		TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
2096 	}
2097 
2098 	/* Clear the read/write max DMA parameters. */
2099 	TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
2100 	    TI_PCISTATE_READ_MAXDMA));
2101 
2102 	/* Get cache line size. */
2103 	cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2104 
2105 	/*
2106 	 * If the system has set enabled the PCI memory write
2107 	 * and invalidate command in the command register, set
2108 	 * the write max parameter accordingly. This is necessary
2109 	 * to use MWI with the Tigon 2.
2110 	 */
2111 	if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2112 		switch (cacheline) {
2113 		case 1:
2114 		case 4:
2115 		case 8:
2116 		case 16:
2117 		case 32:
2118 		case 64:
2119 			break;
2120 		default:
2121 		/* Disable PCI memory write and invalidate. */
2122 			if (bootverbose)
2123 				device_printf(sc->ti_dev, "cache line size %d"
2124 				    " not supported; disabling PCI MWI\n",
2125 				    cacheline);
2126 			CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2127 			    TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
2128 			break;
2129 		}
2130 	}
2131 
2132 	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
2133 
2134 	/* This sets the min dma param all the way up (0xff). */
2135 	TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
2136 
2137 	if (sc->ti_hdrsplit)
2138 		hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT;
2139 	else
2140 		hdrsplit = 0;
2141 
2142 	/* Configure DMA variables. */
2143 #if BYTE_ORDER == BIG_ENDIAN
2144 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
2145 	    TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
2146 	    TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
2147 	    TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit);
2148 #else /* BYTE_ORDER */
2149 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
2150 	    TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
2151 	    TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit);
2152 #endif /* BYTE_ORDER */
2153 
2154 	/*
2155 	 * Only allow 1 DMA channel to be active at a time.
2156 	 * I don't think this is a good idea, but without it
2157 	 * the firmware racks up lots of nicDmaReadRingFull
2158 	 * errors.  This is not compatible with hardware checksums.
2159 	 */
2160 	if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0)
2161 		TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
2162 
2163 	/* Recommended settings from Tigon manual. */
2164 	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
2165 	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
2166 
2167 	if (ti_64bitslot_war(sc)) {
2168 		device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, "
2169 		    "but we aren't");
2170 		return (EINVAL);
2171 	}
2172 
2173 	return (0);
2174 }
2175 
2176 /*
2177  * Initialize the general information block and firmware, and
2178  * start the CPU(s) running.
2179  */
2180 static int
2181 ti_gibinit(struct ti_softc *sc)
2182 {
2183 	struct ifnet *ifp;
2184 	struct ti_rcb *rcb;
2185 	int i;
2186 
2187 	TI_LOCK_ASSERT(sc);
2188 
2189 	ifp = sc->ti_ifp;
2190 
2191 	/* Disable interrupts for now. */
2192 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2193 
2194 	/* Tell the chip where to find the general information block. */
2195 	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI,
2196 	    (uint64_t)sc->ti_rdata.ti_info_paddr >> 32);
2197 	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
2198 	    sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF);
2199 
2200 	/* Load the firmware into SRAM. */
2201 	ti_loadfw(sc);
2202 
2203 	/* Set up the contents of the general info and ring control blocks. */
2204 
2205 	/* Set up the event ring and producer pointer. */
2206 	bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ);
2207 	rcb = &sc->ti_rdata.ti_info->ti_ev_rcb;
2208 	ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr);
2209 	rcb->ti_flags = 0;
2210 	ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr,
2211 	    sc->ti_rdata.ti_status_paddr +
2212 	    offsetof(struct ti_status, ti_ev_prodidx_r));
2213 	sc->ti_ev_prodidx.ti_idx = 0;
2214 	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
2215 	sc->ti_ev_saved_considx = 0;
2216 
2217 	/* Set up the command ring and producer mailbox. */
2218 	rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb;
2219 	ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
2220 	rcb->ti_flags = 0;
2221 	rcb->ti_max_len = 0;
2222 	for (i = 0; i < TI_CMD_RING_CNT; i++) {
2223 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
2224 	}
2225 	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
2226 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
2227 	sc->ti_cmd_saved_prodidx = 0;
2228 
2229 	/*
2230 	 * Assign the address of the stats refresh buffer.
2231 	 * We re-use the current stats buffer for this to
2232 	 * conserve memory.
2233 	 */
2234 	bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats));
2235 	ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr,
2236 	    sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats));
2237 
2238 	/* Set up the standard receive ring. */
2239 	rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb;
2240 	ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr);
2241 	rcb->ti_max_len = TI_FRAMELEN;
2242 	rcb->ti_flags = 0;
2243 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2244 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2245 		     TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2246 	if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2247 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2248 
2249 	/* Set up the jumbo receive ring. */
2250 	rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb;
2251 	ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr);
2252 
2253 #ifndef TI_SF_BUF_JUMBO
2254 	rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN;
2255 	rcb->ti_flags = 0;
2256 #else
2257 	rcb->ti_max_len = PAGE_SIZE;
2258 	rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD;
2259 #endif
2260 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2261 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2262 		     TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2263 	if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2264 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2265 
2266 	/*
2267 	 * Set up the mini ring. Only activated on the
2268 	 * Tigon 2 but the slot in the config block is
2269 	 * still there on the Tigon 1.
2270 	 */
2271 	rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb;
2272 	ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr);
2273 	rcb->ti_max_len = MHLEN - ETHER_ALIGN;
2274 	if (sc->ti_hwrev == TI_HWREV_TIGON)
2275 		rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
2276 	else
2277 		rcb->ti_flags = 0;
2278 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2279 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2280 		     TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2281 	if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2282 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2283 
2284 	/*
2285 	 * Set up the receive return ring.
2286 	 */
2287 	rcb = &sc->ti_rdata.ti_info->ti_return_rcb;
2288 	ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr);
2289 	rcb->ti_flags = 0;
2290 	rcb->ti_max_len = TI_RETURN_RING_CNT;
2291 	ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr,
2292 	    sc->ti_rdata.ti_status_paddr +
2293 	    offsetof(struct ti_status, ti_return_prodidx_r));
2294 
2295 	/*
2296 	 * Set up the tx ring. Note: for the Tigon 2, we have the option
2297 	 * of putting the transmit ring in the host's address space and
2298 	 * letting the chip DMA it instead of leaving the ring in the NIC's
2299 	 * memory and accessing it through the shared memory region. We
2300 	 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
2301 	 * so we have to revert to the shared memory scheme if we detect
2302 	 * a Tigon 1 chip.
2303 	 */
2304 	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
2305 	if (sc->ti_rdata.ti_tx_ring != NULL)
2306 		bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ);
2307 	rcb = &sc->ti_rdata.ti_info->ti_tx_rcb;
2308 	if (sc->ti_hwrev == TI_HWREV_TIGON)
2309 		rcb->ti_flags = 0;
2310 	else
2311 		rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
2312 	if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2313 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
2314 	if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM)
2315 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
2316 		     TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
2317 	rcb->ti_max_len = TI_TX_RING_CNT;
2318 	if (sc->ti_hwrev == TI_HWREV_TIGON)
2319 		ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE);
2320 	else
2321 		ti_hostaddr64(&rcb->ti_hostaddr,
2322 		    sc->ti_rdata.ti_tx_ring_paddr);
2323 	ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr,
2324 	    sc->ti_rdata.ti_status_paddr +
2325 	    offsetof(struct ti_status, ti_tx_considx_r));
2326 
2327 	bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map,
2328 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2329 	bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map,
2330 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2331 	bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag,
2332 	    sc->ti_cdata.ti_event_ring_map,
2333 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2334 	if (sc->ti_rdata.ti_tx_ring != NULL)
2335 		bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2336 		    sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
2337 
2338 	/* Set up tunables */
2339 #if 0
2340 	if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2341 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
2342 		    (sc->ti_rx_coal_ticks / 10));
2343 	else
2344 #endif
2345 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
2346 	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
2347 	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
2348 	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
2349 	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
2350 	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
2351 
2352 	/* Turn interrupts on. */
2353 	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
2354 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2355 
2356 	/* Start CPU. */
2357 	TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
2358 
2359 	return (0);
2360 }
2361 
2362 /*
2363  * Probe for a Tigon chip. Check the PCI vendor and device IDs
2364  * against our list and return its name if we find a match.
2365  */
2366 static int
2367 ti_probe(device_t dev)
2368 {
2369 	const struct ti_type *t;
2370 
2371 	t = ti_devs;
2372 
2373 	while (t->ti_name != NULL) {
2374 		if ((pci_get_vendor(dev) == t->ti_vid) &&
2375 		    (pci_get_device(dev) == t->ti_did)) {
2376 			device_set_desc(dev, t->ti_name);
2377 			return (BUS_PROBE_DEFAULT);
2378 		}
2379 		t++;
2380 	}
2381 
2382 	return (ENXIO);
2383 }
2384 
2385 static int
2386 ti_attach(device_t dev)
2387 {
2388 	struct ifnet *ifp;
2389 	struct ti_softc *sc;
2390 	int error = 0, rid;
2391 	u_char eaddr[6];
2392 
2393 	sc = device_get_softc(dev);
2394 	sc->ti_dev = dev;
2395 
2396 	mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2397 	    MTX_DEF);
2398 	callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0);
2399 	ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
2400 	ifp = sc->ti_ifp = if_alloc(IFT_ETHER);
2401 	if (ifp == NULL) {
2402 		device_printf(dev, "can not if_alloc()\n");
2403 		error = ENOSPC;
2404 		goto fail;
2405 	}
2406 	sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES;
2407 	sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
2408 	sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities;
2409 
2410 	/*
2411 	 * Map control/status registers.
2412 	 */
2413 	pci_enable_busmaster(dev);
2414 
2415 	rid = PCIR_BAR(0);
2416 	sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2417 	    RF_ACTIVE);
2418 
2419 	if (sc->ti_res == NULL) {
2420 		device_printf(dev, "couldn't map memory\n");
2421 		error = ENXIO;
2422 		goto fail;
2423 	}
2424 
2425 	sc->ti_btag = rman_get_bustag(sc->ti_res);
2426 	sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
2427 
2428 	/* Allocate interrupt */
2429 	rid = 0;
2430 
2431 	sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2432 	    RF_SHAREABLE | RF_ACTIVE);
2433 
2434 	if (sc->ti_irq == NULL) {
2435 		device_printf(dev, "couldn't map interrupt\n");
2436 		error = ENXIO;
2437 		goto fail;
2438 	}
2439 
2440 	if (ti_chipinit(sc)) {
2441 		device_printf(dev, "chip initialization failed\n");
2442 		error = ENXIO;
2443 		goto fail;
2444 	}
2445 
2446 	/* Zero out the NIC's on-board SRAM. */
2447 	ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
2448 
2449 	/* Init again -- zeroing memory may have clobbered some registers. */
2450 	if (ti_chipinit(sc)) {
2451 		device_printf(dev, "chip initialization failed\n");
2452 		error = ENXIO;
2453 		goto fail;
2454 	}
2455 
2456 	/*
2457 	 * Get station address from the EEPROM. Note: the manual states
2458 	 * that the MAC address is at offset 0x8c, however the data is
2459 	 * stored as two longwords (since that's how it's loaded into
2460 	 * the NIC). This means the MAC address is actually preceded
2461 	 * by two zero bytes. We need to skip over those.
2462 	 */
2463 	if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2464 		device_printf(dev, "failed to read station address\n");
2465 		error = ENXIO;
2466 		goto fail;
2467 	}
2468 
2469 	/* Allocate working area for memory dump. */
2470 	sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT);
2471 	sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF,
2472 	    M_NOWAIT);
2473 	if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) {
2474 		device_printf(dev, "cannot allocate memory buffer\n");
2475 		error = ENOMEM;
2476 		goto fail;
2477 	}
2478 	if ((error = ti_dma_alloc(sc)) != 0)
2479 		goto fail;
2480 
2481 	/*
2482 	 * We really need a better way to tell a 1000baseTX card
2483 	 * from a 1000baseSX one, since in theory there could be
2484 	 * OEMed 1000baseTX cards from lame vendors who aren't
2485 	 * clever enough to change the PCI ID. For the moment
2486 	 * though, the AceNIC is the only copper card available.
2487 	 */
2488 	if (pci_get_vendor(dev) == ALT_VENDORID &&
2489 	    pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
2490 		sc->ti_copper = 1;
2491 	/* Ok, it's not the only copper card available. */
2492 	if (pci_get_vendor(dev) == NG_VENDORID &&
2493 	    pci_get_device(dev) == NG_DEVICEID_GA620T)
2494 		sc->ti_copper = 1;
2495 
2496 	/* Set default tunable values. */
2497 	ti_sysctl_node(sc);
2498 
2499 	/* Set up ifnet structure */
2500 	ifp->if_softc = sc;
2501 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2502 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2503 	ifp->if_ioctl = ti_ioctl;
2504 	ifp->if_start = ti_start;
2505 	ifp->if_init = ti_init;
2506 	ifp->if_get_counter = ti_get_counter;
2507 	ifp->if_baudrate = IF_Gbps(1UL);
2508 	ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1;
2509 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2510 	IFQ_SET_READY(&ifp->if_snd);
2511 
2512 	/* Set up ifmedia support. */
2513 	if (sc->ti_copper) {
2514 		/*
2515 		 * Copper cards allow manual 10/100 mode selection,
2516 		 * but not manual 1000baseTX mode selection. Why?
2517 		 * Becuase currently there's no way to specify the
2518 		 * master/slave setting through the firmware interface,
2519 		 * so Alteon decided to just bag it and handle it
2520 		 * via autonegotiation.
2521 		 */
2522 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
2523 		ifmedia_add(&sc->ifmedia,
2524 		    IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
2525 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
2526 		ifmedia_add(&sc->ifmedia,
2527 		    IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
2528 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
2529 		ifmedia_add(&sc->ifmedia,
2530 		    IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
2531 	} else {
2532 		/* Fiber cards don't support 10/100 modes. */
2533 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2534 		ifmedia_add(&sc->ifmedia,
2535 		    IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2536 	}
2537 	ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2538 	ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
2539 
2540 	/*
2541 	 * We're assuming here that card initialization is a sequential
2542 	 * thing.  If it isn't, multiple cards probing at the same time
2543 	 * could stomp on the list of softcs here.
2544 	 */
2545 
2546 	/* Register the device */
2547 	sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT,
2548 	    GID_OPERATOR, 0600, "ti%d", device_get_unit(dev));
2549 	sc->dev->si_drv1 = sc;
2550 
2551 	/*
2552 	 * Call MI attach routine.
2553 	 */
2554 	ether_ifattach(ifp, eaddr);
2555 
2556 	/* VLAN capability setup. */
2557 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM |
2558 	    IFCAP_VLAN_HWTAGGING;
2559 	ifp->if_capenable = ifp->if_capabilities;
2560 	/* Tell the upper layer we support VLAN over-sized frames. */
2561 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
2562 
2563 	/* Driver supports link state tracking. */
2564 	ifp->if_capabilities |= IFCAP_LINKSTATE;
2565 	ifp->if_capenable |= IFCAP_LINKSTATE;
2566 
2567 	/* Hook interrupt last to avoid having to lock softc */
2568 	error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE,
2569 	   NULL, ti_intr, sc, &sc->ti_intrhand);
2570 
2571 	if (error) {
2572 		device_printf(dev, "couldn't set up irq\n");
2573 		goto fail;
2574 	}
2575 
2576 fail:
2577 	if (error)
2578 		ti_detach(dev);
2579 
2580 	return (error);
2581 }
2582 
2583 /*
2584  * Shutdown hardware and free up resources. This can be called any
2585  * time after the mutex has been initialized. It is called in both
2586  * the error case in attach and the normal detach case so it needs
2587  * to be careful about only freeing resources that have actually been
2588  * allocated.
2589  */
2590 static int
2591 ti_detach(device_t dev)
2592 {
2593 	struct ti_softc *sc;
2594 	struct ifnet *ifp;
2595 
2596 	sc = device_get_softc(dev);
2597 	if (sc->dev)
2598 		destroy_dev(sc->dev);
2599 	KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized"));
2600 	ifp = sc->ti_ifp;
2601 	if (device_is_attached(dev)) {
2602 		ether_ifdetach(ifp);
2603 		TI_LOCK(sc);
2604 		ti_stop(sc);
2605 		TI_UNLOCK(sc);
2606 	}
2607 
2608 	/* These should only be active if attach succeeded */
2609 	callout_drain(&sc->ti_watchdog);
2610 	bus_generic_detach(dev);
2611 	ti_dma_free(sc);
2612 	ifmedia_removeall(&sc->ifmedia);
2613 
2614 	if (sc->ti_intrhand)
2615 		bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
2616 	if (sc->ti_irq)
2617 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
2618 	if (sc->ti_res) {
2619 		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2620 		    sc->ti_res);
2621 	}
2622 	if (ifp)
2623 		if_free(ifp);
2624 	if (sc->ti_membuf)
2625 		free(sc->ti_membuf, M_DEVBUF);
2626 	if (sc->ti_membuf2)
2627 		free(sc->ti_membuf2, M_DEVBUF);
2628 
2629 	mtx_destroy(&sc->ti_mtx);
2630 
2631 	return (0);
2632 }
2633 
2634 #ifdef TI_JUMBO_HDRSPLIT
2635 /*
2636  * If hdr_len is 0, that means that header splitting wasn't done on
2637  * this packet for some reason.  The two most likely reasons are that
2638  * the protocol isn't a supported protocol for splitting, or this
2639  * packet had a fragment offset that wasn't 0.
2640  *
2641  * The header length, if it is non-zero, will always be the length of
2642  * the headers on the packet, but that length could be longer than the
2643  * first mbuf.  So we take the minimum of the two as the actual
2644  * length.
2645  */
2646 static __inline void
2647 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx)
2648 {
2649 	int i = 0;
2650 	int lengths[4] = {0, 0, 0, 0};
2651 	struct mbuf *m, *mp;
2652 
2653 	if (hdr_len != 0)
2654 		top->m_len = min(hdr_len, top->m_len);
2655 	pkt_len -= top->m_len;
2656 	lengths[i++] = top->m_len;
2657 
2658 	mp = top;
2659 	for (m = top->m_next; m && pkt_len; m = m->m_next) {
2660 		m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len);
2661 		pkt_len -= m->m_len;
2662 		lengths[i++] = m->m_len;
2663 		mp = m;
2664 	}
2665 
2666 #if 0
2667 	if (hdr_len != 0)
2668 		printf("got split packet: ");
2669 	else
2670 		printf("got non-split packet: ");
2671 
2672 	printf("%d,%d,%d,%d = %d\n", lengths[0],
2673 	    lengths[1], lengths[2], lengths[3],
2674 	    lengths[0] + lengths[1] + lengths[2] +
2675 	    lengths[3]);
2676 #endif
2677 
2678 	if (pkt_len)
2679 		panic("header splitting didn't");
2680 
2681 	if (m) {
2682 		m_freem(m);
2683 		mp->m_next = NULL;
2684 
2685 	}
2686 	if (mp->m_next != NULL)
2687 		panic("ti_hdr_split: last mbuf in chain should be null");
2688 }
2689 #endif /* TI_JUMBO_HDRSPLIT */
2690 
2691 static void
2692 ti_discard_std(struct ti_softc *sc, int i)
2693 {
2694 
2695 	struct ti_rx_desc *r;
2696 
2697 	r = &sc->ti_rdata.ti_rx_std_ring[i];
2698 	r->ti_len = MCLBYTES - ETHER_ALIGN;
2699 	r->ti_type = TI_BDTYPE_RECV_BD;
2700 	r->ti_flags = 0;
2701 	r->ti_vlan_tag = 0;
2702 	r->ti_tcp_udp_cksum = 0;
2703 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2704 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2705 	r->ti_idx = i;
2706 }
2707 
2708 static void
2709 ti_discard_mini(struct ti_softc *sc, int i)
2710 {
2711 
2712 	struct ti_rx_desc *r;
2713 
2714 	r = &sc->ti_rdata.ti_rx_mini_ring[i];
2715 	r->ti_len = MHLEN - ETHER_ALIGN;
2716 	r->ti_type = TI_BDTYPE_RECV_BD;
2717 	r->ti_flags = TI_BDFLAG_MINI_RING;
2718 	r->ti_vlan_tag = 0;
2719 	r->ti_tcp_udp_cksum = 0;
2720 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2721 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2722 	r->ti_idx = i;
2723 }
2724 
2725 #ifndef TI_SF_BUF_JUMBO
2726 static void
2727 ti_discard_jumbo(struct ti_softc *sc, int i)
2728 {
2729 
2730 	struct ti_rx_desc *r;
2731 
2732 	r = &sc->ti_rdata.ti_rx_jumbo_ring[i];
2733 	r->ti_len = MJUM9BYTES - ETHER_ALIGN;
2734 	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
2735 	r->ti_flags = TI_BDFLAG_JUMBO_RING;
2736 	r->ti_vlan_tag = 0;
2737 	r->ti_tcp_udp_cksum = 0;
2738 	if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM)
2739 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
2740 	r->ti_idx = i;
2741 }
2742 #endif
2743 
2744 /*
2745  * Frame reception handling. This is called if there's a frame
2746  * on the receive return list.
2747  *
2748  * Note: we have to be able to handle three possibilities here:
2749  * 1) the frame is from the mini receive ring (can only happen)
2750  *    on Tigon 2 boards)
2751  * 2) the frame is from the jumbo recieve ring
2752  * 3) the frame is from the standard receive ring
2753  */
2754 
2755 static void
2756 ti_rxeof(struct ti_softc *sc)
2757 {
2758 	struct ifnet *ifp;
2759 #ifdef TI_SF_BUF_JUMBO
2760 	bus_dmamap_t map;
2761 #endif
2762 	struct ti_cmd_desc cmd;
2763 	int jumbocnt, minicnt, stdcnt, ti_len;
2764 
2765 	TI_LOCK_ASSERT(sc);
2766 
2767 	ifp = sc->ti_ifp;
2768 
2769 	bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2770 	    sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
2771 	if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN)
2772 		bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2773 		    sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
2774 	if (sc->ti_rdata.ti_rx_mini_ring != NULL)
2775 		bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2776 		    sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE);
2777 	bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2778 	    sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
2779 
2780 	jumbocnt = minicnt = stdcnt = 0;
2781 	while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
2782 		struct ti_rx_desc *cur_rx;
2783 		uint32_t rxidx;
2784 		struct mbuf *m = NULL;
2785 		uint16_t vlan_tag = 0;
2786 		int have_tag = 0;
2787 
2788 		cur_rx =
2789 		    &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx];
2790 		rxidx = cur_rx->ti_idx;
2791 		ti_len = cur_rx->ti_len;
2792 		TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
2793 
2794 		if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
2795 			have_tag = 1;
2796 			vlan_tag = cur_rx->ti_vlan_tag;
2797 		}
2798 
2799 		if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
2800 			jumbocnt++;
2801 			TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
2802 			m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
2803 #ifndef TI_SF_BUF_JUMBO
2804 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2805 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2806 				ti_discard_jumbo(sc, rxidx);
2807 				continue;
2808 			}
2809 			if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) {
2810 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2811 				ti_discard_jumbo(sc, rxidx);
2812 				continue;
2813 			}
2814 			m->m_len = ti_len;
2815 #else /* !TI_SF_BUF_JUMBO */
2816 			sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
2817 			map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx];
2818 			bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map,
2819 			    BUS_DMASYNC_POSTREAD);
2820 			bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map);
2821 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2822 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2823 				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2824 				continue;
2825 			}
2826 			if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
2827 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2828 				ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
2829 				continue;
2830 			}
2831 #ifdef TI_JUMBO_HDRSPLIT
2832 			if (sc->ti_hdrsplit)
2833 				ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr),
2834 					     ti_len, rxidx);
2835 			else
2836 #endif /* TI_JUMBO_HDRSPLIT */
2837 			m_adj(m, ti_len - m->m_pkthdr.len);
2838 #endif /* TI_SF_BUF_JUMBO */
2839 		} else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
2840 			minicnt++;
2841 			TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
2842 			m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
2843 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2844 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2845 				ti_discard_mini(sc, rxidx);
2846 				continue;
2847 			}
2848 			if (ti_newbuf_mini(sc, rxidx) != 0) {
2849 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2850 				ti_discard_mini(sc, rxidx);
2851 				continue;
2852 			}
2853 			m->m_len = ti_len;
2854 		} else {
2855 			stdcnt++;
2856 			TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
2857 			m = sc->ti_cdata.ti_rx_std_chain[rxidx];
2858 			if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
2859 				if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2860 				ti_discard_std(sc, rxidx);
2861 				continue;
2862 			}
2863 			if (ti_newbuf_std(sc, rxidx) != 0) {
2864 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2865 				ti_discard_std(sc, rxidx);
2866 				continue;
2867 			}
2868 			m->m_len = ti_len;
2869 		}
2870 
2871 		m->m_pkthdr.len = ti_len;
2872 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2873 		m->m_pkthdr.rcvif = ifp;
2874 
2875 		if (ifp->if_capenable & IFCAP_RXCSUM) {
2876 			if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) {
2877 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2878 				if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
2879 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2880 			}
2881 			if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) {
2882 				m->m_pkthdr.csum_data =
2883 				    cur_rx->ti_tcp_udp_cksum;
2884 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2885 			}
2886 		}
2887 
2888 		/*
2889 		 * If we received a packet with a vlan tag,
2890 		 * tag it before passing the packet upward.
2891 		 */
2892 		if (have_tag) {
2893 			m->m_pkthdr.ether_vtag = vlan_tag;
2894 			m->m_flags |= M_VLANTAG;
2895 		}
2896 		TI_UNLOCK(sc);
2897 		(*ifp->if_input)(ifp, m);
2898 		TI_LOCK(sc);
2899 	}
2900 
2901 	bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag,
2902 	    sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD);
2903 	/* Only necessary on the Tigon 1. */
2904 	if (sc->ti_hwrev == TI_HWREV_TIGON)
2905 		CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2906 		    sc->ti_rx_saved_considx);
2907 
2908 	if (stdcnt > 0) {
2909 		bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag,
2910 		    sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
2911 		TI_UPDATE_STDPROD(sc, sc->ti_std);
2912 	}
2913 	if (minicnt > 0) {
2914 		bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag,
2915 		    sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE);
2916 		TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2917 	}
2918 	if (jumbocnt > 0) {
2919 		bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag,
2920 		    sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
2921 		TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2922 	}
2923 }
2924 
2925 static void
2926 ti_txeof(struct ti_softc *sc)
2927 {
2928 	struct ti_txdesc *txd;
2929 	struct ti_tx_desc txdesc;
2930 	struct ti_tx_desc *cur_tx = NULL;
2931 	struct ifnet *ifp;
2932 	int idx;
2933 
2934 	ifp = sc->ti_ifp;
2935 
2936 	txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2937 	if (txd == NULL)
2938 		return;
2939 
2940 	if (sc->ti_rdata.ti_tx_ring != NULL)
2941 		bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
2942 		    sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE);
2943 	/*
2944 	 * Go through our tx ring and free mbufs for those
2945 	 * frames that have been sent.
2946 	 */
2947 	for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx;
2948 	    TI_INC(idx, TI_TX_RING_CNT)) {
2949 		if (sc->ti_hwrev == TI_HWREV_TIGON) {
2950 			ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
2951 			    sizeof(txdesc), &txdesc);
2952 			cur_tx = &txdesc;
2953 		} else
2954 			cur_tx = &sc->ti_rdata.ti_tx_ring[idx];
2955 		sc->ti_txcnt--;
2956 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2957 		if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0)
2958 			continue;
2959 		bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
2960 		    BUS_DMASYNC_POSTWRITE);
2961 		bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
2962 
2963 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2964 		m_freem(txd->tx_m);
2965 		txd->tx_m = NULL;
2966 		STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q);
2967 		STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q);
2968 		txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq);
2969 	}
2970 	sc->ti_tx_saved_considx = idx;
2971 	if (sc->ti_txcnt == 0)
2972 		sc->ti_timer = 0;
2973 }
2974 
2975 static void
2976 ti_intr(void *xsc)
2977 {
2978 	struct ti_softc *sc;
2979 	struct ifnet *ifp;
2980 
2981 	sc = xsc;
2982 	TI_LOCK(sc);
2983 	ifp = sc->ti_ifp;
2984 
2985 	/* Make sure this is really our interrupt. */
2986 	if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
2987 		TI_UNLOCK(sc);
2988 		return;
2989 	}
2990 
2991 	/* Ack interrupt and stop others from occuring. */
2992 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2993 
2994 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2995 		bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
2996 		    sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD);
2997 		/* Check RX return ring producer/consumer */
2998 		ti_rxeof(sc);
2999 
3000 		/* Check TX ring producer/consumer */
3001 		ti_txeof(sc);
3002 		bus_dmamap_sync(sc->ti_cdata.ti_status_tag,
3003 		    sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD);
3004 	}
3005 
3006 	ti_handle_events(sc);
3007 
3008 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3009 		/* Re-enable interrupts. */
3010 		CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3011 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3012 			ti_start_locked(ifp);
3013 	}
3014 
3015 	TI_UNLOCK(sc);
3016 }
3017 
3018 static uint64_t
3019 ti_get_counter(struct ifnet *ifp, ift_counter cnt)
3020 {
3021 
3022 	switch (cnt) {
3023 	case IFCOUNTER_COLLISIONS:
3024 	    {
3025 		struct ti_softc *sc;
3026 		struct ti_stats *s;
3027 		uint64_t rv;
3028 
3029 		sc = if_getsoftc(ifp);
3030 		s = &sc->ti_rdata.ti_info->ti_stats;
3031 
3032 		TI_LOCK(sc);
3033 		bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3034 		    sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3035 		rv = s->dot3StatsSingleCollisionFrames +
3036 		    s->dot3StatsMultipleCollisionFrames +
3037 		    s->dot3StatsExcessiveCollisions +
3038 		    s->dot3StatsLateCollisions;
3039 		bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3040 		    sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3041 		TI_UNLOCK(sc);
3042 		return (rv);
3043 	    }
3044 	default:
3045 		return (if_get_counter_default(ifp, cnt));
3046 	}
3047 }
3048 
3049 /*
3050  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3051  * pointers to descriptors.
3052  */
3053 static int
3054 ti_encap(struct ti_softc *sc, struct mbuf **m_head)
3055 {
3056 	struct ti_txdesc *txd;
3057 	struct ti_tx_desc *f;
3058 	struct ti_tx_desc txdesc;
3059 	struct mbuf *m;
3060 	bus_dma_segment_t txsegs[TI_MAXTXSEGS];
3061 	uint16_t csum_flags;
3062 	int error, frag, i, nseg;
3063 
3064 	if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL)
3065 		return (ENOBUFS);
3066 
3067 	error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3068 	    *m_head, txsegs, &nseg, 0);
3069 	if (error == EFBIG) {
3070 		m = m_defrag(*m_head, M_NOWAIT);
3071 		if (m == NULL) {
3072 			m_freem(*m_head);
3073 			*m_head = NULL;
3074 			return (ENOMEM);
3075 		}
3076 		*m_head = m;
3077 		error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag,
3078 		    txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
3079 		if (error) {
3080 			m_freem(*m_head);
3081 			*m_head = NULL;
3082 			return (error);
3083 		}
3084 	} else if (error != 0)
3085 		return (error);
3086 	if (nseg == 0) {
3087 		m_freem(*m_head);
3088 		*m_head = NULL;
3089 		return (EIO);
3090 	}
3091 
3092 	if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) {
3093 		bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap);
3094 		return (ENOBUFS);
3095 	}
3096 	bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap,
3097 	    BUS_DMASYNC_PREWRITE);
3098 
3099 	m = *m_head;
3100 	csum_flags = 0;
3101 	if (m->m_pkthdr.csum_flags & CSUM_IP)
3102 		csum_flags |= TI_BDFLAG_IP_CKSUM;
3103 	if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3104 		csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
3105 
3106 	frag = sc->ti_tx_saved_prodidx;
3107 	for (i = 0; i < nseg; i++) {
3108 		if (sc->ti_hwrev == TI_HWREV_TIGON) {
3109 			bzero(&txdesc, sizeof(txdesc));
3110 			f = &txdesc;
3111 		} else
3112 			f = &sc->ti_rdata.ti_tx_ring[frag];
3113 		ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr);
3114 		f->ti_len = txsegs[i].ds_len;
3115 		f->ti_flags = csum_flags;
3116 		if (m->m_flags & M_VLANTAG) {
3117 			f->ti_flags |= TI_BDFLAG_VLAN_TAG;
3118 			f->ti_vlan_tag = m->m_pkthdr.ether_vtag;
3119 		} else {
3120 			f->ti_vlan_tag = 0;
3121 		}
3122 
3123 		if (sc->ti_hwrev == TI_HWREV_TIGON)
3124 			ti_mem_write(sc, TI_TX_RING_BASE + frag *
3125 			    sizeof(txdesc), sizeof(txdesc), &txdesc);
3126 		TI_INC(frag, TI_TX_RING_CNT);
3127 	}
3128 
3129 	sc->ti_tx_saved_prodidx = frag;
3130 	/* set TI_BDFLAG_END on the last descriptor */
3131 	frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT;
3132 	if (sc->ti_hwrev == TI_HWREV_TIGON) {
3133 		txdesc.ti_flags |= TI_BDFLAG_END;
3134 		ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
3135 		    sizeof(txdesc), &txdesc);
3136 	} else
3137 		sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END;
3138 
3139 	STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q);
3140 	STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q);
3141 	txd->tx_m = m;
3142 	sc->ti_txcnt += nseg;
3143 
3144 	return (0);
3145 }
3146 
3147 static void
3148 ti_start(struct ifnet *ifp)
3149 {
3150 	struct ti_softc *sc;
3151 
3152 	sc = ifp->if_softc;
3153 	TI_LOCK(sc);
3154 	ti_start_locked(ifp);
3155 	TI_UNLOCK(sc);
3156 }
3157 
3158 /*
3159  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3160  * to the mbuf data regions directly in the transmit descriptors.
3161  */
3162 static void
3163 ti_start_locked(struct ifnet *ifp)
3164 {
3165 	struct ti_softc *sc;
3166 	struct mbuf *m_head = NULL;
3167 	int enq = 0;
3168 
3169 	sc = ifp->if_softc;
3170 
3171 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
3172 	    sc->ti_txcnt < (TI_TX_RING_CNT - 16);) {
3173 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3174 		if (m_head == NULL)
3175 			break;
3176 
3177 		/*
3178 		 * Pack the data into the transmit ring. If we
3179 		 * don't have room, set the OACTIVE flag and wait
3180 		 * for the NIC to drain the ring.
3181 		 */
3182 		if (ti_encap(sc, &m_head)) {
3183 			if (m_head == NULL)
3184 				break;
3185 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3186 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3187 			break;
3188 		}
3189 
3190 		enq++;
3191 		/*
3192 		 * If there's a BPF listener, bounce a copy of this frame
3193 		 * to him.
3194 		 */
3195 		ETHER_BPF_MTAP(ifp, m_head);
3196 	}
3197 
3198 	if (enq > 0) {
3199 		if (sc->ti_rdata.ti_tx_ring != NULL)
3200 			bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag,
3201 			    sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE);
3202 		/* Transmit */
3203 		CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx);
3204 
3205 		/*
3206 		 * Set a timeout in case the chip goes out to lunch.
3207 		 */
3208 		sc->ti_timer = 5;
3209 	}
3210 }
3211 
3212 static void
3213 ti_init(void *xsc)
3214 {
3215 	struct ti_softc *sc;
3216 
3217 	sc = xsc;
3218 	TI_LOCK(sc);
3219 	ti_init_locked(sc);
3220 	TI_UNLOCK(sc);
3221 }
3222 
3223 static void
3224 ti_init_locked(void *xsc)
3225 {
3226 	struct ti_softc *sc = xsc;
3227 
3228 	if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING)
3229 		return;
3230 
3231 	/* Cancel pending I/O and flush buffers. */
3232 	ti_stop(sc);
3233 
3234 	/* Init the gen info block, ring control blocks and firmware. */
3235 	if (ti_gibinit(sc)) {
3236 		device_printf(sc->ti_dev, "initialization failure\n");
3237 		return;
3238 	}
3239 }
3240 
3241 static void ti_init2(struct ti_softc *sc)
3242 {
3243 	struct ti_cmd_desc cmd;
3244 	struct ifnet *ifp;
3245 	uint8_t *ea;
3246 	struct ifmedia *ifm;
3247 	int tmp;
3248 
3249 	TI_LOCK_ASSERT(sc);
3250 
3251 	ifp = sc->ti_ifp;
3252 
3253 	/* Specify MTU and interface index. */
3254 	CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev));
3255 	CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
3256 	    ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
3257 	TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
3258 
3259 	/* Load our MAC address. */
3260 	ea = IF_LLADDR(sc->ti_ifp);
3261 	CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]);
3262 	CSR_WRITE_4(sc, TI_GCR_PAR1,
3263 	    (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]);
3264 	TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
3265 
3266 	/* Enable or disable promiscuous mode as needed. */
3267 	if (ifp->if_flags & IFF_PROMISC) {
3268 		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
3269 	} else {
3270 		TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
3271 	}
3272 
3273 	/* Program multicast filter. */
3274 	ti_setmulti(sc);
3275 
3276 	/*
3277 	 * If this is a Tigon 1, we should tell the
3278 	 * firmware to use software packet filtering.
3279 	 */
3280 	if (sc->ti_hwrev == TI_HWREV_TIGON) {
3281 		TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
3282 	}
3283 
3284 	/* Init RX ring. */
3285 	if (ti_init_rx_ring_std(sc) != 0) {
3286 		/* XXX */
3287 		device_printf(sc->ti_dev, "no memory for std Rx buffers.\n");
3288 		return;
3289 	}
3290 
3291 	/* Init jumbo RX ring. */
3292 	if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) {
3293 		if (ti_init_rx_ring_jumbo(sc) != 0) {
3294 			/* XXX */
3295 			device_printf(sc->ti_dev,
3296 			    "no memory for jumbo Rx buffers.\n");
3297 			return;
3298 		}
3299 	}
3300 
3301 	/*
3302 	 * If this is a Tigon 2, we can also configure the
3303 	 * mini ring.
3304 	 */
3305 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
3306 		if (ti_init_rx_ring_mini(sc) != 0) {
3307 			/* XXX */
3308 			device_printf(sc->ti_dev,
3309 			    "no memory for mini Rx buffers.\n");
3310 			return;
3311 		}
3312 	}
3313 
3314 	CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
3315 	sc->ti_rx_saved_considx = 0;
3316 
3317 	/* Init TX ring. */
3318 	ti_init_tx_ring(sc);
3319 
3320 	/* Tell firmware we're alive. */
3321 	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
3322 
3323 	/* Enable host interrupts. */
3324 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
3325 
3326 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3327 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3328 	callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3329 
3330 	/*
3331 	 * Make sure to set media properly. We have to do this
3332 	 * here since we have to issue commands in order to set
3333 	 * the link negotiation and we can't issue commands until
3334 	 * the firmware is running.
3335 	 */
3336 	ifm = &sc->ifmedia;
3337 	tmp = ifm->ifm_media;
3338 	ifm->ifm_media = ifm->ifm_cur->ifm_media;
3339 	ti_ifmedia_upd_locked(sc);
3340 	ifm->ifm_media = tmp;
3341 }
3342 
3343 /*
3344  * Set media options.
3345  */
3346 static int
3347 ti_ifmedia_upd(struct ifnet *ifp)
3348 {
3349 	struct ti_softc *sc;
3350 	int error;
3351 
3352 	sc = ifp->if_softc;
3353 	TI_LOCK(sc);
3354 	error = ti_ifmedia_upd(ifp);
3355 	TI_UNLOCK(sc);
3356 
3357 	return (error);
3358 }
3359 
3360 static int
3361 ti_ifmedia_upd_locked(struct ti_softc *sc)
3362 {
3363 	struct ifmedia *ifm;
3364 	struct ti_cmd_desc cmd;
3365 	uint32_t flowctl;
3366 
3367 	ifm = &sc->ifmedia;
3368 
3369 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3370 		return (EINVAL);
3371 
3372 	flowctl = 0;
3373 
3374 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
3375 	case IFM_AUTO:
3376 		/*
3377 		 * Transmit flow control doesn't work on the Tigon 1.
3378 		 */
3379 		flowctl = TI_GLNK_RX_FLOWCTL_Y;
3380 
3381 		/*
3382 		 * Transmit flow control can also cause problems on the
3383 		 * Tigon 2, apparantly with both the copper and fiber
3384 		 * boards.  The symptom is that the interface will just
3385 		 * hang.  This was reproduced with Alteon 180 switches.
3386 		 */
3387 #if 0
3388 		if (sc->ti_hwrev != TI_HWREV_TIGON)
3389 			flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3390 #endif
3391 
3392 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3393 		    TI_GLNK_FULL_DUPLEX| flowctl |
3394 		    TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
3395 
3396 		flowctl = TI_LNK_RX_FLOWCTL_Y;
3397 #if 0
3398 		if (sc->ti_hwrev != TI_HWREV_TIGON)
3399 			flowctl |= TI_LNK_TX_FLOWCTL_Y;
3400 #endif
3401 
3402 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
3403 		    TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl |
3404 		    TI_LNK_AUTONEGENB|TI_LNK_ENB);
3405 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3406 		    TI_CMD_CODE_NEGOTIATE_BOTH, 0);
3407 		break;
3408 	case IFM_1000_SX:
3409 	case IFM_1000_T:
3410 		flowctl = TI_GLNK_RX_FLOWCTL_Y;
3411 #if 0
3412 		if (sc->ti_hwrev != TI_HWREV_TIGON)
3413 			flowctl |= TI_GLNK_TX_FLOWCTL_Y;
3414 #endif
3415 
3416 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
3417 		    flowctl |TI_GLNK_ENB);
3418 		CSR_WRITE_4(sc, TI_GCR_LINK, 0);
3419 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3420 			TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
3421 		}
3422 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3423 		    TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
3424 		break;
3425 	case IFM_100_FX:
3426 	case IFM_10_FL:
3427 	case IFM_100_TX:
3428 	case IFM_10_T:
3429 		flowctl = TI_LNK_RX_FLOWCTL_Y;
3430 #if 0
3431 		if (sc->ti_hwrev != TI_HWREV_TIGON)
3432 			flowctl |= TI_LNK_TX_FLOWCTL_Y;
3433 #endif
3434 
3435 		CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
3436 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl);
3437 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
3438 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
3439 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
3440 		} else {
3441 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
3442 		}
3443 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3444 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
3445 		} else {
3446 			TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
3447 		}
3448 		TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
3449 		    TI_CMD_CODE_NEGOTIATE_10_100, 0);
3450 		break;
3451 	}
3452 
3453 	return (0);
3454 }
3455 
3456 /*
3457  * Report current media status.
3458  */
3459 static void
3460 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3461 {
3462 	struct ti_softc *sc;
3463 	uint32_t media = 0;
3464 
3465 	sc = ifp->if_softc;
3466 
3467 	TI_LOCK(sc);
3468 
3469 	ifmr->ifm_status = IFM_AVALID;
3470 	ifmr->ifm_active = IFM_ETHER;
3471 
3472 	if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
3473 		TI_UNLOCK(sc);
3474 		return;
3475 	}
3476 
3477 	ifmr->ifm_status |= IFM_ACTIVE;
3478 
3479 	if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
3480 		media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3481 		if (sc->ti_copper)
3482 			ifmr->ifm_active |= IFM_1000_T;
3483 		else
3484 			ifmr->ifm_active |= IFM_1000_SX;
3485 		if (media & TI_GLNK_FULL_DUPLEX)
3486 			ifmr->ifm_active |= IFM_FDX;
3487 		else
3488 			ifmr->ifm_active |= IFM_HDX;
3489 	} else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
3490 		media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3491 		if (sc->ti_copper) {
3492 			if (media & TI_LNK_100MB)
3493 				ifmr->ifm_active |= IFM_100_TX;
3494 			if (media & TI_LNK_10MB)
3495 				ifmr->ifm_active |= IFM_10_T;
3496 		} else {
3497 			if (media & TI_LNK_100MB)
3498 				ifmr->ifm_active |= IFM_100_FX;
3499 			if (media & TI_LNK_10MB)
3500 				ifmr->ifm_active |= IFM_10_FL;
3501 		}
3502 		if (media & TI_LNK_FULL_DUPLEX)
3503 			ifmr->ifm_active |= IFM_FDX;
3504 		if (media & TI_LNK_HALF_DUPLEX)
3505 			ifmr->ifm_active |= IFM_HDX;
3506 	}
3507 	TI_UNLOCK(sc);
3508 }
3509 
3510 static int
3511 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3512 {
3513 	struct ti_softc *sc = ifp->if_softc;
3514 	struct ifreq *ifr = (struct ifreq *) data;
3515 	struct ti_cmd_desc cmd;
3516 	int mask, error = 0;
3517 
3518 	switch (command) {
3519 	case SIOCSIFMTU:
3520 		TI_LOCK(sc);
3521 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU)
3522 			error = EINVAL;
3523 		else {
3524 			ifp->if_mtu = ifr->ifr_mtu;
3525 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3526 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3527 				ti_init_locked(sc);
3528 			}
3529 		}
3530 		TI_UNLOCK(sc);
3531 		break;
3532 	case SIOCSIFFLAGS:
3533 		TI_LOCK(sc);
3534 		if (ifp->if_flags & IFF_UP) {
3535 			/*
3536 			 * If only the state of the PROMISC flag changed,
3537 			 * then just use the 'set promisc mode' command
3538 			 * instead of reinitializing the entire NIC. Doing
3539 			 * a full re-init means reloading the firmware and
3540 			 * waiting for it to start up, which may take a
3541 			 * second or two.
3542 			 */
3543 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3544 			    ifp->if_flags & IFF_PROMISC &&
3545 			    !(sc->ti_if_flags & IFF_PROMISC)) {
3546 				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3547 				    TI_CMD_CODE_PROMISC_ENB, 0);
3548 			} else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3549 			    !(ifp->if_flags & IFF_PROMISC) &&
3550 			    sc->ti_if_flags & IFF_PROMISC) {
3551 				TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
3552 				    TI_CMD_CODE_PROMISC_DIS, 0);
3553 			} else
3554 				ti_init_locked(sc);
3555 		} else {
3556 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3557 				ti_stop(sc);
3558 			}
3559 		}
3560 		sc->ti_if_flags = ifp->if_flags;
3561 		TI_UNLOCK(sc);
3562 		break;
3563 	case SIOCADDMULTI:
3564 	case SIOCDELMULTI:
3565 		TI_LOCK(sc);
3566 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3567 			ti_setmulti(sc);
3568 		TI_UNLOCK(sc);
3569 		break;
3570 	case SIOCSIFMEDIA:
3571 	case SIOCGIFMEDIA:
3572 		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
3573 		break;
3574 	case SIOCSIFCAP:
3575 		TI_LOCK(sc);
3576 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3577 		if ((mask & IFCAP_TXCSUM) != 0 &&
3578 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3579 			ifp->if_capenable ^= IFCAP_TXCSUM;
3580 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3581 				ifp->if_hwassist |= TI_CSUM_FEATURES;
3582                         else
3583 				ifp->if_hwassist &= ~TI_CSUM_FEATURES;
3584                 }
3585 		if ((mask & IFCAP_RXCSUM) != 0 &&
3586 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3587 			ifp->if_capenable ^= IFCAP_RXCSUM;
3588 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3589 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0)
3590                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3591 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3592 		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
3593 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
3594 		if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM |
3595 		    IFCAP_VLAN_HWTAGGING)) != 0) {
3596 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3597 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3598 				ti_init_locked(sc);
3599 			}
3600 		}
3601 		TI_UNLOCK(sc);
3602 		VLAN_CAPABILITIES(ifp);
3603 		break;
3604 	default:
3605 		error = ether_ioctl(ifp, command, data);
3606 		break;
3607 	}
3608 
3609 	return (error);
3610 }
3611 
3612 static int
3613 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td)
3614 {
3615 	struct ti_softc *sc;
3616 
3617 	sc = dev->si_drv1;
3618 	if (sc == NULL)
3619 		return (ENODEV);
3620 
3621 	TI_LOCK(sc);
3622 	sc->ti_flags |= TI_FLAG_DEBUGING;
3623 	TI_UNLOCK(sc);
3624 
3625 	return (0);
3626 }
3627 
3628 static int
3629 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td)
3630 {
3631 	struct ti_softc *sc;
3632 
3633 	sc = dev->si_drv1;
3634 	if (sc == NULL)
3635 		return (ENODEV);
3636 
3637 	TI_LOCK(sc);
3638 	sc->ti_flags &= ~TI_FLAG_DEBUGING;
3639 	TI_UNLOCK(sc);
3640 
3641 	return (0);
3642 }
3643 
3644 /*
3645  * This ioctl routine goes along with the Tigon character device.
3646  */
3647 static int
3648 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag,
3649     struct thread *td)
3650 {
3651 	struct ti_softc *sc;
3652 	int error;
3653 
3654 	sc = dev->si_drv1;
3655 	if (sc == NULL)
3656 		return (ENODEV);
3657 
3658 	error = 0;
3659 
3660 	switch (cmd) {
3661 	case TIIOCGETSTATS:
3662 	{
3663 		struct ti_stats *outstats;
3664 
3665 		outstats = (struct ti_stats *)addr;
3666 
3667 		TI_LOCK(sc);
3668 		bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3669 		    sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD);
3670 		bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats,
3671 		    sizeof(struct ti_stats));
3672 		bus_dmamap_sync(sc->ti_cdata.ti_gib_tag,
3673 		    sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD);
3674 		TI_UNLOCK(sc);
3675 		break;
3676 	}
3677 	case TIIOCGETPARAMS:
3678 	{
3679 		struct ti_params *params;
3680 
3681 		params = (struct ti_params *)addr;
3682 
3683 		TI_LOCK(sc);
3684 		params->ti_stat_ticks = sc->ti_stat_ticks;
3685 		params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks;
3686 		params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks;
3687 		params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds;
3688 		params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds;
3689 		params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio;
3690 		params->param_mask = TI_PARAM_ALL;
3691 		TI_UNLOCK(sc);
3692 		break;
3693 	}
3694 	case TIIOCSETPARAMS:
3695 	{
3696 		struct ti_params *params;
3697 
3698 		params = (struct ti_params *)addr;
3699 
3700 		TI_LOCK(sc);
3701 		if (params->param_mask & TI_PARAM_STAT_TICKS) {
3702 			sc->ti_stat_ticks = params->ti_stat_ticks;
3703 			CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
3704 		}
3705 
3706 		if (params->param_mask & TI_PARAM_RX_COAL_TICKS) {
3707 			sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks;
3708 			CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
3709 				    sc->ti_rx_coal_ticks);
3710 		}
3711 
3712 		if (params->param_mask & TI_PARAM_TX_COAL_TICKS) {
3713 			sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks;
3714 			CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS,
3715 				    sc->ti_tx_coal_ticks);
3716 		}
3717 
3718 		if (params->param_mask & TI_PARAM_RX_COAL_BDS) {
3719 			sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds;
3720 			CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD,
3721 				    sc->ti_rx_max_coal_bds);
3722 		}
3723 
3724 		if (params->param_mask & TI_PARAM_TX_COAL_BDS) {
3725 			sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds;
3726 			CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD,
3727 				    sc->ti_tx_max_coal_bds);
3728 		}
3729 
3730 		if (params->param_mask & TI_PARAM_TX_BUF_RATIO) {
3731 			sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio;
3732 			CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO,
3733 				    sc->ti_tx_buf_ratio);
3734 		}
3735 		TI_UNLOCK(sc);
3736 		break;
3737 	}
3738 	case TIIOCSETTRACE: {
3739 		ti_trace_type trace_type;
3740 
3741 		trace_type = *(ti_trace_type *)addr;
3742 
3743 		/*
3744 		 * Set tracing to whatever the user asked for.  Setting
3745 		 * this register to 0 should have the effect of disabling
3746 		 * tracing.
3747 		 */
3748 		TI_LOCK(sc);
3749 		CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type);
3750 		TI_UNLOCK(sc);
3751 		break;
3752 	}
3753 	case TIIOCGETTRACE: {
3754 		struct ti_trace_buf *trace_buf;
3755 		uint32_t trace_start, cur_trace_ptr, trace_len;
3756 
3757 		trace_buf = (struct ti_trace_buf *)addr;
3758 
3759 		TI_LOCK(sc);
3760 		trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3761 		cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3762 		trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);
3763 #if 0
3764 		if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, "
3765 		       "trace_len = %d\n", trace_start,
3766 		       cur_trace_ptr, trace_len);
3767 		if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n",
3768 		       trace_buf->buf_len);
3769 #endif
3770 		error = ti_copy_mem(sc, trace_start, min(trace_len,
3771 		    trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1);
3772 		if (error == 0) {
3773 			trace_buf->fill_len = min(trace_len,
3774 			    trace_buf->buf_len);
3775 			if (cur_trace_ptr < trace_start)
3776 				trace_buf->cur_trace_ptr =
3777 				    trace_start - cur_trace_ptr;
3778 			else
3779 				trace_buf->cur_trace_ptr =
3780 				    cur_trace_ptr - trace_start;
3781 		} else
3782 			trace_buf->fill_len = 0;
3783 		TI_UNLOCK(sc);
3784 		break;
3785 	}
3786 
3787 	/*
3788 	 * For debugging, five ioctls are needed:
3789 	 * ALT_ATTACH
3790 	 * ALT_READ_TG_REG
3791 	 * ALT_WRITE_TG_REG
3792 	 * ALT_READ_TG_MEM
3793 	 * ALT_WRITE_TG_MEM
3794 	 */
3795 	case ALT_ATTACH:
3796 		/*
3797 		 * From what I can tell, Alteon's Solaris Tigon driver
3798 		 * only has one character device, so you have to attach
3799 		 * to the Tigon board you're interested in.  This seems
3800 		 * like a not-so-good way to do things, since unless you
3801 		 * subsequently specify the unit number of the device
3802 		 * you're interested in every ioctl, you'll only be
3803 		 * able to debug one board at a time.
3804 		 */
3805 		break;
3806 	case ALT_READ_TG_MEM:
3807 	case ALT_WRITE_TG_MEM:
3808 	{
3809 		struct tg_mem *mem_param;
3810 		uint32_t sram_end, scratch_end;
3811 
3812 		mem_param = (struct tg_mem *)addr;
3813 
3814 		if (sc->ti_hwrev == TI_HWREV_TIGON) {
3815 			sram_end = TI_END_SRAM_I;
3816 			scratch_end = TI_END_SCRATCH_I;
3817 		} else {
3818 			sram_end = TI_END_SRAM_II;
3819 			scratch_end = TI_END_SCRATCH_II;
3820 		}
3821 
3822 		/*
3823 		 * For now, we'll only handle accessing regular SRAM,
3824 		 * nothing else.
3825 		 */
3826 		TI_LOCK(sc);
3827 		if (mem_param->tgAddr >= TI_BEG_SRAM &&
3828 		    mem_param->tgAddr + mem_param->len <= sram_end) {
3829 			/*
3830 			 * In this instance, we always copy to/from user
3831 			 * space, so the user space argument is set to 1.
3832 			 */
3833 			error = ti_copy_mem(sc, mem_param->tgAddr,
3834 			    mem_param->len, mem_param->userAddr, 1,
3835 			    cmd == ALT_READ_TG_MEM ? 1 : 0);
3836 		} else if (mem_param->tgAddr >= TI_BEG_SCRATCH &&
3837 		    mem_param->tgAddr <= scratch_end) {
3838 			error = ti_copy_scratch(sc, mem_param->tgAddr,
3839 			    mem_param->len, mem_param->userAddr, 1,
3840 			    cmd == ALT_READ_TG_MEM ?  1 : 0, TI_PROCESSOR_A);
3841 		} else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG &&
3842 		    mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) {
3843 			if (sc->ti_hwrev == TI_HWREV_TIGON) {
3844 				if_printf(sc->ti_ifp,
3845 				    "invalid memory range for Tigon I\n");
3846 				error = EINVAL;
3847 				break;
3848 			}
3849 			error = ti_copy_scratch(sc, mem_param->tgAddr -
3850 			    TI_SCRATCH_DEBUG_OFF, mem_param->len,
3851 			    mem_param->userAddr, 1,
3852 			    cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B);
3853 		} else {
3854 			if_printf(sc->ti_ifp, "memory address %#x len %d is "
3855 			        "out of supported range\n",
3856 			        mem_param->tgAddr, mem_param->len);
3857 			error = EINVAL;
3858 		}
3859 		TI_UNLOCK(sc);
3860 		break;
3861 	}
3862 	case ALT_READ_TG_REG:
3863 	case ALT_WRITE_TG_REG:
3864 	{
3865 		struct tg_reg *regs;
3866 		uint32_t tmpval;
3867 
3868 		regs = (struct tg_reg *)addr;
3869 
3870 		/*
3871 		 * Make sure the address in question isn't out of range.
3872 		 */
3873 		if (regs->addr > TI_REG_MAX) {
3874 			error = EINVAL;
3875 			break;
3876 		}
3877 		TI_LOCK(sc);
3878 		if (cmd == ALT_READ_TG_REG) {
3879 			bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
3880 			    regs->addr, &tmpval, 1);
3881 			regs->data = ntohl(tmpval);
3882 #if 0
3883 			if ((regs->addr == TI_CPU_STATE)
3884 			 || (regs->addr == TI_CPU_CTL_B)) {
3885 				if_printf(sc->ti_ifp, "register %#x = %#x\n",
3886 				       regs->addr, tmpval);
3887 			}
3888 #endif
3889 		} else {
3890 			tmpval = htonl(regs->data);
3891 			bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
3892 			    regs->addr, &tmpval, 1);
3893 		}
3894 		TI_UNLOCK(sc);
3895 		break;
3896 	}
3897 	default:
3898 		error = ENOTTY;
3899 		break;
3900 	}
3901 	return (error);
3902 }
3903 
3904 static void
3905 ti_watchdog(void *arg)
3906 {
3907 	struct ti_softc *sc;
3908 	struct ifnet *ifp;
3909 
3910 	sc = arg;
3911 	TI_LOCK_ASSERT(sc);
3912 	callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc);
3913 	if (sc->ti_timer == 0 || --sc->ti_timer > 0)
3914 		return;
3915 
3916 	/*
3917 	 * When we're debugging, the chip is often stopped for long periods
3918 	 * of time, and that would normally cause the watchdog timer to fire.
3919 	 * Since that impedes debugging, we don't want to do that.
3920 	 */
3921 	if (sc->ti_flags & TI_FLAG_DEBUGING)
3922 		return;
3923 
3924 	ifp = sc->ti_ifp;
3925 	if_printf(ifp, "watchdog timeout -- resetting\n");
3926 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3927 	ti_init_locked(sc);
3928 
3929 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3930 }
3931 
3932 /*
3933  * Stop the adapter and free any mbufs allocated to the
3934  * RX and TX lists.
3935  */
3936 static void
3937 ti_stop(struct ti_softc *sc)
3938 {
3939 	struct ifnet *ifp;
3940 	struct ti_cmd_desc cmd;
3941 
3942 	TI_LOCK_ASSERT(sc);
3943 
3944 	ifp = sc->ti_ifp;
3945 
3946 	/* Disable host interrupts. */
3947 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
3948 	/*
3949 	 * Tell firmware we're shutting down.
3950 	 */
3951 	TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
3952 
3953 	/* Halt and reinitialize. */
3954 	if (ti_chipinit(sc) == 0) {
3955 		ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000);
3956 		/* XXX ignore init errors. */
3957 		ti_chipinit(sc);
3958 	}
3959 
3960 	/* Free the RX lists. */
3961 	ti_free_rx_ring_std(sc);
3962 
3963 	/* Free jumbo RX list. */
3964 	ti_free_rx_ring_jumbo(sc);
3965 
3966 	/* Free mini RX list. */
3967 	ti_free_rx_ring_mini(sc);
3968 
3969 	/* Free TX buffers. */
3970 	ti_free_tx_ring(sc);
3971 
3972 	sc->ti_ev_prodidx.ti_idx = 0;
3973 	sc->ti_return_prodidx.ti_idx = 0;
3974 	sc->ti_tx_considx.ti_idx = 0;
3975 	sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
3976 
3977 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3978 	callout_stop(&sc->ti_watchdog);
3979 }
3980 
3981 /*
3982  * Stop all chip I/O so that the kernel's probe routines don't
3983  * get confused by errant DMAs when rebooting.
3984  */
3985 static int
3986 ti_shutdown(device_t dev)
3987 {
3988 	struct ti_softc *sc;
3989 
3990 	sc = device_get_softc(dev);
3991 	TI_LOCK(sc);
3992 	ti_chipinit(sc);
3993 	TI_UNLOCK(sc);
3994 
3995 	return (0);
3996 }
3997 
3998 static void
3999 ti_sysctl_node(struct ti_softc *sc)
4000 {
4001 	struct sysctl_ctx_list *ctx;
4002 	struct sysctl_oid_list *child;
4003 	char tname[32];
4004 
4005 	ctx = device_get_sysctl_ctx(sc->ti_dev);
4006 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev));
4007 
4008 	/* Use DAC */
4009 	sc->ti_dac = 1;
4010 	snprintf(tname, sizeof(tname), "dev.ti.%d.dac",
4011 	    device_get_unit(sc->ti_dev));
4012 	TUNABLE_INT_FETCH(tname, &sc->ti_dac);
4013 
4014 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW,
4015 	    &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks");
4016 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW,
4017 	    &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs");
4018 
4019 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW,
4020 	    &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks");
4021 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW,
4022 	    &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs");
4023 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW,
4024 	    &sc->ti_tx_buf_ratio, 0,
4025 	    "Ratio of NIC memory devoted to TX buffer");
4026 
4027 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW,
4028 	    &sc->ti_stat_ticks, 0,
4029 	    "Number of clock ticks for statistics update interval");
4030 
4031 	/* Pull in device tunables. */
4032 	sc->ti_rx_coal_ticks = 170;
4033 	resource_int_value(device_get_name(sc->ti_dev),
4034 	    device_get_unit(sc->ti_dev), "rx_coal_ticks",
4035 	    &sc->ti_rx_coal_ticks);
4036 	sc->ti_rx_max_coal_bds = 64;
4037 	resource_int_value(device_get_name(sc->ti_dev),
4038 	    device_get_unit(sc->ti_dev), "rx_max_coal_bds",
4039 	    &sc->ti_rx_max_coal_bds);
4040 
4041 	sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
4042 	resource_int_value(device_get_name(sc->ti_dev),
4043 	    device_get_unit(sc->ti_dev), "tx_coal_ticks",
4044 	    &sc->ti_tx_coal_ticks);
4045 	sc->ti_tx_max_coal_bds = 32;
4046 	resource_int_value(device_get_name(sc->ti_dev),
4047 	    device_get_unit(sc->ti_dev), "tx_max_coal_bds",
4048 	    &sc->ti_tx_max_coal_bds);
4049 	sc->ti_tx_buf_ratio = 21;
4050 	resource_int_value(device_get_name(sc->ti_dev),
4051 	    device_get_unit(sc->ti_dev), "tx_buf_ratio",
4052 	    &sc->ti_tx_buf_ratio);
4053 
4054 	sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
4055 	resource_int_value(device_get_name(sc->ti_dev),
4056 	    device_get_unit(sc->ti_dev), "stat_ticks",
4057 	    &sc->ti_stat_ticks);
4058 }
4059