1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 #include <sys/sf_buf.h> 95 96 #include <net/if.h> 97 #include <net/if_var.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_types.h> 103 #include <net/if_vlan_var.h> 104 105 #include <net/bpf.h> 106 107 #include <netinet/in_systm.h> 108 #include <netinet/in.h> 109 #include <netinet/ip.h> 110 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <sys/bus.h> 114 #include <sys/rman.h> 115 116 #ifdef TI_SF_BUF_JUMBO 117 #include <vm/vm.h> 118 #include <vm/vm_page.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 124 #include <sys/tiio.h> 125 #include <dev/ti/if_tireg.h> 126 #include <dev/ti/ti_fw.h> 127 #include <dev/ti/ti_fw2.h> 128 129 #include <sys/sysctl.h> 130 131 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 /* 133 * We can only turn on header splitting if we're using extended receive 134 * BDs. 135 */ 136 #if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 137 #error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 138 #endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 139 140 typedef enum { 141 TI_SWAP_HTON, 142 TI_SWAP_NTOH 143 } ti_swap_type; 144 145 /* 146 * Various supported device vendors/types and their names. 147 */ 148 149 static const struct ti_type ti_devs[] = { 150 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 151 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 152 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 153 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 154 { TC_VENDORID, TC_DEVICEID_3C985, 155 "3Com 3c985-SX Gigabit Ethernet" }, 156 { NG_VENDORID, NG_DEVICEID_GA620, 157 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 158 { NG_VENDORID, NG_DEVICEID_GA620T, 159 "Netgear GA620 1000baseT Gigabit Ethernet" }, 160 { SGI_VENDORID, SGI_DEVICEID_TIGON, 161 "Silicon Graphics Gigabit Ethernet" }, 162 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 163 "Farallon PN9000SX Gigabit Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 168 static d_open_t ti_open; 169 static d_close_t ti_close; 170 static d_ioctl_t ti_ioctl2; 171 172 static struct cdevsw ti_cdevsw = { 173 .d_version = D_VERSION, 174 .d_flags = 0, 175 .d_open = ti_open, 176 .d_close = ti_close, 177 .d_ioctl = ti_ioctl2, 178 .d_name = "ti", 179 }; 180 181 static int ti_probe(device_t); 182 static int ti_attach(device_t); 183 static int ti_detach(device_t); 184 static void ti_txeof(struct ti_softc *); 185 static void ti_rxeof(struct ti_softc *); 186 187 static int ti_encap(struct ti_softc *, struct mbuf **); 188 189 static void ti_intr(void *); 190 static void ti_start(struct ifnet *); 191 static void ti_start_locked(struct ifnet *); 192 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193 static uint64_t ti_get_counter(struct ifnet *, ift_counter); 194 static void ti_init(void *); 195 static void ti_init_locked(void *); 196 static void ti_init2(struct ti_softc *); 197 static void ti_stop(struct ti_softc *); 198 static void ti_watchdog(void *); 199 static int ti_shutdown(device_t); 200 static int ti_ifmedia_upd(struct ifnet *); 201 static int ti_ifmedia_upd_locked(struct ti_softc *); 202 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 203 204 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 205 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 206 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 207 208 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 209 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 210 static void ti_setmulti(struct ti_softc *); 211 212 static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 213 static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 214 static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 215 static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 216 int); 217 static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 218 int, int, int); 219 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 220 static void ti_loadfw(struct ti_softc *); 221 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 222 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 223 static void ti_handle_events(struct ti_softc *); 224 static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 225 static int ti_dma_alloc(struct ti_softc *); 226 static void ti_dma_free(struct ti_softc *); 227 static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 228 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 229 static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 230 bus_dmamap_t, bus_addr_t *); 231 static int ti_newbuf_std(struct ti_softc *, int); 232 static int ti_newbuf_mini(struct ti_softc *, int); 233 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 234 static int ti_init_rx_ring_std(struct ti_softc *); 235 static void ti_free_rx_ring_std(struct ti_softc *); 236 static int ti_init_rx_ring_jumbo(struct ti_softc *); 237 static void ti_free_rx_ring_jumbo(struct ti_softc *); 238 static int ti_init_rx_ring_mini(struct ti_softc *); 239 static void ti_free_rx_ring_mini(struct ti_softc *); 240 static void ti_free_tx_ring(struct ti_softc *); 241 static int ti_init_tx_ring(struct ti_softc *); 242 static void ti_discard_std(struct ti_softc *, int); 243 #ifndef TI_SF_BUF_JUMBO 244 static void ti_discard_jumbo(struct ti_softc *, int); 245 #endif 246 static void ti_discard_mini(struct ti_softc *, int); 247 248 static int ti_64bitslot_war(struct ti_softc *); 249 static int ti_chipinit(struct ti_softc *); 250 static int ti_gibinit(struct ti_softc *); 251 252 #ifdef TI_JUMBO_HDRSPLIT 253 static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 254 int idx); 255 #endif /* TI_JUMBO_HDRSPLIT */ 256 257 static void ti_sysctl_node(struct ti_softc *); 258 259 static device_method_t ti_methods[] = { 260 /* Device interface */ 261 DEVMETHOD(device_probe, ti_probe), 262 DEVMETHOD(device_attach, ti_attach), 263 DEVMETHOD(device_detach, ti_detach), 264 DEVMETHOD(device_shutdown, ti_shutdown), 265 { 0, 0 } 266 }; 267 268 static driver_t ti_driver = { 269 "ti", 270 ti_methods, 271 sizeof(struct ti_softc) 272 }; 273 274 static devclass_t ti_devclass; 275 276 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 277 MODULE_DEPEND(ti, pci, 1, 1, 1); 278 MODULE_DEPEND(ti, ether, 1, 1, 1); 279 280 /* 281 * Send an instruction or address to the EEPROM, check for ACK. 282 */ 283 static uint32_t 284 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 285 { 286 int i, ack = 0; 287 288 /* 289 * Make sure we're in TX mode. 290 */ 291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 292 293 /* 294 * Feed in each bit and stobe the clock. 295 */ 296 for (i = 0x80; i; i >>= 1) { 297 if (byte & i) { 298 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 299 } else { 300 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 301 } 302 DELAY(1); 303 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 304 DELAY(1); 305 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 } 307 308 /* 309 * Turn off TX mode. 310 */ 311 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 312 313 /* 314 * Check for ack. 315 */ 316 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 317 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 318 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 319 320 return (ack); 321 } 322 323 /* 324 * Read a byte of data stored in the EEPROM at address 'addr.' 325 * We have to send two address bytes since the EEPROM can hold 326 * more than 256 bytes of data. 327 */ 328 static uint8_t 329 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 330 { 331 int i; 332 uint8_t byte = 0; 333 334 EEPROM_START; 335 336 /* 337 * Send write control code to EEPROM. 338 */ 339 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 340 device_printf(sc->ti_dev, 341 "failed to send write command, status: %x\n", 342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 343 return (1); 344 } 345 346 /* 347 * Send first byte of address of byte we want to read. 348 */ 349 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 350 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 351 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 352 return (1); 353 } 354 /* 355 * Send second byte address of byte we want to read. 356 */ 357 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 358 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 360 return (1); 361 } 362 363 EEPROM_STOP; 364 EEPROM_START; 365 /* 366 * Send read control code to EEPROM. 367 */ 368 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 369 device_printf(sc->ti_dev, 370 "failed to send read command, status: %x\n", 371 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 372 return (1); 373 } 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 379 for (i = 0x80; i; i >>= 1) { 380 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 381 DELAY(1); 382 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 383 byte |= i; 384 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 385 DELAY(1); 386 } 387 388 EEPROM_STOP; 389 390 /* 391 * No ACK generated for read, so just return byte. 392 */ 393 394 *dest = byte; 395 396 return (0); 397 } 398 399 /* 400 * Read a sequence of bytes from the EEPROM. 401 */ 402 static int 403 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 404 { 405 int err = 0, i; 406 uint8_t byte = 0; 407 408 for (i = 0; i < cnt; i++) { 409 err = ti_eeprom_getbyte(sc, off + i, &byte); 410 if (err) 411 break; 412 *(dest + i) = byte; 413 } 414 415 return (err ? 1 : 0); 416 } 417 418 /* 419 * NIC memory read function. 420 * Can be used to copy data from NIC local memory. 421 */ 422 static void 423 ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 424 { 425 int segptr, segsize, cnt; 426 char *ptr; 427 428 segptr = addr; 429 cnt = len; 430 ptr = buf; 431 432 while (cnt) { 433 if (cnt < TI_WINLEN) 434 segsize = cnt; 435 else 436 segsize = TI_WINLEN - (segptr % TI_WINLEN); 437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 440 segsize / 4); 441 ptr += segsize; 442 segptr += segsize; 443 cnt -= segsize; 444 } 445 } 446 447 448 /* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452 static void 453 ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 454 { 455 int segptr, segsize, cnt; 456 char *ptr; 457 458 segptr = addr; 459 cnt = len; 460 ptr = buf; 461 462 while (cnt) { 463 if (cnt < TI_WINLEN) 464 segsize = cnt; 465 else 466 segsize = TI_WINLEN - (segptr % TI_WINLEN); 467 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 468 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 469 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 470 segsize / 4); 471 ptr += segsize; 472 segptr += segsize; 473 cnt -= segsize; 474 } 475 } 476 477 /* 478 * NIC memory read function. 479 * Can be used to clear a section of NIC local memory. 480 */ 481 static void 482 ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 483 { 484 int segptr, segsize, cnt; 485 486 segptr = addr; 487 cnt = len; 488 489 while (cnt) { 490 if (cnt < TI_WINLEN) 491 segsize = cnt; 492 else 493 segsize = TI_WINLEN - (segptr % TI_WINLEN); 494 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 495 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 496 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 497 segptr += segsize; 498 cnt -= segsize; 499 } 500 } 501 502 static int 503 ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 504 caddr_t buf, int useraddr, int readdata) 505 { 506 int segptr, segsize, cnt; 507 caddr_t ptr; 508 uint32_t origwin; 509 int resid, segresid; 510 int first_pass; 511 512 TI_LOCK_ASSERT(sc); 513 514 /* 515 * At the moment, we don't handle non-aligned cases, we just bail. 516 * If this proves to be a problem, it will be fixed. 517 */ 518 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 519 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 520 "word-aligned\n", __func__, tigon_addr); 521 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 522 "yet supported\n", __func__); 523 return (EINVAL); 524 } 525 526 segptr = tigon_addr & ~0x3; 527 segresid = tigon_addr - segptr; 528 529 /* 530 * This is the non-aligned amount left over that we'll need to 531 * copy. 532 */ 533 resid = len & 0x3; 534 535 /* Add in the left over amount at the front of the buffer */ 536 resid += segresid; 537 538 cnt = len & ~0x3; 539 /* 540 * If resid + segresid is >= 4, add multiples of 4 to the count and 541 * decrease the residual by that much. 542 */ 543 cnt += resid & ~0x3; 544 resid -= resid & ~0x3; 545 546 ptr = buf; 547 548 first_pass = 1; 549 550 /* 551 * Save the old window base value. 552 */ 553 origwin = CSR_READ_4(sc, TI_WINBASE); 554 555 while (cnt) { 556 bus_size_t ti_offset; 557 558 if (cnt < TI_WINLEN) 559 segsize = cnt; 560 else 561 segsize = TI_WINLEN - (segptr % TI_WINLEN); 562 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 563 564 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 565 566 if (readdata) { 567 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 568 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 569 if (useraddr) { 570 /* 571 * Yeah, this is a little on the kludgy 572 * side, but at least this code is only 573 * used for debugging. 574 */ 575 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 576 segsize, TI_SWAP_NTOH); 577 578 TI_UNLOCK(sc); 579 if (first_pass) { 580 copyout(&sc->ti_membuf2[segresid], ptr, 581 segsize - segresid); 582 first_pass = 0; 583 } else 584 copyout(sc->ti_membuf2, ptr, segsize); 585 TI_LOCK(sc); 586 } else { 587 if (first_pass) { 588 589 ti_bcopy_swap(sc->ti_membuf, 590 sc->ti_membuf2, segsize, 591 TI_SWAP_NTOH); 592 TI_UNLOCK(sc); 593 bcopy(&sc->ti_membuf2[segresid], ptr, 594 segsize - segresid); 595 TI_LOCK(sc); 596 first_pass = 0; 597 } else 598 ti_bcopy_swap(sc->ti_membuf, ptr, 599 segsize, TI_SWAP_NTOH); 600 } 601 602 } else { 603 if (useraddr) { 604 TI_UNLOCK(sc); 605 copyin(ptr, sc->ti_membuf2, segsize); 606 TI_LOCK(sc); 607 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 608 segsize, TI_SWAP_HTON); 609 } else 610 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 611 TI_SWAP_HTON); 612 613 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 614 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 615 } 616 segptr += segsize; 617 ptr += segsize; 618 cnt -= segsize; 619 } 620 621 /* 622 * Handle leftover, non-word-aligned bytes. 623 */ 624 if (resid != 0) { 625 uint32_t tmpval, tmpval2; 626 bus_size_t ti_offset; 627 628 /* 629 * Set the segment pointer. 630 */ 631 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 632 633 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 634 635 /* 636 * First, grab whatever is in our source/destination. 637 * We'll obviously need this for reads, but also for 638 * writes, since we'll be doing read/modify/write. 639 */ 640 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 641 ti_offset, &tmpval, 1); 642 643 /* 644 * Next, translate this from little-endian to big-endian 645 * (at least on i386 boxes). 646 */ 647 tmpval2 = ntohl(tmpval); 648 649 if (readdata) { 650 /* 651 * If we're reading, just copy the leftover number 652 * of bytes from the host byte order buffer to 653 * the user's buffer. 654 */ 655 if (useraddr) { 656 TI_UNLOCK(sc); 657 copyout(&tmpval2, ptr, resid); 658 TI_LOCK(sc); 659 } else 660 bcopy(&tmpval2, ptr, resid); 661 } else { 662 /* 663 * If we're writing, first copy the bytes to be 664 * written into the network byte order buffer, 665 * leaving the rest of the buffer with whatever was 666 * originally in there. Then, swap the bytes 667 * around into host order and write them out. 668 * 669 * XXX KDM the read side of this has been verified 670 * to work, but the write side of it has not been 671 * verified. So user beware. 672 */ 673 if (useraddr) { 674 TI_UNLOCK(sc); 675 copyin(ptr, &tmpval2, resid); 676 TI_LOCK(sc); 677 } else 678 bcopy(ptr, &tmpval2, resid); 679 680 tmpval = htonl(tmpval2); 681 682 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 683 ti_offset, &tmpval, 1); 684 } 685 } 686 687 CSR_WRITE_4(sc, TI_WINBASE, origwin); 688 689 return (0); 690 } 691 692 static int 693 ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 694 caddr_t buf, int useraddr, int readdata, int cpu) 695 { 696 uint32_t segptr; 697 int cnt; 698 uint32_t tmpval, tmpval2; 699 caddr_t ptr; 700 701 TI_LOCK_ASSERT(sc); 702 703 /* 704 * At the moment, we don't handle non-aligned cases, we just bail. 705 * If this proves to be a problem, it will be fixed. 706 */ 707 if (tigon_addr & 0x3) { 708 device_printf(sc->ti_dev, "%s: tigon address %#x " 709 "isn't word-aligned\n", __func__, tigon_addr); 710 return (EINVAL); 711 } 712 713 if (len & 0x3) { 714 device_printf(sc->ti_dev, "%s: transfer length %d " 715 "isn't word-aligned\n", __func__, len); 716 return (EINVAL); 717 } 718 719 segptr = tigon_addr; 720 cnt = len; 721 ptr = buf; 722 723 while (cnt) { 724 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 725 726 if (readdata) { 727 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 728 729 tmpval = ntohl(tmpval2); 730 731 /* 732 * Note: I've used this debugging interface 733 * extensively with Alteon's 12.3.15 firmware, 734 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 735 * 736 * When you compile the firmware without 737 * optimization, which is necessary sometimes in 738 * order to properly step through it, you sometimes 739 * read out a bogus value of 0xc0017c instead of 740 * whatever was supposed to be in that scratchpad 741 * location. That value is on the stack somewhere, 742 * but I've never been able to figure out what was 743 * causing the problem. 744 * 745 * The address seems to pop up in random places, 746 * often not in the same place on two subsequent 747 * reads. 748 * 749 * In any case, the underlying data doesn't seem 750 * to be affected, just the value read out. 751 * 752 * KDM, 3/7/2000 753 */ 754 755 if (tmpval2 == 0xc0017c) 756 device_printf(sc->ti_dev, "found 0xc0017c at " 757 "%#x (tmpval2)\n", segptr); 758 759 if (tmpval == 0xc0017c) 760 device_printf(sc->ti_dev, "found 0xc0017c at " 761 "%#x (tmpval)\n", segptr); 762 763 if (useraddr) 764 copyout(&tmpval, ptr, 4); 765 else 766 bcopy(&tmpval, ptr, 4); 767 } else { 768 if (useraddr) 769 copyin(ptr, &tmpval2, 4); 770 else 771 bcopy(ptr, &tmpval2, 4); 772 773 tmpval = htonl(tmpval2); 774 775 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 776 } 777 778 cnt -= 4; 779 segptr += 4; 780 ptr += 4; 781 } 782 783 return (0); 784 } 785 786 static int 787 ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 788 { 789 const uint8_t *tmpsrc; 790 uint8_t *tmpdst; 791 size_t tmplen; 792 793 if (len & 0x3) { 794 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 795 return (-1); 796 } 797 798 tmpsrc = src; 799 tmpdst = dst; 800 tmplen = len; 801 802 while (tmplen) { 803 if (swap_type == TI_SWAP_NTOH) 804 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 805 else 806 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 807 tmpsrc += 4; 808 tmpdst += 4; 809 tmplen -= 4; 810 } 811 812 return (0); 813 } 814 815 /* 816 * Load firmware image into the NIC. Check that the firmware revision 817 * is acceptable and see if we want the firmware for the Tigon 1 or 818 * Tigon 2. 819 */ 820 static void 821 ti_loadfw(struct ti_softc *sc) 822 { 823 824 TI_LOCK_ASSERT(sc); 825 826 switch (sc->ti_hwrev) { 827 case TI_HWREV_TIGON: 828 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 829 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 830 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 831 device_printf(sc->ti_dev, "firmware revision mismatch; " 832 "want %d.%d.%d, got %d.%d.%d\n", 833 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 834 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 835 tigonFwReleaseMinor, tigonFwReleaseFix); 836 return; 837 } 838 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 839 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 840 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 841 tigonFwRodata); 842 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 843 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 844 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 845 break; 846 case TI_HWREV_TIGON_II: 847 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 848 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 849 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 850 device_printf(sc->ti_dev, "firmware revision mismatch; " 851 "want %d.%d.%d, got %d.%d.%d\n", 852 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 853 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 854 tigon2FwReleaseMinor, tigon2FwReleaseFix); 855 return; 856 } 857 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 858 tigon2FwText); 859 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 860 tigon2FwData); 861 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 862 tigon2FwRodata); 863 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 864 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 865 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 866 break; 867 default: 868 device_printf(sc->ti_dev, 869 "can't load firmware: unknown hardware rev\n"); 870 break; 871 } 872 } 873 874 /* 875 * Send the NIC a command via the command ring. 876 */ 877 static void 878 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 879 { 880 int index; 881 882 index = sc->ti_cmd_saved_prodidx; 883 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 884 TI_INC(index, TI_CMD_RING_CNT); 885 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 886 sc->ti_cmd_saved_prodidx = index; 887 } 888 889 /* 890 * Send the NIC an extended command. The 'len' parameter specifies the 891 * number of command slots to include after the initial command. 892 */ 893 static void 894 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 895 { 896 int index; 897 int i; 898 899 index = sc->ti_cmd_saved_prodidx; 900 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 901 TI_INC(index, TI_CMD_RING_CNT); 902 for (i = 0; i < len; i++) { 903 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 904 *(uint32_t *)(&arg[i * 4])); 905 TI_INC(index, TI_CMD_RING_CNT); 906 } 907 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 908 sc->ti_cmd_saved_prodidx = index; 909 } 910 911 /* 912 * Handle events that have triggered interrupts. 913 */ 914 static void 915 ti_handle_events(struct ti_softc *sc) 916 { 917 struct ti_event_desc *e; 918 919 if (sc->ti_rdata.ti_event_ring == NULL) 920 return; 921 922 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 923 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 924 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 925 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 926 switch (TI_EVENT_EVENT(e)) { 927 case TI_EV_LINKSTAT_CHANGED: 928 sc->ti_linkstat = TI_EVENT_CODE(e); 929 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 930 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 931 sc->ti_ifp->if_baudrate = IF_Mbps(100); 932 if (bootverbose) 933 device_printf(sc->ti_dev, 934 "10/100 link up\n"); 935 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 936 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 937 sc->ti_ifp->if_baudrate = IF_Gbps(1UL); 938 if (bootverbose) 939 device_printf(sc->ti_dev, 940 "gigabit link up\n"); 941 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 942 if_link_state_change(sc->ti_ifp, 943 LINK_STATE_DOWN); 944 sc->ti_ifp->if_baudrate = 0; 945 if (bootverbose) 946 device_printf(sc->ti_dev, 947 "link down\n"); 948 } 949 break; 950 case TI_EV_ERROR: 951 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 952 device_printf(sc->ti_dev, "invalid command\n"); 953 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 954 device_printf(sc->ti_dev, "unknown command\n"); 955 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 956 device_printf(sc->ti_dev, "bad config data\n"); 957 break; 958 case TI_EV_FIRMWARE_UP: 959 ti_init2(sc); 960 break; 961 case TI_EV_STATS_UPDATED: 962 case TI_EV_RESET_JUMBO_RING: 963 case TI_EV_MCAST_UPDATED: 964 /* Who cares. */ 965 break; 966 default: 967 device_printf(sc->ti_dev, "unknown event: %d\n", 968 TI_EVENT_EVENT(e)); 969 break; 970 } 971 /* Advance the consumer index. */ 972 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 973 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 974 } 975 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 976 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 977 } 978 979 struct ti_dmamap_arg { 980 bus_addr_t ti_busaddr; 981 }; 982 983 static void 984 ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 985 { 986 struct ti_dmamap_arg *ctx; 987 988 if (error) 989 return; 990 991 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 992 993 ctx = arg; 994 ctx->ti_busaddr = segs->ds_addr; 995 } 996 997 static int 998 ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 999 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1000 const char *msg) 1001 { 1002 struct ti_dmamap_arg ctx; 1003 int error; 1004 1005 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1006 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1007 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1008 if (error != 0) { 1009 device_printf(sc->ti_dev, 1010 "could not create %s dma tag\n", msg); 1011 return (error); 1012 } 1013 /* Allocate DMA'able memory for ring. */ 1014 error = bus_dmamem_alloc(*tag, (void **)ring, 1015 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1016 if (error != 0) { 1017 device_printf(sc->ti_dev, 1018 "could not allocate DMA'able memory for %s\n", msg); 1019 return (error); 1020 } 1021 /* Load the address of the ring. */ 1022 ctx.ti_busaddr = 0; 1023 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1024 &ctx, BUS_DMA_NOWAIT); 1025 if (error != 0) { 1026 device_printf(sc->ti_dev, 1027 "could not load DMA'able memory for %s\n", msg); 1028 return (error); 1029 } 1030 *paddr = ctx.ti_busaddr; 1031 return (0); 1032 } 1033 1034 static void 1035 ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1036 bus_dmamap_t map, bus_addr_t *paddr) 1037 { 1038 1039 if (*paddr != 0) { 1040 bus_dmamap_unload(*tag, map); 1041 *paddr = 0; 1042 } 1043 if (*ring != NULL) { 1044 bus_dmamem_free(*tag, *ring, map); 1045 *ring = NULL; 1046 } 1047 if (*tag) { 1048 bus_dma_tag_destroy(*tag); 1049 *tag = NULL; 1050 } 1051 } 1052 1053 static int 1054 ti_dma_alloc(struct ti_softc *sc) 1055 { 1056 bus_addr_t lowaddr; 1057 int i, error; 1058 1059 lowaddr = BUS_SPACE_MAXADDR; 1060 if (sc->ti_dac == 0) 1061 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1062 1063 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1064 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1065 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1066 &sc->ti_cdata.ti_parent_tag); 1067 if (error != 0) { 1068 device_printf(sc->ti_dev, 1069 "could not allocate parent dma tag\n"); 1070 return (ENOMEM); 1071 } 1072 1073 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1074 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1075 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1076 if (error) 1077 return (error); 1078 1079 /* Producer/consumer status */ 1080 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1081 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1082 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1083 "event ring"); 1084 if (error) 1085 return (error); 1086 1087 /* Event ring */ 1088 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1089 &sc->ti_cdata.ti_event_ring_tag, 1090 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1091 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1092 "event ring"); 1093 if (error) 1094 return (error); 1095 1096 /* Command ring lives in shared memory so no need to create DMA area. */ 1097 1098 /* Standard RX ring */ 1099 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1100 &sc->ti_cdata.ti_rx_std_ring_tag, 1101 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1102 &sc->ti_cdata.ti_rx_std_ring_map, 1103 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1104 if (error) 1105 return (error); 1106 1107 /* Jumbo RX ring */ 1108 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1109 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1110 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1111 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1112 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1113 if (error) 1114 return (error); 1115 1116 /* RX return ring */ 1117 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1118 &sc->ti_cdata.ti_rx_return_ring_tag, 1119 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1120 &sc->ti_cdata.ti_rx_return_ring_map, 1121 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1122 if (error) 1123 return (error); 1124 1125 /* Create DMA tag for standard RX mbufs. */ 1126 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1128 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1129 if (error) { 1130 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1131 return (error); 1132 } 1133 1134 /* Create DMA tag for jumbo RX mbufs. */ 1135 #ifdef TI_SF_BUF_JUMBO 1136 /* 1137 * The VM system will take care of providing aligned pages. Alignment 1138 * is set to 1 here so that busdma resources won't be wasted. 1139 */ 1140 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1141 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1142 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1143 #else 1144 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1146 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1147 #endif 1148 if (error) { 1149 device_printf(sc->ti_dev, 1150 "could not allocate jumbo RX dma tag\n"); 1151 return (error); 1152 } 1153 1154 /* Create DMA tag for TX mbufs. */ 1155 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1156 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1158 &sc->ti_cdata.ti_tx_tag); 1159 if (error) { 1160 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1161 return (ENOMEM); 1162 } 1163 1164 /* Create DMA maps for RX buffers. */ 1165 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1166 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1167 &sc->ti_cdata.ti_rx_std_maps[i]); 1168 if (error) { 1169 device_printf(sc->ti_dev, 1170 "could not create DMA map for RX\n"); 1171 return (error); 1172 } 1173 } 1174 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1175 &sc->ti_cdata.ti_rx_std_sparemap); 1176 if (error) { 1177 device_printf(sc->ti_dev, 1178 "could not create spare DMA map for RX\n"); 1179 return (error); 1180 } 1181 1182 /* Create DMA maps for jumbo RX buffers. */ 1183 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1184 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1185 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1186 if (error) { 1187 device_printf(sc->ti_dev, 1188 "could not create DMA map for jumbo RX\n"); 1189 return (error); 1190 } 1191 } 1192 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1193 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1194 if (error) { 1195 device_printf(sc->ti_dev, 1196 "could not create spare DMA map for jumbo RX\n"); 1197 return (error); 1198 } 1199 1200 /* Create DMA maps for TX buffers. */ 1201 for (i = 0; i < TI_TX_RING_CNT; i++) { 1202 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1203 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1204 if (error) { 1205 device_printf(sc->ti_dev, 1206 "could not create DMA map for TX\n"); 1207 return (ENOMEM); 1208 } 1209 } 1210 1211 /* Mini ring and TX ring is not available on Tigon 1. */ 1212 if (sc->ti_hwrev == TI_HWREV_TIGON) 1213 return (0); 1214 1215 /* TX ring */ 1216 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1217 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1218 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1219 "TX ring"); 1220 if (error) 1221 return (error); 1222 1223 /* Mini RX ring */ 1224 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1225 &sc->ti_cdata.ti_rx_mini_ring_tag, 1226 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1227 &sc->ti_cdata.ti_rx_mini_ring_map, 1228 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1229 if (error) 1230 return (error); 1231 1232 /* Create DMA tag for mini RX mbufs. */ 1233 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1235 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1236 if (error) { 1237 device_printf(sc->ti_dev, 1238 "could not allocate mini RX dma tag\n"); 1239 return (error); 1240 } 1241 1242 /* Create DMA maps for mini RX buffers. */ 1243 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1245 &sc->ti_cdata.ti_rx_mini_maps[i]); 1246 if (error) { 1247 device_printf(sc->ti_dev, 1248 "could not create DMA map for mini RX\n"); 1249 return (error); 1250 } 1251 } 1252 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1253 &sc->ti_cdata.ti_rx_mini_sparemap); 1254 if (error) { 1255 device_printf(sc->ti_dev, 1256 "could not create spare DMA map for mini RX\n"); 1257 return (error); 1258 } 1259 1260 return (0); 1261 } 1262 1263 static void 1264 ti_dma_free(struct ti_softc *sc) 1265 { 1266 int i; 1267 1268 /* Destroy DMA maps for RX buffers. */ 1269 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1270 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1271 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1272 sc->ti_cdata.ti_rx_std_maps[i]); 1273 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1274 } 1275 } 1276 if (sc->ti_cdata.ti_rx_std_sparemap) { 1277 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1278 sc->ti_cdata.ti_rx_std_sparemap); 1279 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1280 } 1281 if (sc->ti_cdata.ti_rx_std_tag) { 1282 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1283 sc->ti_cdata.ti_rx_std_tag = NULL; 1284 } 1285 1286 /* Destroy DMA maps for jumbo RX buffers. */ 1287 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1288 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1289 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1290 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1291 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1292 } 1293 } 1294 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1295 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1296 sc->ti_cdata.ti_rx_jumbo_sparemap); 1297 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1298 } 1299 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1300 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1301 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1302 } 1303 1304 /* Destroy DMA maps for mini RX buffers. */ 1305 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1306 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1307 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1308 sc->ti_cdata.ti_rx_mini_maps[i]); 1309 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1310 } 1311 } 1312 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1313 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1314 sc->ti_cdata.ti_rx_mini_sparemap); 1315 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1316 } 1317 if (sc->ti_cdata.ti_rx_mini_tag) { 1318 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1319 sc->ti_cdata.ti_rx_mini_tag = NULL; 1320 } 1321 1322 /* Destroy DMA maps for TX buffers. */ 1323 for (i = 0; i < TI_TX_RING_CNT; i++) { 1324 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1325 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1326 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1327 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1328 } 1329 } 1330 if (sc->ti_cdata.ti_tx_tag) { 1331 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1332 sc->ti_cdata.ti_tx_tag = NULL; 1333 } 1334 1335 /* Destroy standard RX ring. */ 1336 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1337 (void *)&sc->ti_rdata.ti_rx_std_ring, 1338 sc->ti_cdata.ti_rx_std_ring_map, 1339 &sc->ti_rdata.ti_rx_std_ring_paddr); 1340 /* Destroy jumbo RX ring. */ 1341 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1342 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1343 sc->ti_cdata.ti_rx_jumbo_ring_map, 1344 &sc->ti_rdata.ti_rx_jumbo_ring_paddr); 1345 /* Destroy mini RX ring. */ 1346 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1347 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1348 sc->ti_cdata.ti_rx_mini_ring_map, 1349 &sc->ti_rdata.ti_rx_mini_ring_paddr); 1350 /* Destroy RX return ring. */ 1351 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1352 (void *)&sc->ti_rdata.ti_rx_return_ring, 1353 sc->ti_cdata.ti_rx_return_ring_map, 1354 &sc->ti_rdata.ti_rx_return_ring_paddr); 1355 /* Destroy TX ring. */ 1356 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1357 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map, 1358 &sc->ti_rdata.ti_tx_ring_paddr); 1359 /* Destroy status block. */ 1360 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1361 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map, 1362 &sc->ti_rdata.ti_status_paddr); 1363 /* Destroy event ring. */ 1364 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1365 (void *)&sc->ti_rdata.ti_event_ring, 1366 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr); 1367 /* Destroy GIB */ 1368 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1369 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map, 1370 &sc->ti_rdata.ti_info_paddr); 1371 1372 /* Destroy the parent tag. */ 1373 if (sc->ti_cdata.ti_parent_tag) { 1374 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1375 sc->ti_cdata.ti_parent_tag = NULL; 1376 } 1377 } 1378 1379 /* 1380 * Intialize a standard receive ring descriptor. 1381 */ 1382 static int 1383 ti_newbuf_std(struct ti_softc *sc, int i) 1384 { 1385 bus_dmamap_t map; 1386 bus_dma_segment_t segs[1]; 1387 struct mbuf *m; 1388 struct ti_rx_desc *r; 1389 int error, nsegs; 1390 1391 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1392 if (m == NULL) 1393 return (ENOBUFS); 1394 m->m_len = m->m_pkthdr.len = MCLBYTES; 1395 m_adj(m, ETHER_ALIGN); 1396 1397 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1398 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1399 if (error != 0) { 1400 m_freem(m); 1401 return (error); 1402 } 1403 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1404 1405 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1406 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1407 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1408 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1409 sc->ti_cdata.ti_rx_std_maps[i]); 1410 } 1411 1412 map = sc->ti_cdata.ti_rx_std_maps[i]; 1413 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1414 sc->ti_cdata.ti_rx_std_sparemap = map; 1415 sc->ti_cdata.ti_rx_std_chain[i] = m; 1416 1417 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1418 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1419 r->ti_len = segs[0].ds_len; 1420 r->ti_type = TI_BDTYPE_RECV_BD; 1421 r->ti_flags = 0; 1422 r->ti_vlan_tag = 0; 1423 r->ti_tcp_udp_cksum = 0; 1424 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1425 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1426 r->ti_idx = i; 1427 1428 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1429 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1430 return (0); 1431 } 1432 1433 /* 1434 * Intialize a mini receive ring descriptor. This only applies to 1435 * the Tigon 2. 1436 */ 1437 static int 1438 ti_newbuf_mini(struct ti_softc *sc, int i) 1439 { 1440 bus_dmamap_t map; 1441 bus_dma_segment_t segs[1]; 1442 struct mbuf *m; 1443 struct ti_rx_desc *r; 1444 int error, nsegs; 1445 1446 MGETHDR(m, M_NOWAIT, MT_DATA); 1447 if (m == NULL) 1448 return (ENOBUFS); 1449 m->m_len = m->m_pkthdr.len = MHLEN; 1450 m_adj(m, ETHER_ALIGN); 1451 1452 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1453 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1454 if (error != 0) { 1455 m_freem(m); 1456 return (error); 1457 } 1458 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1459 1460 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1461 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1462 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1463 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1464 sc->ti_cdata.ti_rx_mini_maps[i]); 1465 } 1466 1467 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1468 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1469 sc->ti_cdata.ti_rx_mini_sparemap = map; 1470 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1471 1472 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1473 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1474 r->ti_len = segs[0].ds_len; 1475 r->ti_type = TI_BDTYPE_RECV_BD; 1476 r->ti_flags = TI_BDFLAG_MINI_RING; 1477 r->ti_vlan_tag = 0; 1478 r->ti_tcp_udp_cksum = 0; 1479 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1480 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1481 r->ti_idx = i; 1482 1483 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1484 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1485 return (0); 1486 } 1487 1488 #ifndef TI_SF_BUF_JUMBO 1489 1490 /* 1491 * Initialize a jumbo receive ring descriptor. This allocates 1492 * a jumbo buffer from the pool managed internally by the driver. 1493 */ 1494 static int 1495 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1496 { 1497 bus_dmamap_t map; 1498 bus_dma_segment_t segs[1]; 1499 struct mbuf *m; 1500 struct ti_rx_desc *r; 1501 int error, nsegs; 1502 1503 (void)dummy; 1504 1505 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1506 if (m == NULL) 1507 return (ENOBUFS); 1508 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1509 m_adj(m, ETHER_ALIGN); 1510 1511 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1512 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1513 if (error != 0) { 1514 m_freem(m); 1515 return (error); 1516 } 1517 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1518 1519 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1520 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1521 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1522 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1523 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1524 } 1525 1526 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1527 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1528 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1529 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1530 1531 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1532 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1533 r->ti_len = segs[0].ds_len; 1534 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1535 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1536 r->ti_vlan_tag = 0; 1537 r->ti_tcp_udp_cksum = 0; 1538 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1539 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1540 r->ti_idx = i; 1541 1542 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1543 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1544 return (0); 1545 } 1546 1547 #else 1548 1549 #if (PAGE_SIZE == 4096) 1550 #define NPAYLOAD 2 1551 #else 1552 #define NPAYLOAD 1 1553 #endif 1554 1555 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1556 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1557 #define NFS_HDR_LEN (UDP_HDR_LEN) 1558 static int HDR_LEN = TCP_HDR_LEN; 1559 1560 /* 1561 * Initialize a jumbo receive ring descriptor. This allocates 1562 * a jumbo buffer from the pool managed internally by the driver. 1563 */ 1564 static int 1565 ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1566 { 1567 bus_dmamap_t map; 1568 struct mbuf *cur, *m_new = NULL; 1569 struct mbuf *m[3] = {NULL, NULL, NULL}; 1570 struct ti_rx_desc_ext *r; 1571 vm_page_t frame; 1572 /* 1 extra buf to make nobufs easy*/ 1573 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1574 int i; 1575 bus_dma_segment_t segs[4]; 1576 int nsegs; 1577 1578 if (m_old != NULL) { 1579 m_new = m_old; 1580 cur = m_old->m_next; 1581 for (i = 0; i <= NPAYLOAD; i++){ 1582 m[i] = cur; 1583 cur = cur->m_next; 1584 } 1585 } else { 1586 /* Allocate the mbufs. */ 1587 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1588 if (m_new == NULL) { 1589 device_printf(sc->ti_dev, "mbuf allocation failed " 1590 "-- packet dropped!\n"); 1591 goto nobufs; 1592 } 1593 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA); 1594 if (m[NPAYLOAD] == NULL) { 1595 device_printf(sc->ti_dev, "cluster mbuf allocation " 1596 "failed -- packet dropped!\n"); 1597 goto nobufs; 1598 } 1599 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) { 1600 device_printf(sc->ti_dev, "mbuf allocation failed " 1601 "-- packet dropped!\n"); 1602 goto nobufs; 1603 } 1604 m[NPAYLOAD]->m_len = MCLBYTES; 1605 1606 for (i = 0; i < NPAYLOAD; i++){ 1607 MGET(m[i], M_NOWAIT, MT_DATA); 1608 if (m[i] == NULL) { 1609 device_printf(sc->ti_dev, "mbuf allocation " 1610 "failed -- packet dropped!\n"); 1611 goto nobufs; 1612 } 1613 frame = vm_page_alloc(NULL, 0, 1614 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1615 VM_ALLOC_WIRED); 1616 if (frame == NULL) { 1617 device_printf(sc->ti_dev, "buffer allocation " 1618 "failed -- packet dropped!\n"); 1619 printf(" index %d page %d\n", idx, i); 1620 goto nobufs; 1621 } 1622 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1623 if (sf[i] == NULL) { 1624 vm_page_unwire(frame, PQ_INACTIVE); 1625 vm_page_free(frame); 1626 device_printf(sc->ti_dev, "buffer allocation " 1627 "failed -- packet dropped!\n"); 1628 printf(" index %d page %d\n", idx, i); 1629 goto nobufs; 1630 } 1631 } 1632 for (i = 0; i < NPAYLOAD; i++){ 1633 /* Attach the buffer to the mbuf. */ 1634 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1635 m[i]->m_len = PAGE_SIZE; 1636 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1637 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i], 1638 0, EXT_DISPOSABLE); 1639 m[i]->m_next = m[i+1]; 1640 } 1641 /* link the buffers to the header */ 1642 m_new->m_next = m[0]; 1643 m_new->m_data += ETHER_ALIGN; 1644 if (sc->ti_hdrsplit) 1645 m_new->m_len = MHLEN - ETHER_ALIGN; 1646 else 1647 m_new->m_len = HDR_LEN; 1648 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1649 } 1650 1651 /* Set up the descriptor. */ 1652 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1653 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1654 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1655 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1656 segs, &nsegs, 0)) 1657 return (ENOBUFS); 1658 if ((nsegs < 1) || (nsegs > 4)) 1659 return (ENOBUFS); 1660 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1661 r->ti_len0 = m_new->m_len; 1662 1663 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1664 r->ti_len1 = PAGE_SIZE; 1665 1666 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1667 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1668 1669 if (PAGE_SIZE == 4096) { 1670 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1671 r->ti_len3 = MCLBYTES; 1672 } else { 1673 r->ti_len3 = 0; 1674 } 1675 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1676 1677 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1678 1679 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 1680 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1681 1682 r->ti_idx = idx; 1683 1684 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1685 return (0); 1686 1687 nobufs: 1688 1689 /* 1690 * Warning! : 1691 * This can only be called before the mbufs are strung together. 1692 * If the mbufs are strung together, m_freem() will free the chain, 1693 * so that the later mbufs will be freed multiple times. 1694 */ 1695 if (m_new) 1696 m_freem(m_new); 1697 1698 for (i = 0; i < 3; i++) { 1699 if (m[i]) 1700 m_freem(m[i]); 1701 if (sf[i]) 1702 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]); 1703 } 1704 return (ENOBUFS); 1705 } 1706 #endif 1707 1708 /* 1709 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1710 * that's 1MB or memory, which is a lot. For now, we fill only the first 1711 * 256 ring entries and hope that our CPU is fast enough to keep up with 1712 * the NIC. 1713 */ 1714 static int 1715 ti_init_rx_ring_std(struct ti_softc *sc) 1716 { 1717 int i; 1718 struct ti_cmd_desc cmd; 1719 1720 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1721 if (ti_newbuf_std(sc, i) != 0) 1722 return (ENOBUFS); 1723 }; 1724 1725 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1726 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1727 1728 return (0); 1729 } 1730 1731 static void 1732 ti_free_rx_ring_std(struct ti_softc *sc) 1733 { 1734 bus_dmamap_t map; 1735 int i; 1736 1737 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1738 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1739 map = sc->ti_cdata.ti_rx_std_maps[i]; 1740 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1741 BUS_DMASYNC_POSTREAD); 1742 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1743 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1744 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1745 } 1746 } 1747 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1748 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1749 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1750 } 1751 1752 static int 1753 ti_init_rx_ring_jumbo(struct ti_softc *sc) 1754 { 1755 struct ti_cmd_desc cmd; 1756 int i; 1757 1758 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1759 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1760 return (ENOBUFS); 1761 }; 1762 1763 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1764 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1765 1766 return (0); 1767 } 1768 1769 static void 1770 ti_free_rx_ring_jumbo(struct ti_softc *sc) 1771 { 1772 bus_dmamap_t map; 1773 int i; 1774 1775 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1776 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1777 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1778 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1779 BUS_DMASYNC_POSTREAD); 1780 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1781 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1782 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1783 } 1784 } 1785 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1786 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1787 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1788 } 1789 1790 static int 1791 ti_init_rx_ring_mini(struct ti_softc *sc) 1792 { 1793 int i; 1794 1795 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1796 if (ti_newbuf_mini(sc, i) != 0) 1797 return (ENOBUFS); 1798 }; 1799 1800 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1801 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1802 1803 return (0); 1804 } 1805 1806 static void 1807 ti_free_rx_ring_mini(struct ti_softc *sc) 1808 { 1809 bus_dmamap_t map; 1810 int i; 1811 1812 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1813 return; 1814 1815 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1816 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1817 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1818 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1819 BUS_DMASYNC_POSTREAD); 1820 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1821 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1822 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1823 } 1824 } 1825 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1826 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1827 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1828 } 1829 1830 static void 1831 ti_free_tx_ring(struct ti_softc *sc) 1832 { 1833 struct ti_txdesc *txd; 1834 int i; 1835 1836 if (sc->ti_rdata.ti_tx_ring == NULL) 1837 return; 1838 1839 for (i = 0; i < TI_TX_RING_CNT; i++) { 1840 txd = &sc->ti_cdata.ti_txdesc[i]; 1841 if (txd->tx_m != NULL) { 1842 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1843 BUS_DMASYNC_POSTWRITE); 1844 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1845 txd->tx_dmamap); 1846 m_freem(txd->tx_m); 1847 txd->tx_m = NULL; 1848 } 1849 } 1850 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1851 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1852 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1853 } 1854 1855 static int 1856 ti_init_tx_ring(struct ti_softc *sc) 1857 { 1858 struct ti_txdesc *txd; 1859 int i; 1860 1861 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1862 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1863 for (i = 0; i < TI_TX_RING_CNT; i++) { 1864 txd = &sc->ti_cdata.ti_txdesc[i]; 1865 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1866 } 1867 sc->ti_txcnt = 0; 1868 sc->ti_tx_saved_considx = 0; 1869 sc->ti_tx_saved_prodidx = 0; 1870 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1871 return (0); 1872 } 1873 1874 /* 1875 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1876 * but we have to support the old way too so that Tigon 1 cards will 1877 * work. 1878 */ 1879 static void 1880 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1881 { 1882 struct ti_cmd_desc cmd; 1883 uint16_t *m; 1884 uint32_t ext[2] = {0, 0}; 1885 1886 m = (uint16_t *)&addr->octet[0]; 1887 1888 switch (sc->ti_hwrev) { 1889 case TI_HWREV_TIGON: 1890 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1891 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1892 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1893 break; 1894 case TI_HWREV_TIGON_II: 1895 ext[0] = htons(m[0]); 1896 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1897 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1898 break; 1899 default: 1900 device_printf(sc->ti_dev, "unknown hwrev\n"); 1901 break; 1902 } 1903 } 1904 1905 static void 1906 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1907 { 1908 struct ti_cmd_desc cmd; 1909 uint16_t *m; 1910 uint32_t ext[2] = {0, 0}; 1911 1912 m = (uint16_t *)&addr->octet[0]; 1913 1914 switch (sc->ti_hwrev) { 1915 case TI_HWREV_TIGON: 1916 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1917 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1918 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1919 break; 1920 case TI_HWREV_TIGON_II: 1921 ext[0] = htons(m[0]); 1922 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1923 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1924 break; 1925 default: 1926 device_printf(sc->ti_dev, "unknown hwrev\n"); 1927 break; 1928 } 1929 } 1930 1931 /* 1932 * Configure the Tigon's multicast address filter. 1933 * 1934 * The actual multicast table management is a bit of a pain, thanks to 1935 * slight brain damage on the part of both Alteon and us. With our 1936 * multicast code, we are only alerted when the multicast address table 1937 * changes and at that point we only have the current list of addresses: 1938 * we only know the current state, not the previous state, so we don't 1939 * actually know what addresses were removed or added. The firmware has 1940 * state, but we can't get our grubby mits on it, and there is no 'delete 1941 * all multicast addresses' command. Hence, we have to maintain our own 1942 * state so we know what addresses have been programmed into the NIC at 1943 * any given time. 1944 */ 1945 static void 1946 ti_setmulti(struct ti_softc *sc) 1947 { 1948 struct ifnet *ifp; 1949 struct ifmultiaddr *ifma; 1950 struct ti_cmd_desc cmd; 1951 struct ti_mc_entry *mc; 1952 uint32_t intrs; 1953 1954 TI_LOCK_ASSERT(sc); 1955 1956 ifp = sc->ti_ifp; 1957 1958 if (ifp->if_flags & IFF_ALLMULTI) { 1959 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1960 return; 1961 } else { 1962 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1963 } 1964 1965 /* Disable interrupts. */ 1966 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1967 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1968 1969 /* First, zot all the existing filters. */ 1970 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1971 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1972 ti_del_mcast(sc, &mc->mc_addr); 1973 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1974 free(mc, M_DEVBUF); 1975 } 1976 1977 /* Now program new ones. */ 1978 if_maddr_rlock(ifp); 1979 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1980 if (ifma->ifma_addr->sa_family != AF_LINK) 1981 continue; 1982 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1983 if (mc == NULL) { 1984 device_printf(sc->ti_dev, 1985 "no memory for mcast filter entry\n"); 1986 continue; 1987 } 1988 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1989 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1990 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1991 ti_add_mcast(sc, &mc->mc_addr); 1992 } 1993 if_maddr_runlock(ifp); 1994 1995 /* Re-enable interrupts. */ 1996 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1997 } 1998 1999 /* 2000 * Check to see if the BIOS has configured us for a 64 bit slot when 2001 * we aren't actually in one. If we detect this condition, we can work 2002 * around it on the Tigon 2 by setting a bit in the PCI state register, 2003 * but for the Tigon 1 we must give up and abort the interface attach. 2004 */ 2005 static int 2006 ti_64bitslot_war(struct ti_softc *sc) 2007 { 2008 2009 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 2010 CSR_WRITE_4(sc, 0x600, 0); 2011 CSR_WRITE_4(sc, 0x604, 0); 2012 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2013 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2014 if (sc->ti_hwrev == TI_HWREV_TIGON) 2015 return (EINVAL); 2016 else { 2017 TI_SETBIT(sc, TI_PCI_STATE, 2018 TI_PCISTATE_32BIT_BUS); 2019 return (0); 2020 } 2021 } 2022 } 2023 2024 return (0); 2025 } 2026 2027 /* 2028 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2029 * self-test results. 2030 */ 2031 static int 2032 ti_chipinit(struct ti_softc *sc) 2033 { 2034 uint32_t cacheline; 2035 uint32_t pci_writemax = 0; 2036 uint32_t hdrsplit; 2037 2038 /* Initialize link to down state. */ 2039 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2040 2041 /* Set endianness before we access any non-PCI registers. */ 2042 #if 0 && BYTE_ORDER == BIG_ENDIAN 2043 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2044 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2045 #else 2046 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2047 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2048 #endif 2049 2050 /* Check the ROM failed bit to see if self-tests passed. */ 2051 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2052 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2053 return (ENODEV); 2054 } 2055 2056 /* Halt the CPU. */ 2057 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2058 2059 /* Figure out the hardware revision. */ 2060 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2061 case TI_REV_TIGON_I: 2062 sc->ti_hwrev = TI_HWREV_TIGON; 2063 break; 2064 case TI_REV_TIGON_II: 2065 sc->ti_hwrev = TI_HWREV_TIGON_II; 2066 break; 2067 default: 2068 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2069 return (ENODEV); 2070 } 2071 2072 /* Do special setup for Tigon 2. */ 2073 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2074 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2075 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2076 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2077 } 2078 2079 /* 2080 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2081 * can't do header splitting. 2082 */ 2083 #ifdef TI_JUMBO_HDRSPLIT 2084 if (sc->ti_hwrev != TI_HWREV_TIGON) 2085 sc->ti_hdrsplit = 1; 2086 else 2087 device_printf(sc->ti_dev, 2088 "can't do header splitting on a Tigon I board\n"); 2089 #endif /* TI_JUMBO_HDRSPLIT */ 2090 2091 /* Set up the PCI state register. */ 2092 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2093 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2094 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2095 } 2096 2097 /* Clear the read/write max DMA parameters. */ 2098 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2099 TI_PCISTATE_READ_MAXDMA)); 2100 2101 /* Get cache line size. */ 2102 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2103 2104 /* 2105 * If the system has set enabled the PCI memory write 2106 * and invalidate command in the command register, set 2107 * the write max parameter accordingly. This is necessary 2108 * to use MWI with the Tigon 2. 2109 */ 2110 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2111 switch (cacheline) { 2112 case 1: 2113 case 4: 2114 case 8: 2115 case 16: 2116 case 32: 2117 case 64: 2118 break; 2119 default: 2120 /* Disable PCI memory write and invalidate. */ 2121 if (bootverbose) 2122 device_printf(sc->ti_dev, "cache line size %d" 2123 " not supported; disabling PCI MWI\n", 2124 cacheline); 2125 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2126 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2127 break; 2128 } 2129 } 2130 2131 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2132 2133 /* This sets the min dma param all the way up (0xff). */ 2134 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2135 2136 if (sc->ti_hdrsplit) 2137 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2138 else 2139 hdrsplit = 0; 2140 2141 /* Configure DMA variables. */ 2142 #if BYTE_ORDER == BIG_ENDIAN 2143 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2144 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2145 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2146 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2147 #else /* BYTE_ORDER */ 2148 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2149 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2150 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2151 #endif /* BYTE_ORDER */ 2152 2153 /* 2154 * Only allow 1 DMA channel to be active at a time. 2155 * I don't think this is a good idea, but without it 2156 * the firmware racks up lots of nicDmaReadRingFull 2157 * errors. This is not compatible with hardware checksums. 2158 */ 2159 if ((sc->ti_ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2160 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2161 2162 /* Recommended settings from Tigon manual. */ 2163 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2164 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2165 2166 if (ti_64bitslot_war(sc)) { 2167 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2168 "but we aren't"); 2169 return (EINVAL); 2170 } 2171 2172 return (0); 2173 } 2174 2175 /* 2176 * Initialize the general information block and firmware, and 2177 * start the CPU(s) running. 2178 */ 2179 static int 2180 ti_gibinit(struct ti_softc *sc) 2181 { 2182 struct ifnet *ifp; 2183 struct ti_rcb *rcb; 2184 int i; 2185 2186 TI_LOCK_ASSERT(sc); 2187 2188 ifp = sc->ti_ifp; 2189 2190 /* Disable interrupts for now. */ 2191 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2192 2193 /* Tell the chip where to find the general information block. */ 2194 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2195 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2196 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2197 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2198 2199 /* Load the firmware into SRAM. */ 2200 ti_loadfw(sc); 2201 2202 /* Set up the contents of the general info and ring control blocks. */ 2203 2204 /* Set up the event ring and producer pointer. */ 2205 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2206 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2207 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2208 rcb->ti_flags = 0; 2209 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2210 sc->ti_rdata.ti_status_paddr + 2211 offsetof(struct ti_status, ti_ev_prodidx_r)); 2212 sc->ti_ev_prodidx.ti_idx = 0; 2213 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2214 sc->ti_ev_saved_considx = 0; 2215 2216 /* Set up the command ring and producer mailbox. */ 2217 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2218 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2219 rcb->ti_flags = 0; 2220 rcb->ti_max_len = 0; 2221 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2222 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2223 } 2224 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2225 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2226 sc->ti_cmd_saved_prodidx = 0; 2227 2228 /* 2229 * Assign the address of the stats refresh buffer. 2230 * We re-use the current stats buffer for this to 2231 * conserve memory. 2232 */ 2233 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2234 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2235 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2236 2237 /* Set up the standard receive ring. */ 2238 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2239 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2240 rcb->ti_max_len = TI_FRAMELEN; 2241 rcb->ti_flags = 0; 2242 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2243 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2244 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2245 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2246 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2247 2248 /* Set up the jumbo receive ring. */ 2249 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2250 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2251 2252 #ifndef TI_SF_BUF_JUMBO 2253 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2254 rcb->ti_flags = 0; 2255 #else 2256 rcb->ti_max_len = PAGE_SIZE; 2257 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2258 #endif 2259 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2260 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2261 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2262 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2263 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2264 2265 /* 2266 * Set up the mini ring. Only activated on the 2267 * Tigon 2 but the slot in the config block is 2268 * still there on the Tigon 1. 2269 */ 2270 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2271 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2272 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2273 if (sc->ti_hwrev == TI_HWREV_TIGON) 2274 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2275 else 2276 rcb->ti_flags = 0; 2277 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2278 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2279 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2280 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2281 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2282 2283 /* 2284 * Set up the receive return ring. 2285 */ 2286 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2287 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2288 rcb->ti_flags = 0; 2289 rcb->ti_max_len = TI_RETURN_RING_CNT; 2290 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2291 sc->ti_rdata.ti_status_paddr + 2292 offsetof(struct ti_status, ti_return_prodidx_r)); 2293 2294 /* 2295 * Set up the tx ring. Note: for the Tigon 2, we have the option 2296 * of putting the transmit ring in the host's address space and 2297 * letting the chip DMA it instead of leaving the ring in the NIC's 2298 * memory and accessing it through the shared memory region. We 2299 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2300 * so we have to revert to the shared memory scheme if we detect 2301 * a Tigon 1 chip. 2302 */ 2303 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2304 if (sc->ti_rdata.ti_tx_ring != NULL) 2305 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2306 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2307 if (sc->ti_hwrev == TI_HWREV_TIGON) 2308 rcb->ti_flags = 0; 2309 else 2310 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2311 if (sc->ti_ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2312 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2313 if (sc->ti_ifp->if_capenable & IFCAP_TXCSUM) 2314 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2315 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2316 rcb->ti_max_len = TI_TX_RING_CNT; 2317 if (sc->ti_hwrev == TI_HWREV_TIGON) 2318 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2319 else 2320 ti_hostaddr64(&rcb->ti_hostaddr, 2321 sc->ti_rdata.ti_tx_ring_paddr); 2322 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2323 sc->ti_rdata.ti_status_paddr + 2324 offsetof(struct ti_status, ti_tx_considx_r)); 2325 2326 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2327 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2328 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2330 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2331 sc->ti_cdata.ti_event_ring_map, 2332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2333 if (sc->ti_rdata.ti_tx_ring != NULL) 2334 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2335 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2336 2337 /* Set up tunables */ 2338 #if 0 2339 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2340 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2341 (sc->ti_rx_coal_ticks / 10)); 2342 else 2343 #endif 2344 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2345 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2346 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2347 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2348 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2349 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2350 2351 /* Turn interrupts on. */ 2352 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2353 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2354 2355 /* Start CPU. */ 2356 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2357 2358 return (0); 2359 } 2360 2361 /* 2362 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2363 * against our list and return its name if we find a match. 2364 */ 2365 static int 2366 ti_probe(device_t dev) 2367 { 2368 const struct ti_type *t; 2369 2370 t = ti_devs; 2371 2372 while (t->ti_name != NULL) { 2373 if ((pci_get_vendor(dev) == t->ti_vid) && 2374 (pci_get_device(dev) == t->ti_did)) { 2375 device_set_desc(dev, t->ti_name); 2376 return (BUS_PROBE_DEFAULT); 2377 } 2378 t++; 2379 } 2380 2381 return (ENXIO); 2382 } 2383 2384 static int 2385 ti_attach(device_t dev) 2386 { 2387 struct ifnet *ifp; 2388 struct ti_softc *sc; 2389 int error = 0, rid; 2390 u_char eaddr[6]; 2391 2392 sc = device_get_softc(dev); 2393 sc->ti_dev = dev; 2394 2395 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2396 MTX_DEF); 2397 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2398 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2399 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2400 if (ifp == NULL) { 2401 device_printf(dev, "can not if_alloc()\n"); 2402 error = ENOSPC; 2403 goto fail; 2404 } 2405 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 2406 sc->ti_ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM; 2407 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2408 2409 /* 2410 * Map control/status registers. 2411 */ 2412 pci_enable_busmaster(dev); 2413 2414 rid = PCIR_BAR(0); 2415 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2416 RF_ACTIVE); 2417 2418 if (sc->ti_res == NULL) { 2419 device_printf(dev, "couldn't map memory\n"); 2420 error = ENXIO; 2421 goto fail; 2422 } 2423 2424 sc->ti_btag = rman_get_bustag(sc->ti_res); 2425 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2426 2427 /* Allocate interrupt */ 2428 rid = 0; 2429 2430 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2431 RF_SHAREABLE | RF_ACTIVE); 2432 2433 if (sc->ti_irq == NULL) { 2434 device_printf(dev, "couldn't map interrupt\n"); 2435 error = ENXIO; 2436 goto fail; 2437 } 2438 2439 if (ti_chipinit(sc)) { 2440 device_printf(dev, "chip initialization failed\n"); 2441 error = ENXIO; 2442 goto fail; 2443 } 2444 2445 /* Zero out the NIC's on-board SRAM. */ 2446 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2447 2448 /* Init again -- zeroing memory may have clobbered some registers. */ 2449 if (ti_chipinit(sc)) { 2450 device_printf(dev, "chip initialization failed\n"); 2451 error = ENXIO; 2452 goto fail; 2453 } 2454 2455 /* 2456 * Get station address from the EEPROM. Note: the manual states 2457 * that the MAC address is at offset 0x8c, however the data is 2458 * stored as two longwords (since that's how it's loaded into 2459 * the NIC). This means the MAC address is actually preceded 2460 * by two zero bytes. We need to skip over those. 2461 */ 2462 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2463 device_printf(dev, "failed to read station address\n"); 2464 error = ENXIO; 2465 goto fail; 2466 } 2467 2468 /* Allocate working area for memory dump. */ 2469 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2470 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2471 M_NOWAIT); 2472 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2473 device_printf(dev, "cannot allocate memory buffer\n"); 2474 error = ENOMEM; 2475 goto fail; 2476 } 2477 if ((error = ti_dma_alloc(sc)) != 0) 2478 goto fail; 2479 2480 /* 2481 * We really need a better way to tell a 1000baseTX card 2482 * from a 1000baseSX one, since in theory there could be 2483 * OEMed 1000baseTX cards from lame vendors who aren't 2484 * clever enough to change the PCI ID. For the moment 2485 * though, the AceNIC is the only copper card available. 2486 */ 2487 if (pci_get_vendor(dev) == ALT_VENDORID && 2488 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2489 sc->ti_copper = 1; 2490 /* Ok, it's not the only copper card available. */ 2491 if (pci_get_vendor(dev) == NG_VENDORID && 2492 pci_get_device(dev) == NG_DEVICEID_GA620T) 2493 sc->ti_copper = 1; 2494 2495 /* Set default tunable values. */ 2496 ti_sysctl_node(sc); 2497 2498 /* Set up ifnet structure */ 2499 ifp->if_softc = sc; 2500 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2501 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2502 ifp->if_ioctl = ti_ioctl; 2503 ifp->if_start = ti_start; 2504 ifp->if_init = ti_init; 2505 ifp->if_get_counter = ti_get_counter; 2506 ifp->if_baudrate = IF_Gbps(1UL); 2507 ifp->if_snd.ifq_drv_maxlen = TI_TX_RING_CNT - 1; 2508 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2509 IFQ_SET_READY(&ifp->if_snd); 2510 2511 /* Set up ifmedia support. */ 2512 if (sc->ti_copper) { 2513 /* 2514 * Copper cards allow manual 10/100 mode selection, 2515 * but not manual 1000baseTX mode selection. Why? 2516 * Becuase currently there's no way to specify the 2517 * master/slave setting through the firmware interface, 2518 * so Alteon decided to just bag it and handle it 2519 * via autonegotiation. 2520 */ 2521 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2522 ifmedia_add(&sc->ifmedia, 2523 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2524 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2525 ifmedia_add(&sc->ifmedia, 2526 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2527 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2528 ifmedia_add(&sc->ifmedia, 2529 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2530 } else { 2531 /* Fiber cards don't support 10/100 modes. */ 2532 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2533 ifmedia_add(&sc->ifmedia, 2534 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2535 } 2536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2537 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2538 2539 /* 2540 * We're assuming here that card initialization is a sequential 2541 * thing. If it isn't, multiple cards probing at the same time 2542 * could stomp on the list of softcs here. 2543 */ 2544 2545 /* Register the device */ 2546 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2547 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2548 sc->dev->si_drv1 = sc; 2549 2550 /* 2551 * Call MI attach routine. 2552 */ 2553 ether_ifattach(ifp, eaddr); 2554 2555 /* VLAN capability setup. */ 2556 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2557 IFCAP_VLAN_HWTAGGING; 2558 ifp->if_capenable = ifp->if_capabilities; 2559 /* Tell the upper layer we support VLAN over-sized frames. */ 2560 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2561 2562 /* Driver supports link state tracking. */ 2563 ifp->if_capabilities |= IFCAP_LINKSTATE; 2564 ifp->if_capenable |= IFCAP_LINKSTATE; 2565 2566 /* Hook interrupt last to avoid having to lock softc */ 2567 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2568 NULL, ti_intr, sc, &sc->ti_intrhand); 2569 2570 if (error) { 2571 device_printf(dev, "couldn't set up irq\n"); 2572 goto fail; 2573 } 2574 2575 fail: 2576 if (error) 2577 ti_detach(dev); 2578 2579 return (error); 2580 } 2581 2582 /* 2583 * Shutdown hardware and free up resources. This can be called any 2584 * time after the mutex has been initialized. It is called in both 2585 * the error case in attach and the normal detach case so it needs 2586 * to be careful about only freeing resources that have actually been 2587 * allocated. 2588 */ 2589 static int 2590 ti_detach(device_t dev) 2591 { 2592 struct ti_softc *sc; 2593 struct ifnet *ifp; 2594 2595 sc = device_get_softc(dev); 2596 if (sc->dev) 2597 destroy_dev(sc->dev); 2598 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2599 ifp = sc->ti_ifp; 2600 if (device_is_attached(dev)) { 2601 ether_ifdetach(ifp); 2602 TI_LOCK(sc); 2603 ti_stop(sc); 2604 TI_UNLOCK(sc); 2605 } 2606 2607 /* These should only be active if attach succeeded */ 2608 callout_drain(&sc->ti_watchdog); 2609 bus_generic_detach(dev); 2610 ti_dma_free(sc); 2611 ifmedia_removeall(&sc->ifmedia); 2612 2613 if (sc->ti_intrhand) 2614 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2615 if (sc->ti_irq) 2616 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2617 if (sc->ti_res) { 2618 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2619 sc->ti_res); 2620 } 2621 if (ifp) 2622 if_free(ifp); 2623 if (sc->ti_membuf) 2624 free(sc->ti_membuf, M_DEVBUF); 2625 if (sc->ti_membuf2) 2626 free(sc->ti_membuf2, M_DEVBUF); 2627 2628 mtx_destroy(&sc->ti_mtx); 2629 2630 return (0); 2631 } 2632 2633 #ifdef TI_JUMBO_HDRSPLIT 2634 /* 2635 * If hdr_len is 0, that means that header splitting wasn't done on 2636 * this packet for some reason. The two most likely reasons are that 2637 * the protocol isn't a supported protocol for splitting, or this 2638 * packet had a fragment offset that wasn't 0. 2639 * 2640 * The header length, if it is non-zero, will always be the length of 2641 * the headers on the packet, but that length could be longer than the 2642 * first mbuf. So we take the minimum of the two as the actual 2643 * length. 2644 */ 2645 static __inline void 2646 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2647 { 2648 int i = 0; 2649 int lengths[4] = {0, 0, 0, 0}; 2650 struct mbuf *m, *mp; 2651 2652 if (hdr_len != 0) 2653 top->m_len = min(hdr_len, top->m_len); 2654 pkt_len -= top->m_len; 2655 lengths[i++] = top->m_len; 2656 2657 mp = top; 2658 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2659 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2660 pkt_len -= m->m_len; 2661 lengths[i++] = m->m_len; 2662 mp = m; 2663 } 2664 2665 #if 0 2666 if (hdr_len != 0) 2667 printf("got split packet: "); 2668 else 2669 printf("got non-split packet: "); 2670 2671 printf("%d,%d,%d,%d = %d\n", lengths[0], 2672 lengths[1], lengths[2], lengths[3], 2673 lengths[0] + lengths[1] + lengths[2] + 2674 lengths[3]); 2675 #endif 2676 2677 if (pkt_len) 2678 panic("header splitting didn't"); 2679 2680 if (m) { 2681 m_freem(m); 2682 mp->m_next = NULL; 2683 2684 } 2685 if (mp->m_next != NULL) 2686 panic("ti_hdr_split: last mbuf in chain should be null"); 2687 } 2688 #endif /* TI_JUMBO_HDRSPLIT */ 2689 2690 static void 2691 ti_discard_std(struct ti_softc *sc, int i) 2692 { 2693 2694 struct ti_rx_desc *r; 2695 2696 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2697 r->ti_len = MCLBYTES - ETHER_ALIGN; 2698 r->ti_type = TI_BDTYPE_RECV_BD; 2699 r->ti_flags = 0; 2700 r->ti_vlan_tag = 0; 2701 r->ti_tcp_udp_cksum = 0; 2702 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2703 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2704 r->ti_idx = i; 2705 } 2706 2707 static void 2708 ti_discard_mini(struct ti_softc *sc, int i) 2709 { 2710 2711 struct ti_rx_desc *r; 2712 2713 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2714 r->ti_len = MHLEN - ETHER_ALIGN; 2715 r->ti_type = TI_BDTYPE_RECV_BD; 2716 r->ti_flags = TI_BDFLAG_MINI_RING; 2717 r->ti_vlan_tag = 0; 2718 r->ti_tcp_udp_cksum = 0; 2719 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2720 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2721 r->ti_idx = i; 2722 } 2723 2724 #ifndef TI_SF_BUF_JUMBO 2725 static void 2726 ti_discard_jumbo(struct ti_softc *sc, int i) 2727 { 2728 2729 struct ti_rx_desc *r; 2730 2731 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2732 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2733 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2734 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2735 r->ti_vlan_tag = 0; 2736 r->ti_tcp_udp_cksum = 0; 2737 if (sc->ti_ifp->if_capenable & IFCAP_RXCSUM) 2738 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2739 r->ti_idx = i; 2740 } 2741 #endif 2742 2743 /* 2744 * Frame reception handling. This is called if there's a frame 2745 * on the receive return list. 2746 * 2747 * Note: we have to be able to handle three possibilities here: 2748 * 1) the frame is from the mini receive ring (can only happen) 2749 * on Tigon 2 boards) 2750 * 2) the frame is from the jumbo recieve ring 2751 * 3) the frame is from the standard receive ring 2752 */ 2753 2754 static void 2755 ti_rxeof(struct ti_softc *sc) 2756 { 2757 struct ifnet *ifp; 2758 #ifdef TI_SF_BUF_JUMBO 2759 bus_dmamap_t map; 2760 #endif 2761 struct ti_cmd_desc cmd; 2762 int jumbocnt, minicnt, stdcnt, ti_len; 2763 2764 TI_LOCK_ASSERT(sc); 2765 2766 ifp = sc->ti_ifp; 2767 2768 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2769 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2770 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2771 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2772 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2773 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2774 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2775 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2776 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2777 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2778 2779 jumbocnt = minicnt = stdcnt = 0; 2780 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2781 struct ti_rx_desc *cur_rx; 2782 uint32_t rxidx; 2783 struct mbuf *m = NULL; 2784 uint16_t vlan_tag = 0; 2785 int have_tag = 0; 2786 2787 cur_rx = 2788 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2789 rxidx = cur_rx->ti_idx; 2790 ti_len = cur_rx->ti_len; 2791 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2792 2793 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2794 have_tag = 1; 2795 vlan_tag = cur_rx->ti_vlan_tag; 2796 } 2797 2798 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2799 jumbocnt++; 2800 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2801 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2802 #ifndef TI_SF_BUF_JUMBO 2803 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2804 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2805 ti_discard_jumbo(sc, rxidx); 2806 continue; 2807 } 2808 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2809 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2810 ti_discard_jumbo(sc, rxidx); 2811 continue; 2812 } 2813 m->m_len = ti_len; 2814 #else /* !TI_SF_BUF_JUMBO */ 2815 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2816 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2817 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2818 BUS_DMASYNC_POSTREAD); 2819 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2820 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2821 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2822 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2823 continue; 2824 } 2825 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2826 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2827 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2828 continue; 2829 } 2830 #ifdef TI_JUMBO_HDRSPLIT 2831 if (sc->ti_hdrsplit) 2832 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2833 ti_len, rxidx); 2834 else 2835 #endif /* TI_JUMBO_HDRSPLIT */ 2836 m_adj(m, ti_len - m->m_pkthdr.len); 2837 #endif /* TI_SF_BUF_JUMBO */ 2838 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2839 minicnt++; 2840 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2841 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2842 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2843 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2844 ti_discard_mini(sc, rxidx); 2845 continue; 2846 } 2847 if (ti_newbuf_mini(sc, rxidx) != 0) { 2848 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2849 ti_discard_mini(sc, rxidx); 2850 continue; 2851 } 2852 m->m_len = ti_len; 2853 } else { 2854 stdcnt++; 2855 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2856 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2857 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2858 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2859 ti_discard_std(sc, rxidx); 2860 continue; 2861 } 2862 if (ti_newbuf_std(sc, rxidx) != 0) { 2863 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2864 ti_discard_std(sc, rxidx); 2865 continue; 2866 } 2867 m->m_len = ti_len; 2868 } 2869 2870 m->m_pkthdr.len = ti_len; 2871 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2872 m->m_pkthdr.rcvif = ifp; 2873 2874 if (ifp->if_capenable & IFCAP_RXCSUM) { 2875 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2876 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2877 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2878 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2879 } 2880 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2881 m->m_pkthdr.csum_data = 2882 cur_rx->ti_tcp_udp_cksum; 2883 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2884 } 2885 } 2886 2887 /* 2888 * If we received a packet with a vlan tag, 2889 * tag it before passing the packet upward. 2890 */ 2891 if (have_tag) { 2892 m->m_pkthdr.ether_vtag = vlan_tag; 2893 m->m_flags |= M_VLANTAG; 2894 } 2895 TI_UNLOCK(sc); 2896 (*ifp->if_input)(ifp, m); 2897 TI_LOCK(sc); 2898 } 2899 2900 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2901 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2902 /* Only necessary on the Tigon 1. */ 2903 if (sc->ti_hwrev == TI_HWREV_TIGON) 2904 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2905 sc->ti_rx_saved_considx); 2906 2907 if (stdcnt > 0) { 2908 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2909 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2910 TI_UPDATE_STDPROD(sc, sc->ti_std); 2911 } 2912 if (minicnt > 0) { 2913 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2914 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2915 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2916 } 2917 if (jumbocnt > 0) { 2918 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2919 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2920 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2921 } 2922 } 2923 2924 static void 2925 ti_txeof(struct ti_softc *sc) 2926 { 2927 struct ti_txdesc *txd; 2928 struct ti_tx_desc txdesc; 2929 struct ti_tx_desc *cur_tx = NULL; 2930 struct ifnet *ifp; 2931 int idx; 2932 2933 ifp = sc->ti_ifp; 2934 2935 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2936 if (txd == NULL) 2937 return; 2938 2939 if (sc->ti_rdata.ti_tx_ring != NULL) 2940 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2941 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2942 /* 2943 * Go through our tx ring and free mbufs for those 2944 * frames that have been sent. 2945 */ 2946 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2947 TI_INC(idx, TI_TX_RING_CNT)) { 2948 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2949 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2950 sizeof(txdesc), &txdesc); 2951 cur_tx = &txdesc; 2952 } else 2953 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2954 sc->ti_txcnt--; 2955 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2956 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2957 continue; 2958 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2959 BUS_DMASYNC_POSTWRITE); 2960 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2961 2962 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2963 m_freem(txd->tx_m); 2964 txd->tx_m = NULL; 2965 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2966 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2967 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2968 } 2969 sc->ti_tx_saved_considx = idx; 2970 if (sc->ti_txcnt == 0) 2971 sc->ti_timer = 0; 2972 } 2973 2974 static void 2975 ti_intr(void *xsc) 2976 { 2977 struct ti_softc *sc; 2978 struct ifnet *ifp; 2979 2980 sc = xsc; 2981 TI_LOCK(sc); 2982 ifp = sc->ti_ifp; 2983 2984 /* Make sure this is really our interrupt. */ 2985 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2986 TI_UNLOCK(sc); 2987 return; 2988 } 2989 2990 /* Ack interrupt and stop others from occuring. */ 2991 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2992 2993 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2994 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2995 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2996 /* Check RX return ring producer/consumer */ 2997 ti_rxeof(sc); 2998 2999 /* Check TX ring producer/consumer */ 3000 ti_txeof(sc); 3001 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 3002 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 3003 } 3004 3005 ti_handle_events(sc); 3006 3007 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3008 /* Re-enable interrupts. */ 3009 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3010 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3011 ti_start_locked(ifp); 3012 } 3013 3014 TI_UNLOCK(sc); 3015 } 3016 3017 static uint64_t 3018 ti_get_counter(struct ifnet *ifp, ift_counter cnt) 3019 { 3020 3021 switch (cnt) { 3022 case IFCOUNTER_COLLISIONS: 3023 { 3024 struct ti_softc *sc; 3025 struct ti_stats *s; 3026 uint64_t rv; 3027 3028 sc = if_getsoftc(ifp); 3029 s = &sc->ti_rdata.ti_info->ti_stats; 3030 3031 TI_LOCK(sc); 3032 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3033 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3034 rv = s->dot3StatsSingleCollisionFrames + 3035 s->dot3StatsMultipleCollisionFrames + 3036 s->dot3StatsExcessiveCollisions + 3037 s->dot3StatsLateCollisions; 3038 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3039 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3040 TI_UNLOCK(sc); 3041 return (rv); 3042 } 3043 default: 3044 return (if_get_counter_default(ifp, cnt)); 3045 } 3046 } 3047 3048 /* 3049 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3050 * pointers to descriptors. 3051 */ 3052 static int 3053 ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3054 { 3055 struct ti_txdesc *txd; 3056 struct ti_tx_desc *f; 3057 struct ti_tx_desc txdesc; 3058 struct mbuf *m; 3059 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3060 uint16_t csum_flags; 3061 int error, frag, i, nseg; 3062 3063 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3064 return (ENOBUFS); 3065 3066 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3067 *m_head, txsegs, &nseg, 0); 3068 if (error == EFBIG) { 3069 m = m_defrag(*m_head, M_NOWAIT); 3070 if (m == NULL) { 3071 m_freem(*m_head); 3072 *m_head = NULL; 3073 return (ENOMEM); 3074 } 3075 *m_head = m; 3076 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3077 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3078 if (error) { 3079 m_freem(*m_head); 3080 *m_head = NULL; 3081 return (error); 3082 } 3083 } else if (error != 0) 3084 return (error); 3085 if (nseg == 0) { 3086 m_freem(*m_head); 3087 *m_head = NULL; 3088 return (EIO); 3089 } 3090 3091 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3092 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3093 return (ENOBUFS); 3094 } 3095 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3096 BUS_DMASYNC_PREWRITE); 3097 3098 m = *m_head; 3099 csum_flags = 0; 3100 if (m->m_pkthdr.csum_flags & CSUM_IP) 3101 csum_flags |= TI_BDFLAG_IP_CKSUM; 3102 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3103 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3104 3105 frag = sc->ti_tx_saved_prodidx; 3106 for (i = 0; i < nseg; i++) { 3107 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3108 bzero(&txdesc, sizeof(txdesc)); 3109 f = &txdesc; 3110 } else 3111 f = &sc->ti_rdata.ti_tx_ring[frag]; 3112 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3113 f->ti_len = txsegs[i].ds_len; 3114 f->ti_flags = csum_flags; 3115 if (m->m_flags & M_VLANTAG) { 3116 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3117 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3118 } else { 3119 f->ti_vlan_tag = 0; 3120 } 3121 3122 if (sc->ti_hwrev == TI_HWREV_TIGON) 3123 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3124 sizeof(txdesc), sizeof(txdesc), &txdesc); 3125 TI_INC(frag, TI_TX_RING_CNT); 3126 } 3127 3128 sc->ti_tx_saved_prodidx = frag; 3129 /* set TI_BDFLAG_END on the last descriptor */ 3130 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3131 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3132 txdesc.ti_flags |= TI_BDFLAG_END; 3133 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3134 sizeof(txdesc), &txdesc); 3135 } else 3136 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3137 3138 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3139 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3140 txd->tx_m = m; 3141 sc->ti_txcnt += nseg; 3142 3143 return (0); 3144 } 3145 3146 static void 3147 ti_start(struct ifnet *ifp) 3148 { 3149 struct ti_softc *sc; 3150 3151 sc = ifp->if_softc; 3152 TI_LOCK(sc); 3153 ti_start_locked(ifp); 3154 TI_UNLOCK(sc); 3155 } 3156 3157 /* 3158 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3159 * to the mbuf data regions directly in the transmit descriptors. 3160 */ 3161 static void 3162 ti_start_locked(struct ifnet *ifp) 3163 { 3164 struct ti_softc *sc; 3165 struct mbuf *m_head = NULL; 3166 int enq = 0; 3167 3168 sc = ifp->if_softc; 3169 3170 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 3171 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3172 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3173 if (m_head == NULL) 3174 break; 3175 3176 /* 3177 * Pack the data into the transmit ring. If we 3178 * don't have room, set the OACTIVE flag and wait 3179 * for the NIC to drain the ring. 3180 */ 3181 if (ti_encap(sc, &m_head)) { 3182 if (m_head == NULL) 3183 break; 3184 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3185 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3186 break; 3187 } 3188 3189 enq++; 3190 /* 3191 * If there's a BPF listener, bounce a copy of this frame 3192 * to him. 3193 */ 3194 ETHER_BPF_MTAP(ifp, m_head); 3195 } 3196 3197 if (enq > 0) { 3198 if (sc->ti_rdata.ti_tx_ring != NULL) 3199 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3200 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3201 /* Transmit */ 3202 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3203 3204 /* 3205 * Set a timeout in case the chip goes out to lunch. 3206 */ 3207 sc->ti_timer = 5; 3208 } 3209 } 3210 3211 static void 3212 ti_init(void *xsc) 3213 { 3214 struct ti_softc *sc; 3215 3216 sc = xsc; 3217 TI_LOCK(sc); 3218 ti_init_locked(sc); 3219 TI_UNLOCK(sc); 3220 } 3221 3222 static void 3223 ti_init_locked(void *xsc) 3224 { 3225 struct ti_softc *sc = xsc; 3226 3227 if (sc->ti_ifp->if_drv_flags & IFF_DRV_RUNNING) 3228 return; 3229 3230 /* Cancel pending I/O and flush buffers. */ 3231 ti_stop(sc); 3232 3233 /* Init the gen info block, ring control blocks and firmware. */ 3234 if (ti_gibinit(sc)) { 3235 device_printf(sc->ti_dev, "initialization failure\n"); 3236 return; 3237 } 3238 } 3239 3240 static void ti_init2(struct ti_softc *sc) 3241 { 3242 struct ti_cmd_desc cmd; 3243 struct ifnet *ifp; 3244 uint8_t *ea; 3245 struct ifmedia *ifm; 3246 int tmp; 3247 3248 TI_LOCK_ASSERT(sc); 3249 3250 ifp = sc->ti_ifp; 3251 3252 /* Specify MTU and interface index. */ 3253 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3254 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3255 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3256 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3257 3258 /* Load our MAC address. */ 3259 ea = IF_LLADDR(sc->ti_ifp); 3260 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3261 CSR_WRITE_4(sc, TI_GCR_PAR1, 3262 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3263 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3264 3265 /* Enable or disable promiscuous mode as needed. */ 3266 if (ifp->if_flags & IFF_PROMISC) { 3267 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3268 } else { 3269 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3270 } 3271 3272 /* Program multicast filter. */ 3273 ti_setmulti(sc); 3274 3275 /* 3276 * If this is a Tigon 1, we should tell the 3277 * firmware to use software packet filtering. 3278 */ 3279 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3280 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3281 } 3282 3283 /* Init RX ring. */ 3284 if (ti_init_rx_ring_std(sc) != 0) { 3285 /* XXX */ 3286 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3287 return; 3288 } 3289 3290 /* Init jumbo RX ring. */ 3291 if (ifp->if_mtu > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3292 if (ti_init_rx_ring_jumbo(sc) != 0) { 3293 /* XXX */ 3294 device_printf(sc->ti_dev, 3295 "no memory for jumbo Rx buffers.\n"); 3296 return; 3297 } 3298 } 3299 3300 /* 3301 * If this is a Tigon 2, we can also configure the 3302 * mini ring. 3303 */ 3304 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3305 if (ti_init_rx_ring_mini(sc) != 0) { 3306 /* XXX */ 3307 device_printf(sc->ti_dev, 3308 "no memory for mini Rx buffers.\n"); 3309 return; 3310 } 3311 } 3312 3313 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3314 sc->ti_rx_saved_considx = 0; 3315 3316 /* Init TX ring. */ 3317 ti_init_tx_ring(sc); 3318 3319 /* Tell firmware we're alive. */ 3320 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3321 3322 /* Enable host interrupts. */ 3323 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3324 3325 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3326 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3327 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3328 3329 /* 3330 * Make sure to set media properly. We have to do this 3331 * here since we have to issue commands in order to set 3332 * the link negotiation and we can't issue commands until 3333 * the firmware is running. 3334 */ 3335 ifm = &sc->ifmedia; 3336 tmp = ifm->ifm_media; 3337 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3338 ti_ifmedia_upd_locked(sc); 3339 ifm->ifm_media = tmp; 3340 } 3341 3342 /* 3343 * Set media options. 3344 */ 3345 static int 3346 ti_ifmedia_upd(struct ifnet *ifp) 3347 { 3348 struct ti_softc *sc; 3349 int error; 3350 3351 sc = ifp->if_softc; 3352 TI_LOCK(sc); 3353 error = ti_ifmedia_upd_locked(sc); 3354 TI_UNLOCK(sc); 3355 3356 return (error); 3357 } 3358 3359 static int 3360 ti_ifmedia_upd_locked(struct ti_softc *sc) 3361 { 3362 struct ifmedia *ifm; 3363 struct ti_cmd_desc cmd; 3364 uint32_t flowctl; 3365 3366 ifm = &sc->ifmedia; 3367 3368 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3369 return (EINVAL); 3370 3371 flowctl = 0; 3372 3373 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3374 case IFM_AUTO: 3375 /* 3376 * Transmit flow control doesn't work on the Tigon 1. 3377 */ 3378 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3379 3380 /* 3381 * Transmit flow control can also cause problems on the 3382 * Tigon 2, apparantly with both the copper and fiber 3383 * boards. The symptom is that the interface will just 3384 * hang. This was reproduced with Alteon 180 switches. 3385 */ 3386 #if 0 3387 if (sc->ti_hwrev != TI_HWREV_TIGON) 3388 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3389 #endif 3390 3391 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3392 TI_GLNK_FULL_DUPLEX| flowctl | 3393 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3394 3395 flowctl = TI_LNK_RX_FLOWCTL_Y; 3396 #if 0 3397 if (sc->ti_hwrev != TI_HWREV_TIGON) 3398 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3399 #endif 3400 3401 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3402 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3403 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3404 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3405 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3406 break; 3407 case IFM_1000_SX: 3408 case IFM_1000_T: 3409 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3410 #if 0 3411 if (sc->ti_hwrev != TI_HWREV_TIGON) 3412 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3413 #endif 3414 3415 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3416 flowctl |TI_GLNK_ENB); 3417 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3418 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3419 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3420 } 3421 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3422 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3423 break; 3424 case IFM_100_FX: 3425 case IFM_10_FL: 3426 case IFM_100_TX: 3427 case IFM_10_T: 3428 flowctl = TI_LNK_RX_FLOWCTL_Y; 3429 #if 0 3430 if (sc->ti_hwrev != TI_HWREV_TIGON) 3431 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3432 #endif 3433 3434 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3435 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3436 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3437 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3438 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3439 } else { 3440 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3441 } 3442 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3443 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3444 } else { 3445 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3446 } 3447 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3448 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3449 break; 3450 } 3451 3452 return (0); 3453 } 3454 3455 /* 3456 * Report current media status. 3457 */ 3458 static void 3459 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3460 { 3461 struct ti_softc *sc; 3462 uint32_t media = 0; 3463 3464 sc = ifp->if_softc; 3465 3466 TI_LOCK(sc); 3467 3468 ifmr->ifm_status = IFM_AVALID; 3469 ifmr->ifm_active = IFM_ETHER; 3470 3471 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3472 TI_UNLOCK(sc); 3473 return; 3474 } 3475 3476 ifmr->ifm_status |= IFM_ACTIVE; 3477 3478 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3479 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3480 if (sc->ti_copper) 3481 ifmr->ifm_active |= IFM_1000_T; 3482 else 3483 ifmr->ifm_active |= IFM_1000_SX; 3484 if (media & TI_GLNK_FULL_DUPLEX) 3485 ifmr->ifm_active |= IFM_FDX; 3486 else 3487 ifmr->ifm_active |= IFM_HDX; 3488 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3489 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3490 if (sc->ti_copper) { 3491 if (media & TI_LNK_100MB) 3492 ifmr->ifm_active |= IFM_100_TX; 3493 if (media & TI_LNK_10MB) 3494 ifmr->ifm_active |= IFM_10_T; 3495 } else { 3496 if (media & TI_LNK_100MB) 3497 ifmr->ifm_active |= IFM_100_FX; 3498 if (media & TI_LNK_10MB) 3499 ifmr->ifm_active |= IFM_10_FL; 3500 } 3501 if (media & TI_LNK_FULL_DUPLEX) 3502 ifmr->ifm_active |= IFM_FDX; 3503 if (media & TI_LNK_HALF_DUPLEX) 3504 ifmr->ifm_active |= IFM_HDX; 3505 } 3506 TI_UNLOCK(sc); 3507 } 3508 3509 static int 3510 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3511 { 3512 struct ti_softc *sc = ifp->if_softc; 3513 struct ifreq *ifr = (struct ifreq *) data; 3514 struct ti_cmd_desc cmd; 3515 int mask, error = 0; 3516 3517 switch (command) { 3518 case SIOCSIFMTU: 3519 TI_LOCK(sc); 3520 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3521 error = EINVAL; 3522 else { 3523 ifp->if_mtu = ifr->ifr_mtu; 3524 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3525 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3526 ti_init_locked(sc); 3527 } 3528 } 3529 TI_UNLOCK(sc); 3530 break; 3531 case SIOCSIFFLAGS: 3532 TI_LOCK(sc); 3533 if (ifp->if_flags & IFF_UP) { 3534 /* 3535 * If only the state of the PROMISC flag changed, 3536 * then just use the 'set promisc mode' command 3537 * instead of reinitializing the entire NIC. Doing 3538 * a full re-init means reloading the firmware and 3539 * waiting for it to start up, which may take a 3540 * second or two. 3541 */ 3542 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3543 ifp->if_flags & IFF_PROMISC && 3544 !(sc->ti_if_flags & IFF_PROMISC)) { 3545 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3546 TI_CMD_CODE_PROMISC_ENB, 0); 3547 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3548 !(ifp->if_flags & IFF_PROMISC) && 3549 sc->ti_if_flags & IFF_PROMISC) { 3550 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3551 TI_CMD_CODE_PROMISC_DIS, 0); 3552 } else 3553 ti_init_locked(sc); 3554 } else { 3555 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3556 ti_stop(sc); 3557 } 3558 } 3559 sc->ti_if_flags = ifp->if_flags; 3560 TI_UNLOCK(sc); 3561 break; 3562 case SIOCADDMULTI: 3563 case SIOCDELMULTI: 3564 TI_LOCK(sc); 3565 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3566 ti_setmulti(sc); 3567 TI_UNLOCK(sc); 3568 break; 3569 case SIOCSIFMEDIA: 3570 case SIOCGIFMEDIA: 3571 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3572 break; 3573 case SIOCSIFCAP: 3574 TI_LOCK(sc); 3575 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3576 if ((mask & IFCAP_TXCSUM) != 0 && 3577 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3578 ifp->if_capenable ^= IFCAP_TXCSUM; 3579 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3580 ifp->if_hwassist |= TI_CSUM_FEATURES; 3581 else 3582 ifp->if_hwassist &= ~TI_CSUM_FEATURES; 3583 } 3584 if ((mask & IFCAP_RXCSUM) != 0 && 3585 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3586 ifp->if_capenable ^= IFCAP_RXCSUM; 3587 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3588 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) 3589 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3590 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3591 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3592 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3593 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3594 IFCAP_VLAN_HWTAGGING)) != 0) { 3595 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3596 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3597 ti_init_locked(sc); 3598 } 3599 } 3600 TI_UNLOCK(sc); 3601 VLAN_CAPABILITIES(ifp); 3602 break; 3603 default: 3604 error = ether_ioctl(ifp, command, data); 3605 break; 3606 } 3607 3608 return (error); 3609 } 3610 3611 static int 3612 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3613 { 3614 struct ti_softc *sc; 3615 3616 sc = dev->si_drv1; 3617 if (sc == NULL) 3618 return (ENODEV); 3619 3620 TI_LOCK(sc); 3621 sc->ti_flags |= TI_FLAG_DEBUGING; 3622 TI_UNLOCK(sc); 3623 3624 return (0); 3625 } 3626 3627 static int 3628 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3629 { 3630 struct ti_softc *sc; 3631 3632 sc = dev->si_drv1; 3633 if (sc == NULL) 3634 return (ENODEV); 3635 3636 TI_LOCK(sc); 3637 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3638 TI_UNLOCK(sc); 3639 3640 return (0); 3641 } 3642 3643 /* 3644 * This ioctl routine goes along with the Tigon character device. 3645 */ 3646 static int 3647 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3648 struct thread *td) 3649 { 3650 struct ti_softc *sc; 3651 int error; 3652 3653 sc = dev->si_drv1; 3654 if (sc == NULL) 3655 return (ENODEV); 3656 3657 error = 0; 3658 3659 switch (cmd) { 3660 case TIIOCGETSTATS: 3661 { 3662 struct ti_stats *outstats; 3663 3664 outstats = (struct ti_stats *)addr; 3665 3666 TI_LOCK(sc); 3667 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3668 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3669 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3670 sizeof(struct ti_stats)); 3671 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3672 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3673 TI_UNLOCK(sc); 3674 break; 3675 } 3676 case TIIOCGETPARAMS: 3677 { 3678 struct ti_params *params; 3679 3680 params = (struct ti_params *)addr; 3681 3682 TI_LOCK(sc); 3683 params->ti_stat_ticks = sc->ti_stat_ticks; 3684 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3685 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3686 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3687 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3688 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3689 params->param_mask = TI_PARAM_ALL; 3690 TI_UNLOCK(sc); 3691 break; 3692 } 3693 case TIIOCSETPARAMS: 3694 { 3695 struct ti_params *params; 3696 3697 params = (struct ti_params *)addr; 3698 3699 TI_LOCK(sc); 3700 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3701 sc->ti_stat_ticks = params->ti_stat_ticks; 3702 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3703 } 3704 3705 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3706 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3707 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3708 sc->ti_rx_coal_ticks); 3709 } 3710 3711 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3712 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3713 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3714 sc->ti_tx_coal_ticks); 3715 } 3716 3717 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3718 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3719 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3720 sc->ti_rx_max_coal_bds); 3721 } 3722 3723 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3724 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3725 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3726 sc->ti_tx_max_coal_bds); 3727 } 3728 3729 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3730 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3731 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3732 sc->ti_tx_buf_ratio); 3733 } 3734 TI_UNLOCK(sc); 3735 break; 3736 } 3737 case TIIOCSETTRACE: { 3738 ti_trace_type trace_type; 3739 3740 trace_type = *(ti_trace_type *)addr; 3741 3742 /* 3743 * Set tracing to whatever the user asked for. Setting 3744 * this register to 0 should have the effect of disabling 3745 * tracing. 3746 */ 3747 TI_LOCK(sc); 3748 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3749 TI_UNLOCK(sc); 3750 break; 3751 } 3752 case TIIOCGETTRACE: { 3753 struct ti_trace_buf *trace_buf; 3754 uint32_t trace_start, cur_trace_ptr, trace_len; 3755 3756 trace_buf = (struct ti_trace_buf *)addr; 3757 3758 TI_LOCK(sc); 3759 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3760 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3761 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3762 #if 0 3763 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3764 "trace_len = %d\n", trace_start, 3765 cur_trace_ptr, trace_len); 3766 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3767 trace_buf->buf_len); 3768 #endif 3769 error = ti_copy_mem(sc, trace_start, min(trace_len, 3770 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3771 if (error == 0) { 3772 trace_buf->fill_len = min(trace_len, 3773 trace_buf->buf_len); 3774 if (cur_trace_ptr < trace_start) 3775 trace_buf->cur_trace_ptr = 3776 trace_start - cur_trace_ptr; 3777 else 3778 trace_buf->cur_trace_ptr = 3779 cur_trace_ptr - trace_start; 3780 } else 3781 trace_buf->fill_len = 0; 3782 TI_UNLOCK(sc); 3783 break; 3784 } 3785 3786 /* 3787 * For debugging, five ioctls are needed: 3788 * ALT_ATTACH 3789 * ALT_READ_TG_REG 3790 * ALT_WRITE_TG_REG 3791 * ALT_READ_TG_MEM 3792 * ALT_WRITE_TG_MEM 3793 */ 3794 case ALT_ATTACH: 3795 /* 3796 * From what I can tell, Alteon's Solaris Tigon driver 3797 * only has one character device, so you have to attach 3798 * to the Tigon board you're interested in. This seems 3799 * like a not-so-good way to do things, since unless you 3800 * subsequently specify the unit number of the device 3801 * you're interested in every ioctl, you'll only be 3802 * able to debug one board at a time. 3803 */ 3804 break; 3805 case ALT_READ_TG_MEM: 3806 case ALT_WRITE_TG_MEM: 3807 { 3808 struct tg_mem *mem_param; 3809 uint32_t sram_end, scratch_end; 3810 3811 mem_param = (struct tg_mem *)addr; 3812 3813 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3814 sram_end = TI_END_SRAM_I; 3815 scratch_end = TI_END_SCRATCH_I; 3816 } else { 3817 sram_end = TI_END_SRAM_II; 3818 scratch_end = TI_END_SCRATCH_II; 3819 } 3820 3821 /* 3822 * For now, we'll only handle accessing regular SRAM, 3823 * nothing else. 3824 */ 3825 TI_LOCK(sc); 3826 if (mem_param->tgAddr >= TI_BEG_SRAM && 3827 mem_param->tgAddr + mem_param->len <= sram_end) { 3828 /* 3829 * In this instance, we always copy to/from user 3830 * space, so the user space argument is set to 1. 3831 */ 3832 error = ti_copy_mem(sc, mem_param->tgAddr, 3833 mem_param->len, mem_param->userAddr, 1, 3834 cmd == ALT_READ_TG_MEM ? 1 : 0); 3835 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3836 mem_param->tgAddr <= scratch_end) { 3837 error = ti_copy_scratch(sc, mem_param->tgAddr, 3838 mem_param->len, mem_param->userAddr, 1, 3839 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3840 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3841 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3842 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3843 if_printf(sc->ti_ifp, 3844 "invalid memory range for Tigon I\n"); 3845 error = EINVAL; 3846 break; 3847 } 3848 error = ti_copy_scratch(sc, mem_param->tgAddr - 3849 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3850 mem_param->userAddr, 1, 3851 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3852 } else { 3853 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3854 "out of supported range\n", 3855 mem_param->tgAddr, mem_param->len); 3856 error = EINVAL; 3857 } 3858 TI_UNLOCK(sc); 3859 break; 3860 } 3861 case ALT_READ_TG_REG: 3862 case ALT_WRITE_TG_REG: 3863 { 3864 struct tg_reg *regs; 3865 uint32_t tmpval; 3866 3867 regs = (struct tg_reg *)addr; 3868 3869 /* 3870 * Make sure the address in question isn't out of range. 3871 */ 3872 if (regs->addr > TI_REG_MAX) { 3873 error = EINVAL; 3874 break; 3875 } 3876 TI_LOCK(sc); 3877 if (cmd == ALT_READ_TG_REG) { 3878 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3879 regs->addr, &tmpval, 1); 3880 regs->data = ntohl(tmpval); 3881 #if 0 3882 if ((regs->addr == TI_CPU_STATE) 3883 || (regs->addr == TI_CPU_CTL_B)) { 3884 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3885 regs->addr, tmpval); 3886 } 3887 #endif 3888 } else { 3889 tmpval = htonl(regs->data); 3890 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3891 regs->addr, &tmpval, 1); 3892 } 3893 TI_UNLOCK(sc); 3894 break; 3895 } 3896 default: 3897 error = ENOTTY; 3898 break; 3899 } 3900 return (error); 3901 } 3902 3903 static void 3904 ti_watchdog(void *arg) 3905 { 3906 struct ti_softc *sc; 3907 struct ifnet *ifp; 3908 3909 sc = arg; 3910 TI_LOCK_ASSERT(sc); 3911 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3912 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3913 return; 3914 3915 /* 3916 * When we're debugging, the chip is often stopped for long periods 3917 * of time, and that would normally cause the watchdog timer to fire. 3918 * Since that impedes debugging, we don't want to do that. 3919 */ 3920 if (sc->ti_flags & TI_FLAG_DEBUGING) 3921 return; 3922 3923 ifp = sc->ti_ifp; 3924 if_printf(ifp, "watchdog timeout -- resetting\n"); 3925 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3926 ti_init_locked(sc); 3927 3928 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3929 } 3930 3931 /* 3932 * Stop the adapter and free any mbufs allocated to the 3933 * RX and TX lists. 3934 */ 3935 static void 3936 ti_stop(struct ti_softc *sc) 3937 { 3938 struct ifnet *ifp; 3939 struct ti_cmd_desc cmd; 3940 3941 TI_LOCK_ASSERT(sc); 3942 3943 ifp = sc->ti_ifp; 3944 3945 /* Disable host interrupts. */ 3946 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3947 /* 3948 * Tell firmware we're shutting down. 3949 */ 3950 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3951 3952 /* Halt and reinitialize. */ 3953 if (ti_chipinit(sc) == 0) { 3954 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3955 /* XXX ignore init errors. */ 3956 ti_chipinit(sc); 3957 } 3958 3959 /* Free the RX lists. */ 3960 ti_free_rx_ring_std(sc); 3961 3962 /* Free jumbo RX list. */ 3963 ti_free_rx_ring_jumbo(sc); 3964 3965 /* Free mini RX list. */ 3966 ti_free_rx_ring_mini(sc); 3967 3968 /* Free TX buffers. */ 3969 ti_free_tx_ring(sc); 3970 3971 sc->ti_ev_prodidx.ti_idx = 0; 3972 sc->ti_return_prodidx.ti_idx = 0; 3973 sc->ti_tx_considx.ti_idx = 0; 3974 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3975 3976 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3977 callout_stop(&sc->ti_watchdog); 3978 } 3979 3980 /* 3981 * Stop all chip I/O so that the kernel's probe routines don't 3982 * get confused by errant DMAs when rebooting. 3983 */ 3984 static int 3985 ti_shutdown(device_t dev) 3986 { 3987 struct ti_softc *sc; 3988 3989 sc = device_get_softc(dev); 3990 TI_LOCK(sc); 3991 ti_chipinit(sc); 3992 TI_UNLOCK(sc); 3993 3994 return (0); 3995 } 3996 3997 static void 3998 ti_sysctl_node(struct ti_softc *sc) 3999 { 4000 struct sysctl_ctx_list *ctx; 4001 struct sysctl_oid_list *child; 4002 char tname[32]; 4003 4004 ctx = device_get_sysctl_ctx(sc->ti_dev); 4005 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 4006 4007 /* Use DAC */ 4008 sc->ti_dac = 1; 4009 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 4010 device_get_unit(sc->ti_dev)); 4011 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 4012 4013 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 4014 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4015 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4016 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4017 4018 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4019 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4020 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4021 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4022 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4023 &sc->ti_tx_buf_ratio, 0, 4024 "Ratio of NIC memory devoted to TX buffer"); 4025 4026 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4027 &sc->ti_stat_ticks, 0, 4028 "Number of clock ticks for statistics update interval"); 4029 4030 /* Pull in device tunables. */ 4031 sc->ti_rx_coal_ticks = 170; 4032 resource_int_value(device_get_name(sc->ti_dev), 4033 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4034 &sc->ti_rx_coal_ticks); 4035 sc->ti_rx_max_coal_bds = 64; 4036 resource_int_value(device_get_name(sc->ti_dev), 4037 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4038 &sc->ti_rx_max_coal_bds); 4039 4040 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4041 resource_int_value(device_get_name(sc->ti_dev), 4042 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4043 &sc->ti_tx_coal_ticks); 4044 sc->ti_tx_max_coal_bds = 32; 4045 resource_int_value(device_get_name(sc->ti_dev), 4046 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4047 &sc->ti_tx_max_coal_bds); 4048 sc->ti_tx_buf_ratio = 21; 4049 resource_int_value(device_get_name(sc->ti_dev), 4050 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4051 &sc->ti_tx_buf_ratio); 4052 4053 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4054 resource_int_value(device_get_name(sc->ti_dev), 4055 device_get_unit(sc->ti_dev), "stat_ticks", 4056 &sc->ti_stat_ticks); 4057 } 4058