1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 35 * Manuals, sample driver and firmware source kits are available 36 * from http://www.alteon.com/support/openkits. 37 * 38 * Written by Bill Paul <wpaul@ctr.columbia.edu> 39 * Electrical Engineering Department 40 * Columbia University, New York City 41 */ 42 43 /* 44 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 45 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 46 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 47 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 48 * filtering and jumbo (9014 byte) frames. The hardware is largely 49 * controlled by firmware, which must be loaded into the NIC during 50 * initialization. 51 * 52 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 53 * revision, which supports new features such as extended commands, 54 * extended jumbo receive ring desciptors and a mini receive ring. 55 * 56 * Alteon Networks is to be commended for releasing such a vast amount 57 * of development material for the Tigon NIC without requiring an NDA 58 * (although they really should have done it a long time ago). With 59 * any luck, the other vendors will finally wise up and follow Alteon's 60 * stellar example. 61 * 62 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 63 * this driver by #including it as a C header file. This bloats the 64 * driver somewhat, but it's the easiest method considering that the 65 * driver code and firmware code need to be kept in sync. The source 66 * for the firmware is not provided with the FreeBSD distribution since 67 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 68 * 69 * The following people deserve special thanks: 70 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 71 * for testing 72 * - Raymond Lee of Netgear, for providing a pair of Netgear 73 * GA620 Tigon 2 boards for testing 74 * - Ulf Zimmermann, for bringing the GA260 to my attention and 75 * convincing me to write this driver. 76 * - Andrew Gallatin for providing FreeBSD/Alpha support. 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #include "opt_ti.h" 83 84 #include <sys/param.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/module.h> 91 #include <sys/socket.h> 92 #include <sys/queue.h> 93 #include <sys/conf.h> 94 #include <sys/sf_buf.h> 95 96 #include <net/if.h> 97 #include <net/if_arp.h> 98 #include <net/ethernet.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_types.h> 102 #include <net/if_vlan_var.h> 103 104 #include <net/bpf.h> 105 106 #include <netinet/in_systm.h> 107 #include <netinet/in.h> 108 #include <netinet/ip.h> 109 110 #include <machine/bus.h> 111 #include <machine/resource.h> 112 #include <sys/bus.h> 113 #include <sys/rman.h> 114 115 /* #define TI_PRIVATE_JUMBOS */ 116 #ifndef TI_PRIVATE_JUMBOS 117 #include <vm/vm.h> 118 #include <vm/vm_page.h> 119 #endif 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 124 #include <sys/tiio.h> 125 #include <dev/ti/if_tireg.h> 126 #include <dev/ti/ti_fw.h> 127 #include <dev/ti/ti_fw2.h> 128 129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 130 /* 131 * We can only turn on header splitting if we're using extended receive 132 * BDs. 133 */ 134 #if defined(TI_JUMBO_HDRSPLIT) && defined(TI_PRIVATE_JUMBOS) 135 #error "options TI_JUMBO_HDRSPLIT and TI_PRIVATE_JUMBOS are mutually exclusive" 136 #endif /* TI_JUMBO_HDRSPLIT && TI_JUMBO_HDRSPLIT */ 137 138 typedef enum { 139 TI_SWAP_HTON, 140 TI_SWAP_NTOH 141 } ti_swap_type; 142 143 144 /* 145 * Various supported device vendors/types and their names. 146 */ 147 148 static struct ti_type ti_devs[] = { 149 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 150 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 151 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 152 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 153 { TC_VENDORID, TC_DEVICEID_3C985, 154 "3Com 3c985-SX Gigabit Ethernet" }, 155 { NG_VENDORID, NG_DEVICEID_GA620, 156 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 157 { NG_VENDORID, NG_DEVICEID_GA620T, 158 "Netgear GA620 1000baseT Gigabit Ethernet" }, 159 { SGI_VENDORID, SGI_DEVICEID_TIGON, 160 "Silicon Graphics Gigabit Ethernet" }, 161 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 162 "Farallon PN9000SX Gigabit Ethernet" }, 163 { 0, 0, NULL } 164 }; 165 166 167 static d_open_t ti_open; 168 static d_close_t ti_close; 169 static d_ioctl_t ti_ioctl2; 170 171 static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178 }; 179 180 static int ti_probe(device_t); 181 static int ti_attach(device_t); 182 static int ti_detach(device_t); 183 static void ti_txeof(struct ti_softc *); 184 static void ti_rxeof(struct ti_softc *); 185 186 static void ti_stats_update(struct ti_softc *); 187 static int ti_encap(struct ti_softc *, struct mbuf **); 188 189 static void ti_intr(void *); 190 static void ti_start(struct ifnet *); 191 static void ti_start_locked(struct ifnet *); 192 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 193 static void ti_init(void *); 194 static void ti_init_locked(void *); 195 static void ti_init2(struct ti_softc *); 196 static void ti_stop(struct ti_softc *); 197 static void ti_watchdog(void *); 198 static int ti_shutdown(device_t); 199 static int ti_ifmedia_upd(struct ifnet *); 200 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 201 202 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 203 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 204 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 205 206 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 207 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 208 static void ti_setmulti(struct ti_softc *); 209 210 static void ti_mem_read(struct ti_softc *, u_int32_t, u_int32_t, void *); 211 static void ti_mem_write(struct ti_softc *, u_int32_t, u_int32_t, void *); 212 static void ti_mem_zero(struct ti_softc *, u_int32_t, u_int32_t); 213 static int ti_copy_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, int, int); 214 static int ti_copy_scratch(struct ti_softc *, u_int32_t, u_int32_t, caddr_t, 215 int, int, int); 216 static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 217 static void ti_loadfw(struct ti_softc *); 218 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 219 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 220 static void ti_handle_events(struct ti_softc *); 221 static int ti_alloc_dmamaps(struct ti_softc *); 222 static void ti_free_dmamaps(struct ti_softc *); 223 static int ti_alloc_jumbo_mem(struct ti_softc *); 224 #ifdef TI_PRIVATE_JUMBOS 225 static void *ti_jalloc(struct ti_softc *); 226 static void ti_jfree(void *, void *); 227 #endif /* TI_PRIVATE_JUMBOS */ 228 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *); 229 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *); 230 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 231 static int ti_init_rx_ring_std(struct ti_softc *); 232 static void ti_free_rx_ring_std(struct ti_softc *); 233 static int ti_init_rx_ring_jumbo(struct ti_softc *); 234 static void ti_free_rx_ring_jumbo(struct ti_softc *); 235 static int ti_init_rx_ring_mini(struct ti_softc *); 236 static void ti_free_rx_ring_mini(struct ti_softc *); 237 static void ti_free_tx_ring(struct ti_softc *); 238 static int ti_init_tx_ring(struct ti_softc *); 239 240 static int ti_64bitslot_war(struct ti_softc *); 241 static int ti_chipinit(struct ti_softc *); 242 static int ti_gibinit(struct ti_softc *); 243 244 #ifdef TI_JUMBO_HDRSPLIT 245 static __inline void ti_hdr_split (struct mbuf *top, int hdr_len, 246 int pkt_len, int idx); 247 #endif /* TI_JUMBO_HDRSPLIT */ 248 249 static device_method_t ti_methods[] = { 250 /* Device interface */ 251 DEVMETHOD(device_probe, ti_probe), 252 DEVMETHOD(device_attach, ti_attach), 253 DEVMETHOD(device_detach, ti_detach), 254 DEVMETHOD(device_shutdown, ti_shutdown), 255 { 0, 0 } 256 }; 257 258 static driver_t ti_driver = { 259 "ti", 260 ti_methods, 261 sizeof(struct ti_softc) 262 }; 263 264 static devclass_t ti_devclass; 265 266 DRIVER_MODULE(ti, pci, ti_driver, ti_devclass, 0, 0); 267 MODULE_DEPEND(ti, pci, 1, 1, 1); 268 MODULE_DEPEND(ti, ether, 1, 1, 1); 269 270 /* 271 * Send an instruction or address to the EEPROM, check for ACK. 272 */ 273 static u_int32_t ti_eeprom_putbyte(sc, byte) 274 struct ti_softc *sc; 275 int byte; 276 { 277 int i, ack = 0; 278 279 /* 280 * Make sure we're in TX mode. 281 */ 282 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 283 284 /* 285 * Feed in each bit and stobe the clock. 286 */ 287 for (i = 0x80; i; i >>= 1) { 288 if (byte & i) { 289 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 290 } else { 291 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 292 } 293 DELAY(1); 294 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 295 DELAY(1); 296 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 297 } 298 299 /* 300 * Turn off TX mode. 301 */ 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 303 304 /* 305 * Check for ack. 306 */ 307 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 308 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 311 return (ack); 312 } 313 314 /* 315 * Read a byte of data stored in the EEPROM at address 'addr.' 316 * We have to send two address bytes since the EEPROM can hold 317 * more than 256 bytes of data. 318 */ 319 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 320 struct ti_softc *sc; 321 int addr; 322 u_int8_t *dest; 323 { 324 int i; 325 u_int8_t byte = 0; 326 327 EEPROM_START; 328 329 /* 330 * Send write control code to EEPROM. 331 */ 332 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 333 device_printf(sc->ti_dev, 334 "failed to send write command, status: %x\n", 335 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 336 return (1); 337 } 338 339 /* 340 * Send first byte of address of byte we want to read. 341 */ 342 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 343 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 344 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 345 return (1); 346 } 347 /* 348 * Send second byte address of byte we want to read. 349 */ 350 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 351 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 352 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 353 return (1); 354 } 355 356 EEPROM_STOP; 357 EEPROM_START; 358 /* 359 * Send read control code to EEPROM. 360 */ 361 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 362 device_printf(sc->ti_dev, 363 "failed to send read command, status: %x\n", 364 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 365 return (1); 366 } 367 368 /* 369 * Start reading bits from EEPROM. 370 */ 371 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 372 for (i = 0x80; i; i >>= 1) { 373 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 374 DELAY(1); 375 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 376 byte |= i; 377 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 378 DELAY(1); 379 } 380 381 EEPROM_STOP; 382 383 /* 384 * No ACK generated for read, so just return byte. 385 */ 386 387 *dest = byte; 388 389 return (0); 390 } 391 392 /* 393 * Read a sequence of bytes from the EEPROM. 394 */ 395 static int 396 ti_read_eeprom(sc, dest, off, cnt) 397 struct ti_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401 { 402 int err = 0, i; 403 u_int8_t byte = 0; 404 405 for (i = 0; i < cnt; i++) { 406 err = ti_eeprom_getbyte(sc, off + i, &byte); 407 if (err) 408 break; 409 *(dest + i) = byte; 410 } 411 412 return (err ? 1 : 0); 413 } 414 415 /* 416 * NIC memory read function. 417 * Can be used to copy data from NIC local memory. 418 */ 419 static void 420 ti_mem_read(sc, addr, len, buf) 421 struct ti_softc *sc; 422 u_int32_t addr, len; 423 void *buf; 424 { 425 int segptr, segsize, cnt; 426 char *ptr; 427 428 segptr = addr; 429 cnt = len; 430 ptr = buf; 431 432 while (cnt) { 433 if (cnt < TI_WINLEN) 434 segsize = cnt; 435 else 436 segsize = TI_WINLEN - (segptr % TI_WINLEN); 437 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 438 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 439 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 440 segsize / 4); 441 ptr += segsize; 442 segptr += segsize; 443 cnt -= segsize; 444 } 445 } 446 447 448 /* 449 * NIC memory write function. 450 * Can be used to copy data into NIC local memory. 451 */ 452 static void 453 ti_mem_write(sc, addr, len, buf) 454 struct ti_softc *sc; 455 u_int32_t addr, len; 456 void *buf; 457 { 458 int segptr, segsize, cnt; 459 char *ptr; 460 461 segptr = addr; 462 cnt = len; 463 ptr = buf; 464 465 while (cnt) { 466 if (cnt < TI_WINLEN) 467 segsize = cnt; 468 else 469 segsize = TI_WINLEN - (segptr % TI_WINLEN); 470 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 471 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 472 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (u_int32_t *)ptr, 473 segsize / 4); 474 ptr += segsize; 475 segptr += segsize; 476 cnt -= segsize; 477 } 478 } 479 480 /* 481 * NIC memory read function. 482 * Can be used to clear a section of NIC local memory. 483 */ 484 static void 485 ti_mem_zero(sc, addr, len) 486 struct ti_softc *sc; 487 u_int32_t addr, len; 488 { 489 int segptr, segsize, cnt; 490 491 segptr = addr; 492 cnt = len; 493 494 while (cnt) { 495 if (cnt < TI_WINLEN) 496 segsize = cnt; 497 else 498 segsize = TI_WINLEN - (segptr % TI_WINLEN); 499 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 500 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 501 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 502 segptr += segsize; 503 cnt -= segsize; 504 } 505 } 506 507 static int 508 ti_copy_mem(sc, tigon_addr, len, buf, useraddr, readdata) 509 struct ti_softc *sc; 510 u_int32_t tigon_addr, len; 511 caddr_t buf; 512 int useraddr, readdata; 513 { 514 int segptr, segsize, cnt; 515 caddr_t ptr; 516 u_int32_t origwin; 517 u_int8_t tmparray[TI_WINLEN], tmparray2[TI_WINLEN]; 518 int resid, segresid; 519 int first_pass; 520 521 TI_LOCK_ASSERT(sc); 522 523 /* 524 * At the moment, we don't handle non-aligned cases, we just bail. 525 * If this proves to be a problem, it will be fixed. 526 */ 527 if ((readdata == 0) 528 && (tigon_addr & 0x3)) { 529 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 530 "word-aligned\n", __func__, tigon_addr); 531 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 532 "yet supported\n", __func__); 533 return (EINVAL); 534 } 535 536 segptr = tigon_addr & ~0x3; 537 segresid = tigon_addr - segptr; 538 539 /* 540 * This is the non-aligned amount left over that we'll need to 541 * copy. 542 */ 543 resid = len & 0x3; 544 545 /* Add in the left over amount at the front of the buffer */ 546 resid += segresid; 547 548 cnt = len & ~0x3; 549 /* 550 * If resid + segresid is >= 4, add multiples of 4 to the count and 551 * decrease the residual by that much. 552 */ 553 cnt += resid & ~0x3; 554 resid -= resid & ~0x3; 555 556 ptr = buf; 557 558 first_pass = 1; 559 560 /* 561 * Save the old window base value. 562 */ 563 origwin = CSR_READ_4(sc, TI_WINBASE); 564 565 while (cnt) { 566 bus_size_t ti_offset; 567 568 if (cnt < TI_WINLEN) 569 segsize = cnt; 570 else 571 segsize = TI_WINLEN - (segptr % TI_WINLEN); 572 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 573 574 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 575 576 if (readdata) { 577 578 bus_space_read_region_4(sc->ti_btag, 579 sc->ti_bhandle, ti_offset, 580 (u_int32_t *)tmparray, 581 segsize >> 2); 582 if (useraddr) { 583 /* 584 * Yeah, this is a little on the kludgy 585 * side, but at least this code is only 586 * used for debugging. 587 */ 588 ti_bcopy_swap(tmparray, tmparray2, segsize, 589 TI_SWAP_NTOH); 590 591 TI_UNLOCK(sc); 592 if (first_pass) { 593 copyout(&tmparray2[segresid], ptr, 594 segsize - segresid); 595 first_pass = 0; 596 } else 597 copyout(tmparray2, ptr, segsize); 598 TI_LOCK(sc); 599 } else { 600 if (first_pass) { 601 602 ti_bcopy_swap(tmparray, tmparray2, 603 segsize, TI_SWAP_NTOH); 604 TI_UNLOCK(sc); 605 bcopy(&tmparray2[segresid], ptr, 606 segsize - segresid); 607 TI_LOCK(sc); 608 first_pass = 0; 609 } else 610 ti_bcopy_swap(tmparray, ptr, segsize, 611 TI_SWAP_NTOH); 612 } 613 614 } else { 615 if (useraddr) { 616 TI_UNLOCK(sc); 617 copyin(ptr, tmparray2, segsize); 618 TI_LOCK(sc); 619 ti_bcopy_swap(tmparray2, tmparray, segsize, 620 TI_SWAP_HTON); 621 } else 622 ti_bcopy_swap(ptr, tmparray, segsize, 623 TI_SWAP_HTON); 624 625 bus_space_write_region_4(sc->ti_btag, 626 sc->ti_bhandle, ti_offset, 627 (u_int32_t *)tmparray, 628 segsize >> 2); 629 } 630 segptr += segsize; 631 ptr += segsize; 632 cnt -= segsize; 633 } 634 635 /* 636 * Handle leftover, non-word-aligned bytes. 637 */ 638 if (resid != 0) { 639 u_int32_t tmpval, tmpval2; 640 bus_size_t ti_offset; 641 642 /* 643 * Set the segment pointer. 644 */ 645 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 646 647 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 648 649 /* 650 * First, grab whatever is in our source/destination. 651 * We'll obviously need this for reads, but also for 652 * writes, since we'll be doing read/modify/write. 653 */ 654 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 655 ti_offset, &tmpval, 1); 656 657 /* 658 * Next, translate this from little-endian to big-endian 659 * (at least on i386 boxes). 660 */ 661 tmpval2 = ntohl(tmpval); 662 663 if (readdata) { 664 /* 665 * If we're reading, just copy the leftover number 666 * of bytes from the host byte order buffer to 667 * the user's buffer. 668 */ 669 if (useraddr) { 670 TI_UNLOCK(sc); 671 copyout(&tmpval2, ptr, resid); 672 TI_LOCK(sc); 673 } else 674 bcopy(&tmpval2, ptr, resid); 675 } else { 676 /* 677 * If we're writing, first copy the bytes to be 678 * written into the network byte order buffer, 679 * leaving the rest of the buffer with whatever was 680 * originally in there. Then, swap the bytes 681 * around into host order and write them out. 682 * 683 * XXX KDM the read side of this has been verified 684 * to work, but the write side of it has not been 685 * verified. So user beware. 686 */ 687 if (useraddr) { 688 TI_UNLOCK(sc); 689 copyin(ptr, &tmpval2, resid); 690 TI_LOCK(sc); 691 } else 692 bcopy(ptr, &tmpval2, resid); 693 694 tmpval = htonl(tmpval2); 695 696 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 697 ti_offset, &tmpval, 1); 698 } 699 } 700 701 CSR_WRITE_4(sc, TI_WINBASE, origwin); 702 703 return (0); 704 } 705 706 static int 707 ti_copy_scratch(sc, tigon_addr, len, buf, useraddr, readdata, cpu) 708 struct ti_softc *sc; 709 u_int32_t tigon_addr, len; 710 caddr_t buf; 711 int useraddr, readdata; 712 int cpu; 713 { 714 u_int32_t segptr; 715 int cnt; 716 u_int32_t tmpval, tmpval2; 717 caddr_t ptr; 718 719 TI_LOCK_ASSERT(sc); 720 721 /* 722 * At the moment, we don't handle non-aligned cases, we just bail. 723 * If this proves to be a problem, it will be fixed. 724 */ 725 if (tigon_addr & 0x3) { 726 device_printf(sc->ti_dev, "%s: tigon address %#x " 727 "isn't word-aligned\n", __func__, tigon_addr); 728 return (EINVAL); 729 } 730 731 if (len & 0x3) { 732 device_printf(sc->ti_dev, "%s: transfer length %d " 733 "isn't word-aligned\n", __func__, len); 734 return (EINVAL); 735 } 736 737 segptr = tigon_addr; 738 cnt = len; 739 ptr = buf; 740 741 while (cnt) { 742 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 743 744 if (readdata) { 745 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 746 747 tmpval = ntohl(tmpval2); 748 749 /* 750 * Note: I've used this debugging interface 751 * extensively with Alteon's 12.3.15 firmware, 752 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 753 * 754 * When you compile the firmware without 755 * optimization, which is necessary sometimes in 756 * order to properly step through it, you sometimes 757 * read out a bogus value of 0xc0017c instead of 758 * whatever was supposed to be in that scratchpad 759 * location. That value is on the stack somewhere, 760 * but I've never been able to figure out what was 761 * causing the problem. 762 * 763 * The address seems to pop up in random places, 764 * often not in the same place on two subsequent 765 * reads. 766 * 767 * In any case, the underlying data doesn't seem 768 * to be affected, just the value read out. 769 * 770 * KDM, 3/7/2000 771 */ 772 773 if (tmpval2 == 0xc0017c) 774 device_printf(sc->ti_dev, "found 0xc0017c at " 775 "%#x (tmpval2)\n", segptr); 776 777 if (tmpval == 0xc0017c) 778 device_printf(sc->ti_dev, "found 0xc0017c at " 779 "%#x (tmpval)\n", segptr); 780 781 if (useraddr) 782 copyout(&tmpval, ptr, 4); 783 else 784 bcopy(&tmpval, ptr, 4); 785 } else { 786 if (useraddr) 787 copyin(ptr, &tmpval2, 4); 788 else 789 bcopy(ptr, &tmpval2, 4); 790 791 tmpval = htonl(tmpval2); 792 793 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), tmpval); 794 } 795 796 cnt -= 4; 797 segptr += 4; 798 ptr += 4; 799 } 800 801 return (0); 802 } 803 804 static int 805 ti_bcopy_swap(src, dst, len, swap_type) 806 const void *src; 807 void *dst; 808 size_t len; 809 ti_swap_type swap_type; 810 { 811 const u_int8_t *tmpsrc; 812 u_int8_t *tmpdst; 813 size_t tmplen; 814 815 if (len & 0x3) { 816 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", 817 len); 818 return (-1); 819 } 820 821 tmpsrc = src; 822 tmpdst = dst; 823 tmplen = len; 824 825 while (tmplen) { 826 if (swap_type == TI_SWAP_NTOH) 827 *(u_int32_t *)tmpdst = 828 ntohl(*(const u_int32_t *)tmpsrc); 829 else 830 *(u_int32_t *)tmpdst = 831 htonl(*(const u_int32_t *)tmpsrc); 832 833 tmpsrc += 4; 834 tmpdst += 4; 835 tmplen -= 4; 836 } 837 838 return (0); 839 } 840 841 /* 842 * Load firmware image into the NIC. Check that the firmware revision 843 * is acceptable and see if we want the firmware for the Tigon 1 or 844 * Tigon 2. 845 */ 846 static void 847 ti_loadfw(sc) 848 struct ti_softc *sc; 849 { 850 851 TI_LOCK_ASSERT(sc); 852 853 switch (sc->ti_hwrev) { 854 case TI_HWREV_TIGON: 855 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 856 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 857 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 858 device_printf(sc->ti_dev, "firmware revision mismatch; " 859 "want %d.%d.%d, got %d.%d.%d\n", 860 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 861 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 862 tigonFwReleaseMinor, tigonFwReleaseFix); 863 return; 864 } 865 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 866 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 867 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 868 tigonFwRodata); 869 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 870 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 871 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 872 break; 873 case TI_HWREV_TIGON_II: 874 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 875 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 876 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 877 device_printf(sc->ti_dev, "firmware revision mismatch; " 878 "want %d.%d.%d, got %d.%d.%d\n", 879 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 880 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 881 tigon2FwReleaseMinor, tigon2FwReleaseFix); 882 return; 883 } 884 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 885 tigon2FwText); 886 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 887 tigon2FwData); 888 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 889 tigon2FwRodata); 890 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 891 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 892 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 893 break; 894 default: 895 device_printf(sc->ti_dev, 896 "can't load firmware: unknown hardware rev\n"); 897 break; 898 } 899 } 900 901 /* 902 * Send the NIC a command via the command ring. 903 */ 904 static void 905 ti_cmd(sc, cmd) 906 struct ti_softc *sc; 907 struct ti_cmd_desc *cmd; 908 { 909 int index; 910 911 index = sc->ti_cmd_saved_prodidx; 912 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 913 TI_INC(index, TI_CMD_RING_CNT); 914 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 915 sc->ti_cmd_saved_prodidx = index; 916 } 917 918 /* 919 * Send the NIC an extended command. The 'len' parameter specifies the 920 * number of command slots to include after the initial command. 921 */ 922 static void 923 ti_cmd_ext(sc, cmd, arg, len) 924 struct ti_softc *sc; 925 struct ti_cmd_desc *cmd; 926 caddr_t arg; 927 int len; 928 { 929 int index; 930 int i; 931 932 index = sc->ti_cmd_saved_prodidx; 933 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 934 TI_INC(index, TI_CMD_RING_CNT); 935 for (i = 0; i < len; i++) { 936 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 937 *(u_int32_t *)(&arg[i * 4])); 938 TI_INC(index, TI_CMD_RING_CNT); 939 } 940 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 941 sc->ti_cmd_saved_prodidx = index; 942 } 943 944 /* 945 * Handle events that have triggered interrupts. 946 */ 947 static void 948 ti_handle_events(sc) 949 struct ti_softc *sc; 950 { 951 struct ti_event_desc *e; 952 953 if (sc->ti_rdata->ti_event_ring == NULL) 954 return; 955 956 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 957 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 958 switch (TI_EVENT_EVENT(e)) { 959 case TI_EV_LINKSTAT_CHANGED: 960 sc->ti_linkstat = TI_EVENT_CODE(e); 961 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 962 device_printf(sc->ti_dev, "10/100 link up\n"); 963 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 964 device_printf(sc->ti_dev, "gigabit link up\n"); 965 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 966 device_printf(sc->ti_dev, "link down\n"); 967 break; 968 case TI_EV_ERROR: 969 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 970 device_printf(sc->ti_dev, "invalid command\n"); 971 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 972 device_printf(sc->ti_dev, "unknown command\n"); 973 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 974 device_printf(sc->ti_dev, "bad config data\n"); 975 break; 976 case TI_EV_FIRMWARE_UP: 977 ti_init2(sc); 978 break; 979 case TI_EV_STATS_UPDATED: 980 ti_stats_update(sc); 981 break; 982 case TI_EV_RESET_JUMBO_RING: 983 case TI_EV_MCAST_UPDATED: 984 /* Who cares. */ 985 break; 986 default: 987 device_printf(sc->ti_dev, "unknown event: %d\n", 988 TI_EVENT_EVENT(e)); 989 break; 990 } 991 /* Advance the consumer index. */ 992 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 993 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 994 } 995 } 996 997 static int 998 ti_alloc_dmamaps(struct ti_softc *sc) 999 { 1000 int i; 1001 1002 for (i = 0; i < TI_TX_RING_CNT; i++) { 1003 sc->ti_cdata.ti_txdesc[i].tx_m = NULL; 1004 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1005 if (bus_dmamap_create(sc->ti_mbuftx_dmat, 0, 1006 &sc->ti_cdata.ti_txdesc[i].tx_dmamap)) 1007 return (ENOBUFS); 1008 } 1009 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1010 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1011 &sc->ti_cdata.ti_rx_std_maps[i])) 1012 return (ENOBUFS); 1013 } 1014 1015 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1016 if (bus_dmamap_create(sc->ti_jumbo_dmat, 0, 1017 &sc->ti_cdata.ti_rx_jumbo_maps[i])) 1018 return (ENOBUFS); 1019 } 1020 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1021 if (bus_dmamap_create(sc->ti_mbufrx_dmat, 0, 1022 &sc->ti_cdata.ti_rx_mini_maps[i])) 1023 return (ENOBUFS); 1024 } 1025 1026 return (0); 1027 } 1028 1029 static void 1030 ti_free_dmamaps(struct ti_softc *sc) 1031 { 1032 int i; 1033 1034 if (sc->ti_mbuftx_dmat) 1035 for (i = 0; i < TI_TX_RING_CNT; i++) 1036 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1037 bus_dmamap_destroy(sc->ti_mbuftx_dmat, 1038 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1039 sc->ti_cdata.ti_txdesc[i].tx_dmamap = 0; 1040 } 1041 1042 if (sc->ti_mbufrx_dmat) 1043 for (i = 0; i < TI_STD_RX_RING_CNT; i++) 1044 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1045 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1046 sc->ti_cdata.ti_rx_std_maps[i]); 1047 sc->ti_cdata.ti_rx_std_maps[i] = 0; 1048 } 1049 1050 if (sc->ti_jumbo_dmat) 1051 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) 1052 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1053 bus_dmamap_destroy(sc->ti_jumbo_dmat, 1054 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1055 sc->ti_cdata.ti_rx_jumbo_maps[i] = 0; 1056 } 1057 if (sc->ti_mbufrx_dmat) 1058 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) 1059 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1060 bus_dmamap_destroy(sc->ti_mbufrx_dmat, 1061 sc->ti_cdata.ti_rx_mini_maps[i]); 1062 sc->ti_cdata.ti_rx_mini_maps[i] = 0; 1063 } 1064 } 1065 1066 #ifdef TI_PRIVATE_JUMBOS 1067 1068 /* 1069 * Memory management for the jumbo receive ring is a pain in the 1070 * butt. We need to allocate at least 9018 bytes of space per frame, 1071 * _and_ it has to be contiguous (unless you use the extended 1072 * jumbo descriptor format). Using malloc() all the time won't 1073 * work: malloc() allocates memory in powers of two, which means we 1074 * would end up wasting a considerable amount of space by allocating 1075 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 1076 * to do our own memory management. 1077 * 1078 * The driver needs to allocate a contiguous chunk of memory at boot 1079 * time. We then chop this up ourselves into 9K pieces and use them 1080 * as external mbuf storage. 1081 * 1082 * One issue here is how much memory to allocate. The jumbo ring has 1083 * 256 slots in it, but at 9K per slot than can consume over 2MB of 1084 * RAM. This is a bit much, especially considering we also need 1085 * RAM for the standard ring and mini ring (on the Tigon 2). To 1086 * save space, we only actually allocate enough memory for 64 slots 1087 * by default, which works out to between 500 and 600K. This can 1088 * be tuned by changing a #define in if_tireg.h. 1089 */ 1090 1091 static int 1092 ti_alloc_jumbo_mem(sc) 1093 struct ti_softc *sc; 1094 { 1095 caddr_t ptr; 1096 int i; 1097 struct ti_jpool_entry *entry; 1098 1099 /* 1100 * Grab a big chunk o' storage. Since we are chopping this pool up 1101 * into ~9k chunks, there doesn't appear to be a need to use page 1102 * alignment. 1103 */ 1104 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1105 1, 0, /* algnmnt, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 TI_JMEM, /* maxsize */ 1110 1, /* nsegments */ 1111 TI_JMEM, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ti_jumbo_dmat) != 0) { 1115 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1116 return (ENOBUFS); 1117 } 1118 1119 if (bus_dmamem_alloc(sc->ti_jumbo_dmat, 1120 (void**)&sc->ti_cdata.ti_jumbo_buf, 1121 BUS_DMA_NOWAIT, &sc->ti_jumbo_dmamap) != 0) { 1122 device_printf(sc->ti_dev, "Failed to allocate jumbo memory\n"); 1123 return (ENOBUFS); 1124 } 1125 1126 SLIST_INIT(&sc->ti_jfree_listhead); 1127 SLIST_INIT(&sc->ti_jinuse_listhead); 1128 1129 /* 1130 * Now divide it up into 9K pieces and save the addresses 1131 * in an array. 1132 */ 1133 ptr = sc->ti_cdata.ti_jumbo_buf; 1134 for (i = 0; i < TI_JSLOTS; i++) { 1135 sc->ti_cdata.ti_jslots[i] = ptr; 1136 ptr += TI_JLEN; 1137 entry = malloc(sizeof(struct ti_jpool_entry), 1138 M_DEVBUF, M_NOWAIT); 1139 if (entry == NULL) { 1140 device_printf(sc->ti_dev, "no memory for jumbo " 1141 "buffer queue!\n"); 1142 return (ENOBUFS); 1143 } 1144 entry->slot = i; 1145 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1146 } 1147 1148 return (0); 1149 } 1150 1151 /* 1152 * Allocate a jumbo buffer. 1153 */ 1154 static void *ti_jalloc(sc) 1155 struct ti_softc *sc; 1156 { 1157 struct ti_jpool_entry *entry; 1158 1159 entry = SLIST_FIRST(&sc->ti_jfree_listhead); 1160 1161 if (entry == NULL) { 1162 device_printf(sc->ti_dev, "no free jumbo buffers\n"); 1163 return (NULL); 1164 } 1165 1166 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 1167 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 1168 return (sc->ti_cdata.ti_jslots[entry->slot]); 1169 } 1170 1171 /* 1172 * Release a jumbo buffer. 1173 */ 1174 static void 1175 ti_jfree(buf, args) 1176 void *buf; 1177 void *args; 1178 { 1179 struct ti_softc *sc; 1180 int i; 1181 struct ti_jpool_entry *entry; 1182 1183 /* Extract the softc struct pointer. */ 1184 sc = (struct ti_softc *)args; 1185 1186 if (sc == NULL) 1187 panic("ti_jfree: didn't get softc pointer!"); 1188 1189 /* calculate the slot this buffer belongs to */ 1190 i = ((vm_offset_t)buf 1191 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 1192 1193 if ((i < 0) || (i >= TI_JSLOTS)) 1194 panic("ti_jfree: asked to free buffer that we don't manage!"); 1195 1196 entry = SLIST_FIRST(&sc->ti_jinuse_listhead); 1197 if (entry == NULL) 1198 panic("ti_jfree: buffer not in use!"); 1199 entry->slot = i; 1200 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 1201 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 1202 } 1203 1204 #else 1205 1206 static int 1207 ti_alloc_jumbo_mem(sc) 1208 struct ti_softc *sc; 1209 { 1210 1211 /* 1212 * The VM system will take care of providing aligned pages. Alignment 1213 * is set to 1 here so that busdma resources won't be wasted. 1214 */ 1215 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 1216 1, 0, /* algnmnt, boundary */ 1217 BUS_SPACE_MAXADDR, /* lowaddr */ 1218 BUS_SPACE_MAXADDR, /* highaddr */ 1219 NULL, NULL, /* filter, filterarg */ 1220 PAGE_SIZE * 4 /*XXX*/, /* maxsize */ 1221 4, /* nsegments */ 1222 PAGE_SIZE, /* maxsegsize */ 1223 0, /* flags */ 1224 NULL, NULL, /* lockfunc, lockarg */ 1225 &sc->ti_jumbo_dmat) != 0) { 1226 device_printf(sc->ti_dev, "Failed to allocate jumbo dmat\n"); 1227 return (ENOBUFS); 1228 } 1229 1230 return (0); 1231 } 1232 1233 #endif /* TI_PRIVATE_JUMBOS */ 1234 1235 /* 1236 * Intialize a standard receive ring descriptor. 1237 */ 1238 static int 1239 ti_newbuf_std(sc, i, m) 1240 struct ti_softc *sc; 1241 int i; 1242 struct mbuf *m; 1243 { 1244 bus_dmamap_t map; 1245 bus_dma_segment_t segs; 1246 struct mbuf *m_new = NULL; 1247 struct ti_rx_desc *r; 1248 int nsegs; 1249 1250 nsegs = 0; 1251 if (m == NULL) { 1252 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1253 if (m_new == NULL) 1254 return (ENOBUFS); 1255 1256 MCLGET(m_new, M_DONTWAIT); 1257 if (!(m_new->m_flags & M_EXT)) { 1258 m_freem(m_new); 1259 return (ENOBUFS); 1260 } 1261 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1262 } else { 1263 m_new = m; 1264 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1265 m_new->m_data = m_new->m_ext.ext_buf; 1266 } 1267 1268 m_adj(m_new, ETHER_ALIGN); 1269 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 1270 r = &sc->ti_rdata->ti_rx_std_ring[i]; 1271 map = sc->ti_cdata.ti_rx_std_maps[i]; 1272 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1273 &nsegs, 0)) 1274 return (ENOBUFS); 1275 if (nsegs != 1) 1276 return (ENOBUFS); 1277 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1278 r->ti_len = segs.ds_len; 1279 r->ti_type = TI_BDTYPE_RECV_BD; 1280 r->ti_flags = 0; 1281 if (sc->ti_ifp->if_hwassist) 1282 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1283 r->ti_idx = i; 1284 1285 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1286 return (0); 1287 } 1288 1289 /* 1290 * Intialize a mini receive ring descriptor. This only applies to 1291 * the Tigon 2. 1292 */ 1293 static int 1294 ti_newbuf_mini(sc, i, m) 1295 struct ti_softc *sc; 1296 int i; 1297 struct mbuf *m; 1298 { 1299 bus_dma_segment_t segs; 1300 bus_dmamap_t map; 1301 struct mbuf *m_new = NULL; 1302 struct ti_rx_desc *r; 1303 int nsegs; 1304 1305 nsegs = 0; 1306 if (m == NULL) { 1307 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1308 if (m_new == NULL) { 1309 return (ENOBUFS); 1310 } 1311 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1312 } else { 1313 m_new = m; 1314 m_new->m_data = m_new->m_pktdat; 1315 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 1316 } 1317 1318 m_adj(m_new, ETHER_ALIGN); 1319 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 1320 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 1321 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1322 if (bus_dmamap_load_mbuf_sg(sc->ti_mbufrx_dmat, map, m_new, &segs, 1323 &nsegs, 0)) 1324 return (ENOBUFS); 1325 if (nsegs != 1) 1326 return (ENOBUFS); 1327 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1328 r->ti_len = segs.ds_len; 1329 r->ti_type = TI_BDTYPE_RECV_BD; 1330 r->ti_flags = TI_BDFLAG_MINI_RING; 1331 if (sc->ti_ifp->if_hwassist) 1332 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1333 r->ti_idx = i; 1334 1335 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, BUS_DMASYNC_PREREAD); 1336 return (0); 1337 } 1338 1339 #ifdef TI_PRIVATE_JUMBOS 1340 1341 /* 1342 * Initialize a jumbo receive ring descriptor. This allocates 1343 * a jumbo buffer from the pool managed internally by the driver. 1344 */ 1345 static int 1346 ti_newbuf_jumbo(sc, i, m) 1347 struct ti_softc *sc; 1348 int i; 1349 struct mbuf *m; 1350 { 1351 bus_dmamap_t map; 1352 struct mbuf *m_new = NULL; 1353 struct ti_rx_desc *r; 1354 int nsegs; 1355 bus_dma_segment_t segs; 1356 1357 if (m == NULL) { 1358 caddr_t *buf = NULL; 1359 1360 /* Allocate the mbuf. */ 1361 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1362 if (m_new == NULL) { 1363 return (ENOBUFS); 1364 } 1365 1366 /* Allocate the jumbo buffer */ 1367 buf = ti_jalloc(sc); 1368 if (buf == NULL) { 1369 m_freem(m_new); 1370 device_printf(sc->ti_dev, "jumbo allocation failed " 1371 "-- packet dropped!\n"); 1372 return (ENOBUFS); 1373 } 1374 1375 /* Attach the buffer to the mbuf. */ 1376 m_new->m_data = (void *) buf; 1377 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN; 1378 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree, 1379 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1380 } else { 1381 m_new = m; 1382 m_new->m_data = m_new->m_ext.ext_buf; 1383 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 1384 } 1385 1386 m_adj(m_new, ETHER_ALIGN); 1387 /* Set up the descriptor. */ 1388 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 1389 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 1390 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1391 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, &segs, 1392 &nsegs, 0)) 1393 return (ENOBUFS); 1394 if (nsegs != 1) 1395 return (ENOBUFS); 1396 ti_hostaddr64(&r->ti_addr, segs.ds_addr); 1397 r->ti_len = segs.ds_len; 1398 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1399 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1400 if (sc->ti_ifp->if_hwassist) 1401 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1402 r->ti_idx = i; 1403 1404 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1405 return (0); 1406 } 1407 1408 #else 1409 1410 #if (PAGE_SIZE == 4096) 1411 #define NPAYLOAD 2 1412 #else 1413 #define NPAYLOAD 1 1414 #endif 1415 1416 #define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1417 #define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1418 #define NFS_HDR_LEN (UDP_HDR_LEN) 1419 static int HDR_LEN = TCP_HDR_LEN; 1420 1421 1422 /* 1423 * Initialize a jumbo receive ring descriptor. This allocates 1424 * a jumbo buffer from the pool managed internally by the driver. 1425 */ 1426 static int 1427 ti_newbuf_jumbo(sc, idx, m_old) 1428 struct ti_softc *sc; 1429 int idx; 1430 struct mbuf *m_old; 1431 { 1432 bus_dmamap_t map; 1433 struct mbuf *cur, *m_new = NULL; 1434 struct mbuf *m[3] = {NULL, NULL, NULL}; 1435 struct ti_rx_desc_ext *r; 1436 vm_page_t frame; 1437 static int color; 1438 /* 1 extra buf to make nobufs easy*/ 1439 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1440 int i; 1441 bus_dma_segment_t segs[4]; 1442 int nsegs; 1443 1444 if (m_old != NULL) { 1445 m_new = m_old; 1446 cur = m_old->m_next; 1447 for (i = 0; i <= NPAYLOAD; i++){ 1448 m[i] = cur; 1449 cur = cur->m_next; 1450 } 1451 } else { 1452 /* Allocate the mbufs. */ 1453 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1454 if (m_new == NULL) { 1455 device_printf(sc->ti_dev, "mbuf allocation failed " 1456 "-- packet dropped!\n"); 1457 goto nobufs; 1458 } 1459 MGET(m[NPAYLOAD], M_DONTWAIT, MT_DATA); 1460 if (m[NPAYLOAD] == NULL) { 1461 device_printf(sc->ti_dev, "cluster mbuf allocation " 1462 "failed -- packet dropped!\n"); 1463 goto nobufs; 1464 } 1465 MCLGET(m[NPAYLOAD], M_DONTWAIT); 1466 if ((m[NPAYLOAD]->m_flags & M_EXT) == 0) { 1467 device_printf(sc->ti_dev, "mbuf allocation failed " 1468 "-- packet dropped!\n"); 1469 goto nobufs; 1470 } 1471 m[NPAYLOAD]->m_len = MCLBYTES; 1472 1473 for (i = 0; i < NPAYLOAD; i++){ 1474 MGET(m[i], M_DONTWAIT, MT_DATA); 1475 if (m[i] == NULL) { 1476 device_printf(sc->ti_dev, "mbuf allocation " 1477 "failed -- packet dropped!\n"); 1478 goto nobufs; 1479 } 1480 frame = vm_page_alloc(NULL, color++, 1481 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1482 VM_ALLOC_WIRED); 1483 if (frame == NULL) { 1484 device_printf(sc->ti_dev, "buffer allocation " 1485 "failed -- packet dropped!\n"); 1486 printf(" index %d page %d\n", idx, i); 1487 goto nobufs; 1488 } 1489 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1490 if (sf[i] == NULL) { 1491 vm_page_unwire(frame, 0); 1492 vm_page_free(frame); 1493 device_printf(sc->ti_dev, "buffer allocation " 1494 "failed -- packet dropped!\n"); 1495 printf(" index %d page %d\n", idx, i); 1496 goto nobufs; 1497 } 1498 } 1499 for (i = 0; i < NPAYLOAD; i++){ 1500 /* Attach the buffer to the mbuf. */ 1501 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1502 m[i]->m_len = PAGE_SIZE; 1503 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1504 sf_buf_mext, (void*)sf_buf_kva(sf[i]), sf[i], 1505 0, EXT_DISPOSABLE); 1506 m[i]->m_next = m[i+1]; 1507 } 1508 /* link the buffers to the header */ 1509 m_new->m_next = m[0]; 1510 m_new->m_data += ETHER_ALIGN; 1511 if (sc->ti_hdrsplit) 1512 m_new->m_len = MHLEN - ETHER_ALIGN; 1513 else 1514 m_new->m_len = HDR_LEN; 1515 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1516 } 1517 1518 /* Set up the descriptor. */ 1519 r = &sc->ti_rdata->ti_rx_jumbo_ring[idx]; 1520 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1521 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1522 if (bus_dmamap_load_mbuf_sg(sc->ti_jumbo_dmat, map, m_new, segs, 1523 &nsegs, 0)) 1524 return (ENOBUFS); 1525 if ((nsegs < 1) || (nsegs > 4)) 1526 return (ENOBUFS); 1527 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1528 r->ti_len0 = m_new->m_len; 1529 1530 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1531 r->ti_len1 = PAGE_SIZE; 1532 1533 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1534 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1535 1536 if (PAGE_SIZE == 4096) { 1537 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1538 r->ti_len3 = MCLBYTES; 1539 } else { 1540 r->ti_len3 = 0; 1541 } 1542 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1543 1544 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1545 1546 if (sc->ti_ifp->if_hwassist) 1547 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1548 1549 r->ti_idx = idx; 1550 1551 bus_dmamap_sync(sc->ti_jumbo_dmat, map, BUS_DMASYNC_PREREAD); 1552 return (0); 1553 1554 nobufs: 1555 1556 /* 1557 * Warning! : 1558 * This can only be called before the mbufs are strung together. 1559 * If the mbufs are strung together, m_freem() will free the chain, 1560 * so that the later mbufs will be freed multiple times. 1561 */ 1562 if (m_new) 1563 m_freem(m_new); 1564 1565 for (i = 0; i < 3; i++) { 1566 if (m[i]) 1567 m_freem(m[i]); 1568 if (sf[i]) 1569 sf_buf_mext((void *)sf_buf_kva(sf[i]), sf[i]); 1570 } 1571 return (ENOBUFS); 1572 } 1573 #endif 1574 1575 1576 1577 /* 1578 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1579 * that's 1MB or memory, which is a lot. For now, we fill only the first 1580 * 256 ring entries and hope that our CPU is fast enough to keep up with 1581 * the NIC. 1582 */ 1583 static int 1584 ti_init_rx_ring_std(sc) 1585 struct ti_softc *sc; 1586 { 1587 int i; 1588 struct ti_cmd_desc cmd; 1589 1590 for (i = 0; i < TI_SSLOTS; i++) { 1591 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS) 1592 return (ENOBUFS); 1593 }; 1594 1595 TI_UPDATE_STDPROD(sc, i - 1); 1596 sc->ti_std = i - 1; 1597 1598 return (0); 1599 } 1600 1601 static void 1602 ti_free_rx_ring_std(sc) 1603 struct ti_softc *sc; 1604 { 1605 bus_dmamap_t map; 1606 int i; 1607 1608 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1609 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1610 map = sc->ti_cdata.ti_rx_std_maps[i]; 1611 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1612 BUS_DMASYNC_POSTREAD); 1613 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1614 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1615 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1616 } 1617 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 1618 sizeof(struct ti_rx_desc)); 1619 } 1620 } 1621 1622 static int 1623 ti_init_rx_ring_jumbo(sc) 1624 struct ti_softc *sc; 1625 { 1626 int i; 1627 struct ti_cmd_desc cmd; 1628 1629 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1630 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1631 return (ENOBUFS); 1632 }; 1633 1634 TI_UPDATE_JUMBOPROD(sc, i - 1); 1635 sc->ti_jumbo = i - 1; 1636 1637 return (0); 1638 } 1639 1640 static void 1641 ti_free_rx_ring_jumbo(sc) 1642 struct ti_softc *sc; 1643 { 1644 bus_dmamap_t map; 1645 int i; 1646 1647 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1648 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1649 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1650 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 1651 BUS_DMASYNC_POSTREAD); 1652 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 1653 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1654 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1655 } 1656 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1657 sizeof(struct ti_rx_desc)); 1658 } 1659 } 1660 1661 static int 1662 ti_init_rx_ring_mini(sc) 1663 struct ti_softc *sc; 1664 { 1665 int i; 1666 1667 for (i = 0; i < TI_MSLOTS; i++) { 1668 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS) 1669 return (ENOBUFS); 1670 }; 1671 1672 TI_UPDATE_MINIPROD(sc, i - 1); 1673 sc->ti_mini = i - 1; 1674 1675 return (0); 1676 } 1677 1678 static void 1679 ti_free_rx_ring_mini(sc) 1680 struct ti_softc *sc; 1681 { 1682 bus_dmamap_t map; 1683 int i; 1684 1685 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1686 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1687 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1688 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 1689 BUS_DMASYNC_POSTREAD); 1690 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 1691 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1692 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1693 } 1694 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1695 sizeof(struct ti_rx_desc)); 1696 } 1697 } 1698 1699 static void 1700 ti_free_tx_ring(sc) 1701 struct ti_softc *sc; 1702 { 1703 struct ti_txdesc *txd; 1704 int i; 1705 1706 if (sc->ti_rdata->ti_tx_ring == NULL) 1707 return; 1708 1709 for (i = 0; i < TI_TX_RING_CNT; i++) { 1710 txd = &sc->ti_cdata.ti_txdesc[i]; 1711 if (txd->tx_m != NULL) { 1712 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 1713 BUS_DMASYNC_POSTWRITE); 1714 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 1715 m_freem(txd->tx_m); 1716 txd->tx_m = NULL; 1717 } 1718 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1719 sizeof(struct ti_tx_desc)); 1720 } 1721 } 1722 1723 static int 1724 ti_init_tx_ring(sc) 1725 struct ti_softc *sc; 1726 { 1727 struct ti_txdesc *txd; 1728 int i; 1729 1730 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1731 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1732 for (i = 0; i < TI_TX_RING_CNT; i++) { 1733 txd = &sc->ti_cdata.ti_txdesc[i]; 1734 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1735 } 1736 sc->ti_txcnt = 0; 1737 sc->ti_tx_saved_considx = 0; 1738 sc->ti_tx_saved_prodidx = 0; 1739 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1740 return (0); 1741 } 1742 1743 /* 1744 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1745 * but we have to support the old way too so that Tigon 1 cards will 1746 * work. 1747 */ 1748 static void 1749 ti_add_mcast(sc, addr) 1750 struct ti_softc *sc; 1751 struct ether_addr *addr; 1752 { 1753 struct ti_cmd_desc cmd; 1754 u_int16_t *m; 1755 u_int32_t ext[2] = {0, 0}; 1756 1757 m = (u_int16_t *)&addr->octet[0]; 1758 1759 switch (sc->ti_hwrev) { 1760 case TI_HWREV_TIGON: 1761 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1762 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1763 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1764 break; 1765 case TI_HWREV_TIGON_II: 1766 ext[0] = htons(m[0]); 1767 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1768 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1769 break; 1770 default: 1771 device_printf(sc->ti_dev, "unknown hwrev\n"); 1772 break; 1773 } 1774 } 1775 1776 static void 1777 ti_del_mcast(sc, addr) 1778 struct ti_softc *sc; 1779 struct ether_addr *addr; 1780 { 1781 struct ti_cmd_desc cmd; 1782 u_int16_t *m; 1783 u_int32_t ext[2] = {0, 0}; 1784 1785 m = (u_int16_t *)&addr->octet[0]; 1786 1787 switch (sc->ti_hwrev) { 1788 case TI_HWREV_TIGON: 1789 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1790 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1791 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1792 break; 1793 case TI_HWREV_TIGON_II: 1794 ext[0] = htons(m[0]); 1795 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1796 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1797 break; 1798 default: 1799 device_printf(sc->ti_dev, "unknown hwrev\n"); 1800 break; 1801 } 1802 } 1803 1804 /* 1805 * Configure the Tigon's multicast address filter. 1806 * 1807 * The actual multicast table management is a bit of a pain, thanks to 1808 * slight brain damage on the part of both Alteon and us. With our 1809 * multicast code, we are only alerted when the multicast address table 1810 * changes and at that point we only have the current list of addresses: 1811 * we only know the current state, not the previous state, so we don't 1812 * actually know what addresses were removed or added. The firmware has 1813 * state, but we can't get our grubby mits on it, and there is no 'delete 1814 * all multicast addresses' command. Hence, we have to maintain our own 1815 * state so we know what addresses have been programmed into the NIC at 1816 * any given time. 1817 */ 1818 static void 1819 ti_setmulti(sc) 1820 struct ti_softc *sc; 1821 { 1822 struct ifnet *ifp; 1823 struct ifmultiaddr *ifma; 1824 struct ti_cmd_desc cmd; 1825 struct ti_mc_entry *mc; 1826 u_int32_t intrs; 1827 1828 TI_LOCK_ASSERT(sc); 1829 1830 ifp = sc->ti_ifp; 1831 1832 if (ifp->if_flags & IFF_ALLMULTI) { 1833 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1834 return; 1835 } else { 1836 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1837 } 1838 1839 /* Disable interrupts. */ 1840 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1841 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1842 1843 /* First, zot all the existing filters. */ 1844 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) { 1845 mc = SLIST_FIRST(&sc->ti_mc_listhead); 1846 ti_del_mcast(sc, &mc->mc_addr); 1847 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1848 free(mc, M_DEVBUF); 1849 } 1850 1851 /* Now program new ones. */ 1852 if_maddr_rlock(ifp); 1853 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1854 if (ifma->ifma_addr->sa_family != AF_LINK) 1855 continue; 1856 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1857 if (mc == NULL) { 1858 device_printf(sc->ti_dev, 1859 "no memory for mcast filter entry\n"); 1860 continue; 1861 } 1862 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1863 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1864 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1865 ti_add_mcast(sc, &mc->mc_addr); 1866 } 1867 if_maddr_runlock(ifp); 1868 1869 /* Re-enable interrupts. */ 1870 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1871 } 1872 1873 /* 1874 * Check to see if the BIOS has configured us for a 64 bit slot when 1875 * we aren't actually in one. If we detect this condition, we can work 1876 * around it on the Tigon 2 by setting a bit in the PCI state register, 1877 * but for the Tigon 1 we must give up and abort the interface attach. 1878 */ 1879 static int ti_64bitslot_war(sc) 1880 struct ti_softc *sc; 1881 { 1882 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1883 CSR_WRITE_4(sc, 0x600, 0); 1884 CSR_WRITE_4(sc, 0x604, 0); 1885 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1886 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1887 if (sc->ti_hwrev == TI_HWREV_TIGON) 1888 return (EINVAL); 1889 else { 1890 TI_SETBIT(sc, TI_PCI_STATE, 1891 TI_PCISTATE_32BIT_BUS); 1892 return (0); 1893 } 1894 } 1895 } 1896 1897 return (0); 1898 } 1899 1900 /* 1901 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1902 * self-test results. 1903 */ 1904 static int 1905 ti_chipinit(sc) 1906 struct ti_softc *sc; 1907 { 1908 u_int32_t cacheline; 1909 u_int32_t pci_writemax = 0; 1910 u_int32_t hdrsplit; 1911 1912 /* Initialize link to down state. */ 1913 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1914 1915 if (sc->ti_ifp->if_capenable & IFCAP_HWCSUM) 1916 sc->ti_ifp->if_hwassist = TI_CSUM_FEATURES; 1917 else 1918 sc->ti_ifp->if_hwassist = 0; 1919 1920 /* Set endianness before we access any non-PCI registers. */ 1921 #if 0 && BYTE_ORDER == BIG_ENDIAN 1922 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1923 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1924 #else 1925 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1926 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1927 #endif 1928 1929 /* Check the ROM failed bit to see if self-tests passed. */ 1930 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1931 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 1932 return (ENODEV); 1933 } 1934 1935 /* Halt the CPU. */ 1936 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1937 1938 /* Figure out the hardware revision. */ 1939 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1940 case TI_REV_TIGON_I: 1941 sc->ti_hwrev = TI_HWREV_TIGON; 1942 break; 1943 case TI_REV_TIGON_II: 1944 sc->ti_hwrev = TI_HWREV_TIGON_II; 1945 break; 1946 default: 1947 device_printf(sc->ti_dev, "unsupported chip revision\n"); 1948 return (ENODEV); 1949 } 1950 1951 /* Do special setup for Tigon 2. */ 1952 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1953 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1954 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 1955 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1956 } 1957 1958 /* 1959 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 1960 * can't do header splitting. 1961 */ 1962 #ifdef TI_JUMBO_HDRSPLIT 1963 if (sc->ti_hwrev != TI_HWREV_TIGON) 1964 sc->ti_hdrsplit = 1; 1965 else 1966 device_printf(sc->ti_dev, 1967 "can't do header splitting on a Tigon I board\n"); 1968 #endif /* TI_JUMBO_HDRSPLIT */ 1969 1970 /* Set up the PCI state register. */ 1971 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1972 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1973 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1974 } 1975 1976 /* Clear the read/write max DMA parameters. */ 1977 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1978 TI_PCISTATE_READ_MAXDMA)); 1979 1980 /* Get cache line size. */ 1981 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 1982 1983 /* 1984 * If the system has set enabled the PCI memory write 1985 * and invalidate command in the command register, set 1986 * the write max parameter accordingly. This is necessary 1987 * to use MWI with the Tigon 2. 1988 */ 1989 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 1990 switch (cacheline) { 1991 case 1: 1992 case 4: 1993 case 8: 1994 case 16: 1995 case 32: 1996 case 64: 1997 break; 1998 default: 1999 /* Disable PCI memory write and invalidate. */ 2000 if (bootverbose) 2001 device_printf(sc->ti_dev, "cache line size %d" 2002 " not supported; disabling PCI MWI\n", 2003 cacheline); 2004 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2005 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2006 break; 2007 } 2008 } 2009 2010 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2011 2012 /* This sets the min dma param all the way up (0xff). */ 2013 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2014 2015 if (sc->ti_hdrsplit) 2016 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2017 else 2018 hdrsplit = 0; 2019 2020 /* Configure DMA variables. */ 2021 #if BYTE_ORDER == BIG_ENDIAN 2022 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2023 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2024 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2025 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2026 #else /* BYTE_ORDER */ 2027 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2028 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2029 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2030 #endif /* BYTE_ORDER */ 2031 2032 /* 2033 * Only allow 1 DMA channel to be active at a time. 2034 * I don't think this is a good idea, but without it 2035 * the firmware racks up lots of nicDmaReadRingFull 2036 * errors. This is not compatible with hardware checksums. 2037 */ 2038 if (sc->ti_ifp->if_hwassist == 0) 2039 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2040 2041 /* Recommended settings from Tigon manual. */ 2042 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2043 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2044 2045 if (ti_64bitslot_war(sc)) { 2046 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2047 "but we aren't"); 2048 return (EINVAL); 2049 } 2050 2051 return (0); 2052 } 2053 2054 /* 2055 * Initialize the general information block and firmware, and 2056 * start the CPU(s) running. 2057 */ 2058 static int 2059 ti_gibinit(sc) 2060 struct ti_softc *sc; 2061 { 2062 struct ti_rcb *rcb; 2063 int i; 2064 struct ifnet *ifp; 2065 uint32_t rdphys; 2066 2067 TI_LOCK_ASSERT(sc); 2068 2069 ifp = sc->ti_ifp; 2070 rdphys = sc->ti_rdata_phys; 2071 2072 /* Disable interrupts for now. */ 2073 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2074 2075 /* 2076 * Tell the chip where to find the general information block. 2077 * While this struct could go into >4GB memory, we allocate it in a 2078 * single slab with the other descriptors, and those don't seem to 2079 * support being located in a 64-bit region. 2080 */ 2081 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 2082 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, rdphys + TI_RD_OFF(ti_info)); 2083 2084 /* Load the firmware into SRAM. */ 2085 ti_loadfw(sc); 2086 2087 /* Set up the contents of the general info and ring control blocks. */ 2088 2089 /* Set up the event ring and producer pointer. */ 2090 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 2091 2092 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_event_ring); 2093 rcb->ti_flags = 0; 2094 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 2095 rdphys + TI_RD_OFF(ti_ev_prodidx_r); 2096 sc->ti_ev_prodidx.ti_idx = 0; 2097 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2098 sc->ti_ev_saved_considx = 0; 2099 2100 /* Set up the command ring and producer mailbox. */ 2101 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 2102 2103 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 2104 rcb->ti_flags = 0; 2105 rcb->ti_max_len = 0; 2106 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2107 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2108 } 2109 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2110 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2111 sc->ti_cmd_saved_prodidx = 0; 2112 2113 /* 2114 * Assign the address of the stats refresh buffer. 2115 * We re-use the current stats buffer for this to 2116 * conserve memory. 2117 */ 2118 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 2119 rdphys + TI_RD_OFF(ti_info.ti_stats); 2120 2121 /* Set up the standard receive ring. */ 2122 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 2123 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_std_ring); 2124 rcb->ti_max_len = TI_FRAMELEN; 2125 rcb->ti_flags = 0; 2126 if (sc->ti_ifp->if_hwassist) 2127 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2128 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2129 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2130 2131 /* Set up the jumbo receive ring. */ 2132 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 2133 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_jumbo_ring); 2134 2135 #ifdef TI_PRIVATE_JUMBOS 2136 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 2137 rcb->ti_flags = 0; 2138 #else 2139 rcb->ti_max_len = PAGE_SIZE; 2140 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2141 #endif 2142 if (sc->ti_ifp->if_hwassist) 2143 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2144 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2145 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2146 2147 /* 2148 * Set up the mini ring. Only activated on the 2149 * Tigon 2 but the slot in the config block is 2150 * still there on the Tigon 1. 2151 */ 2152 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 2153 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_mini_ring); 2154 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2155 if (sc->ti_hwrev == TI_HWREV_TIGON) 2156 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2157 else 2158 rcb->ti_flags = 0; 2159 if (sc->ti_ifp->if_hwassist) 2160 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2161 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2162 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2163 2164 /* 2165 * Set up the receive return ring. 2166 */ 2167 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 2168 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_rx_return_ring); 2169 rcb->ti_flags = 0; 2170 rcb->ti_max_len = TI_RETURN_RING_CNT; 2171 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 2172 rdphys + TI_RD_OFF(ti_return_prodidx_r); 2173 2174 /* 2175 * Set up the tx ring. Note: for the Tigon 2, we have the option 2176 * of putting the transmit ring in the host's address space and 2177 * letting the chip DMA it instead of leaving the ring in the NIC's 2178 * memory and accessing it through the shared memory region. We 2179 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2180 * so we have to revert to the shared memory scheme if we detect 2181 * a Tigon 1 chip. 2182 */ 2183 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2184 bzero((char *)sc->ti_rdata->ti_tx_ring, 2185 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 2186 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 2187 if (sc->ti_hwrev == TI_HWREV_TIGON) 2188 rcb->ti_flags = 0; 2189 else 2190 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2191 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2192 if (sc->ti_ifp->if_hwassist) 2193 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2194 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2195 rcb->ti_max_len = TI_TX_RING_CNT; 2196 if (sc->ti_hwrev == TI_HWREV_TIGON) 2197 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 2198 else 2199 TI_HOSTADDR(rcb->ti_hostaddr) = rdphys + TI_RD_OFF(ti_tx_ring); 2200 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 2201 rdphys + TI_RD_OFF(ti_tx_considx_r); 2202 2203 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2204 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2205 2206 /* Set up tuneables */ 2207 #if 0 2208 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2209 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2210 (sc->ti_rx_coal_ticks / 10)); 2211 else 2212 #endif 2213 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2214 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2215 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2216 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2217 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2218 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2219 2220 /* Turn interrupts on. */ 2221 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2222 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2223 2224 /* Start CPU. */ 2225 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2226 2227 return (0); 2228 } 2229 2230 static void 2231 ti_rdata_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2232 { 2233 struct ti_softc *sc; 2234 2235 sc = arg; 2236 if (error || nseg != 1) 2237 return; 2238 2239 /* 2240 * All of the Tigon data structures need to live at <4GB. This 2241 * cast is fine since busdma was told about this constraint. 2242 */ 2243 sc->ti_rdata_phys = segs[0].ds_addr; 2244 return; 2245 } 2246 2247 /* 2248 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2249 * against our list and return its name if we find a match. 2250 */ 2251 static int 2252 ti_probe(dev) 2253 device_t dev; 2254 { 2255 struct ti_type *t; 2256 2257 t = ti_devs; 2258 2259 while (t->ti_name != NULL) { 2260 if ((pci_get_vendor(dev) == t->ti_vid) && 2261 (pci_get_device(dev) == t->ti_did)) { 2262 device_set_desc(dev, t->ti_name); 2263 return (BUS_PROBE_DEFAULT); 2264 } 2265 t++; 2266 } 2267 2268 return (ENXIO); 2269 } 2270 2271 static int 2272 ti_attach(dev) 2273 device_t dev; 2274 { 2275 struct ifnet *ifp; 2276 struct ti_softc *sc; 2277 int error = 0, rid; 2278 u_char eaddr[6]; 2279 2280 sc = device_get_softc(dev); 2281 sc->ti_unit = device_get_unit(dev); 2282 sc->ti_dev = dev; 2283 2284 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2285 MTX_DEF); 2286 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2287 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2288 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2289 if (ifp == NULL) { 2290 device_printf(dev, "can not if_alloc()\n"); 2291 error = ENOSPC; 2292 goto fail; 2293 } 2294 sc->ti_ifp->if_capabilities = IFCAP_HWCSUM | 2295 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2296 sc->ti_ifp->if_capenable = sc->ti_ifp->if_capabilities; 2297 2298 /* 2299 * Map control/status registers. 2300 */ 2301 pci_enable_busmaster(dev); 2302 2303 rid = TI_PCI_LOMEM; 2304 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2305 RF_ACTIVE); 2306 2307 if (sc->ti_res == NULL) { 2308 device_printf(dev, "couldn't map memory\n"); 2309 error = ENXIO; 2310 goto fail; 2311 } 2312 2313 sc->ti_btag = rman_get_bustag(sc->ti_res); 2314 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2315 2316 /* Allocate interrupt */ 2317 rid = 0; 2318 2319 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2320 RF_SHAREABLE | RF_ACTIVE); 2321 2322 if (sc->ti_irq == NULL) { 2323 device_printf(dev, "couldn't map interrupt\n"); 2324 error = ENXIO; 2325 goto fail; 2326 } 2327 2328 if (ti_chipinit(sc)) { 2329 device_printf(dev, "chip initialization failed\n"); 2330 error = ENXIO; 2331 goto fail; 2332 } 2333 2334 /* Zero out the NIC's on-board SRAM. */ 2335 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2336 2337 /* Init again -- zeroing memory may have clobbered some registers. */ 2338 if (ti_chipinit(sc)) { 2339 device_printf(dev, "chip initialization failed\n"); 2340 error = ENXIO; 2341 goto fail; 2342 } 2343 2344 /* 2345 * Get station address from the EEPROM. Note: the manual states 2346 * that the MAC address is at offset 0x8c, however the data is 2347 * stored as two longwords (since that's how it's loaded into 2348 * the NIC). This means the MAC address is actually preceded 2349 * by two zero bytes. We need to skip over those. 2350 */ 2351 if (ti_read_eeprom(sc, eaddr, 2352 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2353 device_printf(dev, "failed to read station address\n"); 2354 error = ENXIO; 2355 goto fail; 2356 } 2357 2358 /* Allocate the general information block and ring buffers. */ 2359 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 2360 1, 0, /* algnmnt, boundary */ 2361 BUS_SPACE_MAXADDR, /* lowaddr */ 2362 BUS_SPACE_MAXADDR, /* highaddr */ 2363 NULL, NULL, /* filter, filterarg */ 2364 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 2365 0, /* nsegments */ 2366 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2367 0, /* flags */ 2368 NULL, NULL, /* lockfunc, lockarg */ 2369 &sc->ti_parent_dmat) != 0) { 2370 device_printf(dev, "Failed to allocate parent dmat\n"); 2371 error = ENOMEM; 2372 goto fail; 2373 } 2374 2375 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2376 PAGE_SIZE, 0, /* algnmnt, boundary */ 2377 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2378 BUS_SPACE_MAXADDR, /* highaddr */ 2379 NULL, NULL, /* filter, filterarg */ 2380 sizeof(struct ti_ring_data), /* maxsize */ 2381 1, /* nsegments */ 2382 sizeof(struct ti_ring_data), /* maxsegsize */ 2383 0, /* flags */ 2384 NULL, NULL, /* lockfunc, lockarg */ 2385 &sc->ti_rdata_dmat) != 0) { 2386 device_printf(dev, "Failed to allocate rdata dmat\n"); 2387 error = ENOMEM; 2388 goto fail; 2389 } 2390 2391 if (bus_dmamem_alloc(sc->ti_rdata_dmat, (void**)&sc->ti_rdata, 2392 BUS_DMA_NOWAIT, &sc->ti_rdata_dmamap) != 0) { 2393 device_printf(dev, "Failed to allocate rdata memory\n"); 2394 error = ENOMEM; 2395 goto fail; 2396 } 2397 2398 if (bus_dmamap_load(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2399 sc->ti_rdata, sizeof(struct ti_ring_data), 2400 ti_rdata_cb, sc, BUS_DMA_NOWAIT) != 0) { 2401 device_printf(dev, "Failed to load rdata segments\n"); 2402 error = ENOMEM; 2403 goto fail; 2404 } 2405 2406 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 2407 2408 /* Try to allocate memory for jumbo buffers. */ 2409 if (ti_alloc_jumbo_mem(sc)) { 2410 device_printf(dev, "jumbo buffer allocation failed\n"); 2411 error = ENXIO; 2412 goto fail; 2413 } 2414 2415 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2416 1, 0, /* algnmnt, boundary */ 2417 BUS_SPACE_MAXADDR, /* lowaddr */ 2418 BUS_SPACE_MAXADDR, /* highaddr */ 2419 NULL, NULL, /* filter, filterarg */ 2420 MCLBYTES * TI_MAXTXSEGS,/* maxsize */ 2421 TI_MAXTXSEGS, /* nsegments */ 2422 MCLBYTES, /* maxsegsize */ 2423 0, /* flags */ 2424 NULL, NULL, /* lockfunc, lockarg */ 2425 &sc->ti_mbuftx_dmat) != 0) { 2426 device_printf(dev, "Failed to allocate rdata dmat\n"); 2427 error = ENOMEM; 2428 goto fail; 2429 } 2430 2431 if (bus_dma_tag_create(sc->ti_parent_dmat, /* parent */ 2432 1, 0, /* algnmnt, boundary */ 2433 BUS_SPACE_MAXADDR, /* lowaddr */ 2434 BUS_SPACE_MAXADDR, /* highaddr */ 2435 NULL, NULL, /* filter, filterarg */ 2436 MCLBYTES, /* maxsize */ 2437 1, /* nsegments */ 2438 MCLBYTES, /* maxsegsize */ 2439 0, /* flags */ 2440 NULL, NULL, /* lockfunc, lockarg */ 2441 &sc->ti_mbufrx_dmat) != 0) { 2442 device_printf(dev, "Failed to allocate rdata dmat\n"); 2443 error = ENOMEM; 2444 goto fail; 2445 } 2446 2447 if (ti_alloc_dmamaps(sc)) { 2448 device_printf(dev, "dma map creation failed\n"); 2449 error = ENXIO; 2450 goto fail; 2451 } 2452 2453 /* 2454 * We really need a better way to tell a 1000baseTX card 2455 * from a 1000baseSX one, since in theory there could be 2456 * OEMed 1000baseTX cards from lame vendors who aren't 2457 * clever enough to change the PCI ID. For the moment 2458 * though, the AceNIC is the only copper card available. 2459 */ 2460 if (pci_get_vendor(dev) == ALT_VENDORID && 2461 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2462 sc->ti_copper = 1; 2463 /* Ok, it's not the only copper card available. */ 2464 if (pci_get_vendor(dev) == NG_VENDORID && 2465 pci_get_device(dev) == NG_DEVICEID_GA620T) 2466 sc->ti_copper = 1; 2467 2468 /* Set default tuneable values. */ 2469 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 2470 #if 0 2471 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 2472 #endif 2473 sc->ti_rx_coal_ticks = 170; 2474 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 2475 sc->ti_rx_max_coal_bds = 64; 2476 #if 0 2477 sc->ti_tx_max_coal_bds = 128; 2478 #endif 2479 sc->ti_tx_max_coal_bds = 32; 2480 sc->ti_tx_buf_ratio = 21; 2481 2482 /* Set up ifnet structure */ 2483 ifp->if_softc = sc; 2484 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2486 ifp->if_ioctl = ti_ioctl; 2487 ifp->if_start = ti_start; 2488 ifp->if_init = ti_init; 2489 ifp->if_baudrate = 1000000000; 2490 ifp->if_mtu = ETHERMTU; 2491 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 2492 2493 /* Set up ifmedia support. */ 2494 if (sc->ti_copper) { 2495 /* 2496 * Copper cards allow manual 10/100 mode selection, 2497 * but not manual 1000baseTX mode selection. Why? 2498 * Becuase currently there's no way to specify the 2499 * master/slave setting through the firmware interface, 2500 * so Alteon decided to just bag it and handle it 2501 * via autonegotiation. 2502 */ 2503 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2504 ifmedia_add(&sc->ifmedia, 2505 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2506 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2507 ifmedia_add(&sc->ifmedia, 2508 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2510 ifmedia_add(&sc->ifmedia, 2511 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2512 } else { 2513 /* Fiber cards don't support 10/100 modes. */ 2514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2515 ifmedia_add(&sc->ifmedia, 2516 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2517 } 2518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2519 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2520 2521 /* 2522 * We're assuming here that card initialization is a sequential 2523 * thing. If it isn't, multiple cards probing at the same time 2524 * could stomp on the list of softcs here. 2525 */ 2526 2527 /* Register the device */ 2528 sc->dev = make_dev(&ti_cdevsw, sc->ti_unit, UID_ROOT, GID_OPERATOR, 2529 0600, "ti%d", sc->ti_unit); 2530 sc->dev->si_drv1 = sc; 2531 2532 /* 2533 * Call MI attach routine. 2534 */ 2535 ether_ifattach(ifp, eaddr); 2536 2537 /* Hook interrupt last to avoid having to lock softc */ 2538 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2539 NULL, ti_intr, sc, &sc->ti_intrhand); 2540 2541 if (error) { 2542 device_printf(dev, "couldn't set up irq\n"); 2543 goto fail; 2544 } 2545 2546 fail: 2547 if (error) 2548 ti_detach(dev); 2549 2550 return (error); 2551 } 2552 2553 /* 2554 * Shutdown hardware and free up resources. This can be called any 2555 * time after the mutex has been initialized. It is called in both 2556 * the error case in attach and the normal detach case so it needs 2557 * to be careful about only freeing resources that have actually been 2558 * allocated. 2559 */ 2560 static int 2561 ti_detach(dev) 2562 device_t dev; 2563 { 2564 struct ti_softc *sc; 2565 struct ifnet *ifp; 2566 2567 sc = device_get_softc(dev); 2568 if (sc->dev) 2569 destroy_dev(sc->dev); 2570 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2571 ifp = sc->ti_ifp; 2572 if (device_is_attached(dev)) { 2573 ether_ifdetach(ifp); 2574 TI_LOCK(sc); 2575 ti_stop(sc); 2576 TI_UNLOCK(sc); 2577 } 2578 2579 /* These should only be active if attach succeeded */ 2580 callout_drain(&sc->ti_watchdog); 2581 bus_generic_detach(dev); 2582 ti_free_dmamaps(sc); 2583 ifmedia_removeall(&sc->ifmedia); 2584 2585 #ifdef TI_PRIVATE_JUMBOS 2586 if (sc->ti_cdata.ti_jumbo_buf) 2587 bus_dmamem_free(sc->ti_jumbo_dmat, sc->ti_cdata.ti_jumbo_buf, 2588 sc->ti_jumbo_dmamap); 2589 #endif 2590 if (sc->ti_jumbo_dmat) 2591 bus_dma_tag_destroy(sc->ti_jumbo_dmat); 2592 if (sc->ti_mbuftx_dmat) 2593 bus_dma_tag_destroy(sc->ti_mbuftx_dmat); 2594 if (sc->ti_mbufrx_dmat) 2595 bus_dma_tag_destroy(sc->ti_mbufrx_dmat); 2596 if (sc->ti_rdata) 2597 bus_dmamem_free(sc->ti_rdata_dmat, sc->ti_rdata, 2598 sc->ti_rdata_dmamap); 2599 if (sc->ti_rdata_dmat) 2600 bus_dma_tag_destroy(sc->ti_rdata_dmat); 2601 if (sc->ti_parent_dmat) 2602 bus_dma_tag_destroy(sc->ti_parent_dmat); 2603 if (sc->ti_intrhand) 2604 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2605 if (sc->ti_irq) 2606 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2607 if (sc->ti_res) { 2608 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, 2609 sc->ti_res); 2610 } 2611 if (ifp) 2612 if_free(ifp); 2613 2614 mtx_destroy(&sc->ti_mtx); 2615 2616 return (0); 2617 } 2618 2619 #ifdef TI_JUMBO_HDRSPLIT 2620 /* 2621 * If hdr_len is 0, that means that header splitting wasn't done on 2622 * this packet for some reason. The two most likely reasons are that 2623 * the protocol isn't a supported protocol for splitting, or this 2624 * packet had a fragment offset that wasn't 0. 2625 * 2626 * The header length, if it is non-zero, will always be the length of 2627 * the headers on the packet, but that length could be longer than the 2628 * first mbuf. So we take the minimum of the two as the actual 2629 * length. 2630 */ 2631 static __inline void 2632 ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2633 { 2634 int i = 0; 2635 int lengths[4] = {0, 0, 0, 0}; 2636 struct mbuf *m, *mp; 2637 2638 if (hdr_len != 0) 2639 top->m_len = min(hdr_len, top->m_len); 2640 pkt_len -= top->m_len; 2641 lengths[i++] = top->m_len; 2642 2643 mp = top; 2644 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2645 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2646 pkt_len -= m->m_len; 2647 lengths[i++] = m->m_len; 2648 mp = m; 2649 } 2650 2651 #if 0 2652 if (hdr_len != 0) 2653 printf("got split packet: "); 2654 else 2655 printf("got non-split packet: "); 2656 2657 printf("%d,%d,%d,%d = %d\n", lengths[0], 2658 lengths[1], lengths[2], lengths[3], 2659 lengths[0] + lengths[1] + lengths[2] + 2660 lengths[3]); 2661 #endif 2662 2663 if (pkt_len) 2664 panic("header splitting didn't"); 2665 2666 if (m) { 2667 m_freem(m); 2668 mp->m_next = NULL; 2669 2670 } 2671 if (mp->m_next != NULL) 2672 panic("ti_hdr_split: last mbuf in chain should be null"); 2673 } 2674 #endif /* TI_JUMBO_HDRSPLIT */ 2675 2676 /* 2677 * Frame reception handling. This is called if there's a frame 2678 * on the receive return list. 2679 * 2680 * Note: we have to be able to handle three possibilities here: 2681 * 1) the frame is from the mini receive ring (can only happen) 2682 * on Tigon 2 boards) 2683 * 2) the frame is from the jumbo recieve ring 2684 * 3) the frame is from the standard receive ring 2685 */ 2686 2687 static void 2688 ti_rxeof(sc) 2689 struct ti_softc *sc; 2690 { 2691 bus_dmamap_t map; 2692 struct ifnet *ifp; 2693 struct ti_cmd_desc cmd; 2694 2695 TI_LOCK_ASSERT(sc); 2696 2697 ifp = sc->ti_ifp; 2698 2699 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2700 struct ti_rx_desc *cur_rx; 2701 u_int32_t rxidx; 2702 struct mbuf *m = NULL; 2703 u_int16_t vlan_tag = 0; 2704 int have_tag = 0; 2705 2706 cur_rx = 2707 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 2708 rxidx = cur_rx->ti_idx; 2709 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2710 2711 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2712 have_tag = 1; 2713 vlan_tag = cur_rx->ti_vlan_tag & 0xfff; 2714 } 2715 2716 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2717 2718 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2719 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2720 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2721 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2722 bus_dmamap_sync(sc->ti_jumbo_dmat, map, 2723 BUS_DMASYNC_POSTREAD); 2724 bus_dmamap_unload(sc->ti_jumbo_dmat, map); 2725 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2726 ifp->if_ierrors++; 2727 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2728 continue; 2729 } 2730 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2731 ifp->if_ierrors++; 2732 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2733 continue; 2734 } 2735 #ifdef TI_PRIVATE_JUMBOS 2736 m->m_len = cur_rx->ti_len; 2737 #else /* TI_PRIVATE_JUMBOS */ 2738 #ifdef TI_JUMBO_HDRSPLIT 2739 if (sc->ti_hdrsplit) 2740 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2741 cur_rx->ti_len, rxidx); 2742 else 2743 #endif /* TI_JUMBO_HDRSPLIT */ 2744 m_adj(m, cur_rx->ti_len - m->m_pkthdr.len); 2745 #endif /* TI_PRIVATE_JUMBOS */ 2746 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2747 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2748 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2749 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 2750 map = sc->ti_cdata.ti_rx_mini_maps[rxidx]; 2751 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2752 BUS_DMASYNC_POSTREAD); 2753 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2754 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2755 ifp->if_ierrors++; 2756 ti_newbuf_mini(sc, sc->ti_mini, m); 2757 continue; 2758 } 2759 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) { 2760 ifp->if_ierrors++; 2761 ti_newbuf_mini(sc, sc->ti_mini, m); 2762 continue; 2763 } 2764 m->m_len = cur_rx->ti_len; 2765 } else { 2766 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2767 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2768 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2769 map = sc->ti_cdata.ti_rx_std_maps[rxidx]; 2770 bus_dmamap_sync(sc->ti_mbufrx_dmat, map, 2771 BUS_DMASYNC_POSTREAD); 2772 bus_dmamap_unload(sc->ti_mbufrx_dmat, map); 2773 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2774 ifp->if_ierrors++; 2775 ti_newbuf_std(sc, sc->ti_std, m); 2776 continue; 2777 } 2778 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) { 2779 ifp->if_ierrors++; 2780 ti_newbuf_std(sc, sc->ti_std, m); 2781 continue; 2782 } 2783 m->m_len = cur_rx->ti_len; 2784 } 2785 2786 m->m_pkthdr.len = cur_rx->ti_len; 2787 ifp->if_ipackets++; 2788 m->m_pkthdr.rcvif = ifp; 2789 2790 if (ifp->if_hwassist) { 2791 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 2792 CSUM_DATA_VALID; 2793 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2794 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2795 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum; 2796 } 2797 2798 /* 2799 * If we received a packet with a vlan tag, 2800 * tag it before passing the packet upward. 2801 */ 2802 if (have_tag) { 2803 m->m_pkthdr.ether_vtag = vlan_tag; 2804 m->m_flags |= M_VLANTAG; 2805 } 2806 TI_UNLOCK(sc); 2807 (*ifp->if_input)(ifp, m); 2808 TI_LOCK(sc); 2809 } 2810 2811 /* Only necessary on the Tigon 1. */ 2812 if (sc->ti_hwrev == TI_HWREV_TIGON) 2813 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2814 sc->ti_rx_saved_considx); 2815 2816 TI_UPDATE_STDPROD(sc, sc->ti_std); 2817 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2818 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2819 } 2820 2821 static void 2822 ti_txeof(sc) 2823 struct ti_softc *sc; 2824 { 2825 struct ti_txdesc *txd; 2826 struct ti_tx_desc txdesc; 2827 struct ti_tx_desc *cur_tx = NULL; 2828 struct ifnet *ifp; 2829 int idx; 2830 2831 ifp = sc->ti_ifp; 2832 2833 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2834 if (txd == NULL) 2835 return; 2836 /* 2837 * Go through our tx ring and free mbufs for those 2838 * frames that have been sent. 2839 */ 2840 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2841 TI_INC(idx, TI_TX_RING_CNT)) { 2842 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2843 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2844 sizeof(txdesc), &txdesc); 2845 cur_tx = &txdesc; 2846 } else 2847 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2848 sc->ti_txcnt--; 2849 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2850 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2851 continue; 2852 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2853 BUS_DMASYNC_POSTWRITE); 2854 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2855 2856 ifp->if_opackets++; 2857 m_freem(txd->tx_m); 2858 txd->tx_m = NULL; 2859 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2860 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2861 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2862 } 2863 sc->ti_tx_saved_considx = idx; 2864 2865 sc->ti_timer = sc->ti_txcnt > 0 ? 5 : 0; 2866 } 2867 2868 static void 2869 ti_intr(xsc) 2870 void *xsc; 2871 { 2872 struct ti_softc *sc; 2873 struct ifnet *ifp; 2874 2875 sc = xsc; 2876 TI_LOCK(sc); 2877 ifp = sc->ti_ifp; 2878 2879 /*#ifdef notdef*/ 2880 /* Avoid this for now -- checking this register is expensive. */ 2881 /* Make sure this is really our interrupt. */ 2882 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2883 TI_UNLOCK(sc); 2884 return; 2885 } 2886 /*#endif*/ 2887 2888 /* Ack interrupt and stop others from occuring. */ 2889 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2890 2891 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2892 /* Check RX return ring producer/consumer */ 2893 ti_rxeof(sc); 2894 2895 /* Check TX ring producer/consumer */ 2896 ti_txeof(sc); 2897 } 2898 2899 ti_handle_events(sc); 2900 2901 /* Re-enable interrupts. */ 2902 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2903 2904 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2905 ifp->if_snd.ifq_head != NULL) 2906 ti_start_locked(ifp); 2907 2908 TI_UNLOCK(sc); 2909 } 2910 2911 static void 2912 ti_stats_update(sc) 2913 struct ti_softc *sc; 2914 { 2915 struct ifnet *ifp; 2916 2917 ifp = sc->ti_ifp; 2918 2919 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2920 BUS_DMASYNC_POSTREAD); 2921 2922 ifp->if_collisions += 2923 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2924 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2925 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2926 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2927 ifp->if_collisions; 2928 2929 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2930 BUS_DMASYNC_PREREAD); 2931 } 2932 2933 /* 2934 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2935 * pointers to descriptors. 2936 */ 2937 static int 2938 ti_encap(sc, m_head) 2939 struct ti_softc *sc; 2940 struct mbuf **m_head; 2941 { 2942 struct ti_txdesc *txd; 2943 struct ti_tx_desc *f; 2944 struct ti_tx_desc txdesc; 2945 struct mbuf *m; 2946 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 2947 u_int16_t csum_flags; 2948 int error, frag, i, nseg; 2949 2950 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 2951 return (ENOBUFS); 2952 2953 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2954 *m_head, txsegs, &nseg, 0); 2955 if (error == EFBIG) { 2956 m = m_defrag(*m_head, M_DONTWAIT); 2957 if (m == NULL) { 2958 m_freem(*m_head); 2959 *m_head = NULL; 2960 return (ENOMEM); 2961 } 2962 *m_head = m; 2963 error = bus_dmamap_load_mbuf_sg(sc->ti_mbuftx_dmat, 2964 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 2965 if (error) { 2966 m_freem(*m_head); 2967 *m_head = NULL; 2968 return (error); 2969 } 2970 } else if (error != 0) 2971 return (error); 2972 if (nseg == 0) { 2973 m_freem(*m_head); 2974 *m_head = NULL; 2975 return (EIO); 2976 } 2977 2978 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 2979 bus_dmamap_unload(sc->ti_mbuftx_dmat, txd->tx_dmamap); 2980 return (ENOBUFS); 2981 } 2982 2983 m = *m_head; 2984 csum_flags = 0; 2985 if (m->m_pkthdr.csum_flags) { 2986 if (m->m_pkthdr.csum_flags & CSUM_IP) 2987 csum_flags |= TI_BDFLAG_IP_CKSUM; 2988 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2989 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2990 if (m->m_flags & M_LASTFRAG) 2991 csum_flags |= TI_BDFLAG_IP_FRAG_END; 2992 else if (m->m_flags & M_FRAG) 2993 csum_flags |= TI_BDFLAG_IP_FRAG; 2994 } 2995 2996 bus_dmamap_sync(sc->ti_mbuftx_dmat, txd->tx_dmamap, 2997 BUS_DMASYNC_PREWRITE); 2998 bus_dmamap_sync(sc->ti_rdata_dmat, sc->ti_rdata_dmamap, 2999 BUS_DMASYNC_PREWRITE); 3000 3001 frag = sc->ti_tx_saved_prodidx; 3002 for (i = 0; i < nseg; i++) { 3003 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3004 bzero(&txdesc, sizeof(txdesc)); 3005 f = &txdesc; 3006 } else 3007 f = &sc->ti_rdata->ti_tx_ring[frag]; 3008 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3009 f->ti_len = txsegs[i].ds_len; 3010 f->ti_flags = csum_flags; 3011 if (m->m_flags & M_VLANTAG) { 3012 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3013 f->ti_vlan_tag = m->m_pkthdr.ether_vtag & 0xfff; 3014 } else { 3015 f->ti_vlan_tag = 0; 3016 } 3017 3018 if (sc->ti_hwrev == TI_HWREV_TIGON) 3019 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3020 sizeof(txdesc), sizeof(txdesc), &txdesc); 3021 TI_INC(frag, TI_TX_RING_CNT); 3022 } 3023 3024 sc->ti_tx_saved_prodidx = frag; 3025 /* set TI_BDFLAG_END on the last descriptor */ 3026 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3027 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3028 txdesc.ti_flags |= TI_BDFLAG_END; 3029 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3030 sizeof(txdesc), &txdesc); 3031 } else 3032 sc->ti_rdata->ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3033 3034 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3035 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3036 txd->tx_m = m; 3037 sc->ti_txcnt += nseg; 3038 3039 return (0); 3040 } 3041 3042 static void 3043 ti_start(ifp) 3044 struct ifnet *ifp; 3045 { 3046 struct ti_softc *sc; 3047 3048 sc = ifp->if_softc; 3049 TI_LOCK(sc); 3050 ti_start_locked(ifp); 3051 TI_UNLOCK(sc); 3052 } 3053 3054 /* 3055 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3056 * to the mbuf data regions directly in the transmit descriptors. 3057 */ 3058 static void 3059 ti_start_locked(ifp) 3060 struct ifnet *ifp; 3061 { 3062 struct ti_softc *sc; 3063 struct mbuf *m_head = NULL; 3064 int enq = 0; 3065 3066 sc = ifp->if_softc; 3067 3068 for (; ifp->if_snd.ifq_head != NULL && 3069 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3070 IF_DEQUEUE(&ifp->if_snd, m_head); 3071 if (m_head == NULL) 3072 break; 3073 3074 /* 3075 * XXX 3076 * safety overkill. If this is a fragmented packet chain 3077 * with delayed TCP/UDP checksums, then only encapsulate 3078 * it if we have enough descriptors to handle the entire 3079 * chain at once. 3080 * (paranoia -- may not actually be needed) 3081 */ 3082 if (m_head->m_flags & M_FIRSTFRAG && 3083 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3084 if ((TI_TX_RING_CNT - sc->ti_txcnt) < 3085 m_head->m_pkthdr.csum_data + 16) { 3086 IF_PREPEND(&ifp->if_snd, m_head); 3087 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3088 break; 3089 } 3090 } 3091 3092 /* 3093 * Pack the data into the transmit ring. If we 3094 * don't have room, set the OACTIVE flag and wait 3095 * for the NIC to drain the ring. 3096 */ 3097 if (ti_encap(sc, &m_head)) { 3098 if (m_head == NULL) 3099 break; 3100 IF_PREPEND(&ifp->if_snd, m_head); 3101 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3102 break; 3103 } 3104 3105 enq++; 3106 /* 3107 * If there's a BPF listener, bounce a copy of this frame 3108 * to him. 3109 */ 3110 ETHER_BPF_MTAP(ifp, m_head); 3111 } 3112 3113 if (enq > 0) { 3114 /* Transmit */ 3115 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3116 3117 /* 3118 * Set a timeout in case the chip goes out to lunch. 3119 */ 3120 sc->ti_timer = 5; 3121 } 3122 } 3123 3124 static void 3125 ti_init(xsc) 3126 void *xsc; 3127 { 3128 struct ti_softc *sc; 3129 3130 sc = xsc; 3131 TI_LOCK(sc); 3132 ti_init_locked(sc); 3133 TI_UNLOCK(sc); 3134 } 3135 3136 static void 3137 ti_init_locked(xsc) 3138 void *xsc; 3139 { 3140 struct ti_softc *sc = xsc; 3141 3142 /* Cancel pending I/O and flush buffers. */ 3143 ti_stop(sc); 3144 3145 /* Init the gen info block, ring control blocks and firmware. */ 3146 if (ti_gibinit(sc)) { 3147 device_printf(sc->ti_dev, "initialization failure\n"); 3148 return; 3149 } 3150 } 3151 3152 static void ti_init2(sc) 3153 struct ti_softc *sc; 3154 { 3155 struct ti_cmd_desc cmd; 3156 struct ifnet *ifp; 3157 u_int8_t *ea; 3158 struct ifmedia *ifm; 3159 int tmp; 3160 3161 TI_LOCK_ASSERT(sc); 3162 3163 ifp = sc->ti_ifp; 3164 3165 /* Specify MTU and interface index. */ 3166 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->ti_unit); 3167 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 3168 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3169 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3170 3171 /* Load our MAC address. */ 3172 ea = IF_LLADDR(sc->ti_ifp); 3173 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3174 CSR_WRITE_4(sc, TI_GCR_PAR1, 3175 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3176 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3177 3178 /* Enable or disable promiscuous mode as needed. */ 3179 if (ifp->if_flags & IFF_PROMISC) { 3180 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3181 } else { 3182 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3183 } 3184 3185 /* Program multicast filter. */ 3186 ti_setmulti(sc); 3187 3188 /* 3189 * If this is a Tigon 1, we should tell the 3190 * firmware to use software packet filtering. 3191 */ 3192 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3193 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3194 } 3195 3196 /* Init RX ring. */ 3197 ti_init_rx_ring_std(sc); 3198 3199 /* Init jumbo RX ring. */ 3200 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3201 ti_init_rx_ring_jumbo(sc); 3202 3203 /* 3204 * If this is a Tigon 2, we can also configure the 3205 * mini ring. 3206 */ 3207 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 3208 ti_init_rx_ring_mini(sc); 3209 3210 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3211 sc->ti_rx_saved_considx = 0; 3212 3213 /* Init TX ring. */ 3214 ti_init_tx_ring(sc); 3215 3216 /* Tell firmware we're alive. */ 3217 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3218 3219 /* Enable host interrupts. */ 3220 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3221 3222 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3223 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3224 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3225 3226 /* 3227 * Make sure to set media properly. We have to do this 3228 * here since we have to issue commands in order to set 3229 * the link negotiation and we can't issue commands until 3230 * the firmware is running. 3231 */ 3232 ifm = &sc->ifmedia; 3233 tmp = ifm->ifm_media; 3234 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3235 ti_ifmedia_upd(ifp); 3236 ifm->ifm_media = tmp; 3237 } 3238 3239 /* 3240 * Set media options. 3241 */ 3242 static int 3243 ti_ifmedia_upd(ifp) 3244 struct ifnet *ifp; 3245 { 3246 struct ti_softc *sc; 3247 struct ifmedia *ifm; 3248 struct ti_cmd_desc cmd; 3249 u_int32_t flowctl; 3250 3251 sc = ifp->if_softc; 3252 ifm = &sc->ifmedia; 3253 3254 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3255 return (EINVAL); 3256 3257 flowctl = 0; 3258 3259 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3260 case IFM_AUTO: 3261 /* 3262 * Transmit flow control doesn't work on the Tigon 1. 3263 */ 3264 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3265 3266 /* 3267 * Transmit flow control can also cause problems on the 3268 * Tigon 2, apparantly with both the copper and fiber 3269 * boards. The symptom is that the interface will just 3270 * hang. This was reproduced with Alteon 180 switches. 3271 */ 3272 #if 0 3273 if (sc->ti_hwrev != TI_HWREV_TIGON) 3274 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3275 #endif 3276 3277 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3278 TI_GLNK_FULL_DUPLEX| flowctl | 3279 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3280 3281 flowctl = TI_LNK_RX_FLOWCTL_Y; 3282 #if 0 3283 if (sc->ti_hwrev != TI_HWREV_TIGON) 3284 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3285 #endif 3286 3287 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3288 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3289 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3290 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3291 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3292 break; 3293 case IFM_1000_SX: 3294 case IFM_1000_T: 3295 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3296 #if 0 3297 if (sc->ti_hwrev != TI_HWREV_TIGON) 3298 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3299 #endif 3300 3301 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3302 flowctl |TI_GLNK_ENB); 3303 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3304 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3305 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3306 } 3307 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3308 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3309 break; 3310 case IFM_100_FX: 3311 case IFM_10_FL: 3312 case IFM_100_TX: 3313 case IFM_10_T: 3314 flowctl = TI_LNK_RX_FLOWCTL_Y; 3315 #if 0 3316 if (sc->ti_hwrev != TI_HWREV_TIGON) 3317 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3318 #endif 3319 3320 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3321 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3322 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3323 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3324 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3325 } else { 3326 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3327 } 3328 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3329 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3330 } else { 3331 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3332 } 3333 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3334 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3335 break; 3336 } 3337 3338 return (0); 3339 } 3340 3341 /* 3342 * Report current media status. 3343 */ 3344 static void 3345 ti_ifmedia_sts(ifp, ifmr) 3346 struct ifnet *ifp; 3347 struct ifmediareq *ifmr; 3348 { 3349 struct ti_softc *sc; 3350 u_int32_t media = 0; 3351 3352 sc = ifp->if_softc; 3353 3354 ifmr->ifm_status = IFM_AVALID; 3355 ifmr->ifm_active = IFM_ETHER; 3356 3357 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 3358 return; 3359 3360 ifmr->ifm_status |= IFM_ACTIVE; 3361 3362 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3363 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3364 if (sc->ti_copper) 3365 ifmr->ifm_active |= IFM_1000_T; 3366 else 3367 ifmr->ifm_active |= IFM_1000_SX; 3368 if (media & TI_GLNK_FULL_DUPLEX) 3369 ifmr->ifm_active |= IFM_FDX; 3370 else 3371 ifmr->ifm_active |= IFM_HDX; 3372 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3373 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3374 if (sc->ti_copper) { 3375 if (media & TI_LNK_100MB) 3376 ifmr->ifm_active |= IFM_100_TX; 3377 if (media & TI_LNK_10MB) 3378 ifmr->ifm_active |= IFM_10_T; 3379 } else { 3380 if (media & TI_LNK_100MB) 3381 ifmr->ifm_active |= IFM_100_FX; 3382 if (media & TI_LNK_10MB) 3383 ifmr->ifm_active |= IFM_10_FL; 3384 } 3385 if (media & TI_LNK_FULL_DUPLEX) 3386 ifmr->ifm_active |= IFM_FDX; 3387 if (media & TI_LNK_HALF_DUPLEX) 3388 ifmr->ifm_active |= IFM_HDX; 3389 } 3390 } 3391 3392 static int 3393 ti_ioctl(ifp, command, data) 3394 struct ifnet *ifp; 3395 u_long command; 3396 caddr_t data; 3397 { 3398 struct ti_softc *sc = ifp->if_softc; 3399 struct ifreq *ifr = (struct ifreq *) data; 3400 int mask, error = 0; 3401 struct ti_cmd_desc cmd; 3402 3403 switch (command) { 3404 case SIOCSIFMTU: 3405 TI_LOCK(sc); 3406 if (ifr->ifr_mtu > TI_JUMBO_MTU) 3407 error = EINVAL; 3408 else { 3409 ifp->if_mtu = ifr->ifr_mtu; 3410 ti_init_locked(sc); 3411 } 3412 TI_UNLOCK(sc); 3413 break; 3414 case SIOCSIFFLAGS: 3415 TI_LOCK(sc); 3416 if (ifp->if_flags & IFF_UP) { 3417 /* 3418 * If only the state of the PROMISC flag changed, 3419 * then just use the 'set promisc mode' command 3420 * instead of reinitializing the entire NIC. Doing 3421 * a full re-init means reloading the firmware and 3422 * waiting for it to start up, which may take a 3423 * second or two. 3424 */ 3425 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3426 ifp->if_flags & IFF_PROMISC && 3427 !(sc->ti_if_flags & IFF_PROMISC)) { 3428 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3429 TI_CMD_CODE_PROMISC_ENB, 0); 3430 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3431 !(ifp->if_flags & IFF_PROMISC) && 3432 sc->ti_if_flags & IFF_PROMISC) { 3433 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3434 TI_CMD_CODE_PROMISC_DIS, 0); 3435 } else 3436 ti_init_locked(sc); 3437 } else { 3438 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3439 ti_stop(sc); 3440 } 3441 } 3442 sc->ti_if_flags = ifp->if_flags; 3443 TI_UNLOCK(sc); 3444 break; 3445 case SIOCADDMULTI: 3446 case SIOCDELMULTI: 3447 TI_LOCK(sc); 3448 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3449 ti_setmulti(sc); 3450 TI_UNLOCK(sc); 3451 break; 3452 case SIOCSIFMEDIA: 3453 case SIOCGIFMEDIA: 3454 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3455 break; 3456 case SIOCSIFCAP: 3457 TI_LOCK(sc); 3458 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3459 if (mask & IFCAP_HWCSUM) { 3460 if (IFCAP_HWCSUM & ifp->if_capenable) 3461 ifp->if_capenable &= ~IFCAP_HWCSUM; 3462 else 3463 ifp->if_capenable |= IFCAP_HWCSUM; 3464 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3465 ti_init_locked(sc); 3466 } 3467 TI_UNLOCK(sc); 3468 break; 3469 default: 3470 error = ether_ioctl(ifp, command, data); 3471 break; 3472 } 3473 3474 return (error); 3475 } 3476 3477 static int 3478 ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3479 { 3480 struct ti_softc *sc; 3481 3482 sc = dev->si_drv1; 3483 if (sc == NULL) 3484 return (ENODEV); 3485 3486 TI_LOCK(sc); 3487 sc->ti_flags |= TI_FLAG_DEBUGING; 3488 TI_UNLOCK(sc); 3489 3490 return (0); 3491 } 3492 3493 static int 3494 ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3495 { 3496 struct ti_softc *sc; 3497 3498 sc = dev->si_drv1; 3499 if (sc == NULL) 3500 return (ENODEV); 3501 3502 TI_LOCK(sc); 3503 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3504 TI_UNLOCK(sc); 3505 3506 return (0); 3507 } 3508 3509 /* 3510 * This ioctl routine goes along with the Tigon character device. 3511 */ 3512 static int 3513 ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3514 struct thread *td) 3515 { 3516 int error; 3517 struct ti_softc *sc; 3518 3519 sc = dev->si_drv1; 3520 if (sc == NULL) 3521 return (ENODEV); 3522 3523 error = 0; 3524 3525 switch (cmd) { 3526 case TIIOCGETSTATS: 3527 { 3528 struct ti_stats *outstats; 3529 3530 outstats = (struct ti_stats *)addr; 3531 3532 TI_LOCK(sc); 3533 bcopy(&sc->ti_rdata->ti_info.ti_stats, outstats, 3534 sizeof(struct ti_stats)); 3535 TI_UNLOCK(sc); 3536 break; 3537 } 3538 case TIIOCGETPARAMS: 3539 { 3540 struct ti_params *params; 3541 3542 params = (struct ti_params *)addr; 3543 3544 TI_LOCK(sc); 3545 params->ti_stat_ticks = sc->ti_stat_ticks; 3546 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3547 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3548 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3549 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3550 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3551 params->param_mask = TI_PARAM_ALL; 3552 TI_UNLOCK(sc); 3553 3554 error = 0; 3555 3556 break; 3557 } 3558 case TIIOCSETPARAMS: 3559 { 3560 struct ti_params *params; 3561 3562 params = (struct ti_params *)addr; 3563 3564 TI_LOCK(sc); 3565 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3566 sc->ti_stat_ticks = params->ti_stat_ticks; 3567 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3568 } 3569 3570 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3571 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3572 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3573 sc->ti_rx_coal_ticks); 3574 } 3575 3576 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3577 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3578 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3579 sc->ti_tx_coal_ticks); 3580 } 3581 3582 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3583 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3584 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3585 sc->ti_rx_max_coal_bds); 3586 } 3587 3588 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3589 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3590 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3591 sc->ti_tx_max_coal_bds); 3592 } 3593 3594 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3595 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3596 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3597 sc->ti_tx_buf_ratio); 3598 } 3599 TI_UNLOCK(sc); 3600 3601 error = 0; 3602 3603 break; 3604 } 3605 case TIIOCSETTRACE: { 3606 ti_trace_type trace_type; 3607 3608 trace_type = *(ti_trace_type *)addr; 3609 3610 /* 3611 * Set tracing to whatever the user asked for. Setting 3612 * this register to 0 should have the effect of disabling 3613 * tracing. 3614 */ 3615 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3616 3617 error = 0; 3618 3619 break; 3620 } 3621 case TIIOCGETTRACE: { 3622 struct ti_trace_buf *trace_buf; 3623 u_int32_t trace_start, cur_trace_ptr, trace_len; 3624 3625 trace_buf = (struct ti_trace_buf *)addr; 3626 3627 TI_LOCK(sc); 3628 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3629 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3630 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3631 3632 #if 0 3633 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3634 "trace_len = %d\n", trace_start, 3635 cur_trace_ptr, trace_len); 3636 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3637 trace_buf->buf_len); 3638 #endif 3639 3640 error = ti_copy_mem(sc, trace_start, min(trace_len, 3641 trace_buf->buf_len), 3642 (caddr_t)trace_buf->buf, 1, 1); 3643 3644 if (error == 0) { 3645 trace_buf->fill_len = min(trace_len, 3646 trace_buf->buf_len); 3647 if (cur_trace_ptr < trace_start) 3648 trace_buf->cur_trace_ptr = 3649 trace_start - cur_trace_ptr; 3650 else 3651 trace_buf->cur_trace_ptr = 3652 cur_trace_ptr - trace_start; 3653 } else 3654 trace_buf->fill_len = 0; 3655 TI_UNLOCK(sc); 3656 3657 break; 3658 } 3659 3660 /* 3661 * For debugging, five ioctls are needed: 3662 * ALT_ATTACH 3663 * ALT_READ_TG_REG 3664 * ALT_WRITE_TG_REG 3665 * ALT_READ_TG_MEM 3666 * ALT_WRITE_TG_MEM 3667 */ 3668 case ALT_ATTACH: 3669 /* 3670 * From what I can tell, Alteon's Solaris Tigon driver 3671 * only has one character device, so you have to attach 3672 * to the Tigon board you're interested in. This seems 3673 * like a not-so-good way to do things, since unless you 3674 * subsequently specify the unit number of the device 3675 * you're interested in every ioctl, you'll only be 3676 * able to debug one board at a time. 3677 */ 3678 error = 0; 3679 break; 3680 case ALT_READ_TG_MEM: 3681 case ALT_WRITE_TG_MEM: 3682 { 3683 struct tg_mem *mem_param; 3684 u_int32_t sram_end, scratch_end; 3685 3686 mem_param = (struct tg_mem *)addr; 3687 3688 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3689 sram_end = TI_END_SRAM_I; 3690 scratch_end = TI_END_SCRATCH_I; 3691 } else { 3692 sram_end = TI_END_SRAM_II; 3693 scratch_end = TI_END_SCRATCH_II; 3694 } 3695 3696 /* 3697 * For now, we'll only handle accessing regular SRAM, 3698 * nothing else. 3699 */ 3700 TI_LOCK(sc); 3701 if ((mem_param->tgAddr >= TI_BEG_SRAM) 3702 && ((mem_param->tgAddr + mem_param->len) <= sram_end)) { 3703 /* 3704 * In this instance, we always copy to/from user 3705 * space, so the user space argument is set to 1. 3706 */ 3707 error = ti_copy_mem(sc, mem_param->tgAddr, 3708 mem_param->len, 3709 mem_param->userAddr, 1, 3710 (cmd == ALT_READ_TG_MEM) ? 1 : 0); 3711 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH) 3712 && (mem_param->tgAddr <= scratch_end)) { 3713 error = ti_copy_scratch(sc, mem_param->tgAddr, 3714 mem_param->len, 3715 mem_param->userAddr, 1, 3716 (cmd == ALT_READ_TG_MEM) ? 3717 1 : 0, TI_PROCESSOR_A); 3718 } else if ((mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG) 3719 && (mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG)) { 3720 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3721 if_printf(sc->ti_ifp, 3722 "invalid memory range for Tigon I\n"); 3723 error = EINVAL; 3724 break; 3725 } 3726 error = ti_copy_scratch(sc, mem_param->tgAddr - 3727 TI_SCRATCH_DEBUG_OFF, 3728 mem_param->len, 3729 mem_param->userAddr, 1, 3730 (cmd == ALT_READ_TG_MEM) ? 3731 1 : 0, TI_PROCESSOR_B); 3732 } else { 3733 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3734 "out of supported range\n", 3735 mem_param->tgAddr, mem_param->len); 3736 error = EINVAL; 3737 } 3738 TI_UNLOCK(sc); 3739 3740 break; 3741 } 3742 case ALT_READ_TG_REG: 3743 case ALT_WRITE_TG_REG: 3744 { 3745 struct tg_reg *regs; 3746 u_int32_t tmpval; 3747 3748 regs = (struct tg_reg *)addr; 3749 3750 /* 3751 * Make sure the address in question isn't out of range. 3752 */ 3753 if (regs->addr > TI_REG_MAX) { 3754 error = EINVAL; 3755 break; 3756 } 3757 TI_LOCK(sc); 3758 if (cmd == ALT_READ_TG_REG) { 3759 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3760 regs->addr, &tmpval, 1); 3761 regs->data = ntohl(tmpval); 3762 #if 0 3763 if ((regs->addr == TI_CPU_STATE) 3764 || (regs->addr == TI_CPU_CTL_B)) { 3765 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3766 regs->addr, tmpval); 3767 } 3768 #endif 3769 } else { 3770 tmpval = htonl(regs->data); 3771 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3772 regs->addr, &tmpval, 1); 3773 } 3774 TI_UNLOCK(sc); 3775 3776 break; 3777 } 3778 default: 3779 error = ENOTTY; 3780 break; 3781 } 3782 return (error); 3783 } 3784 3785 static void 3786 ti_watchdog(void *arg) 3787 { 3788 struct ti_softc *sc; 3789 struct ifnet *ifp; 3790 3791 sc = arg; 3792 TI_LOCK_ASSERT(sc); 3793 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3794 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3795 return; 3796 3797 /* 3798 * When we're debugging, the chip is often stopped for long periods 3799 * of time, and that would normally cause the watchdog timer to fire. 3800 * Since that impedes debugging, we don't want to do that. 3801 */ 3802 if (sc->ti_flags & TI_FLAG_DEBUGING) 3803 return; 3804 3805 ifp = sc->ti_ifp; 3806 if_printf(ifp, "watchdog timeout -- resetting\n"); 3807 ti_stop(sc); 3808 ti_init_locked(sc); 3809 3810 ifp->if_oerrors++; 3811 } 3812 3813 /* 3814 * Stop the adapter and free any mbufs allocated to the 3815 * RX and TX lists. 3816 */ 3817 static void 3818 ti_stop(sc) 3819 struct ti_softc *sc; 3820 { 3821 struct ifnet *ifp; 3822 struct ti_cmd_desc cmd; 3823 3824 TI_LOCK_ASSERT(sc); 3825 3826 ifp = sc->ti_ifp; 3827 3828 /* Disable host interrupts. */ 3829 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3830 /* 3831 * Tell firmware we're shutting down. 3832 */ 3833 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3834 3835 /* Halt and reinitialize. */ 3836 if (ti_chipinit(sc) != 0) 3837 return; 3838 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3839 if (ti_chipinit(sc) != 0) 3840 return; 3841 3842 /* Free the RX lists. */ 3843 ti_free_rx_ring_std(sc); 3844 3845 /* Free jumbo RX list. */ 3846 ti_free_rx_ring_jumbo(sc); 3847 3848 /* Free mini RX list. */ 3849 ti_free_rx_ring_mini(sc); 3850 3851 /* Free TX buffers. */ 3852 ti_free_tx_ring(sc); 3853 3854 sc->ti_ev_prodidx.ti_idx = 0; 3855 sc->ti_return_prodidx.ti_idx = 0; 3856 sc->ti_tx_considx.ti_idx = 0; 3857 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3858 3859 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3860 callout_stop(&sc->ti_watchdog); 3861 } 3862 3863 /* 3864 * Stop all chip I/O so that the kernel's probe routines don't 3865 * get confused by errant DMAs when rebooting. 3866 */ 3867 static int 3868 ti_shutdown(dev) 3869 device_t dev; 3870 { 3871 struct ti_softc *sc; 3872 3873 sc = device_get_softc(dev); 3874 TI_LOCK(sc); 3875 ti_chipinit(sc); 3876 TI_UNLOCK(sc); 3877 3878 return (0); 3879 } 3880